root / hw / etraxfs_ser.c @ c9c3c80a
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1 | 83fa1010 | ths | /*
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2 | 83fa1010 | ths | * QEMU ETRAX System Emulator
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3 | 83fa1010 | ths | *
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4 | 83fa1010 | ths | * Copyright (c) 2007 Edgar E. Iglesias, Axis Communications AB.
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5 | 83fa1010 | ths | *
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6 | 83fa1010 | ths | * Permission is hereby granted, free of charge, to any person obtaining a copy
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7 | 83fa1010 | ths | * of this software and associated documentation files (the "Software"), to deal
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8 | 83fa1010 | ths | * in the Software without restriction, including without limitation the rights
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9 | 83fa1010 | ths | * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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10 | 83fa1010 | ths | * copies of the Software, and to permit persons to whom the Software is
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11 | 83fa1010 | ths | * furnished to do so, subject to the following conditions:
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12 | 83fa1010 | ths | *
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13 | 83fa1010 | ths | * The above copyright notice and this permission notice shall be included in
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14 | 83fa1010 | ths | * all copies or substantial portions of the Software.
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15 | 83fa1010 | ths | *
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16 | 83fa1010 | ths | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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17 | 83fa1010 | ths | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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18 | 83fa1010 | ths | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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19 | 83fa1010 | ths | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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20 | 83fa1010 | ths | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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21 | 83fa1010 | ths | * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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22 | 83fa1010 | ths | * THE SOFTWARE.
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23 | 83fa1010 | ths | */
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24 | 83fa1010 | ths | |
25 | 4b816985 | Edgar E. Iglesias | #include "sysbus.h" |
26 | f062058f | edgar_igl | #include "qemu-char.h" |
27 | 8cc7c395 | Edgar E. Iglesias | #include "qemu-log.h" |
28 | 83fa1010 | ths | |
29 | bbaf29c7 | edgar_igl | #define D(x)
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30 | bbaf29c7 | edgar_igl | |
31 | 72af9170 | Edgar E. Iglesias | #define RW_TR_CTRL (0x00 / 4) |
32 | 72af9170 | Edgar E. Iglesias | #define RW_TR_DMA_EN (0x04 / 4) |
33 | 72af9170 | Edgar E. Iglesias | #define RW_REC_CTRL (0x08 / 4) |
34 | 72af9170 | Edgar E. Iglesias | #define RW_DOUT (0x1c / 4) |
35 | 72af9170 | Edgar E. Iglesias | #define RS_STAT_DIN (0x20 / 4) |
36 | 72af9170 | Edgar E. Iglesias | #define R_STAT_DIN (0x24 / 4) |
37 | 72af9170 | Edgar E. Iglesias | #define RW_INTR_MASK (0x2c / 4) |
38 | 72af9170 | Edgar E. Iglesias | #define RW_ACK_INTR (0x30 / 4) |
39 | 72af9170 | Edgar E. Iglesias | #define R_INTR (0x34 / 4) |
40 | 72af9170 | Edgar E. Iglesias | #define R_MASKED_INTR (0x38 / 4) |
41 | 72af9170 | Edgar E. Iglesias | #define R_MAX (0x3c / 4) |
42 | 83fa1010 | ths | |
43 | f062058f | edgar_igl | #define STAT_DAV 16 |
44 | f062058f | edgar_igl | #define STAT_TR_IDLE 22 |
45 | f062058f | edgar_igl | #define STAT_TR_RDY 24 |
46 | f062058f | edgar_igl | |
47 | f2964260 | Edgar E. Iglesias | struct etrax_serial
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48 | 83fa1010 | ths | { |
49 | 2a9859e7 | Edgar E. Iglesias | SysBusDevice busdev; |
50 | dbfb57f3 | Edgar E. Iglesias | MemoryRegion mmio; |
51 | 2a9859e7 | Edgar E. Iglesias | CharDriverState *chr; |
52 | 2a9859e7 | Edgar E. Iglesias | qemu_irq irq; |
53 | f062058f | edgar_igl | |
54 | 2a9859e7 | Edgar E. Iglesias | int pending_tx;
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55 | f062058f | edgar_igl | |
56 | f2fcffbb | Edgar E. Iglesias | uint8_t rx_fifo[16];
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57 | f2fcffbb | Edgar E. Iglesias | unsigned int rx_fifo_pos; |
58 | f2fcffbb | Edgar E. Iglesias | unsigned int rx_fifo_len; |
59 | f2fcffbb | Edgar E. Iglesias | |
60 | 2a9859e7 | Edgar E. Iglesias | /* Control registers. */
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61 | 2a9859e7 | Edgar E. Iglesias | uint32_t regs[R_MAX]; |
62 | f062058f | edgar_igl | }; |
63 | f062058f | edgar_igl | |
64 | f2964260 | Edgar E. Iglesias | static void ser_update_irq(struct etrax_serial *s) |
65 | f062058f | edgar_igl | { |
66 | 72af9170 | Edgar E. Iglesias | |
67 | f2fcffbb | Edgar E. Iglesias | if (s->rx_fifo_len) {
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68 | f2fcffbb | Edgar E. Iglesias | s->regs[R_INTR] |= 8;
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69 | f2fcffbb | Edgar E. Iglesias | } else {
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70 | f2fcffbb | Edgar E. Iglesias | s->regs[R_INTR] &= ~8;
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71 | f2fcffbb | Edgar E. Iglesias | } |
72 | f2fcffbb | Edgar E. Iglesias | |
73 | f2fcffbb | Edgar E. Iglesias | s->regs[R_MASKED_INTR] = s->regs[R_INTR] & s->regs[RW_INTR_MASK]; |
74 | 2a9859e7 | Edgar E. Iglesias | qemu_set_irq(s->irq, !!s->regs[R_MASKED_INTR]); |
75 | 83fa1010 | ths | } |
76 | f062058f | edgar_igl | |
77 | dbfb57f3 | Edgar E. Iglesias | static uint64_t
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78 | dbfb57f3 | Edgar E. Iglesias | ser_read(void *opaque, target_phys_addr_t addr, unsigned int size) |
79 | 83fa1010 | ths | { |
80 | 2a9859e7 | Edgar E. Iglesias | struct etrax_serial *s = opaque;
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81 | 2a9859e7 | Edgar E. Iglesias | D(CPUState *env = s->env); |
82 | 2a9859e7 | Edgar E. Iglesias | uint32_t r = 0;
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83 | 2a9859e7 | Edgar E. Iglesias | |
84 | 2a9859e7 | Edgar E. Iglesias | addr >>= 2;
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85 | 2a9859e7 | Edgar E. Iglesias | switch (addr)
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86 | 2a9859e7 | Edgar E. Iglesias | { |
87 | 2a9859e7 | Edgar E. Iglesias | case R_STAT_DIN:
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88 | f2fcffbb | Edgar E. Iglesias | r = s->rx_fifo[(s->rx_fifo_pos - s->rx_fifo_len) & 15];
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89 | f2fcffbb | Edgar E. Iglesias | if (s->rx_fifo_len) {
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90 | f2fcffbb | Edgar E. Iglesias | r |= 1 << STAT_DAV;
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91 | f2fcffbb | Edgar E. Iglesias | } |
92 | f2fcffbb | Edgar E. Iglesias | r |= 1 << STAT_TR_RDY;
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93 | f2fcffbb | Edgar E. Iglesias | r |= 1 << STAT_TR_IDLE;
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94 | 2a9859e7 | Edgar E. Iglesias | break;
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95 | 2a9859e7 | Edgar E. Iglesias | case RS_STAT_DIN:
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96 | f2fcffbb | Edgar E. Iglesias | r = s->rx_fifo[(s->rx_fifo_pos - s->rx_fifo_len) & 15];
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97 | f2fcffbb | Edgar E. Iglesias | if (s->rx_fifo_len) {
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98 | f2fcffbb | Edgar E. Iglesias | r |= 1 << STAT_DAV;
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99 | f2fcffbb | Edgar E. Iglesias | s->rx_fifo_len--; |
100 | f2fcffbb | Edgar E. Iglesias | } |
101 | f2fcffbb | Edgar E. Iglesias | r |= 1 << STAT_TR_RDY;
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102 | f2fcffbb | Edgar E. Iglesias | r |= 1 << STAT_TR_IDLE;
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103 | 2a9859e7 | Edgar E. Iglesias | break;
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104 | 2a9859e7 | Edgar E. Iglesias | default:
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105 | 2a9859e7 | Edgar E. Iglesias | r = s->regs[addr]; |
106 | 8cc7c395 | Edgar E. Iglesias | D(qemu_log("%s " TARGET_FMT_plx "=%x\n", __func__, addr, r)); |
107 | 2a9859e7 | Edgar E. Iglesias | break;
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108 | 2a9859e7 | Edgar E. Iglesias | } |
109 | 2a9859e7 | Edgar E. Iglesias | return r;
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110 | 83fa1010 | ths | } |
111 | 83fa1010 | ths | |
112 | 83fa1010 | ths | static void |
113 | dbfb57f3 | Edgar E. Iglesias | ser_write(void *opaque, target_phys_addr_t addr,
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114 | dbfb57f3 | Edgar E. Iglesias | uint64_t val64, unsigned int size) |
115 | 83fa1010 | ths | { |
116 | 2a9859e7 | Edgar E. Iglesias | struct etrax_serial *s = opaque;
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117 | dbfb57f3 | Edgar E. Iglesias | uint32_t value = val64; |
118 | dbfb57f3 | Edgar E. Iglesias | unsigned char ch = val64; |
119 | 2a9859e7 | Edgar E. Iglesias | D(CPUState *env = s->env); |
120 | 2a9859e7 | Edgar E. Iglesias | |
121 | 8cc7c395 | Edgar E. Iglesias | D(qemu_log("%s " TARGET_FMT_plx "=%x\n", __func__, addr, value)); |
122 | 2a9859e7 | Edgar E. Iglesias | addr >>= 2;
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123 | 2a9859e7 | Edgar E. Iglesias | switch (addr)
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124 | 2a9859e7 | Edgar E. Iglesias | { |
125 | 2a9859e7 | Edgar E. Iglesias | case RW_DOUT:
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126 | 2cc6e0a1 | Anthony Liguori | qemu_chr_fe_write(s->chr, &ch, 1);
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127 | f2fcffbb | Edgar E. Iglesias | s->regs[R_INTR] |= 3;
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128 | 2a9859e7 | Edgar E. Iglesias | s->pending_tx = 1;
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129 | 2a9859e7 | Edgar E. Iglesias | s->regs[addr] = value; |
130 | 2a9859e7 | Edgar E. Iglesias | break;
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131 | 2a9859e7 | Edgar E. Iglesias | case RW_ACK_INTR:
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132 | f2fcffbb | Edgar E. Iglesias | if (s->pending_tx) {
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133 | f2fcffbb | Edgar E. Iglesias | value &= ~1;
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134 | 2a9859e7 | Edgar E. Iglesias | s->pending_tx = 0;
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135 | 8cc7c395 | Edgar E. Iglesias | D(qemu_log("fixedup value=%x r_intr=%x\n",
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136 | 8cc7c395 | Edgar E. Iglesias | value, s->regs[R_INTR])); |
137 | 2a9859e7 | Edgar E. Iglesias | } |
138 | f2fcffbb | Edgar E. Iglesias | s->regs[addr] = value; |
139 | f2fcffbb | Edgar E. Iglesias | s->regs[R_INTR] &= ~value; |
140 | f2fcffbb | Edgar E. Iglesias | D(printf("r_intr=%x\n", s->regs[R_INTR]));
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141 | 2a9859e7 | Edgar E. Iglesias | break;
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142 | 2a9859e7 | Edgar E. Iglesias | default:
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143 | 2a9859e7 | Edgar E. Iglesias | s->regs[addr] = value; |
144 | 2a9859e7 | Edgar E. Iglesias | break;
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145 | 2a9859e7 | Edgar E. Iglesias | } |
146 | 2a9859e7 | Edgar E. Iglesias | ser_update_irq(s); |
147 | 83fa1010 | ths | } |
148 | 83fa1010 | ths | |
149 | dbfb57f3 | Edgar E. Iglesias | static const MemoryRegionOps ser_ops = { |
150 | dbfb57f3 | Edgar E. Iglesias | .read = ser_read, |
151 | dbfb57f3 | Edgar E. Iglesias | .write = ser_write, |
152 | dbfb57f3 | Edgar E. Iglesias | .endianness = DEVICE_NATIVE_ENDIAN, |
153 | dbfb57f3 | Edgar E. Iglesias | .valid = { |
154 | dbfb57f3 | Edgar E. Iglesias | .min_access_size = 4,
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155 | dbfb57f3 | Edgar E. Iglesias | .max_access_size = 4
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156 | dbfb57f3 | Edgar E. Iglesias | } |
157 | 83fa1010 | ths | }; |
158 | 83fa1010 | ths | |
159 | f062058f | edgar_igl | static void serial_receive(void *opaque, const uint8_t *buf, int size) |
160 | 83fa1010 | ths | { |
161 | 2a9859e7 | Edgar E. Iglesias | struct etrax_serial *s = opaque;
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162 | f2fcffbb | Edgar E. Iglesias | int i;
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163 | f2fcffbb | Edgar E. Iglesias | |
164 | f2fcffbb | Edgar E. Iglesias | /* Got a byte. */
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165 | f2fcffbb | Edgar E. Iglesias | if (s->rx_fifo_len >= 16) { |
166 | 8cc7c395 | Edgar E. Iglesias | qemu_log("WARNING: UART dropped char.\n");
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167 | f2fcffbb | Edgar E. Iglesias | return;
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168 | f2fcffbb | Edgar E. Iglesias | } |
169 | f2fcffbb | Edgar E. Iglesias | |
170 | f2fcffbb | Edgar E. Iglesias | for (i = 0; i < size; i++) { |
171 | f2fcffbb | Edgar E. Iglesias | s->rx_fifo[s->rx_fifo_pos] = buf[i]; |
172 | f2fcffbb | Edgar E. Iglesias | s->rx_fifo_pos++; |
173 | f2fcffbb | Edgar E. Iglesias | s->rx_fifo_pos &= 15;
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174 | f2fcffbb | Edgar E. Iglesias | s->rx_fifo_len++; |
175 | f2fcffbb | Edgar E. Iglesias | } |
176 | f062058f | edgar_igl | |
177 | 2a9859e7 | Edgar E. Iglesias | ser_update_irq(s); |
178 | f062058f | edgar_igl | } |
179 | f062058f | edgar_igl | |
180 | f062058f | edgar_igl | static int serial_can_receive(void *opaque) |
181 | f062058f | edgar_igl | { |
182 | 2a9859e7 | Edgar E. Iglesias | struct etrax_serial *s = opaque;
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183 | 2a9859e7 | Edgar E. Iglesias | int r;
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184 | f062058f | edgar_igl | |
185 | 2a9859e7 | Edgar E. Iglesias | /* Is the receiver enabled? */
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186 | f2fcffbb | Edgar E. Iglesias | if (!(s->regs[RW_REC_CTRL] & (1 << 3))) { |
187 | f2fcffbb | Edgar E. Iglesias | return 0; |
188 | f2fcffbb | Edgar E. Iglesias | } |
189 | f062058f | edgar_igl | |
190 | f2fcffbb | Edgar E. Iglesias | r = sizeof(s->rx_fifo) - s->rx_fifo_len;
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191 | 2a9859e7 | Edgar E. Iglesias | return r;
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192 | f062058f | edgar_igl | } |
193 | f062058f | edgar_igl | |
194 | f062058f | edgar_igl | static void serial_event(void *opaque, int event) |
195 | f062058f | edgar_igl | { |
196 | f062058f | edgar_igl | |
197 | f062058f | edgar_igl | } |
198 | f062058f | edgar_igl | |
199 | 20be39de | Edgar E. Iglesias | static void etraxfs_ser_reset(DeviceState *d) |
200 | f062058f | edgar_igl | { |
201 | 20be39de | Edgar E. Iglesias | struct etrax_serial *s = container_of(d, typeof(*s), busdev.qdev);
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202 | 2a9859e7 | Edgar E. Iglesias | |
203 | 2a9859e7 | Edgar E. Iglesias | /* transmitter begins ready and idle. */
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204 | 2a9859e7 | Edgar E. Iglesias | s->regs[RS_STAT_DIN] |= (1 << STAT_TR_RDY);
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205 | 2a9859e7 | Edgar E. Iglesias | s->regs[RS_STAT_DIN] |= (1 << STAT_TR_IDLE);
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206 | 2a9859e7 | Edgar E. Iglesias | |
207 | 20be39de | Edgar E. Iglesias | s->regs[RW_REC_CTRL] = 0x10000;
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208 | 20be39de | Edgar E. Iglesias | |
209 | 20be39de | Edgar E. Iglesias | } |
210 | 20be39de | Edgar E. Iglesias | |
211 | 20be39de | Edgar E. Iglesias | static int etraxfs_ser_init(SysBusDevice *dev) |
212 | 20be39de | Edgar E. Iglesias | { |
213 | 20be39de | Edgar E. Iglesias | struct etrax_serial *s = FROM_SYSBUS(typeof (*s), dev);
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214 | 20be39de | Edgar E. Iglesias | |
215 | 2a9859e7 | Edgar E. Iglesias | sysbus_init_irq(dev, &s->irq); |
216 | dbfb57f3 | Edgar E. Iglesias | memory_region_init_io(&s->mmio, &ser_ops, s, "etraxfs-serial", R_MAX * 4); |
217 | 750ecd44 | Avi Kivity | sysbus_init_mmio(dev, &s->mmio); |
218 | dbfb57f3 | Edgar E. Iglesias | |
219 | 2a9859e7 | Edgar E. Iglesias | s->chr = qdev_init_chardev(&dev->qdev); |
220 | 2a9859e7 | Edgar E. Iglesias | if (s->chr)
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221 | 2a9859e7 | Edgar E. Iglesias | qemu_chr_add_handlers(s->chr, |
222 | 2a9859e7 | Edgar E. Iglesias | serial_can_receive, serial_receive, |
223 | 2a9859e7 | Edgar E. Iglesias | serial_event, s); |
224 | 81a322d4 | Gerd Hoffmann | return 0; |
225 | 83fa1010 | ths | } |
226 | 4b816985 | Edgar E. Iglesias | |
227 | 20be39de | Edgar E. Iglesias | static SysBusDeviceInfo etraxfs_ser_info = {
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228 | 20be39de | Edgar E. Iglesias | .init = etraxfs_ser_init, |
229 | 20be39de | Edgar E. Iglesias | .qdev.name = "etraxfs,serial",
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230 | 20be39de | Edgar E. Iglesias | .qdev.size = sizeof(struct etrax_serial), |
231 | 20be39de | Edgar E. Iglesias | .qdev.reset = etraxfs_ser_reset, |
232 | 20be39de | Edgar E. Iglesias | }; |
233 | 20be39de | Edgar E. Iglesias | |
234 | 4b816985 | Edgar E. Iglesias | static void etraxfs_serial_register(void) |
235 | 4b816985 | Edgar E. Iglesias | { |
236 | 20be39de | Edgar E. Iglesias | sysbus_register_withprop(&etraxfs_ser_info); |
237 | 4b816985 | Edgar E. Iglesias | } |
238 | 4b816985 | Edgar E. Iglesias | |
239 | 4b816985 | Edgar E. Iglesias | device_init(etraxfs_serial_register) |