Revision c9cda20b

b/target-xtensa/translate.c
1652 1652
            case 11: /*MULSHi*/
1653 1653
                HAS_OPTION(XTENSA_OPTION_32_BIT_IMUL_HIGH);
1654 1654
                {
1655
                    TCGv_i64 r = tcg_temp_new_i64();
1656
                    TCGv_i64 s = tcg_temp_new_i64();
1657
                    TCGv_i64 t = tcg_temp_new_i64();
1655
                    TCGv lo = tcg_temp_new();
1658 1656

  
1659 1657
                    if (OP2 == 10) {
1660
                        tcg_gen_extu_i32_i64(s, cpu_R[RRR_S]);
1661
                        tcg_gen_extu_i32_i64(t, cpu_R[RRR_T]);
1658
                        tcg_gen_mulu2_i32(lo, cpu_R[RRR_R],
1659
                                          cpu_R[RRR_S], cpu_R[RRR_T]);
1662 1660
                    } else {
1663
                        tcg_gen_ext_i32_i64(s, cpu_R[RRR_S]);
1664
                        tcg_gen_ext_i32_i64(t, cpu_R[RRR_T]);
1661
                        tcg_gen_muls2_i32(lo, cpu_R[RRR_R],
1662
                                          cpu_R[RRR_S], cpu_R[RRR_T]);
1665 1663
                    }
1666
                    tcg_gen_mul_i64(r, s, t);
1667
                    tcg_gen_shri_i64(r, r, 32);
1668
                    tcg_gen_trunc_i64_i32(cpu_R[RRR_R], r);
1669

  
1670
                    tcg_temp_free_i64(r);
1671
                    tcg_temp_free_i64(s);
1672
                    tcg_temp_free_i64(t);
1664
                    tcg_temp_free(lo);
1673 1665
                }
1674 1666
                break;
1675 1667

  

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