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1 | 6515b203 | bellard | /*
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2 | 6515b203 | bellard | * ACPI implementation
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3 | 5fafdf24 | ths | *
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4 | 6515b203 | bellard | * Copyright (c) 2006 Fabrice Bellard
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5 | 5fafdf24 | ths | *
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6 | 6515b203 | bellard | * This library is free software; you can redistribute it and/or
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7 | 6515b203 | bellard | * modify it under the terms of the GNU Lesser General Public
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8 | 6515b203 | bellard | * License version 2 as published by the Free Software Foundation.
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9 | 6515b203 | bellard | *
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10 | 6515b203 | bellard | * This library is distributed in the hope that it will be useful,
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11 | 6515b203 | bellard | * but WITHOUT ANY WARRANTY; without even the implied warranty of
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12 | 6515b203 | bellard | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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13 | 6515b203 | bellard | * Lesser General Public License for more details.
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14 | 6515b203 | bellard | *
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15 | 6515b203 | bellard | * You should have received a copy of the GNU Lesser General Public
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16 | 6515b203 | bellard | * License along with this library; if not, write to the Free Software
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17 | 6515b203 | bellard | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
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18 | 6515b203 | bellard | */
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19 | 6515b203 | bellard | #include "vl.h" |
20 | 6515b203 | bellard | |
21 | 6515b203 | bellard | //#define DEBUG
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22 | 6515b203 | bellard | |
23 | 6515b203 | bellard | /* i82731AB (PIIX4) compatible power management function */
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24 | 6515b203 | bellard | #define PM_FREQ 3579545 |
25 | 6515b203 | bellard | |
26 | 6515b203 | bellard | #define ACPI_DBG_IO_ADDR 0xb044 |
27 | 6515b203 | bellard | |
28 | 6515b203 | bellard | typedef struct PIIX4PMState { |
29 | 6515b203 | bellard | PCIDevice dev; |
30 | 6515b203 | bellard | uint16_t pmsts; |
31 | 6515b203 | bellard | uint16_t pmen; |
32 | 6515b203 | bellard | uint16_t pmcntrl; |
33 | ab1e34ad | bellard | uint8_t apmc; |
34 | ab1e34ad | bellard | uint8_t apms; |
35 | 6515b203 | bellard | QEMUTimer *tmr_timer; |
36 | 6515b203 | bellard | int64_t tmr_overflow_time; |
37 | 0ff596d0 | pbrook | i2c_bus *smbus; |
38 | 3fffc223 | ths | uint8_t smb_stat; |
39 | 3fffc223 | ths | uint8_t smb_ctl; |
40 | 3fffc223 | ths | uint8_t smb_cmd; |
41 | 3fffc223 | ths | uint8_t smb_addr; |
42 | 3fffc223 | ths | uint8_t smb_data0; |
43 | 3fffc223 | ths | uint8_t smb_data1; |
44 | 3fffc223 | ths | uint8_t smb_data[32];
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45 | 3fffc223 | ths | uint8_t smb_index; |
46 | 6515b203 | bellard | } PIIX4PMState; |
47 | 6515b203 | bellard | |
48 | 6515b203 | bellard | #define RTC_EN (1 << 10) |
49 | 6515b203 | bellard | #define PWRBTN_EN (1 << 8) |
50 | 6515b203 | bellard | #define GBL_EN (1 << 5) |
51 | 6515b203 | bellard | #define TMROF_EN (1 << 0) |
52 | 6515b203 | bellard | |
53 | 6515b203 | bellard | #define SCI_EN (1 << 0) |
54 | 6515b203 | bellard | |
55 | 6515b203 | bellard | #define SUS_EN (1 << 13) |
56 | 6515b203 | bellard | |
57 | 24bc1cbc | ths | #define ACPI_ENABLE 0xf1 |
58 | 24bc1cbc | ths | #define ACPI_DISABLE 0xf0 |
59 | 24bc1cbc | ths | |
60 | 3fffc223 | ths | #define SMBHSTSTS 0x00 |
61 | 3fffc223 | ths | #define SMBHSTCNT 0x02 |
62 | 3fffc223 | ths | #define SMBHSTCMD 0x03 |
63 | 3fffc223 | ths | #define SMBHSTADD 0x04 |
64 | 3fffc223 | ths | #define SMBHSTDAT0 0x05 |
65 | 3fffc223 | ths | #define SMBHSTDAT1 0x06 |
66 | 3fffc223 | ths | #define SMBBLKDAT 0x07 |
67 | 3fffc223 | ths | |
68 | 6515b203 | bellard | static uint32_t get_pmtmr(PIIX4PMState *s)
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69 | 6515b203 | bellard | { |
70 | 6515b203 | bellard | uint32_t d; |
71 | 6515b203 | bellard | d = muldiv64(qemu_get_clock(vm_clock), PM_FREQ, ticks_per_sec); |
72 | 6515b203 | bellard | return d & 0xffffff; |
73 | 6515b203 | bellard | } |
74 | 6515b203 | bellard | |
75 | 6515b203 | bellard | static int get_pmsts(PIIX4PMState *s) |
76 | 6515b203 | bellard | { |
77 | 6515b203 | bellard | int64_t d; |
78 | 6515b203 | bellard | int pmsts;
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79 | 6515b203 | bellard | pmsts = s->pmsts; |
80 | 6515b203 | bellard | d = muldiv64(qemu_get_clock(vm_clock), PM_FREQ, ticks_per_sec); |
81 | 6515b203 | bellard | if (d >= s->tmr_overflow_time)
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82 | 6515b203 | bellard | s->pmsts |= TMROF_EN; |
83 | 6515b203 | bellard | return pmsts;
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84 | 6515b203 | bellard | } |
85 | 6515b203 | bellard | |
86 | 6515b203 | bellard | static void pm_update_sci(PIIX4PMState *s) |
87 | 6515b203 | bellard | { |
88 | 6515b203 | bellard | int sci_level, pmsts;
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89 | 6515b203 | bellard | int64_t expire_time; |
90 | 3b46e624 | ths | |
91 | 6515b203 | bellard | pmsts = get_pmsts(s); |
92 | 5fafdf24 | ths | sci_level = (((pmsts & s->pmen) & |
93 | 6515b203 | bellard | (RTC_EN | PWRBTN_EN | GBL_EN | TMROF_EN)) != 0);
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94 | d537cf6c | pbrook | qemu_set_irq(s->dev.irq[0], sci_level);
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95 | 6515b203 | bellard | /* schedule a timer interruption if needed */
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96 | 6515b203 | bellard | if ((s->pmen & TMROF_EN) && !(pmsts & TMROF_EN)) {
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97 | 6515b203 | bellard | expire_time = muldiv64(s->tmr_overflow_time, ticks_per_sec, PM_FREQ); |
98 | 6515b203 | bellard | qemu_mod_timer(s->tmr_timer, expire_time); |
99 | 6515b203 | bellard | } else {
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100 | 6515b203 | bellard | qemu_del_timer(s->tmr_timer); |
101 | 6515b203 | bellard | } |
102 | 6515b203 | bellard | } |
103 | 6515b203 | bellard | |
104 | 6515b203 | bellard | static void pm_tmr_timer(void *opaque) |
105 | 6515b203 | bellard | { |
106 | 6515b203 | bellard | PIIX4PMState *s = opaque; |
107 | 6515b203 | bellard | pm_update_sci(s); |
108 | 6515b203 | bellard | } |
109 | 6515b203 | bellard | |
110 | 6515b203 | bellard | static void pm_ioport_writew(void *opaque, uint32_t addr, uint32_t val) |
111 | 6515b203 | bellard | { |
112 | 6515b203 | bellard | PIIX4PMState *s = opaque; |
113 | 6515b203 | bellard | addr &= 0x3f;
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114 | 6515b203 | bellard | switch(addr) {
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115 | 6515b203 | bellard | case 0x00: |
116 | 6515b203 | bellard | { |
117 | 6515b203 | bellard | int64_t d; |
118 | 6515b203 | bellard | int pmsts;
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119 | 6515b203 | bellard | pmsts = get_pmsts(s); |
120 | 6515b203 | bellard | if (pmsts & val & TMROF_EN) {
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121 | 6515b203 | bellard | /* if TMRSTS is reset, then compute the new overflow time */
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122 | 6515b203 | bellard | d = muldiv64(qemu_get_clock(vm_clock), PM_FREQ, ticks_per_sec); |
123 | 6515b203 | bellard | s->tmr_overflow_time = (d + 0x800000LL) & ~0x7fffffLL; |
124 | 6515b203 | bellard | } |
125 | 6515b203 | bellard | s->pmsts &= ~val; |
126 | 6515b203 | bellard | pm_update_sci(s); |
127 | 6515b203 | bellard | } |
128 | 6515b203 | bellard | break;
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129 | 6515b203 | bellard | case 0x02: |
130 | 6515b203 | bellard | s->pmen = val; |
131 | 6515b203 | bellard | pm_update_sci(s); |
132 | 6515b203 | bellard | break;
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133 | 6515b203 | bellard | case 0x04: |
134 | 6515b203 | bellard | { |
135 | 6515b203 | bellard | int sus_typ;
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136 | 6515b203 | bellard | s->pmcntrl = val & ~(SUS_EN); |
137 | 6515b203 | bellard | if (val & SUS_EN) {
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138 | 6515b203 | bellard | /* change suspend type */
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139 | 6515b203 | bellard | sus_typ = (val >> 10) & 3; |
140 | 6515b203 | bellard | switch(sus_typ) {
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141 | 6515b203 | bellard | case 0: /* soft power off */ |
142 | 6515b203 | bellard | qemu_system_shutdown_request(); |
143 | 6515b203 | bellard | break;
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144 | 6515b203 | bellard | default:
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145 | 6515b203 | bellard | break;
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146 | 6515b203 | bellard | } |
147 | 6515b203 | bellard | } |
148 | 6515b203 | bellard | } |
149 | 6515b203 | bellard | break;
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150 | 6515b203 | bellard | default:
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151 | 6515b203 | bellard | break;
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152 | 6515b203 | bellard | } |
153 | 6515b203 | bellard | #ifdef DEBUG
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154 | 6515b203 | bellard | printf("PM writew port=0x%04x val=0x%04x\n", addr, val);
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155 | 6515b203 | bellard | #endif
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156 | 6515b203 | bellard | } |
157 | 6515b203 | bellard | |
158 | 6515b203 | bellard | static uint32_t pm_ioport_readw(void *opaque, uint32_t addr) |
159 | 6515b203 | bellard | { |
160 | 6515b203 | bellard | PIIX4PMState *s = opaque; |
161 | 6515b203 | bellard | uint32_t val; |
162 | 6515b203 | bellard | |
163 | 6515b203 | bellard | addr &= 0x3f;
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164 | 6515b203 | bellard | switch(addr) {
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165 | 6515b203 | bellard | case 0x00: |
166 | 6515b203 | bellard | val = get_pmsts(s); |
167 | 6515b203 | bellard | break;
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168 | 6515b203 | bellard | case 0x02: |
169 | 6515b203 | bellard | val = s->pmen; |
170 | 6515b203 | bellard | break;
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171 | 6515b203 | bellard | case 0x04: |
172 | 6515b203 | bellard | val = s->pmcntrl; |
173 | 6515b203 | bellard | break;
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174 | 6515b203 | bellard | default:
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175 | 6515b203 | bellard | val = 0;
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176 | 6515b203 | bellard | break;
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177 | 6515b203 | bellard | } |
178 | 6515b203 | bellard | #ifdef DEBUG
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179 | 6515b203 | bellard | printf("PM readw port=0x%04x val=0x%04x\n", addr, val);
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180 | 6515b203 | bellard | #endif
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181 | 6515b203 | bellard | return val;
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182 | 6515b203 | bellard | } |
183 | 6515b203 | bellard | |
184 | 6515b203 | bellard | static void pm_ioport_writel(void *opaque, uint32_t addr, uint32_t val) |
185 | 6515b203 | bellard | { |
186 | 6515b203 | bellard | // PIIX4PMState *s = opaque;
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187 | 6515b203 | bellard | addr &= 0x3f;
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188 | 6515b203 | bellard | #ifdef DEBUG
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189 | 6515b203 | bellard | printf("PM writel port=0x%04x val=0x%08x\n", addr, val);
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190 | 6515b203 | bellard | #endif
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191 | 6515b203 | bellard | } |
192 | 6515b203 | bellard | |
193 | 6515b203 | bellard | static uint32_t pm_ioport_readl(void *opaque, uint32_t addr) |
194 | 6515b203 | bellard | { |
195 | 6515b203 | bellard | PIIX4PMState *s = opaque; |
196 | 6515b203 | bellard | uint32_t val; |
197 | 6515b203 | bellard | |
198 | 6515b203 | bellard | addr &= 0x3f;
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199 | 6515b203 | bellard | switch(addr) {
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200 | 6515b203 | bellard | case 0x08: |
201 | 6515b203 | bellard | val = get_pmtmr(s); |
202 | 6515b203 | bellard | break;
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203 | 6515b203 | bellard | default:
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204 | 6515b203 | bellard | val = 0;
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205 | 6515b203 | bellard | break;
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206 | 6515b203 | bellard | } |
207 | 6515b203 | bellard | #ifdef DEBUG
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208 | 6515b203 | bellard | printf("PM readl port=0x%04x val=0x%08x\n", addr, val);
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209 | 6515b203 | bellard | #endif
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210 | 6515b203 | bellard | return val;
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211 | 6515b203 | bellard | } |
212 | 6515b203 | bellard | |
213 | ab1e34ad | bellard | static void pm_smi_writeb(void *opaque, uint32_t addr, uint32_t val) |
214 | 6515b203 | bellard | { |
215 | 6515b203 | bellard | PIIX4PMState *s = opaque; |
216 | ab1e34ad | bellard | addr &= 1;
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217 | 6515b203 | bellard | #ifdef DEBUG
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218 | ab1e34ad | bellard | printf("pm_smi_writeb addr=0x%x val=0x%02x\n", addr, val);
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219 | 6515b203 | bellard | #endif
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220 | ab1e34ad | bellard | if (addr == 0) { |
221 | ab1e34ad | bellard | s->apmc = val; |
222 | 24bc1cbc | ths | |
223 | 24bc1cbc | ths | /* ACPI specs 3.0, 4.7.2.5 */
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224 | 24bc1cbc | ths | if (val == ACPI_ENABLE) {
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225 | 24bc1cbc | ths | s->pmcntrl |= SCI_EN; |
226 | 24bc1cbc | ths | } else if (val == ACPI_DISABLE) { |
227 | 24bc1cbc | ths | s->pmcntrl &= ~SCI_EN; |
228 | 24bc1cbc | ths | } |
229 | 24bc1cbc | ths | |
230 | 47d02f6d | bellard | if (s->dev.config[0x5b] & (1 << 1)) { |
231 | 47d02f6d | bellard | cpu_interrupt(first_cpu, CPU_INTERRUPT_SMI); |
232 | ab1e34ad | bellard | } |
233 | ab1e34ad | bellard | } else {
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234 | ab1e34ad | bellard | s->apms = val; |
235 | 6515b203 | bellard | } |
236 | 6515b203 | bellard | } |
237 | 6515b203 | bellard | |
238 | ab1e34ad | bellard | static uint32_t pm_smi_readb(void *opaque, uint32_t addr) |
239 | ab1e34ad | bellard | { |
240 | ab1e34ad | bellard | PIIX4PMState *s = opaque; |
241 | ab1e34ad | bellard | uint32_t val; |
242 | 3b46e624 | ths | |
243 | ab1e34ad | bellard | addr &= 1;
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244 | ab1e34ad | bellard | if (addr == 0) { |
245 | ab1e34ad | bellard | val = s->apmc; |
246 | ab1e34ad | bellard | } else {
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247 | ab1e34ad | bellard | val = s->apms; |
248 | ab1e34ad | bellard | } |
249 | ab1e34ad | bellard | #ifdef DEBUG
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250 | ab1e34ad | bellard | printf("pm_smi_readb addr=0x%x val=0x%02x\n", addr, val);
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251 | ab1e34ad | bellard | #endif
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252 | ab1e34ad | bellard | return val;
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253 | ab1e34ad | bellard | } |
254 | ab1e34ad | bellard | |
255 | 6515b203 | bellard | static void acpi_dbg_writel(void *opaque, uint32_t addr, uint32_t val) |
256 | 6515b203 | bellard | { |
257 | 6515b203 | bellard | #if defined(DEBUG)
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258 | 6515b203 | bellard | printf("ACPI: DBG: 0x%08x\n", val);
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259 | 6515b203 | bellard | #endif
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260 | 6515b203 | bellard | } |
261 | 6515b203 | bellard | |
262 | 3fffc223 | ths | static void smb_transaction(PIIX4PMState *s) |
263 | 3fffc223 | ths | { |
264 | 3fffc223 | ths | uint8_t prot = (s->smb_ctl >> 2) & 0x07; |
265 | 3fffc223 | ths | uint8_t read = s->smb_addr & 0x01;
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266 | 3fffc223 | ths | uint8_t cmd = s->smb_cmd; |
267 | 3fffc223 | ths | uint8_t addr = s->smb_addr >> 1;
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268 | 0ff596d0 | pbrook | i2c_bus *bus = s->smbus; |
269 | 3fffc223 | ths | |
270 | 3fffc223 | ths | #ifdef DEBUG
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271 | 3fffc223 | ths | printf("SMBus trans addr=0x%02x prot=0x%02x\n", addr, prot);
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272 | 3fffc223 | ths | #endif
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273 | 3fffc223 | ths | switch(prot) {
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274 | 3fffc223 | ths | case 0x0: |
275 | 0ff596d0 | pbrook | smbus_quick_command(bus, addr, read); |
276 | 3fffc223 | ths | break;
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277 | 3fffc223 | ths | case 0x1: |
278 | 3fffc223 | ths | if (read) {
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279 | 0ff596d0 | pbrook | s->smb_data0 = smbus_receive_byte(bus, addr); |
280 | 0ff596d0 | pbrook | } else {
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281 | 0ff596d0 | pbrook | smbus_send_byte(bus, addr, cmd); |
282 | 3fffc223 | ths | } |
283 | 3fffc223 | ths | break;
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284 | 3fffc223 | ths | case 0x2: |
285 | 3fffc223 | ths | if (read) {
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286 | 0ff596d0 | pbrook | s->smb_data0 = smbus_read_byte(bus, addr, cmd); |
287 | 0ff596d0 | pbrook | } else {
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288 | 0ff596d0 | pbrook | smbus_write_byte(bus, addr, cmd, s->smb_data0); |
289 | 3fffc223 | ths | } |
290 | 3fffc223 | ths | break;
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291 | 3fffc223 | ths | case 0x3: |
292 | 3fffc223 | ths | if (read) {
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293 | 3fffc223 | ths | uint16_t val; |
294 | 0ff596d0 | pbrook | val = smbus_read_word(bus, addr, cmd); |
295 | 3fffc223 | ths | s->smb_data0 = val; |
296 | 3fffc223 | ths | s->smb_data1 = val >> 8;
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297 | 0ff596d0 | pbrook | } else {
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298 | 0ff596d0 | pbrook | smbus_write_word(bus, addr, cmd, (s->smb_data1 << 8) | s->smb_data0);
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299 | 3fffc223 | ths | } |
300 | 3fffc223 | ths | break;
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301 | 3fffc223 | ths | case 0x5: |
302 | 3fffc223 | ths | if (read) {
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303 | 0ff596d0 | pbrook | s->smb_data0 = smbus_read_block(bus, addr, cmd, s->smb_data); |
304 | 0ff596d0 | pbrook | } else {
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305 | 0ff596d0 | pbrook | smbus_write_block(bus, addr, cmd, s->smb_data, s->smb_data0); |
306 | 3fffc223 | ths | } |
307 | 3fffc223 | ths | break;
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308 | 3fffc223 | ths | default:
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309 | 3fffc223 | ths | goto error;
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310 | 3fffc223 | ths | } |
311 | 3fffc223 | ths | return;
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312 | 3fffc223 | ths | |
313 | 3fffc223 | ths | error:
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314 | 3fffc223 | ths | s->smb_stat |= 0x04;
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315 | 3fffc223 | ths | } |
316 | 3fffc223 | ths | |
317 | 3fffc223 | ths | static void smb_ioport_writeb(void *opaque, uint32_t addr, uint32_t val) |
318 | 3fffc223 | ths | { |
319 | 3fffc223 | ths | PIIX4PMState *s = opaque; |
320 | 3fffc223 | ths | addr &= 0x3f;
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321 | 3fffc223 | ths | #ifdef DEBUG
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322 | 3fffc223 | ths | printf("SMB writeb port=0x%04x val=0x%02x\n", addr, val);
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323 | 3fffc223 | ths | #endif
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324 | 3fffc223 | ths | switch(addr) {
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325 | 3fffc223 | ths | case SMBHSTSTS:
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326 | 3fffc223 | ths | s->smb_stat = 0;
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327 | 3fffc223 | ths | s->smb_index = 0;
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328 | 3fffc223 | ths | break;
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329 | 3fffc223 | ths | case SMBHSTCNT:
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330 | 3fffc223 | ths | s->smb_ctl = val; |
331 | 3fffc223 | ths | if (val & 0x40) |
332 | 3fffc223 | ths | smb_transaction(s); |
333 | 3fffc223 | ths | break;
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334 | 3fffc223 | ths | case SMBHSTCMD:
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335 | 3fffc223 | ths | s->smb_cmd = val; |
336 | 3fffc223 | ths | break;
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337 | 3fffc223 | ths | case SMBHSTADD:
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338 | 3fffc223 | ths | s->smb_addr = val; |
339 | 3fffc223 | ths | break;
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340 | 3fffc223 | ths | case SMBHSTDAT0:
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341 | 3fffc223 | ths | s->smb_data0 = val; |
342 | 3fffc223 | ths | break;
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343 | 3fffc223 | ths | case SMBHSTDAT1:
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344 | 3fffc223 | ths | s->smb_data1 = val; |
345 | 3fffc223 | ths | break;
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346 | 3fffc223 | ths | case SMBBLKDAT:
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347 | 3fffc223 | ths | s->smb_data[s->smb_index++] = val; |
348 | 3fffc223 | ths | if (s->smb_index > 31) |
349 | 3fffc223 | ths | s->smb_index = 0;
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350 | 3fffc223 | ths | break;
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351 | 3fffc223 | ths | default:
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352 | 3fffc223 | ths | break;
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353 | 3fffc223 | ths | } |
354 | 3fffc223 | ths | } |
355 | 3fffc223 | ths | |
356 | 3fffc223 | ths | static uint32_t smb_ioport_readb(void *opaque, uint32_t addr) |
357 | 3fffc223 | ths | { |
358 | 3fffc223 | ths | PIIX4PMState *s = opaque; |
359 | 3fffc223 | ths | uint32_t val; |
360 | 3fffc223 | ths | |
361 | 3fffc223 | ths | addr &= 0x3f;
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362 | 3fffc223 | ths | switch(addr) {
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363 | 3fffc223 | ths | case SMBHSTSTS:
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364 | 3fffc223 | ths | val = s->smb_stat; |
365 | 3fffc223 | ths | break;
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366 | 3fffc223 | ths | case SMBHSTCNT:
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367 | 3fffc223 | ths | s->smb_index = 0;
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368 | 3fffc223 | ths | val = s->smb_ctl & 0x1f;
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369 | 3fffc223 | ths | break;
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370 | 3fffc223 | ths | case SMBHSTCMD:
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371 | 3fffc223 | ths | val = s->smb_cmd; |
372 | 3fffc223 | ths | break;
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373 | 3fffc223 | ths | case SMBHSTADD:
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374 | 3fffc223 | ths | val = s->smb_addr; |
375 | 3fffc223 | ths | break;
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376 | 3fffc223 | ths | case SMBHSTDAT0:
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377 | 3fffc223 | ths | val = s->smb_data0; |
378 | 3fffc223 | ths | break;
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379 | 3fffc223 | ths | case SMBHSTDAT1:
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380 | 3fffc223 | ths | val = s->smb_data1; |
381 | 3fffc223 | ths | break;
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382 | 3fffc223 | ths | case SMBBLKDAT:
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383 | 3fffc223 | ths | val = s->smb_data[s->smb_index++]; |
384 | 3fffc223 | ths | if (s->smb_index > 31) |
385 | 3fffc223 | ths | s->smb_index = 0;
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386 | 3fffc223 | ths | break;
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387 | 3fffc223 | ths | default:
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388 | 3fffc223 | ths | val = 0;
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389 | 3fffc223 | ths | break;
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390 | 3fffc223 | ths | } |
391 | 3fffc223 | ths | #ifdef DEBUG
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392 | 3fffc223 | ths | printf("SMB readb port=0x%04x val=0x%02x\n", addr, val);
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393 | 3fffc223 | ths | #endif
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394 | 3fffc223 | ths | return val;
|
395 | 3fffc223 | ths | } |
396 | 3fffc223 | ths | |
397 | ab1e34ad | bellard | static void pm_io_space_update(PIIX4PMState *s) |
398 | ab1e34ad | bellard | { |
399 | ab1e34ad | bellard | uint32_t pm_io_base; |
400 | ab1e34ad | bellard | |
401 | ab1e34ad | bellard | if (s->dev.config[0x80] & 1) { |
402 | ab1e34ad | bellard | pm_io_base = le32_to_cpu(*(uint32_t *)(s->dev.config + 0x40));
|
403 | bf367b54 | ths | pm_io_base &= 0xffc0;
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404 | ab1e34ad | bellard | |
405 | ab1e34ad | bellard | /* XXX: need to improve memory and ioport allocation */
|
406 | ab1e34ad | bellard | #if defined(DEBUG)
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407 | ab1e34ad | bellard | printf("PM: mapping to 0x%x\n", pm_io_base);
|
408 | ab1e34ad | bellard | #endif
|
409 | ab1e34ad | bellard | register_ioport_write(pm_io_base, 64, 2, pm_ioport_writew, s); |
410 | ab1e34ad | bellard | register_ioport_read(pm_io_base, 64, 2, pm_ioport_readw, s); |
411 | ab1e34ad | bellard | register_ioport_write(pm_io_base, 64, 4, pm_ioport_writel, s); |
412 | ab1e34ad | bellard | register_ioport_read(pm_io_base, 64, 4, pm_ioport_readl, s); |
413 | ab1e34ad | bellard | } |
414 | ab1e34ad | bellard | } |
415 | ab1e34ad | bellard | |
416 | 5fafdf24 | ths | static void pm_write_config(PCIDevice *d, |
417 | ab1e34ad | bellard | uint32_t address, uint32_t val, int len)
|
418 | ab1e34ad | bellard | { |
419 | ab1e34ad | bellard | pci_default_write_config(d, address, val, len); |
420 | ab1e34ad | bellard | if (address == 0x80) |
421 | ab1e34ad | bellard | pm_io_space_update((PIIX4PMState *)d); |
422 | ab1e34ad | bellard | } |
423 | ab1e34ad | bellard | |
424 | ab1e34ad | bellard | static void pm_save(QEMUFile* f,void *opaque) |
425 | ab1e34ad | bellard | { |
426 | ab1e34ad | bellard | PIIX4PMState *s = opaque; |
427 | ab1e34ad | bellard | |
428 | ab1e34ad | bellard | pci_device_save(&s->dev, f); |
429 | ab1e34ad | bellard | |
430 | ab1e34ad | bellard | qemu_put_be16s(f, &s->pmsts); |
431 | ab1e34ad | bellard | qemu_put_be16s(f, &s->pmen); |
432 | ab1e34ad | bellard | qemu_put_be16s(f, &s->pmcntrl); |
433 | ab1e34ad | bellard | qemu_put_8s(f, &s->apmc); |
434 | ab1e34ad | bellard | qemu_put_8s(f, &s->apms); |
435 | ab1e34ad | bellard | qemu_put_timer(f, s->tmr_timer); |
436 | ab1e34ad | bellard | qemu_put_be64s(f, &s->tmr_overflow_time); |
437 | ab1e34ad | bellard | } |
438 | ab1e34ad | bellard | |
439 | ab1e34ad | bellard | static int pm_load(QEMUFile* f,void* opaque,int version_id) |
440 | ab1e34ad | bellard | { |
441 | ab1e34ad | bellard | PIIX4PMState *s = opaque; |
442 | ab1e34ad | bellard | int ret;
|
443 | ab1e34ad | bellard | |
444 | ab1e34ad | bellard | if (version_id > 1) |
445 | ab1e34ad | bellard | return -EINVAL;
|
446 | ab1e34ad | bellard | |
447 | ab1e34ad | bellard | ret = pci_device_load(&s->dev, f); |
448 | ab1e34ad | bellard | if (ret < 0) |
449 | ab1e34ad | bellard | return ret;
|
450 | ab1e34ad | bellard | |
451 | ab1e34ad | bellard | qemu_get_be16s(f, &s->pmsts); |
452 | ab1e34ad | bellard | qemu_get_be16s(f, &s->pmen); |
453 | ab1e34ad | bellard | qemu_get_be16s(f, &s->pmcntrl); |
454 | ab1e34ad | bellard | qemu_get_8s(f, &s->apmc); |
455 | ab1e34ad | bellard | qemu_get_8s(f, &s->apms); |
456 | ab1e34ad | bellard | qemu_get_timer(f, s->tmr_timer); |
457 | ab1e34ad | bellard | qemu_get_be64s(f, &s->tmr_overflow_time); |
458 | ab1e34ad | bellard | |
459 | ab1e34ad | bellard | pm_io_space_update(s); |
460 | ab1e34ad | bellard | |
461 | ab1e34ad | bellard | return 0; |
462 | ab1e34ad | bellard | } |
463 | ab1e34ad | bellard | |
464 | 7b717336 | ths | i2c_bus *piix4_pm_init(PCIBus *bus, int devfn, uint32_t smb_io_base)
|
465 | 6515b203 | bellard | { |
466 | 6515b203 | bellard | PIIX4PMState *s; |
467 | 6515b203 | bellard | uint8_t *pci_conf; |
468 | 6515b203 | bellard | |
469 | 6515b203 | bellard | s = (PIIX4PMState *)pci_register_device(bus, |
470 | 6515b203 | bellard | "PM", sizeof(PIIX4PMState), |
471 | ab1e34ad | bellard | devfn, NULL, pm_write_config);
|
472 | 6515b203 | bellard | pci_conf = s->dev.config; |
473 | 6515b203 | bellard | pci_conf[0x00] = 0x86; |
474 | 6515b203 | bellard | pci_conf[0x01] = 0x80; |
475 | 6515b203 | bellard | pci_conf[0x02] = 0x13; |
476 | 7ef4da1c | bellard | pci_conf[0x03] = 0x71; |
477 | bf367b54 | ths | pci_conf[0x06] = 0x80; |
478 | bf367b54 | ths | pci_conf[0x07] = 0x02; |
479 | 6515b203 | bellard | pci_conf[0x08] = 0x00; // revision number |
480 | 6515b203 | bellard | pci_conf[0x09] = 0x00; |
481 | 6515b203 | bellard | pci_conf[0x0a] = 0x80; // other bridge device |
482 | 6515b203 | bellard | pci_conf[0x0b] = 0x06; // bridge device |
483 | 6515b203 | bellard | pci_conf[0x0e] = 0x00; // header_type |
484 | 6515b203 | bellard | pci_conf[0x3d] = 0x01; // interrupt pin 1 |
485 | 3b46e624 | ths | |
486 | ab1e34ad | bellard | pci_conf[0x40] = 0x01; /* PM io base read only bit */ |
487 | 3b46e624 | ths | |
488 | ab1e34ad | bellard | register_ioport_write(0xb2, 2, 1, pm_smi_writeb, s); |
489 | ab1e34ad | bellard | register_ioport_read(0xb2, 2, 1, pm_smi_readb, s); |
490 | ab1e34ad | bellard | |
491 | 6515b203 | bellard | register_ioport_write(ACPI_DBG_IO_ADDR, 4, 4, acpi_dbg_writel, s); |
492 | 6515b203 | bellard | |
493 | 1ce549ab | bellard | /* XXX: which specification is used ? The i82731AB has different
|
494 | 1ce549ab | bellard | mappings */
|
495 | 1ce549ab | bellard | pci_conf[0x5f] = (parallel_hds[0] != NULL ? 0x80 : 0) | 0x10; |
496 | 1ce549ab | bellard | pci_conf[0x63] = 0x60; |
497 | 1ce549ab | bellard | pci_conf[0x67] = (serial_hds[0] != NULL ? 0x08 : 0) | |
498 | 1ce549ab | bellard | (serial_hds[1] != NULL ? 0x90 : 0); |
499 | 1ce549ab | bellard | |
500 | 3fffc223 | ths | pci_conf[0x90] = smb_io_base | 1; |
501 | 3fffc223 | ths | pci_conf[0x91] = smb_io_base >> 8; |
502 | 3fffc223 | ths | pci_conf[0xd2] = 0x09; |
503 | 3fffc223 | ths | register_ioport_write(smb_io_base, 64, 1, smb_ioport_writeb, s); |
504 | 3fffc223 | ths | register_ioport_read(smb_io_base, 64, 1, smb_ioport_readb, s); |
505 | 3fffc223 | ths | |
506 | 6515b203 | bellard | s->tmr_timer = qemu_new_timer(vm_clock, pm_tmr_timer, s); |
507 | 6515b203 | bellard | |
508 | ab1e34ad | bellard | register_savevm("piix4_pm", 0, 1, pm_save, pm_load, s); |
509 | 3fffc223 | ths | |
510 | 0ff596d0 | pbrook | s->smbus = i2c_init_bus(); |
511 | 0ff596d0 | pbrook | return s->smbus;
|
512 | 6515b203 | bellard | } |