root / hw / slavio_misc.c @ ca02f319
History | View | Annotate | Download (8.7 kB)
1 | 3475187d | bellard | /*
|
---|---|---|---|
2 | 3475187d | bellard | * QEMU Sparc SLAVIO aux io port emulation
|
3 | 5fafdf24 | ths | *
|
4 | 3475187d | bellard | * Copyright (c) 2005 Fabrice Bellard
|
5 | 5fafdf24 | ths | *
|
6 | 3475187d | bellard | * Permission is hereby granted, free of charge, to any person obtaining a copy
|
7 | 3475187d | bellard | * of this software and associated documentation files (the "Software"), to deal
|
8 | 3475187d | bellard | * in the Software without restriction, including without limitation the rights
|
9 | 3475187d | bellard | * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
|
10 | 3475187d | bellard | * copies of the Software, and to permit persons to whom the Software is
|
11 | 3475187d | bellard | * furnished to do so, subject to the following conditions:
|
12 | 3475187d | bellard | *
|
13 | 3475187d | bellard | * The above copyright notice and this permission notice shall be included in
|
14 | 3475187d | bellard | * all copies or substantial portions of the Software.
|
15 | 3475187d | bellard | *
|
16 | 3475187d | bellard | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
|
17 | 3475187d | bellard | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
|
18 | 3475187d | bellard | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
|
19 | 3475187d | bellard | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
|
20 | 3475187d | bellard | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
|
21 | 3475187d | bellard | * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
|
22 | 3475187d | bellard | * THE SOFTWARE.
|
23 | 3475187d | bellard | */
|
24 | 3475187d | bellard | #include "vl.h" |
25 | 3475187d | bellard | /* debug misc */
|
26 | 3475187d | bellard | //#define DEBUG_MISC
|
27 | 3475187d | bellard | |
28 | 3475187d | bellard | /*
|
29 | 3475187d | bellard | * This is the auxio port, chip control and system control part of
|
30 | 3475187d | bellard | * chip STP2001 (Slave I/O), also produced as NCR89C105. See
|
31 | 3475187d | bellard | * http://www.ibiblio.org/pub/historic-linux/early-ports/Sparc/NCR/NCR89C105.txt
|
32 | 3475187d | bellard | *
|
33 | 3475187d | bellard | * This also includes the PMC CPU idle controller.
|
34 | 3475187d | bellard | */
|
35 | 3475187d | bellard | |
36 | 3475187d | bellard | #ifdef DEBUG_MISC
|
37 | 3475187d | bellard | #define MISC_DPRINTF(fmt, args...) \
|
38 | 3475187d | bellard | do { printf("MISC: " fmt , ##args); } while (0) |
39 | 3475187d | bellard | #else
|
40 | 3475187d | bellard | #define MISC_DPRINTF(fmt, args...)
|
41 | 3475187d | bellard | #endif
|
42 | 3475187d | bellard | |
43 | 3475187d | bellard | typedef struct MiscState { |
44 | d537cf6c | pbrook | qemu_irq irq; |
45 | 3475187d | bellard | uint8_t config; |
46 | 3475187d | bellard | uint8_t aux1, aux2; |
47 | bfa30a38 | blueswir1 | uint8_t diag, mctrl; |
48 | bfa30a38 | blueswir1 | uint32_t sysctrl; |
49 | 3475187d | bellard | } MiscState; |
50 | 3475187d | bellard | |
51 | 5aca8c3b | blueswir1 | #define MISC_SIZE 1 |
52 | bfa30a38 | blueswir1 | #define SYSCTRL_MAXADDR 3 |
53 | bfa30a38 | blueswir1 | #define SYSCTRL_SIZE (SYSCTRL_MAXADDR + 1) |
54 | 3475187d | bellard | |
55 | 3475187d | bellard | static void slavio_misc_update_irq(void *opaque) |
56 | 3475187d | bellard | { |
57 | 3475187d | bellard | MiscState *s = opaque; |
58 | 3475187d | bellard | |
59 | 3475187d | bellard | if ((s->aux2 & 0x4) && (s->config & 0x8)) { |
60 | d537cf6c | pbrook | MISC_DPRINTF("Raise IRQ\n");
|
61 | d537cf6c | pbrook | qemu_irq_raise(s->irq); |
62 | 3475187d | bellard | } else {
|
63 | d537cf6c | pbrook | MISC_DPRINTF("Lower IRQ\n");
|
64 | d537cf6c | pbrook | qemu_irq_lower(s->irq); |
65 | 3475187d | bellard | } |
66 | 3475187d | bellard | } |
67 | 3475187d | bellard | |
68 | 3475187d | bellard | static void slavio_misc_reset(void *opaque) |
69 | 3475187d | bellard | { |
70 | 3475187d | bellard | MiscState *s = opaque; |
71 | 3475187d | bellard | |
72 | 4e3b1ea1 | bellard | // Diagnostic and system control registers not cleared in reset
|
73 | 3475187d | bellard | s->config = s->aux1 = s->aux2 = s->mctrl = 0;
|
74 | 3475187d | bellard | } |
75 | 3475187d | bellard | |
76 | 3475187d | bellard | void slavio_set_power_fail(void *opaque, int power_failing) |
77 | 3475187d | bellard | { |
78 | 3475187d | bellard | MiscState *s = opaque; |
79 | 3475187d | bellard | |
80 | 3475187d | bellard | MISC_DPRINTF("Power fail: %d, config: %d\n", power_failing, s->config);
|
81 | 3475187d | bellard | if (power_failing && (s->config & 0x8)) { |
82 | f930d07e | blueswir1 | s->aux2 |= 0x4;
|
83 | 3475187d | bellard | } else {
|
84 | f930d07e | blueswir1 | s->aux2 &= ~0x4;
|
85 | 3475187d | bellard | } |
86 | 3475187d | bellard | slavio_misc_update_irq(s); |
87 | 3475187d | bellard | } |
88 | 3475187d | bellard | |
89 | bfa30a38 | blueswir1 | static void slavio_misc_mem_writeb(void *opaque, target_phys_addr_t addr, |
90 | bfa30a38 | blueswir1 | uint32_t val) |
91 | 3475187d | bellard | { |
92 | 3475187d | bellard | MiscState *s = opaque; |
93 | 3475187d | bellard | |
94 | 3475187d | bellard | switch (addr & 0xfff0000) { |
95 | 3475187d | bellard | case 0x1800000: |
96 | f930d07e | blueswir1 | MISC_DPRINTF("Write config %2.2x\n", val & 0xff); |
97 | f930d07e | blueswir1 | s->config = val & 0xff;
|
98 | f930d07e | blueswir1 | slavio_misc_update_irq(s); |
99 | f930d07e | blueswir1 | break;
|
100 | 3475187d | bellard | case 0x1900000: |
101 | f930d07e | blueswir1 | MISC_DPRINTF("Write aux1 %2.2x\n", val & 0xff); |
102 | f930d07e | blueswir1 | s->aux1 = val & 0xff;
|
103 | f930d07e | blueswir1 | break;
|
104 | 3475187d | bellard | case 0x1910000: |
105 | f930d07e | blueswir1 | val &= 0x3;
|
106 | f930d07e | blueswir1 | MISC_DPRINTF("Write aux2 %2.2x\n", val);
|
107 | f930d07e | blueswir1 | val |= s->aux2 & 0x4;
|
108 | f930d07e | blueswir1 | if (val & 0x2) // Clear Power Fail int |
109 | f930d07e | blueswir1 | val &= 0x1;
|
110 | f930d07e | blueswir1 | s->aux2 = val; |
111 | f930d07e | blueswir1 | if (val & 1) |
112 | f930d07e | blueswir1 | qemu_system_shutdown_request(); |
113 | f930d07e | blueswir1 | slavio_misc_update_irq(s); |
114 | f930d07e | blueswir1 | break;
|
115 | 3475187d | bellard | case 0x1a00000: |
116 | f930d07e | blueswir1 | MISC_DPRINTF("Write diag %2.2x\n", val & 0xff); |
117 | f930d07e | blueswir1 | s->diag = val & 0xff;
|
118 | f930d07e | blueswir1 | break;
|
119 | 3475187d | bellard | case 0x1b00000: |
120 | f930d07e | blueswir1 | MISC_DPRINTF("Write modem control %2.2x\n", val & 0xff); |
121 | f930d07e | blueswir1 | s->mctrl = val & 0xff;
|
122 | f930d07e | blueswir1 | break;
|
123 | 3475187d | bellard | case 0xa000000: |
124 | f930d07e | blueswir1 | MISC_DPRINTF("Write power management %2.2x\n", val & 0xff); |
125 | ba3c64fb | bellard | cpu_interrupt(cpu_single_env, CPU_INTERRUPT_HALT); |
126 | f930d07e | blueswir1 | break;
|
127 | 3475187d | bellard | } |
128 | 3475187d | bellard | } |
129 | 3475187d | bellard | |
130 | 3475187d | bellard | static uint32_t slavio_misc_mem_readb(void *opaque, target_phys_addr_t addr) |
131 | 3475187d | bellard | { |
132 | 3475187d | bellard | MiscState *s = opaque; |
133 | 3475187d | bellard | uint32_t ret = 0;
|
134 | 3475187d | bellard | |
135 | 3475187d | bellard | switch (addr & 0xfff0000) { |
136 | 3475187d | bellard | case 0x1800000: |
137 | f930d07e | blueswir1 | ret = s->config; |
138 | f930d07e | blueswir1 | MISC_DPRINTF("Read config %2.2x\n", ret);
|
139 | f930d07e | blueswir1 | break;
|
140 | 3475187d | bellard | case 0x1900000: |
141 | f930d07e | blueswir1 | ret = s->aux1; |
142 | f930d07e | blueswir1 | MISC_DPRINTF("Read aux1 %2.2x\n", ret);
|
143 | f930d07e | blueswir1 | break;
|
144 | 3475187d | bellard | case 0x1910000: |
145 | f930d07e | blueswir1 | ret = s->aux2; |
146 | f930d07e | blueswir1 | MISC_DPRINTF("Read aux2 %2.2x\n", ret);
|
147 | f930d07e | blueswir1 | break;
|
148 | 3475187d | bellard | case 0x1a00000: |
149 | f930d07e | blueswir1 | ret = s->diag; |
150 | f930d07e | blueswir1 | MISC_DPRINTF("Read diag %2.2x\n", ret);
|
151 | f930d07e | blueswir1 | break;
|
152 | 3475187d | bellard | case 0x1b00000: |
153 | f930d07e | blueswir1 | ret = s->mctrl; |
154 | f930d07e | blueswir1 | MISC_DPRINTF("Read modem control %2.2x\n", ret);
|
155 | f930d07e | blueswir1 | break;
|
156 | 3475187d | bellard | case 0xa000000: |
157 | f930d07e | blueswir1 | MISC_DPRINTF("Read power management %2.2x\n", ret);
|
158 | f930d07e | blueswir1 | break;
|
159 | 3475187d | bellard | } |
160 | 3475187d | bellard | return ret;
|
161 | 3475187d | bellard | } |
162 | 3475187d | bellard | |
163 | 3475187d | bellard | static CPUReadMemoryFunc *slavio_misc_mem_read[3] = { |
164 | 3475187d | bellard | slavio_misc_mem_readb, |
165 | 3475187d | bellard | slavio_misc_mem_readb, |
166 | 3475187d | bellard | slavio_misc_mem_readb, |
167 | 3475187d | bellard | }; |
168 | 3475187d | bellard | |
169 | 3475187d | bellard | static CPUWriteMemoryFunc *slavio_misc_mem_write[3] = { |
170 | 3475187d | bellard | slavio_misc_mem_writeb, |
171 | 3475187d | bellard | slavio_misc_mem_writeb, |
172 | 3475187d | bellard | slavio_misc_mem_writeb, |
173 | 3475187d | bellard | }; |
174 | 3475187d | bellard | |
175 | bfa30a38 | blueswir1 | static uint32_t slavio_sysctrl_mem_readl(void *opaque, target_phys_addr_t addr) |
176 | bfa30a38 | blueswir1 | { |
177 | bfa30a38 | blueswir1 | MiscState *s = opaque; |
178 | bfa30a38 | blueswir1 | uint32_t ret = 0, saddr;
|
179 | bfa30a38 | blueswir1 | |
180 | bfa30a38 | blueswir1 | saddr = addr & SYSCTRL_MAXADDR; |
181 | bfa30a38 | blueswir1 | switch (saddr) {
|
182 | bfa30a38 | blueswir1 | case 0: |
183 | bfa30a38 | blueswir1 | ret = s->sysctrl; |
184 | bfa30a38 | blueswir1 | break;
|
185 | bfa30a38 | blueswir1 | default:
|
186 | bfa30a38 | blueswir1 | break;
|
187 | bfa30a38 | blueswir1 | } |
188 | bfa30a38 | blueswir1 | MISC_DPRINTF("Read system control reg 0x" TARGET_FMT_plx " = %x\n", addr, |
189 | bfa30a38 | blueswir1 | ret); |
190 | bfa30a38 | blueswir1 | return ret;
|
191 | bfa30a38 | blueswir1 | } |
192 | bfa30a38 | blueswir1 | |
193 | bfa30a38 | blueswir1 | static void slavio_sysctrl_mem_writel(void *opaque, target_phys_addr_t addr, |
194 | bfa30a38 | blueswir1 | uint32_t val) |
195 | bfa30a38 | blueswir1 | { |
196 | bfa30a38 | blueswir1 | MiscState *s = opaque; |
197 | bfa30a38 | blueswir1 | uint32_t saddr; |
198 | bfa30a38 | blueswir1 | |
199 | bfa30a38 | blueswir1 | saddr = addr & SYSCTRL_MAXADDR; |
200 | bfa30a38 | blueswir1 | MISC_DPRINTF("Write system control reg 0x" TARGET_FMT_plx " = %x\n", addr, |
201 | bfa30a38 | blueswir1 | val); |
202 | bfa30a38 | blueswir1 | switch (saddr) {
|
203 | bfa30a38 | blueswir1 | case 0: |
204 | bfa30a38 | blueswir1 | if (val & 1) { |
205 | bfa30a38 | blueswir1 | s->sysctrl = 0x2;
|
206 | bfa30a38 | blueswir1 | qemu_system_reset_request(); |
207 | bfa30a38 | blueswir1 | } |
208 | bfa30a38 | blueswir1 | break;
|
209 | bfa30a38 | blueswir1 | default:
|
210 | bfa30a38 | blueswir1 | break;
|
211 | bfa30a38 | blueswir1 | } |
212 | bfa30a38 | blueswir1 | } |
213 | bfa30a38 | blueswir1 | |
214 | bfa30a38 | blueswir1 | static CPUReadMemoryFunc *slavio_sysctrl_mem_read[3] = { |
215 | bfa30a38 | blueswir1 | slavio_sysctrl_mem_readl, |
216 | bfa30a38 | blueswir1 | slavio_sysctrl_mem_readl, |
217 | bfa30a38 | blueswir1 | slavio_sysctrl_mem_readl, |
218 | bfa30a38 | blueswir1 | }; |
219 | bfa30a38 | blueswir1 | |
220 | bfa30a38 | blueswir1 | static CPUWriteMemoryFunc *slavio_sysctrl_mem_write[3] = { |
221 | bfa30a38 | blueswir1 | slavio_sysctrl_mem_writel, |
222 | bfa30a38 | blueswir1 | slavio_sysctrl_mem_writel, |
223 | bfa30a38 | blueswir1 | slavio_sysctrl_mem_writel, |
224 | bfa30a38 | blueswir1 | }; |
225 | bfa30a38 | blueswir1 | |
226 | 3475187d | bellard | static void slavio_misc_save(QEMUFile *f, void *opaque) |
227 | 3475187d | bellard | { |
228 | 3475187d | bellard | MiscState *s = opaque; |
229 | d537cf6c | pbrook | int tmp;
|
230 | bfa30a38 | blueswir1 | uint8_t tmp8; |
231 | 3475187d | bellard | |
232 | d537cf6c | pbrook | tmp = 0;
|
233 | d537cf6c | pbrook | qemu_put_be32s(f, &tmp); /* ignored, was IRQ. */
|
234 | 3475187d | bellard | qemu_put_8s(f, &s->config); |
235 | 3475187d | bellard | qemu_put_8s(f, &s->aux1); |
236 | 3475187d | bellard | qemu_put_8s(f, &s->aux2); |
237 | 3475187d | bellard | qemu_put_8s(f, &s->diag); |
238 | 3475187d | bellard | qemu_put_8s(f, &s->mctrl); |
239 | bfa30a38 | blueswir1 | tmp8 = s->sysctrl & 0xff;
|
240 | bfa30a38 | blueswir1 | qemu_put_8s(f, &tmp8); |
241 | 3475187d | bellard | } |
242 | 3475187d | bellard | |
243 | 3475187d | bellard | static int slavio_misc_load(QEMUFile *f, void *opaque, int version_id) |
244 | 3475187d | bellard | { |
245 | 3475187d | bellard | MiscState *s = opaque; |
246 | d537cf6c | pbrook | int tmp;
|
247 | bfa30a38 | blueswir1 | uint8_t tmp8; |
248 | 3475187d | bellard | |
249 | 3475187d | bellard | if (version_id != 1) |
250 | 3475187d | bellard | return -EINVAL;
|
251 | 3475187d | bellard | |
252 | d537cf6c | pbrook | qemu_get_be32s(f, &tmp); |
253 | 3475187d | bellard | qemu_get_8s(f, &s->config); |
254 | 3475187d | bellard | qemu_get_8s(f, &s->aux1); |
255 | 3475187d | bellard | qemu_get_8s(f, &s->aux2); |
256 | 3475187d | bellard | qemu_get_8s(f, &s->diag); |
257 | 3475187d | bellard | qemu_get_8s(f, &s->mctrl); |
258 | bfa30a38 | blueswir1 | qemu_get_8s(f, &tmp8); |
259 | bfa30a38 | blueswir1 | s->sysctrl = (uint32_t)tmp8; |
260 | 3475187d | bellard | return 0; |
261 | 3475187d | bellard | } |
262 | 3475187d | bellard | |
263 | 5dcb6b91 | blueswir1 | void *slavio_misc_init(target_phys_addr_t base, target_phys_addr_t power_base,
|
264 | 5dcb6b91 | blueswir1 | qemu_irq irq) |
265 | 3475187d | bellard | { |
266 | 3475187d | bellard | int slavio_misc_io_memory;
|
267 | 3475187d | bellard | MiscState *s; |
268 | 3475187d | bellard | |
269 | 3475187d | bellard | s = qemu_mallocz(sizeof(MiscState));
|
270 | 3475187d | bellard | if (!s)
|
271 | 3475187d | bellard | return NULL; |
272 | 3475187d | bellard | |
273 | bfa30a38 | blueswir1 | /* 8 bit registers */
|
274 | bfa30a38 | blueswir1 | slavio_misc_io_memory = cpu_register_io_memory(0, slavio_misc_mem_read,
|
275 | bfa30a38 | blueswir1 | slavio_misc_mem_write, s); |
276 | 3475187d | bellard | // Slavio control
|
277 | 5aca8c3b | blueswir1 | cpu_register_physical_memory(base + 0x1800000, MISC_SIZE,
|
278 | 5aca8c3b | blueswir1 | slavio_misc_io_memory); |
279 | 3475187d | bellard | // AUX 1
|
280 | 5aca8c3b | blueswir1 | cpu_register_physical_memory(base + 0x1900000, MISC_SIZE,
|
281 | 5aca8c3b | blueswir1 | slavio_misc_io_memory); |
282 | 3475187d | bellard | // AUX 2
|
283 | 5aca8c3b | blueswir1 | cpu_register_physical_memory(base + 0x1910000, MISC_SIZE,
|
284 | 5aca8c3b | blueswir1 | slavio_misc_io_memory); |
285 | 3475187d | bellard | // Diagnostics
|
286 | 5aca8c3b | blueswir1 | cpu_register_physical_memory(base + 0x1a00000, MISC_SIZE,
|
287 | 5aca8c3b | blueswir1 | slavio_misc_io_memory); |
288 | 3475187d | bellard | // Modem control
|
289 | 5aca8c3b | blueswir1 | cpu_register_physical_memory(base + 0x1b00000, MISC_SIZE,
|
290 | 5aca8c3b | blueswir1 | slavio_misc_io_memory); |
291 | 3475187d | bellard | // Power management
|
292 | 5aca8c3b | blueswir1 | cpu_register_physical_memory(power_base, MISC_SIZE, slavio_misc_io_memory); |
293 | 3475187d | bellard | |
294 | bfa30a38 | blueswir1 | /* 32 bit registers */
|
295 | bfa30a38 | blueswir1 | slavio_misc_io_memory = cpu_register_io_memory(0, slavio_sysctrl_mem_read,
|
296 | bfa30a38 | blueswir1 | slavio_sysctrl_mem_write, |
297 | bfa30a38 | blueswir1 | s); |
298 | bfa30a38 | blueswir1 | // System control
|
299 | bfa30a38 | blueswir1 | cpu_register_physical_memory(base + 0x1f00000, SYSCTRL_SIZE,
|
300 | bfa30a38 | blueswir1 | slavio_misc_io_memory); |
301 | bfa30a38 | blueswir1 | |
302 | 3475187d | bellard | s->irq = irq; |
303 | 3475187d | bellard | |
304 | bfa30a38 | blueswir1 | register_savevm("slavio_misc", base, 1, slavio_misc_save, slavio_misc_load, |
305 | bfa30a38 | blueswir1 | s); |
306 | 3475187d | bellard | qemu_register_reset(slavio_misc_reset, s); |
307 | 3475187d | bellard | slavio_misc_reset(s); |
308 | 3475187d | bellard | return s;
|
309 | 3475187d | bellard | } |