Revision ca87d03b hw/etraxfs_timer.c
| b/hw/etraxfs_timer.c | ||
|---|---|---|
| 28 | 28 |
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| 29 | 29 |
#define D(x) |
| 30 | 30 |
|
| 31 |
#define R_TIME 0xb001e038 |
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| 32 |
#define RW_TMR0_DIV 0xb001e000 |
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| 33 |
#define R_TMR0_DATA 0xb001e004 |
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#define RW_TMR0_CTRL 0xb001e008 |
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#define RW_TMR1_DIV 0xb001e010 |
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| 36 |
#define R_TMR1_DATA 0xb001e014 |
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#define RW_TMR1_CTRL 0xb001e018 |
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| 38 |
|
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#define RW_WD_CTRL 0xb001e040 |
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#define RW_INTR_MASK 0xb001e048 |
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#define RW_ACK_INTR 0xb001e04c |
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#define R_INTR 0xb001e050 |
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#define R_MASKED_INTR 0xb001e054 |
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#define RW_TMR0_DIV 0x00 |
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#define R_TMR0_DATA 0x04 |
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#define RW_TMR0_CTRL 0x08 |
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#define RW_TMR1_DIV 0x10 |
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#define R_TMR1_DATA 0x14 |
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#define RW_TMR1_CTRL 0x18 |
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#define R_TIME 0x38 |
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#define RW_WD_CTRL 0x40 |
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#define RW_INTR_MASK 0x48 |
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#define RW_ACK_INTR 0x4c |
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#define R_INTR 0x50 |
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#define R_MASKED_INTR 0x54 |
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| 44 | 43 |
|
| 45 | 44 |
struct fs_timer_t {
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CPUState *env; |
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qemu_irq *irq; |
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target_phys_addr_t base; |
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|
|
| 46 | 49 |
QEMUBH *bh; |
| 50 |
ptimer_state *ptimer; |
|
| 47 | 51 |
unsigned int limit; |
| 48 | 52 |
int scale; |
| 49 |
ptimer_state *ptimer; |
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CPUState *env; |
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qemu_irq *irq; |
|
| 52 | 53 |
uint32_t mask; |
| 53 | 54 |
struct timeval last; |
| 54 | 55 |
|
| ... | ... | |
| 57 | 58 |
uint32_t r_intr; |
| 58 | 59 |
}; |
| 59 | 60 |
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static struct fs_timer_t timer[2]; |
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|
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static inline int timer_index(target_phys_addr_t addr) |
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{
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int t = 0; |
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if (addr >= 0xb005e000) |
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t = 1; |
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return t; |
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} |
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|
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/* diff two timevals. Return a single int in us. */ |
| 71 | 62 |
int diff_timeval_us(struct timeval *a, struct timeval *b) |
| 72 | 63 |
{
|
| ... | ... | |
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return diff; |
| 79 | 70 |
} |
| 80 | 71 |
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static uint32_t timer_readb (void *opaque, target_phys_addr_t addr)
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static uint32_t timer_rinvalid (void *opaque, target_phys_addr_t addr)
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{
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CPUState *env; |
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uint32_t r = 0; |
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env = opaque; |
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D(printf ("%s %x pc=%x\n", __func__, addr, env->pc));
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return r; |
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} |
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static uint32_t timer_readw (void *opaque, target_phys_addr_t addr) |
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{
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CPUState *env; |
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uint32_t r = 0; |
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env = opaque; |
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D(printf ("%s %x pc=%x\n", __func__, addr, env->pc));
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return r; |
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struct fs_timer_t *t = opaque; |
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CPUState *env = t->env; |
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cpu_abort(env, "Unsupported short access. reg=%x pc=%x.\n", |
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addr, env->pc); |
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return 0; |
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} |
| 99 | 80 |
|
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static uint32_t timer_readl (void *opaque, target_phys_addr_t addr) |
| 101 | 82 |
{
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CPUState *env = opaque; |
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struct fs_timer_t *t = opaque; |
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D(CPUState *env = t->env); |
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uint32_t r = 0; |
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int t = timer_index(addr); |
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/* Make addr relative to this instances base. */ |
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addr -= t->base; |
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switch (addr) {
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| 107 | 90 |
case R_TMR0_DATA: |
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break; |
| ... | ... | |
| 113 | 96 |
{
|
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struct timeval now; |
| 115 | 98 |
gettimeofday(&now, NULL); |
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if (!(timer[t].last.tv_sec == 0
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&& timer[t].last.tv_usec == 0)) {
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r = diff_timeval_us(&now, &timer[t].last);
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if (!(t->last.tv_sec == 0
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&& t->last.tv_usec == 0)) {
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r = diff_timeval_us(&now, &t->last);
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r *= 1000; /* convert to ns. */ |
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r++; /* make sure we increase for each call. */ |
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} |
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timer[t].last = now;
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t->last = now;
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break; |
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} |
| 125 | 108 |
|
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case RW_INTR_MASK: |
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r = timer[t].rw_intr_mask;
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r = t->rw_intr_mask;
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break; |
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case R_MASKED_INTR: |
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r = timer[t].r_intr & timer[t].rw_intr_mask;
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r = t->r_intr & t->rw_intr_mask;
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break; |
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default: |
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D(printf ("%s %x p=%x\n", __func__, addr, env->pc));
|
| ... | ... | |
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} |
| 138 | 121 |
|
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static void |
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timer_writeb (void *opaque, target_phys_addr_t addr, uint32_t value)
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timer_winvalid (void *opaque, target_phys_addr_t addr, uint32_t value)
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{
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CPUState *env; |
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env = opaque; |
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D(printf ("%s %x %x pc=%x\n", __func__, addr, value, env->pc));
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} |
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static void |
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timer_writew (void *opaque, target_phys_addr_t addr, uint32_t value) |
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{
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CPUState *env; |
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env = opaque; |
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D(printf ("%s %x %x pc=%x\n", __func__, addr, value, env->pc));
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struct fs_timer_t *t = opaque; |
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CPUState *env = t->env; |
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cpu_abort(env, "Unsupported short access. reg=%x pc=%x.\n", |
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addr, env->pc); |
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} |
| 153 | 130 |
|
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static void write_ctrl(struct fs_timer_t *t, uint32_t v) |
| ... | ... | |
| 212 | 189 |
static void |
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timer_writel (void *opaque, target_phys_addr_t addr, uint32_t value) |
| 214 | 191 |
{
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CPUState *env = opaque;
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int t = timer_index(addr);
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struct fs_timer_t *t = opaque;
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CPUState *env = t->env;
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D(printf ("%s %x %x pc=%x\n",
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__func__, addr, value, env->pc)); |
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/* Make addr relative to this instances base. */ |
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addr -= t->base; |
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| 220 | 199 |
switch (addr) |
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{
|
| 222 | 201 |
case RW_TMR0_DIV: |
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D(printf ("RW_TMR0_DIV=%x\n", value));
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timer[t].limit = value;
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t->limit = value;
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break; |
| 226 | 205 |
case RW_TMR0_CTRL: |
| 227 | 206 |
D(printf ("RW_TMR0_CTRL=%x\n", value));
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write_ctrl(&timer[t], value);
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write_ctrl(t, value);
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break; |
| 230 | 209 |
case RW_TMR1_DIV: |
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D(printf ("RW_TMR1_DIV=%x\n", value));
|
| ... | ... | |
| 235 | 214 |
break; |
| 236 | 215 |
case RW_INTR_MASK: |
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D(printf ("RW_INTR_MASK=%x\n", value));
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timer[t].rw_intr_mask = value;
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t->rw_intr_mask = value;
|
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| 239 | 218 |
break; |
| 240 | 219 |
case RW_WD_CTRL: |
| 241 | 220 |
D(printf ("RW_WD_CTRL=%x\n", value));
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| 242 | 221 |
break; |
| 243 | 222 |
case RW_ACK_INTR: |
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timer[t].r_intr &= ~value;
|
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timer_ack_irq(&timer[t]);
|
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t->r_intr &= ~value;
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timer_ack_irq(t);
|
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| 246 | 225 |
break; |
| 247 | 226 |
default: |
| 248 | 227 |
printf ("%s %x %x pc=%x\n",
|
| ... | ... | |
| 252 | 231 |
} |
| 253 | 232 |
|
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static CPUReadMemoryFunc *timer_read[] = {
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&timer_readb,
|
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&timer_readw,
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&timer_rinvalid,
|
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&timer_rinvalid,
|
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| 257 | 236 |
&timer_readl, |
| 258 | 237 |
}; |
| 259 | 238 |
|
| 260 | 239 |
static CPUWriteMemoryFunc *timer_write[] = {
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&timer_writeb,
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&timer_writew,
|
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&timer_winvalid,
|
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&timer_winvalid,
|
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| 263 | 242 |
&timer_writel, |
| 264 | 243 |
}; |
| 265 | 244 |
|
| ... | ... | |
| 273 | 252 |
} |
| 274 | 253 |
} |
| 275 | 254 |
|
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void etraxfs_timer_init(CPUState *env, qemu_irq *irqs) |
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void etraxfs_timer_init(CPUState *env, qemu_irq *irqs, |
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target_phys_addr_t base) |
|
| 277 | 257 |
{
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static struct fs_timer_t *t; |
|
| 278 | 259 |
int timer_regs; |
| 279 | 260 |
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timer[0].bh = qemu_bh_new(timer_irq, &timer[0]); |
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timer[0].ptimer = ptimer_init(timer[0].bh); |
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timer[0].irq = irqs + 26; |
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timer[0].mask = 1; |
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timer[0].env = env; |
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t = qemu_mallocz(sizeof *t); |
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| 262 |
if (!t) |
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return; |
|
| 285 | 264 |
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timer[1].bh = qemu_bh_new(timer_irq, &timer[1]); |
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timer[1].ptimer = ptimer_init(timer[1].bh); |
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timer[1].irq = irqs + 26; |
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timer[1].mask = 1; |
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timer[1].env = env; |
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t->bh = qemu_bh_new(timer_irq, t); |
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t->ptimer = ptimer_init(t->bh); |
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t->irq = irqs + 26; |
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t->mask = 1; |
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t->env = env; |
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t->base = base; |
|
| 291 | 271 |
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timer_regs = cpu_register_io_memory(0, timer_read, timer_write, env); |
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cpu_register_physical_memory (0xb001e000, 0x5c, timer_regs); |
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cpu_register_physical_memory (0xb005e000, 0x5c, timer_regs); |
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timer_regs = cpu_register_io_memory(0, timer_read, timer_write, t); |
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cpu_register_physical_memory (base, 0x5c, timer_regs); |
|
| 295 | 274 |
} |
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