root / pc-bios / bios.diff @ caa88be0
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? _rombios_.c
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? _rombiosl_.c
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? biossums
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? rombios.s
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? rombios.sym
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? rombios.txt
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? rombios16.bin
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? rombios32.bin
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? rombios32.out
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? rombiosl.s
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? rombiosl.sym
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? rombiosl.txt
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Index: BIOS-bochs-latest
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===================================================================
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RCS file: /cvsroot/bochs/bochs/bios/BIOS-bochs-latest,v
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retrieving revision 1.173
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diff -u -d -p -r1.173 BIOS-bochs-latest
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Binary files /tmp/cvsItPJ31 and BIOS-bochs-latest differ
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Index: BIOS-bochs-legacy
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===================================================================
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RCS file: /cvsroot/bochs/bochs/bios/BIOS-bochs-legacy,v
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retrieving revision 1.33
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diff -u -d -p -r1.33 BIOS-bochs-legacy
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Binary files /tmp/cvsMYE2Kz and BIOS-bochs-legacy differ
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Index: rombios.c
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===================================================================
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RCS file: /cvsroot/bochs/bochs/bios/rombios.c,v
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retrieving revision 1.207
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diff -u -d -p -r1.207 rombios.c
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--- rombios.c 21 Apr 2008 14:22:01 -0000 1.207
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+++ rombios.c 28 Apr 2008 07:53:57 -0000
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@@ -4404,22 +4404,25 @@ BX_DEBUG_INT15("case default:\n"); |
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#endif // BX_USE_PS2_MOUSE |
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-void set_e820_range(ES, DI, start, end, type)
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+void set_e820_range(ES, DI, start, end, extra_start, extra_end, type)
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Bit16u ES; |
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Bit16u DI; |
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Bit32u start; |
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Bit32u end; |
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+ Bit8u extra_start;
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+ Bit8u extra_end;
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Bit16u type; |
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{
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write_word(ES, DI, start); |
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write_word(ES, DI+2, start >> 16); |
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- write_word(ES, DI+4, 0x00);
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+ write_word(ES, DI+4, extra_start);
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write_word(ES, DI+6, 0x00); |
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end -= start; |
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+ extra_end -= extra_start;
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write_word(ES, DI+8, end);
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write_word(ES, DI+10, end >> 16); |
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- write_word(ES, DI+12, 0x0000);
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+ write_word(ES, DI+12, extra_end);
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write_word(ES, DI+14, 0x0000); |
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write_word(ES, DI+16, type);
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@@ -4432,7 +4435,9 @@ int15_function32(regs, ES, DS, FLAGS)
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Bit16u ES, DS, FLAGS; |
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{
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Bit32u extended_memory_size=0; // 64bits long |
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+ Bit32u extra_lowbits_memory_size=0;
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Bit16u CX,DX; |
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+ Bit8u extra_highbits_memory_size=0;
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BX_DEBUG_INT15("int15 AX=%04x\n",regs.u.r16.ax);
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@@ -4506,11 +4511,18 @@ ASM_END
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extended_memory_size += (1L * 1024 * 1024); |
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} |
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+ extra_lowbits_memory_size = inb_cmos(0x5c);
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+ extra_lowbits_memory_size <<= 8;
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+ extra_lowbits_memory_size |= inb_cmos(0x5b);
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+ extra_lowbits_memory_size *= 64;
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+ extra_lowbits_memory_size *= 1024;
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+ extra_highbits_memory_size = inb_cmos(0x5d);
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+
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switch(regs.u.r16.bx)
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{
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case 0: |
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set_e820_range(ES, regs.u.r16.di, |
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- 0x0000000L, 0x0009fc00L, 1);
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+ 0x0000000L, 0x0009fc00L, 0, 0, 1);
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regs.u.r32.ebx = 1;
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regs.u.r32.eax = 0x534D4150;
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regs.u.r32.ecx = 0x14;
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@@ -4519,7 +4531,7 @@ ASM_END
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break;
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case 1: |
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set_e820_range(ES, regs.u.r16.di, |
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- 0x0009fc00L, 0x000a0000L, 2);
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+ 0x0009fc00L, 0x000a0000L, 0, 0, 2);
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regs.u.r32.ebx = 2;
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regs.u.r32.eax = 0x534D4150;
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regs.u.r32.ecx = 0x14;
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@@ -4528,7 +4540,7 @@ ASM_END
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break;
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case 2: |
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set_e820_range(ES, regs.u.r16.di, |
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- 0x000e8000L, 0x00100000L, 2);
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+ 0x000e8000L, 0x00100000L, 0, 0, 2);
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regs.u.r32.ebx = 3;
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regs.u.r32.eax = 0x534D4150;
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regs.u.r32.ecx = 0x14;
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@@ -4539,7 +4551,7 @@ ASM_END
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#if BX_ROMBIOS32
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set_e820_range(ES, regs.u.r16.di, |
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0x00100000L,
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- extended_memory_size - ACPI_DATA_SIZE, 1);
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+ extended_memory_size - ACPI_DATA_SIZE ,0, 0, 1);
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regs.u.r32.ebx = 4;
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#else
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set_e820_range(ES, regs.u.r16.di, |
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@@ -4555,7 +4567,7 @@ ASM_END
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case 4: |
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set_e820_range(ES, regs.u.r16.di, |
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extended_memory_size - ACPI_DATA_SIZE, |
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- extended_memory_size, 3); // ACPI RAM
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+ extended_memory_size ,0, 0, 3); // ACPI RAM
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regs.u.r32.ebx = 5;
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regs.u.r32.eax = 0x534D4150;
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regs.u.r32.ecx = 0x14;
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@@ -4565,7 +4577,20 @@ ASM_END
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case 5: |
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/* 256KB BIOS area at the end of 4 GB */
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set_e820_range(ES, regs.u.r16.di, |
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- 0xfffc0000L, 0x00000000L, 2);
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+ 0xfffc0000L, 0x00000000L ,0, 0, 2);
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+ if (extra_highbits_memory_size || extra_lowbits_memory_size)
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+ regs.u.r32.ebx = 6;
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+ else
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+ regs.u.r32.ebx = 0;
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+ regs.u.r32.eax = 0x534D4150;
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+ regs.u.r32.ecx = 0x14;
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+ CLEAR_CF();
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+ return;
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+ case 6:
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+ /* Maping of memory above 4 GB */
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+ set_e820_range(ES, regs.u.r16.di, 0x00000000L,
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+ extra_lowbits_memory_size, 1, extra_highbits_memory_size
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+ + 1, 1);
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regs.u.r32.ebx = 0;
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regs.u.r32.eax = 0x534D4150;
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regs.u.r32.ecx = 0x14;
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Index: rombios.h
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===================================================================
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RCS file: /cvsroot/bochs/bochs/bios/rombios.h,v
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retrieving revision 1.6
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diff -u -d -p -r1.6 rombios.h
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--- rombios.h 26 Jan 2008 09:15:27 -0000 1.6
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+++ rombios.h 28 Apr 2008 07:53:57 -0000
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@@ -19,7 +19,7 @@
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// Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA
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/* define it to include QEMU specific code */
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-//#define BX_QEMU
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+#define BX_QEMU
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#ifndef LEGACY
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# define BX_ROMBIOS32 1 |
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Index: rombios32.c
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===================================================================
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RCS file: /cvsroot/bochs/bochs/bios/rombios32.c,v
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retrieving revision 1.26
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diff -u -d -p -r1.26 rombios32.c
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--- rombios32.c 8 Apr 2008 16:41:18 -0000 1.26
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+++ rombios32.c 28 Apr 2008 07:53:58 -0000
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@@ -478,7 +478,12 @@ void smp_probe(void) |
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sipi_vector = AP_BOOT_ADDR >> 12;
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writel(APIC_BASE + APIC_ICR_LOW, 0x000C4600 | sipi_vector);
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+#ifndef BX_QEMU
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delay_ms(10);
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+#else
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+ while (cmos_readb(0x5f) + 1 != readw((void *)CPU_COUNT_ADDR))
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+ ;
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+#endif
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smp_cpus = readw((void *)CPU_COUNT_ADDR);
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} |
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@@ -1423,9 +1428,8 @@ void acpi_bios_init(void) |
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fadt->pm1_evt_len = 4;
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fadt->pm1_cnt_len = 2;
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fadt->pm_tmr_len = 4;
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- fadt->plvl2_lat = cpu_to_le16(50);
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- fadt->plvl3_lat = cpu_to_le16(50);
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- fadt->plvl3_lat = cpu_to_le16(50);
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+ fadt->plvl2_lat = cpu_to_le16(0x0fff); // C2 state not supported
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+ fadt->plvl3_lat = cpu_to_le16(0x0fff); // C3 state not supported
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/* WBINVD + PROC_C1 + PWR_BUTTON + SLP_BUTTON + FIX_RTC */
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fadt->flags = cpu_to_le32((1 << 0) | (1 << 2) | (1 << 4) | (1 << 5) | (1 << 6)); |
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acpi_build_table_header((struct acpi_table_header *)fadt, "FACP", |