root / exec-i386.c @ cabb4d61
History | View | Annotate | Download (14.1 kB)
1 | 7d13299d | bellard | /*
|
---|---|---|---|
2 | 7d13299d | bellard | * i386 emulator main execution loop
|
3 | 7d13299d | bellard | *
|
4 | 7d13299d | bellard | * Copyright (c) 2003 Fabrice Bellard
|
5 | 7d13299d | bellard | *
|
6 | 3ef693a0 | bellard | * This library is free software; you can redistribute it and/or
|
7 | 3ef693a0 | bellard | * modify it under the terms of the GNU Lesser General Public
|
8 | 3ef693a0 | bellard | * License as published by the Free Software Foundation; either
|
9 | 3ef693a0 | bellard | * version 2 of the License, or (at your option) any later version.
|
10 | 7d13299d | bellard | *
|
11 | 3ef693a0 | bellard | * This library is distributed in the hope that it will be useful,
|
12 | 3ef693a0 | bellard | * but WITHOUT ANY WARRANTY; without even the implied warranty of
|
13 | 3ef693a0 | bellard | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
|
14 | 3ef693a0 | bellard | * Lesser General Public License for more details.
|
15 | 7d13299d | bellard | *
|
16 | 3ef693a0 | bellard | * You should have received a copy of the GNU Lesser General Public
|
17 | 3ef693a0 | bellard | * License along with this library; if not, write to the Free Software
|
18 | 3ef693a0 | bellard | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
|
19 | 7d13299d | bellard | */
|
20 | 7d13299d | bellard | #include "exec-i386.h" |
21 | 956034d7 | bellard | #include "disas.h" |
22 | 7d13299d | bellard | |
23 | dc99065b | bellard | //#define DEBUG_EXEC
|
24 | 7d13299d | bellard | #define DEBUG_FLUSH
|
25 | 9de5e440 | bellard | //#define DEBUG_SIGNAL
|
26 | 7d13299d | bellard | |
27 | 7d13299d | bellard | /* main execution loop */
|
28 | 7d13299d | bellard | |
29 | 7d13299d | bellard | /* maximum total translate dcode allocated */
|
30 | 7d13299d | bellard | #define CODE_GEN_BUFFER_SIZE (2048 * 1024) |
31 | 7d13299d | bellard | //#define CODE_GEN_BUFFER_SIZE (128 * 1024)
|
32 | 7d13299d | bellard | #define CODE_GEN_MAX_SIZE 65536 |
33 | 7d13299d | bellard | #define CODE_GEN_ALIGN 16 /* must be >= of the size of a icache line */ |
34 | 7d13299d | bellard | |
35 | 7d13299d | bellard | /* threshold to flush the translated code buffer */
|
36 | 7d13299d | bellard | #define CODE_GEN_BUFFER_MAX_SIZE (CODE_GEN_BUFFER_SIZE - CODE_GEN_MAX_SIZE)
|
37 | 7d13299d | bellard | |
38 | 7d13299d | bellard | #define CODE_GEN_MAX_BLOCKS (CODE_GEN_BUFFER_SIZE / 64) |
39 | 7d13299d | bellard | #define CODE_GEN_HASH_BITS 15 |
40 | 7d13299d | bellard | #define CODE_GEN_HASH_SIZE (1 << CODE_GEN_HASH_BITS) |
41 | 6dbad63e | bellard | |
42 | 7d13299d | bellard | typedef struct TranslationBlock { |
43 | dab2ed99 | bellard | unsigned long pc; /* simulated PC corresponding to this block (EIP + CS base) */ |
44 | dab2ed99 | bellard | unsigned long cs_base; /* CS base for this block */ |
45 | 6dbad63e | bellard | unsigned int flags; /* flags defining in which context the code was generated */ |
46 | 7d13299d | bellard | uint8_t *tc_ptr; /* pointer to the translated code */
|
47 | 7d13299d | bellard | struct TranslationBlock *hash_next; /* next matching block */ |
48 | 7d13299d | bellard | } TranslationBlock; |
49 | 7d13299d | bellard | |
50 | 7d13299d | bellard | TranslationBlock tbs[CODE_GEN_MAX_BLOCKS]; |
51 | 7d13299d | bellard | TranslationBlock *tb_hash[CODE_GEN_HASH_SIZE]; |
52 | 7d13299d | bellard | int nb_tbs;
|
53 | 7d13299d | bellard | |
54 | 7d13299d | bellard | uint8_t code_gen_buffer[CODE_GEN_BUFFER_SIZE]; |
55 | 7d13299d | bellard | uint8_t *code_gen_ptr; |
56 | 7d13299d | bellard | |
57 | 1b6b029e | bellard | /* thread support */
|
58 | 1b6b029e | bellard | |
59 | 1b6b029e | bellard | #ifdef __powerpc__
|
60 | 1b6b029e | bellard | static inline int testandset (int *p) |
61 | 1b6b029e | bellard | { |
62 | 1b6b029e | bellard | int ret;
|
63 | 1b6b029e | bellard | __asm__ __volatile__ ( |
64 | 1b6b029e | bellard | "0: lwarx %0,0,%1 ;"
|
65 | 1b6b029e | bellard | " xor. %0,%3,%0;"
|
66 | 1b6b029e | bellard | " bne 1f;"
|
67 | 1b6b029e | bellard | " stwcx. %2,0,%1;"
|
68 | 1b6b029e | bellard | " bne- 0b;"
|
69 | 1b6b029e | bellard | "1: "
|
70 | 1b6b029e | bellard | : "=&r" (ret)
|
71 | 1b6b029e | bellard | : "r" (p), "r" (1), "r" (0) |
72 | 1b6b029e | bellard | : "cr0", "memory"); |
73 | 1b6b029e | bellard | return ret;
|
74 | 1b6b029e | bellard | } |
75 | 1b6b029e | bellard | #endif
|
76 | 1b6b029e | bellard | |
77 | 1b6b029e | bellard | #ifdef __i386__
|
78 | 1b6b029e | bellard | static inline int testandset (int *p) |
79 | 1b6b029e | bellard | { |
80 | 1b6b029e | bellard | char ret;
|
81 | 1b6b029e | bellard | long int readval; |
82 | 1b6b029e | bellard | |
83 | 1b6b029e | bellard | __asm__ __volatile__ ("lock; cmpxchgl %3, %1; sete %0"
|
84 | 1b6b029e | bellard | : "=q" (ret), "=m" (*p), "=a" (readval) |
85 | 1b6b029e | bellard | : "r" (1), "m" (*p), "a" (0) |
86 | 1b6b029e | bellard | : "memory");
|
87 | 1b6b029e | bellard | return ret;
|
88 | 1b6b029e | bellard | } |
89 | 1b6b029e | bellard | #endif
|
90 | 1b6b029e | bellard | |
91 | fb3e5849 | bellard | #ifdef __s390__
|
92 | fb3e5849 | bellard | static inline int testandset (int *p) |
93 | fb3e5849 | bellard | { |
94 | fb3e5849 | bellard | int ret;
|
95 | fb3e5849 | bellard | |
96 | fb3e5849 | bellard | __asm__ __volatile__ ("0: cs %0,%1,0(%2)\n"
|
97 | fb3e5849 | bellard | " jl 0b"
|
98 | fb3e5849 | bellard | : "=&d" (ret)
|
99 | fb3e5849 | bellard | : "r" (1), "a" (p), "0" (*p) |
100 | fb3e5849 | bellard | : "cc", "memory" ); |
101 | fb3e5849 | bellard | return ret;
|
102 | fb3e5849 | bellard | } |
103 | fb3e5849 | bellard | #endif
|
104 | fb3e5849 | bellard | |
105 | e026db58 | bellard | #ifdef __alpha__
|
106 | e026db58 | bellard | int testandset (int *p) |
107 | e026db58 | bellard | { |
108 | e026db58 | bellard | int ret;
|
109 | e026db58 | bellard | unsigned long one; |
110 | e026db58 | bellard | |
111 | e026db58 | bellard | __asm__ __volatile__ ("0: mov 1,%2\n"
|
112 | e026db58 | bellard | " ldl_l %0,%1\n"
|
113 | e026db58 | bellard | " stl_c %2,%1\n"
|
114 | e026db58 | bellard | " beq %2,1f\n"
|
115 | e026db58 | bellard | ".subsection 2\n"
|
116 | e026db58 | bellard | "1: br 0b\n"
|
117 | e026db58 | bellard | ".previous"
|
118 | e026db58 | bellard | : "=r" (ret), "=m" (*p), "=r" (one) |
119 | e026db58 | bellard | : "m" (*p));
|
120 | e026db58 | bellard | return ret;
|
121 | e026db58 | bellard | } |
122 | e026db58 | bellard | #endif
|
123 | e026db58 | bellard | |
124 | d014c98c | bellard | #ifdef __sparc__
|
125 | d014c98c | bellard | static inline int testandset (int *p) |
126 | d014c98c | bellard | { |
127 | d014c98c | bellard | int ret;
|
128 | d014c98c | bellard | |
129 | d014c98c | bellard | __asm__ __volatile__("ldstub [%1], %0"
|
130 | d014c98c | bellard | : "=r" (ret)
|
131 | d014c98c | bellard | : "r" (p)
|
132 | d014c98c | bellard | : "memory");
|
133 | d014c98c | bellard | |
134 | d014c98c | bellard | return (ret ? 1 : 0); |
135 | d014c98c | bellard | } |
136 | d014c98c | bellard | #endif
|
137 | d014c98c | bellard | |
138 | 1b6b029e | bellard | int global_cpu_lock = 0; |
139 | 1b6b029e | bellard | |
140 | 1b6b029e | bellard | void cpu_lock(void) |
141 | 1b6b029e | bellard | { |
142 | 1b6b029e | bellard | while (testandset(&global_cpu_lock));
|
143 | 1b6b029e | bellard | } |
144 | 1b6b029e | bellard | |
145 | 1b6b029e | bellard | void cpu_unlock(void) |
146 | 1b6b029e | bellard | { |
147 | 1b6b029e | bellard | global_cpu_lock = 0;
|
148 | 1b6b029e | bellard | } |
149 | 1b6b029e | bellard | |
150 | 9de5e440 | bellard | /* exception support */
|
151 | 9de5e440 | bellard | /* NOTE: not static to force relocation generation by GCC */
|
152 | b56dad1c | bellard | void raise_exception_err(int exception_index, int error_code) |
153 | 9de5e440 | bellard | { |
154 | 9de5e440 | bellard | /* NOTE: the register at this point must be saved by hand because
|
155 | 9de5e440 | bellard | longjmp restore them */
|
156 | 9de5e440 | bellard | #ifdef reg_EAX
|
157 | 9de5e440 | bellard | env->regs[R_EAX] = EAX; |
158 | 9de5e440 | bellard | #endif
|
159 | 9de5e440 | bellard | #ifdef reg_ECX
|
160 | 9de5e440 | bellard | env->regs[R_ECX] = ECX; |
161 | 9de5e440 | bellard | #endif
|
162 | 9de5e440 | bellard | #ifdef reg_EDX
|
163 | 9de5e440 | bellard | env->regs[R_EDX] = EDX; |
164 | 9de5e440 | bellard | #endif
|
165 | 9de5e440 | bellard | #ifdef reg_EBX
|
166 | 9de5e440 | bellard | env->regs[R_EBX] = EBX; |
167 | 9de5e440 | bellard | #endif
|
168 | 9de5e440 | bellard | #ifdef reg_ESP
|
169 | 9de5e440 | bellard | env->regs[R_ESP] = ESP; |
170 | 9de5e440 | bellard | #endif
|
171 | 9de5e440 | bellard | #ifdef reg_EBP
|
172 | 9de5e440 | bellard | env->regs[R_EBP] = EBP; |
173 | 9de5e440 | bellard | #endif
|
174 | 9de5e440 | bellard | #ifdef reg_ESI
|
175 | 9de5e440 | bellard | env->regs[R_ESI] = ESI; |
176 | 9de5e440 | bellard | #endif
|
177 | 9de5e440 | bellard | #ifdef reg_EDI
|
178 | 9de5e440 | bellard | env->regs[R_EDI] = EDI; |
179 | 9de5e440 | bellard | #endif
|
180 | 9de5e440 | bellard | env->exception_index = exception_index; |
181 | b56dad1c | bellard | env->error_code = error_code; |
182 | 9de5e440 | bellard | longjmp(env->jmp_env, 1);
|
183 | 9de5e440 | bellard | } |
184 | 9de5e440 | bellard | |
185 | b56dad1c | bellard | /* short cut if error_code is 0 or not present */
|
186 | b56dad1c | bellard | void raise_exception(int exception_index) |
187 | b56dad1c | bellard | { |
188 | b56dad1c | bellard | raise_exception_err(exception_index, 0);
|
189 | b56dad1c | bellard | } |
190 | b56dad1c | bellard | |
191 | 7d13299d | bellard | void cpu_x86_tblocks_init(void) |
192 | 7d13299d | bellard | { |
193 | 7d13299d | bellard | if (!code_gen_ptr) {
|
194 | 7d13299d | bellard | code_gen_ptr = code_gen_buffer; |
195 | 7d13299d | bellard | } |
196 | 7d13299d | bellard | } |
197 | 7d13299d | bellard | |
198 | 7d13299d | bellard | /* flush all the translation blocks */
|
199 | 7d13299d | bellard | static void tb_flush(void) |
200 | 7d13299d | bellard | { |
201 | 7d13299d | bellard | int i;
|
202 | 7d13299d | bellard | #ifdef DEBUG_FLUSH
|
203 | 7d13299d | bellard | printf("gemu: flush code_size=%d nb_tbs=%d avg_tb_size=%d\n",
|
204 | 7d13299d | bellard | code_gen_ptr - code_gen_buffer, |
205 | 7d13299d | bellard | nb_tbs, |
206 | 7d13299d | bellard | (code_gen_ptr - code_gen_buffer) / nb_tbs); |
207 | 7d13299d | bellard | #endif
|
208 | 7d13299d | bellard | nb_tbs = 0;
|
209 | 7d13299d | bellard | for(i = 0;i < CODE_GEN_HASH_SIZE; i++) |
210 | 7d13299d | bellard | tb_hash[i] = NULL;
|
211 | 7d13299d | bellard | code_gen_ptr = code_gen_buffer; |
212 | 7d13299d | bellard | /* XXX: flush processor icache at this point */
|
213 | 7d13299d | bellard | } |
214 | 7d13299d | bellard | |
215 | 7d13299d | bellard | /* find a translation block in the translation cache. If not found,
|
216 | 9de5e440 | bellard | return NULL and the pointer to the last element of the list in pptb */
|
217 | 9de5e440 | bellard | static inline TranslationBlock *tb_find(TranslationBlock ***pptb, |
218 | 9de5e440 | bellard | unsigned long pc, |
219 | 9de5e440 | bellard | unsigned long cs_base, |
220 | 9de5e440 | bellard | unsigned int flags) |
221 | 7d13299d | bellard | { |
222 | 7d13299d | bellard | TranslationBlock **ptb, *tb; |
223 | 7d13299d | bellard | unsigned int h; |
224 | 7d13299d | bellard | |
225 | 7d13299d | bellard | h = pc & (CODE_GEN_HASH_SIZE - 1);
|
226 | 7d13299d | bellard | ptb = &tb_hash[h]; |
227 | b56dad1c | bellard | #if 0
|
228 | b56dad1c | bellard | /* XXX: hack to handle 16 bit modyfing code */
|
229 | b56dad1c | bellard | if (flags & (1 << GEN_FLAG_CODE32_SHIFT))
|
230 | b56dad1c | bellard | #endif
|
231 | b56dad1c | bellard | for(;;) {
|
232 | b56dad1c | bellard | tb = *ptb; |
233 | b56dad1c | bellard | if (!tb)
|
234 | b56dad1c | bellard | break;
|
235 | b56dad1c | bellard | if (tb->pc == pc && tb->cs_base == cs_base && tb->flags == flags)
|
236 | 7d13299d | bellard | return tb;
|
237 | b56dad1c | bellard | ptb = &tb->hash_next; |
238 | b56dad1c | bellard | } |
239 | 9de5e440 | bellard | *pptb = ptb; |
240 | 9de5e440 | bellard | return NULL; |
241 | 9de5e440 | bellard | } |
242 | 9de5e440 | bellard | |
243 | 9de5e440 | bellard | /* allocate a new translation block. flush the translation buffer if
|
244 | 9de5e440 | bellard | too many translation blocks or too much generated code */
|
245 | 9de5e440 | bellard | static inline TranslationBlock *tb_alloc(void) |
246 | 9de5e440 | bellard | { |
247 | 9de5e440 | bellard | TranslationBlock *tb; |
248 | 7d13299d | bellard | if (nb_tbs >= CODE_GEN_MAX_BLOCKS ||
|
249 | 7d13299d | bellard | (code_gen_ptr - code_gen_buffer) >= CODE_GEN_BUFFER_MAX_SIZE) |
250 | 7d13299d | bellard | tb_flush(); |
251 | 7d13299d | bellard | tb = &tbs[nb_tbs++]; |
252 | 7d13299d | bellard | return tb;
|
253 | 7d13299d | bellard | } |
254 | 7d13299d | bellard | |
255 | 7d13299d | bellard | int cpu_x86_exec(CPUX86State *env1)
|
256 | 7d13299d | bellard | { |
257 | 7d13299d | bellard | int saved_T0, saved_T1, saved_A0;
|
258 | 7d13299d | bellard | CPUX86State *saved_env; |
259 | 04369ff2 | bellard | #ifdef reg_EAX
|
260 | 04369ff2 | bellard | int saved_EAX;
|
261 | 04369ff2 | bellard | #endif
|
262 | 04369ff2 | bellard | #ifdef reg_ECX
|
263 | 04369ff2 | bellard | int saved_ECX;
|
264 | 04369ff2 | bellard | #endif
|
265 | 04369ff2 | bellard | #ifdef reg_EDX
|
266 | 04369ff2 | bellard | int saved_EDX;
|
267 | 04369ff2 | bellard | #endif
|
268 | 04369ff2 | bellard | #ifdef reg_EBX
|
269 | 04369ff2 | bellard | int saved_EBX;
|
270 | 04369ff2 | bellard | #endif
|
271 | 04369ff2 | bellard | #ifdef reg_ESP
|
272 | 04369ff2 | bellard | int saved_ESP;
|
273 | 04369ff2 | bellard | #endif
|
274 | 04369ff2 | bellard | #ifdef reg_EBP
|
275 | 04369ff2 | bellard | int saved_EBP;
|
276 | 04369ff2 | bellard | #endif
|
277 | 04369ff2 | bellard | #ifdef reg_ESI
|
278 | 04369ff2 | bellard | int saved_ESI;
|
279 | 04369ff2 | bellard | #endif
|
280 | 04369ff2 | bellard | #ifdef reg_EDI
|
281 | 04369ff2 | bellard | int saved_EDI;
|
282 | 04369ff2 | bellard | #endif
|
283 | 7d13299d | bellard | int code_gen_size, ret;
|
284 | 7d13299d | bellard | void (*gen_func)(void); |
285 | 9de5e440 | bellard | TranslationBlock *tb, **ptb; |
286 | dab2ed99 | bellard | uint8_t *tc_ptr, *cs_base, *pc; |
287 | 6dbad63e | bellard | unsigned int flags; |
288 | 6dbad63e | bellard | |
289 | 7d13299d | bellard | /* first we save global registers */
|
290 | 7d13299d | bellard | saved_T0 = T0; |
291 | 7d13299d | bellard | saved_T1 = T1; |
292 | 7d13299d | bellard | saved_A0 = A0; |
293 | 7d13299d | bellard | saved_env = env; |
294 | 7d13299d | bellard | env = env1; |
295 | 04369ff2 | bellard | #ifdef reg_EAX
|
296 | 04369ff2 | bellard | saved_EAX = EAX; |
297 | 04369ff2 | bellard | EAX = env->regs[R_EAX]; |
298 | 04369ff2 | bellard | #endif
|
299 | 04369ff2 | bellard | #ifdef reg_ECX
|
300 | 04369ff2 | bellard | saved_ECX = ECX; |
301 | 04369ff2 | bellard | ECX = env->regs[R_ECX]; |
302 | 04369ff2 | bellard | #endif
|
303 | 04369ff2 | bellard | #ifdef reg_EDX
|
304 | 04369ff2 | bellard | saved_EDX = EDX; |
305 | 04369ff2 | bellard | EDX = env->regs[R_EDX]; |
306 | 04369ff2 | bellard | #endif
|
307 | 04369ff2 | bellard | #ifdef reg_EBX
|
308 | 04369ff2 | bellard | saved_EBX = EBX; |
309 | 04369ff2 | bellard | EBX = env->regs[R_EBX]; |
310 | 04369ff2 | bellard | #endif
|
311 | 04369ff2 | bellard | #ifdef reg_ESP
|
312 | 04369ff2 | bellard | saved_ESP = ESP; |
313 | 04369ff2 | bellard | ESP = env->regs[R_ESP]; |
314 | 04369ff2 | bellard | #endif
|
315 | 04369ff2 | bellard | #ifdef reg_EBP
|
316 | 04369ff2 | bellard | saved_EBP = EBP; |
317 | 04369ff2 | bellard | EBP = env->regs[R_EBP]; |
318 | 04369ff2 | bellard | #endif
|
319 | 04369ff2 | bellard | #ifdef reg_ESI
|
320 | 04369ff2 | bellard | saved_ESI = ESI; |
321 | 04369ff2 | bellard | ESI = env->regs[R_ESI]; |
322 | 04369ff2 | bellard | #endif
|
323 | 04369ff2 | bellard | #ifdef reg_EDI
|
324 | 04369ff2 | bellard | saved_EDI = EDI; |
325 | 04369ff2 | bellard | EDI = env->regs[R_EDI]; |
326 | 04369ff2 | bellard | #endif
|
327 | 7d13299d | bellard | |
328 | 9de5e440 | bellard | /* put eflags in CPU temporary format */
|
329 | fc2b4c48 | bellard | CC_SRC = env->eflags & (CC_O | CC_S | CC_Z | CC_A | CC_P | CC_C); |
330 | fc2b4c48 | bellard | DF = 1 - (2 * ((env->eflags >> 10) & 1)); |
331 | 9de5e440 | bellard | CC_OP = CC_OP_EFLAGS; |
332 | fc2b4c48 | bellard | env->eflags &= ~(DF_MASK | CC_O | CC_S | CC_Z | CC_A | CC_P | CC_C); |
333 | 9de5e440 | bellard | env->interrupt_request = 0;
|
334 | 9d27abd9 | bellard | |
335 | 7d13299d | bellard | /* prepare setjmp context for exception handling */
|
336 | 7d13299d | bellard | if (setjmp(env->jmp_env) == 0) { |
337 | 7d13299d | bellard | for(;;) {
|
338 | 9de5e440 | bellard | if (env->interrupt_request) {
|
339 | 9de5e440 | bellard | raise_exception(EXCP_INTERRUPT); |
340 | 9de5e440 | bellard | } |
341 | 7d13299d | bellard | #ifdef DEBUG_EXEC
|
342 | 7d13299d | bellard | if (loglevel) {
|
343 | 9d27abd9 | bellard | /* XXX: save all volatile state in cpu state */
|
344 | 9d27abd9 | bellard | /* restore flags in standard format */
|
345 | 9d27abd9 | bellard | env->regs[R_EAX] = EAX; |
346 | 9d27abd9 | bellard | env->regs[R_EBX] = EBX; |
347 | 9d27abd9 | bellard | env->regs[R_ECX] = ECX; |
348 | 9d27abd9 | bellard | env->regs[R_EDX] = EDX; |
349 | 9d27abd9 | bellard | env->regs[R_ESI] = ESI; |
350 | 9d27abd9 | bellard | env->regs[R_EDI] = EDI; |
351 | 9d27abd9 | bellard | env->regs[R_EBP] = EBP; |
352 | 9d27abd9 | bellard | env->regs[R_ESP] = ESP; |
353 | 9d27abd9 | bellard | env->eflags = env->eflags | cc_table[CC_OP].compute_all() | (DF & DF_MASK); |
354 | 9d27abd9 | bellard | cpu_x86_dump_state(env, logfile, 0);
|
355 | 9d27abd9 | bellard | env->eflags &= ~(DF_MASK | CC_O | CC_S | CC_Z | CC_A | CC_P | CC_C); |
356 | 7d13299d | bellard | } |
357 | 7d13299d | bellard | #endif
|
358 | 6dbad63e | bellard | /* we compute the CPU state. We assume it will not
|
359 | 6dbad63e | bellard | change during the whole generated block. */
|
360 | 6dbad63e | bellard | flags = env->seg_cache[R_CS].seg_32bit << GEN_FLAG_CODE32_SHIFT; |
361 | dab2ed99 | bellard | flags |= env->seg_cache[R_SS].seg_32bit << GEN_FLAG_SS32_SHIFT; |
362 | 6dbad63e | bellard | flags |= (((unsigned long)env->seg_cache[R_DS].base | |
363 | 6dbad63e | bellard | (unsigned long)env->seg_cache[R_ES].base | |
364 | 6dbad63e | bellard | (unsigned long)env->seg_cache[R_SS].base) != 0) << |
365 | 6dbad63e | bellard | GEN_FLAG_ADDSEG_SHIFT; |
366 | 9d27abd9 | bellard | if (!(env->eflags & VM_MASK)) {
|
367 | 9d27abd9 | bellard | flags |= (env->segs[R_CS] & 3) << GEN_FLAG_CPL_SHIFT;
|
368 | 9d27abd9 | bellard | } else {
|
369 | 9d27abd9 | bellard | /* NOTE: a dummy CPL is kept */
|
370 | 9d27abd9 | bellard | flags |= (1 << GEN_FLAG_VM_SHIFT);
|
371 | 9d27abd9 | bellard | flags |= (3 << GEN_FLAG_CPL_SHIFT);
|
372 | 9d27abd9 | bellard | } |
373 | b56dad1c | bellard | flags |= (env->eflags & IOPL_MASK) >> (12 - GEN_FLAG_IOPL_SHIFT);
|
374 | cabb4d61 | bellard | flags |= (env->eflags & TF_MASK) << (GEN_FLAG_TF_SHIFT - 8);
|
375 | dab2ed99 | bellard | cs_base = env->seg_cache[R_CS].base; |
376 | dab2ed99 | bellard | pc = cs_base + env->eip; |
377 | 9de5e440 | bellard | tb = tb_find(&ptb, (unsigned long)pc, (unsigned long)cs_base, |
378 | 9de5e440 | bellard | flags); |
379 | 9de5e440 | bellard | if (!tb) {
|
380 | 7d13299d | bellard | /* if no translated code available, then translate it now */
|
381 | 1b6b029e | bellard | /* XXX: very inefficient: we lock all the cpus when
|
382 | 1b6b029e | bellard | generating code */
|
383 | 1b6b029e | bellard | cpu_lock(); |
384 | 7d13299d | bellard | tc_ptr = code_gen_ptr; |
385 | 9de5e440 | bellard | ret = cpu_x86_gen_code(code_gen_ptr, CODE_GEN_MAX_SIZE, |
386 | 9de5e440 | bellard | &code_gen_size, pc, cs_base, flags); |
387 | 9de5e440 | bellard | /* if invalid instruction, signal it */
|
388 | 9de5e440 | bellard | if (ret != 0) { |
389 | 9de5e440 | bellard | cpu_unlock(); |
390 | 9de5e440 | bellard | raise_exception(EXCP06_ILLOP); |
391 | 9de5e440 | bellard | } |
392 | 9de5e440 | bellard | tb = tb_alloc(); |
393 | 9de5e440 | bellard | *ptb = tb; |
394 | 9de5e440 | bellard | tb->pc = (unsigned long)pc; |
395 | 9de5e440 | bellard | tb->cs_base = (unsigned long)cs_base; |
396 | 9de5e440 | bellard | tb->flags = flags; |
397 | 7d13299d | bellard | tb->tc_ptr = tc_ptr; |
398 | 9de5e440 | bellard | tb->hash_next = NULL;
|
399 | 7d13299d | bellard | code_gen_ptr = (void *)(((unsigned long)code_gen_ptr + code_gen_size + CODE_GEN_ALIGN - 1) & ~(CODE_GEN_ALIGN - 1)); |
400 | 1b6b029e | bellard | cpu_unlock(); |
401 | 7d13299d | bellard | } |
402 | 9d27abd9 | bellard | #ifdef DEBUG_EXEC
|
403 | 956034d7 | bellard | if (loglevel) {
|
404 | 956034d7 | bellard | fprintf(logfile, "Trace 0x%08lx [0x%08lx] %s\n",
|
405 | 956034d7 | bellard | (long)tb->tc_ptr, (long)tb->pc, |
406 | 956034d7 | bellard | lookup_symbol((void *)tb->pc));
|
407 | 956034d7 | bellard | } |
408 | 9d27abd9 | bellard | #endif
|
409 | 7d13299d | bellard | /* execute the generated code */
|
410 | 9de5e440 | bellard | tc_ptr = tb->tc_ptr; |
411 | 7d13299d | bellard | gen_func = (void *)tc_ptr;
|
412 | 7d13299d | bellard | gen_func(); |
413 | 7d13299d | bellard | } |
414 | 7d13299d | bellard | } |
415 | 7d13299d | bellard | ret = env->exception_index; |
416 | 7d13299d | bellard | |
417 | 9de5e440 | bellard | /* restore flags in standard format */
|
418 | fc2b4c48 | bellard | env->eflags = env->eflags | cc_table[CC_OP].compute_all() | (DF & DF_MASK); |
419 | 9de5e440 | bellard | |
420 | 7d13299d | bellard | /* restore global registers */
|
421 | 04369ff2 | bellard | #ifdef reg_EAX
|
422 | 04369ff2 | bellard | EAX = saved_EAX; |
423 | 04369ff2 | bellard | #endif
|
424 | 04369ff2 | bellard | #ifdef reg_ECX
|
425 | 04369ff2 | bellard | ECX = saved_ECX; |
426 | 04369ff2 | bellard | #endif
|
427 | 04369ff2 | bellard | #ifdef reg_EDX
|
428 | 04369ff2 | bellard | EDX = saved_EDX; |
429 | 04369ff2 | bellard | #endif
|
430 | 04369ff2 | bellard | #ifdef reg_EBX
|
431 | 04369ff2 | bellard | EBX = saved_EBX; |
432 | 04369ff2 | bellard | #endif
|
433 | 04369ff2 | bellard | #ifdef reg_ESP
|
434 | 04369ff2 | bellard | ESP = saved_ESP; |
435 | 04369ff2 | bellard | #endif
|
436 | 04369ff2 | bellard | #ifdef reg_EBP
|
437 | 04369ff2 | bellard | EBP = saved_EBP; |
438 | 04369ff2 | bellard | #endif
|
439 | 04369ff2 | bellard | #ifdef reg_ESI
|
440 | 04369ff2 | bellard | ESI = saved_ESI; |
441 | 04369ff2 | bellard | #endif
|
442 | 04369ff2 | bellard | #ifdef reg_EDI
|
443 | 04369ff2 | bellard | EDI = saved_EDI; |
444 | 04369ff2 | bellard | #endif
|
445 | 7d13299d | bellard | T0 = saved_T0; |
446 | 7d13299d | bellard | T1 = saved_T1; |
447 | 7d13299d | bellard | A0 = saved_A0; |
448 | 7d13299d | bellard | env = saved_env; |
449 | 7d13299d | bellard | return ret;
|
450 | 7d13299d | bellard | } |
451 | 6dbad63e | bellard | |
452 | 9de5e440 | bellard | void cpu_x86_interrupt(CPUX86State *s)
|
453 | 9de5e440 | bellard | { |
454 | 9de5e440 | bellard | s->interrupt_request = 1;
|
455 | 9de5e440 | bellard | } |
456 | 9de5e440 | bellard | |
457 | 9de5e440 | bellard | |
458 | 6dbad63e | bellard | void cpu_x86_load_seg(CPUX86State *s, int seg_reg, int selector) |
459 | 6dbad63e | bellard | { |
460 | 6dbad63e | bellard | CPUX86State *saved_env; |
461 | 6dbad63e | bellard | |
462 | 6dbad63e | bellard | saved_env = env; |
463 | 6dbad63e | bellard | env = s; |
464 | 6dbad63e | bellard | load_seg(seg_reg, selector); |
465 | 6dbad63e | bellard | env = saved_env; |
466 | 6dbad63e | bellard | } |
467 | 9de5e440 | bellard | |
468 | 9de5e440 | bellard | #undef EAX
|
469 | 9de5e440 | bellard | #undef ECX
|
470 | 9de5e440 | bellard | #undef EDX
|
471 | 9de5e440 | bellard | #undef EBX
|
472 | 9de5e440 | bellard | #undef ESP
|
473 | 9de5e440 | bellard | #undef EBP
|
474 | 9de5e440 | bellard | #undef ESI
|
475 | 9de5e440 | bellard | #undef EDI
|
476 | 9de5e440 | bellard | #undef EIP
|
477 | 9de5e440 | bellard | #include <signal.h> |
478 | 9de5e440 | bellard | #include <sys/ucontext.h> |
479 | 9de5e440 | bellard | |
480 | b56dad1c | bellard | /* 'pc' is the host PC at which the exception was raised. 'address' is
|
481 | b56dad1c | bellard | the effective address of the memory exception */
|
482 | 9de5e440 | bellard | static inline int handle_cpu_signal(unsigned long pc, |
483 | b56dad1c | bellard | unsigned long address, |
484 | 9de5e440 | bellard | sigset_t *old_set) |
485 | 9de5e440 | bellard | { |
486 | 9de5e440 | bellard | #ifdef DEBUG_SIGNAL
|
487 | 9de5e440 | bellard | printf("gemu: SIGSEGV pc=0x%08lx oldset=0x%08lx\n",
|
488 | 9de5e440 | bellard | pc, *(unsigned long *)old_set); |
489 | 9de5e440 | bellard | #endif
|
490 | 9de5e440 | bellard | if (pc >= (unsigned long)code_gen_buffer && |
491 | 9de5e440 | bellard | pc < (unsigned long)code_gen_buffer + CODE_GEN_BUFFER_SIZE) { |
492 | 9de5e440 | bellard | /* the PC is inside the translated code. It means that we have
|
493 | 9de5e440 | bellard | a virtual CPU fault */
|
494 | 9de5e440 | bellard | /* we restore the process signal mask as the sigreturn should
|
495 | 9de5e440 | bellard | do it */
|
496 | 9de5e440 | bellard | sigprocmask(SIG_SETMASK, old_set, NULL);
|
497 | 9de5e440 | bellard | /* XXX: need to compute virtual pc position by retranslating
|
498 | 9de5e440 | bellard | code. The rest of the CPU state should be correct. */
|
499 | b56dad1c | bellard | env->cr2 = address; |
500 | b56dad1c | bellard | /* XXX: more precise exception code */
|
501 | b56dad1c | bellard | raise_exception_err(EXCP0E_PAGE, 4);
|
502 | 9de5e440 | bellard | /* never comes here */
|
503 | 9de5e440 | bellard | return 1; |
504 | 9de5e440 | bellard | } else {
|
505 | 9de5e440 | bellard | return 0; |
506 | 9de5e440 | bellard | } |
507 | 9de5e440 | bellard | } |
508 | 9de5e440 | bellard | |
509 | 9de5e440 | bellard | int cpu_x86_signal_handler(int host_signum, struct siginfo *info, |
510 | 9de5e440 | bellard | void *puc)
|
511 | 9de5e440 | bellard | { |
512 | 9de5e440 | bellard | #if defined(__i386__)
|
513 | 9de5e440 | bellard | struct ucontext *uc = puc;
|
514 | 9de5e440 | bellard | unsigned long pc; |
515 | 9de5e440 | bellard | sigset_t *pold_set; |
516 | 9de5e440 | bellard | |
517 | d691f669 | bellard | #ifndef REG_EIP
|
518 | d691f669 | bellard | /* for glibc 2.1 */
|
519 | d691f669 | bellard | #define REG_EIP EIP
|
520 | d691f669 | bellard | #endif
|
521 | fc2b4c48 | bellard | pc = uc->uc_mcontext.gregs[REG_EIP]; |
522 | 9de5e440 | bellard | pold_set = &uc->uc_sigmask; |
523 | b56dad1c | bellard | return handle_cpu_signal(pc, (unsigned long)info->si_addr, pold_set); |
524 | 9de5e440 | bellard | #else
|
525 | 9de5e440 | bellard | #warning No CPU specific signal handler: cannot handle target SIGSEGV events
|
526 | 9de5e440 | bellard | return 0; |
527 | 9de5e440 | bellard | #endif
|
528 | 9de5e440 | bellard | } |