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/*
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 * QEMU Floppy disk emulator (Intel 82078)
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 *
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 * Copyright (c) 2003, 2007 Jocelyn Mayer
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 * Copyright (c) 2008 Herv? Poussineau
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 *
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 * Permission is hereby granted, free of charge, to any person obtaining a copy
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 * of this software and associated documentation files (the "Software"), to deal
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 * in the Software without restriction, including without limitation the rights
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 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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 * copies of the Software, and to permit persons to whom the Software is
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 * furnished to do so, subject to the following conditions:
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 *
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 * The above copyright notice and this permission notice shall be included in
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 * all copies or substantial portions of the Software.
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 *
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 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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 * THE SOFTWARE.
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 */
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/*
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 * The controller is used in Sun4m systems in a slightly different
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 * way. There are changes in DOR register and DMA is not available.
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 */
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#include "hw.h"
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#include "fdc.h"
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#include "qemu-error.h"
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#include "qemu-timer.h"
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#include "isa.h"
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#include "sysbus.h"
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#include "qdev-addr.h"
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#include "blockdev.h"
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#include "sysemu.h"
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/********************************************************/
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/* debug Floppy devices */
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//#define DEBUG_FLOPPY
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#ifdef DEBUG_FLOPPY
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#define FLOPPY_DPRINTF(fmt, ...)                                \
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    do { printf("FLOPPY: " fmt , ## __VA_ARGS__); } while (0)
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#else
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#define FLOPPY_DPRINTF(fmt, ...)
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#endif
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#define FLOPPY_ERROR(fmt, ...)                                          \
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    do { printf("FLOPPY ERROR: %s: " fmt, __func__ , ## __VA_ARGS__); } while (0)
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/********************************************************/
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/* Floppy drive emulation                               */
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#define GET_CUR_DRV(fdctrl) ((fdctrl)->cur_drv)
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#define SET_CUR_DRV(fdctrl, drive) ((fdctrl)->cur_drv = (drive))
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/* Will always be a fixed parameter for us */
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#define FD_SECTOR_LEN          512
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#define FD_SECTOR_SC           2   /* Sector size code */
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#define FD_RESET_SENSEI_COUNT  4   /* Number of sense interrupts on RESET */
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/* Floppy disk drive emulation */
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typedef enum FDiskType {
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    FDRIVE_DISK_288   = 0x01, /* 2.88 MB disk           */
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    FDRIVE_DISK_144   = 0x02, /* 1.44 MB disk           */
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    FDRIVE_DISK_720   = 0x03, /* 720 kB disk            */
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    FDRIVE_DISK_USER  = 0x04, /* User defined geometry  */
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    FDRIVE_DISK_NONE  = 0x05, /* No disk                */
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} FDiskType;
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typedef enum FDriveType {
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    FDRIVE_DRV_144  = 0x00,   /* 1.44 MB 3"5 drive      */
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    FDRIVE_DRV_288  = 0x01,   /* 2.88 MB 3"5 drive      */
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    FDRIVE_DRV_120  = 0x02,   /* 1.2  MB 5"25 drive     */
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    FDRIVE_DRV_NONE = 0x03,   /* No drive connected     */
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} FDriveType;
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typedef enum FDiskFlags {
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    FDISK_DBL_SIDES  = 0x01,
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} FDiskFlags;
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typedef struct FDrive {
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    BlockDriverState *bs;
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    /* Drive status */
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    FDriveType drive;
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    uint8_t perpendicular;    /* 2.88 MB access mode    */
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    /* Position */
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    uint8_t head;
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    uint8_t track;
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    uint8_t sect;
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    /* Media */
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    FDiskFlags flags;
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    uint8_t last_sect;        /* Nb sector per track    */
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    uint8_t max_track;        /* Nb of tracks           */
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    uint16_t bps;             /* Bytes per sector       */
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    uint8_t ro;               /* Is read-only           */
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} FDrive;
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static void fd_init(FDrive *drv)
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{
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    /* Drive */
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    drv->drive = FDRIVE_DRV_NONE;
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    drv->perpendicular = 0;
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    /* Disk */
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    drv->last_sect = 0;
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    drv->max_track = 0;
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}
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static int fd_sector_calc(uint8_t head, uint8_t track, uint8_t sect,
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                          uint8_t last_sect)
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{
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    return (((track * 2) + head) * last_sect) + sect - 1;
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}
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/* Returns current position, in sectors, for given drive */
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static int fd_sector(FDrive *drv)
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{
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    return fd_sector_calc(drv->head, drv->track, drv->sect, drv->last_sect);
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}
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/* Seek to a new position:
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 * returns 0 if already on right track
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 * returns 1 if track changed
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 * returns 2 if track is invalid
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 * returns 3 if sector is invalid
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 * returns 4 if seek is disabled
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 */
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static int fd_seek(FDrive *drv, uint8_t head, uint8_t track, uint8_t sect,
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                   int enable_seek)
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{
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    uint32_t sector;
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    int ret;
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    if (track > drv->max_track ||
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        (head != 0 && (drv->flags & FDISK_DBL_SIDES) == 0)) {
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        FLOPPY_DPRINTF("try to read %d %02x %02x (max=%d %d %02x %02x)\n",
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                       head, track, sect, 1,
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                       (drv->flags & FDISK_DBL_SIDES) == 0 ? 0 : 1,
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                       drv->max_track, drv->last_sect);
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        return 2;
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    }
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    if (sect > drv->last_sect) {
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        FLOPPY_DPRINTF("try to read %d %02x %02x (max=%d %d %02x %02x)\n",
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                       head, track, sect, 1,
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                       (drv->flags & FDISK_DBL_SIDES) == 0 ? 0 : 1,
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                       drv->max_track, drv->last_sect);
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        return 3;
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    }
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    sector = fd_sector_calc(head, track, sect, drv->last_sect);
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    ret = 0;
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    if (sector != fd_sector(drv)) {
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#if 0
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        if (!enable_seek) {
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            FLOPPY_ERROR("no implicit seek %d %02x %02x (max=%d %02x %02x)\n",
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                         head, track, sect, 1, drv->max_track, drv->last_sect);
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            return 4;
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        }
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#endif
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        drv->head = head;
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        if (drv->track != track)
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            ret = 1;
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        drv->track = track;
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        drv->sect = sect;
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    }
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    return ret;
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}
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/* Set drive back to track 0 */
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static void fd_recalibrate(FDrive *drv)
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{
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    FLOPPY_DPRINTF("recalibrate\n");
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    drv->head = 0;
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    drv->track = 0;
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    drv->sect = 1;
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}
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/* Recognize floppy formats */
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typedef struct FDFormat {
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    FDriveType drive;
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    FDiskType  disk;
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    uint8_t last_sect;
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    uint8_t max_track;
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    uint8_t max_head;
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    const char *str;
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} FDFormat;
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static const FDFormat fd_formats[] = {
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    /* First entry is default format */
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    /* 1.44 MB 3"1/2 floppy disks */
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    { FDRIVE_DRV_144, FDRIVE_DISK_144, 18, 80, 1, "1.44 MB 3\"1/2", },
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    { FDRIVE_DRV_144, FDRIVE_DISK_144, 20, 80, 1,  "1.6 MB 3\"1/2", },
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    { FDRIVE_DRV_144, FDRIVE_DISK_144, 21, 80, 1, "1.68 MB 3\"1/2", },
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    { FDRIVE_DRV_144, FDRIVE_DISK_144, 21, 82, 1, "1.72 MB 3\"1/2", },
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    { FDRIVE_DRV_144, FDRIVE_DISK_144, 21, 83, 1, "1.74 MB 3\"1/2", },
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    { FDRIVE_DRV_144, FDRIVE_DISK_144, 22, 80, 1, "1.76 MB 3\"1/2", },
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    { FDRIVE_DRV_144, FDRIVE_DISK_144, 23, 80, 1, "1.84 MB 3\"1/2", },
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    { FDRIVE_DRV_144, FDRIVE_DISK_144, 24, 80, 1, "1.92 MB 3\"1/2", },
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    /* 2.88 MB 3"1/2 floppy disks */
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    { FDRIVE_DRV_288, FDRIVE_DISK_288, 36, 80, 1, "2.88 MB 3\"1/2", },
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    { FDRIVE_DRV_288, FDRIVE_DISK_288, 39, 80, 1, "3.12 MB 3\"1/2", },
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    { FDRIVE_DRV_288, FDRIVE_DISK_288, 40, 80, 1,  "3.2 MB 3\"1/2", },
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    { FDRIVE_DRV_288, FDRIVE_DISK_288, 44, 80, 1, "3.52 MB 3\"1/2", },
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    { FDRIVE_DRV_288, FDRIVE_DISK_288, 48, 80, 1, "3.84 MB 3\"1/2", },
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    /* 720 kB 3"1/2 floppy disks */
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    { FDRIVE_DRV_144, FDRIVE_DISK_720,  9, 80, 1,  "720 kB 3\"1/2", },
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    { FDRIVE_DRV_144, FDRIVE_DISK_720, 10, 80, 1,  "800 kB 3\"1/2", },
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    { FDRIVE_DRV_144, FDRIVE_DISK_720, 10, 82, 1,  "820 kB 3\"1/2", },
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    { FDRIVE_DRV_144, FDRIVE_DISK_720, 10, 83, 1,  "830 kB 3\"1/2", },
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    { FDRIVE_DRV_144, FDRIVE_DISK_720, 13, 80, 1, "1.04 MB 3\"1/2", },
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    { FDRIVE_DRV_144, FDRIVE_DISK_720, 14, 80, 1, "1.12 MB 3\"1/2", },
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    /* 1.2 MB 5"1/4 floppy disks */
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    { FDRIVE_DRV_120, FDRIVE_DISK_288, 15, 80, 1,  "1.2 kB 5\"1/4", },
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    { FDRIVE_DRV_120, FDRIVE_DISK_288, 18, 80, 1, "1.44 MB 5\"1/4", },
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    { FDRIVE_DRV_120, FDRIVE_DISK_288, 18, 82, 1, "1.48 MB 5\"1/4", },
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    { FDRIVE_DRV_120, FDRIVE_DISK_288, 18, 83, 1, "1.49 MB 5\"1/4", },
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    { FDRIVE_DRV_120, FDRIVE_DISK_288, 20, 80, 1,  "1.6 MB 5\"1/4", },
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    /* 720 kB 5"1/4 floppy disks */
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    { FDRIVE_DRV_120, FDRIVE_DISK_288,  9, 80, 1,  "720 kB 5\"1/4", },
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    { FDRIVE_DRV_120, FDRIVE_DISK_288, 11, 80, 1,  "880 kB 5\"1/4", },
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    /* 360 kB 5"1/4 floppy disks */
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    { FDRIVE_DRV_120, FDRIVE_DISK_288,  9, 40, 1,  "360 kB 5\"1/4", },
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    { FDRIVE_DRV_120, FDRIVE_DISK_288,  9, 40, 0,  "180 kB 5\"1/4", },
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    { FDRIVE_DRV_120, FDRIVE_DISK_288, 10, 41, 1,  "410 kB 5\"1/4", },
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    { FDRIVE_DRV_120, FDRIVE_DISK_288, 10, 42, 1,  "420 kB 5\"1/4", },
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    /* 320 kB 5"1/4 floppy disks */
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    { FDRIVE_DRV_120, FDRIVE_DISK_288,  8, 40, 1,  "320 kB 5\"1/4", },
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    { FDRIVE_DRV_120, FDRIVE_DISK_288,  8, 40, 0,  "160 kB 5\"1/4", },
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    /* 360 kB must match 5"1/4 better than 3"1/2... */
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    { FDRIVE_DRV_144, FDRIVE_DISK_720,  9, 80, 0,  "360 kB 3\"1/2", },
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    /* end */
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    { FDRIVE_DRV_NONE, FDRIVE_DISK_NONE, -1, -1, 0, NULL, },
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};
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/* Revalidate a disk drive after a disk change */
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static void fd_revalidate(FDrive *drv)
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{
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    const FDFormat *parse;
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    uint64_t nb_sectors, size;
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    int i, first_match, match;
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    int nb_heads, max_track, last_sect, ro;
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    FLOPPY_DPRINTF("revalidate\n");
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    if (drv->bs != NULL && bdrv_is_inserted(drv->bs)) {
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        ro = bdrv_is_read_only(drv->bs);
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        bdrv_get_geometry_hint(drv->bs, &nb_heads, &max_track, &last_sect);
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        if (nb_heads != 0 && max_track != 0 && last_sect != 0) {
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            FLOPPY_DPRINTF("User defined disk (%d %d %d)",
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                           nb_heads - 1, max_track, last_sect);
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        } else {
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            bdrv_get_geometry(drv->bs, &nb_sectors);
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            match = -1;
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            first_match = -1;
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            for (i = 0;; i++) {
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                parse = &fd_formats[i];
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                if (parse->drive == FDRIVE_DRV_NONE)
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                    break;
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                if (drv->drive == parse->drive ||
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                    drv->drive == FDRIVE_DRV_NONE) {
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                    size = (parse->max_head + 1) * parse->max_track *
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                        parse->last_sect;
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                    if (nb_sectors == size) {
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                        match = i;
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                        break;
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                    }
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                    if (first_match == -1)
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                        first_match = i;
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                }
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            }
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            if (match == -1) {
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                if (first_match == -1)
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                    match = 1;
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                else
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                    match = first_match;
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                parse = &fd_formats[match];
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            }
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            nb_heads = parse->max_head + 1;
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            max_track = parse->max_track;
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            last_sect = parse->last_sect;
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            drv->drive = parse->drive;
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            FLOPPY_DPRINTF("%s floppy disk (%d h %d t %d s) %s\n", parse->str,
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                           nb_heads, max_track, last_sect, ro ? "ro" : "rw");
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        }
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        if (nb_heads == 1) {
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            drv->flags &= ~FDISK_DBL_SIDES;
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        } else {
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            drv->flags |= FDISK_DBL_SIDES;
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        }
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        drv->max_track = max_track;
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        drv->last_sect = last_sect;
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        drv->ro = ro;
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    } else {
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        FLOPPY_DPRINTF("No disk in drive\n");
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        drv->last_sect = 0;
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        drv->max_track = 0;
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        drv->flags &= ~FDISK_DBL_SIDES;
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    }
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}
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/********************************************************/
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/* Intel 82078 floppy disk controller emulation          */
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static void fdctrl_reset(FDCtrl *fdctrl, int do_irq);
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static void fdctrl_reset_fifo(FDCtrl *fdctrl);
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static int fdctrl_transfer_handler (void *opaque, int nchan,
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                                    int dma_pos, int dma_len);
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static void fdctrl_raise_irq(FDCtrl *fdctrl, uint8_t status0);
311 5c02c033 Blue Swirl
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static uint32_t fdctrl_read_statusA(FDCtrl *fdctrl);
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static uint32_t fdctrl_read_statusB(FDCtrl *fdctrl);
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static uint32_t fdctrl_read_dor(FDCtrl *fdctrl);
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static void fdctrl_write_dor(FDCtrl *fdctrl, uint32_t value);
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static uint32_t fdctrl_read_tape(FDCtrl *fdctrl);
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static void fdctrl_write_tape(FDCtrl *fdctrl, uint32_t value);
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static uint32_t fdctrl_read_main_status(FDCtrl *fdctrl);
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static void fdctrl_write_rate(FDCtrl *fdctrl, uint32_t value);
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static uint32_t fdctrl_read_data(FDCtrl *fdctrl);
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static void fdctrl_write_data(FDCtrl *fdctrl, uint32_t value);
322 5c02c033 Blue Swirl
static uint32_t fdctrl_read_dir(FDCtrl *fdctrl);
323 8977f3c1 bellard
324 8977f3c1 bellard
enum {
325 8977f3c1 bellard
    FD_DIR_WRITE   = 0,
326 8977f3c1 bellard
    FD_DIR_READ    = 1,
327 8977f3c1 bellard
    FD_DIR_SCANE   = 2,
328 8977f3c1 bellard
    FD_DIR_SCANL   = 3,
329 8977f3c1 bellard
    FD_DIR_SCANH   = 4,
330 8977f3c1 bellard
};
331 8977f3c1 bellard
332 8977f3c1 bellard
enum {
333 b9b3d225 blueswir1
    FD_STATE_MULTI  = 0x01,        /* multi track flag */
334 b9b3d225 blueswir1
    FD_STATE_FORMAT = 0x02,        /* format flag */
335 b9b3d225 blueswir1
    FD_STATE_SEEK   = 0x04,        /* seek flag */
336 8977f3c1 bellard
};
337 8977f3c1 bellard
338 9fea808a blueswir1
enum {
339 8c6a4d77 blueswir1
    FD_REG_SRA = 0x00,
340 8c6a4d77 blueswir1
    FD_REG_SRB = 0x01,
341 9fea808a blueswir1
    FD_REG_DOR = 0x02,
342 9fea808a blueswir1
    FD_REG_TDR = 0x03,
343 9fea808a blueswir1
    FD_REG_MSR = 0x04,
344 9fea808a blueswir1
    FD_REG_DSR = 0x04,
345 9fea808a blueswir1
    FD_REG_FIFO = 0x05,
346 9fea808a blueswir1
    FD_REG_DIR = 0x07,
347 9fea808a blueswir1
};
348 9fea808a blueswir1
349 9fea808a blueswir1
enum {
350 65cef780 blueswir1
    FD_CMD_READ_TRACK = 0x02,
351 9fea808a blueswir1
    FD_CMD_SPECIFY = 0x03,
352 9fea808a blueswir1
    FD_CMD_SENSE_DRIVE_STATUS = 0x04,
353 65cef780 blueswir1
    FD_CMD_WRITE = 0x05,
354 65cef780 blueswir1
    FD_CMD_READ = 0x06,
355 9fea808a blueswir1
    FD_CMD_RECALIBRATE = 0x07,
356 9fea808a blueswir1
    FD_CMD_SENSE_INTERRUPT_STATUS = 0x08,
357 65cef780 blueswir1
    FD_CMD_WRITE_DELETED = 0x09,
358 65cef780 blueswir1
    FD_CMD_READ_ID = 0x0a,
359 65cef780 blueswir1
    FD_CMD_READ_DELETED = 0x0c,
360 65cef780 blueswir1
    FD_CMD_FORMAT_TRACK = 0x0d,
361 9fea808a blueswir1
    FD_CMD_DUMPREG = 0x0e,
362 9fea808a blueswir1
    FD_CMD_SEEK = 0x0f,
363 9fea808a blueswir1
    FD_CMD_VERSION = 0x10,
364 65cef780 blueswir1
    FD_CMD_SCAN_EQUAL = 0x11,
365 9fea808a blueswir1
    FD_CMD_PERPENDICULAR_MODE = 0x12,
366 9fea808a blueswir1
    FD_CMD_CONFIGURE = 0x13,
367 65cef780 blueswir1
    FD_CMD_LOCK = 0x14,
368 65cef780 blueswir1
    FD_CMD_VERIFY = 0x16,
369 9fea808a blueswir1
    FD_CMD_POWERDOWN_MODE = 0x17,
370 9fea808a blueswir1
    FD_CMD_PART_ID = 0x18,
371 65cef780 blueswir1
    FD_CMD_SCAN_LOW_OR_EQUAL = 0x19,
372 65cef780 blueswir1
    FD_CMD_SCAN_HIGH_OR_EQUAL = 0x1d,
373 bb350a5e Jes Sorensen
    FD_CMD_SAVE = 0x2e,
374 9fea808a blueswir1
    FD_CMD_OPTION = 0x33,
375 bb350a5e Jes Sorensen
    FD_CMD_RESTORE = 0x4e,
376 9fea808a blueswir1
    FD_CMD_DRIVE_SPECIFICATION_COMMAND = 0x8e,
377 9fea808a blueswir1
    FD_CMD_RELATIVE_SEEK_OUT = 0x8f,
378 9fea808a blueswir1
    FD_CMD_FORMAT_AND_WRITE = 0xcd,
379 9fea808a blueswir1
    FD_CMD_RELATIVE_SEEK_IN = 0xcf,
380 9fea808a blueswir1
};
381 9fea808a blueswir1
382 9fea808a blueswir1
enum {
383 9fea808a blueswir1
    FD_CONFIG_PRETRK = 0xff, /* Pre-compensation set to track 0 */
384 9fea808a blueswir1
    FD_CONFIG_FIFOTHR = 0x0f, /* FIFO threshold set to 1 byte */
385 9fea808a blueswir1
    FD_CONFIG_POLL  = 0x10, /* Poll enabled */
386 9fea808a blueswir1
    FD_CONFIG_EFIFO = 0x20, /* FIFO disabled */
387 9fea808a blueswir1
    FD_CONFIG_EIS   = 0x40, /* No implied seeks */
388 9fea808a blueswir1
};
389 9fea808a blueswir1
390 9fea808a blueswir1
enum {
391 9fea808a blueswir1
    FD_SR0_EQPMT    = 0x10,
392 9fea808a blueswir1
    FD_SR0_SEEK     = 0x20,
393 9fea808a blueswir1
    FD_SR0_ABNTERM  = 0x40,
394 9fea808a blueswir1
    FD_SR0_INVCMD   = 0x80,
395 9fea808a blueswir1
    FD_SR0_RDYCHG   = 0xc0,
396 9fea808a blueswir1
};
397 9fea808a blueswir1
398 9fea808a blueswir1
enum {
399 77370520 blueswir1
    FD_SR1_EC       = 0x80, /* End of cylinder */
400 77370520 blueswir1
};
401 77370520 blueswir1
402 77370520 blueswir1
enum {
403 77370520 blueswir1
    FD_SR2_SNS      = 0x04, /* Scan not satisfied */
404 77370520 blueswir1
    FD_SR2_SEH      = 0x08, /* Scan equal hit */
405 77370520 blueswir1
};
406 77370520 blueswir1
407 77370520 blueswir1
enum {
408 8c6a4d77 blueswir1
    FD_SRA_DIR      = 0x01,
409 8c6a4d77 blueswir1
    FD_SRA_nWP      = 0x02,
410 8c6a4d77 blueswir1
    FD_SRA_nINDX    = 0x04,
411 8c6a4d77 blueswir1
    FD_SRA_HDSEL    = 0x08,
412 8c6a4d77 blueswir1
    FD_SRA_nTRK0    = 0x10,
413 8c6a4d77 blueswir1
    FD_SRA_STEP     = 0x20,
414 8c6a4d77 blueswir1
    FD_SRA_nDRV2    = 0x40,
415 8c6a4d77 blueswir1
    FD_SRA_INTPEND  = 0x80,
416 8c6a4d77 blueswir1
};
417 8c6a4d77 blueswir1
418 8c6a4d77 blueswir1
enum {
419 8c6a4d77 blueswir1
    FD_SRB_MTR0     = 0x01,
420 8c6a4d77 blueswir1
    FD_SRB_MTR1     = 0x02,
421 8c6a4d77 blueswir1
    FD_SRB_WGATE    = 0x04,
422 8c6a4d77 blueswir1
    FD_SRB_RDATA    = 0x08,
423 8c6a4d77 blueswir1
    FD_SRB_WDATA    = 0x10,
424 8c6a4d77 blueswir1
    FD_SRB_DR0      = 0x20,
425 8c6a4d77 blueswir1
};
426 8c6a4d77 blueswir1
427 8c6a4d77 blueswir1
enum {
428 78ae820c blueswir1
#if MAX_FD == 4
429 78ae820c blueswir1
    FD_DOR_SELMASK  = 0x03,
430 78ae820c blueswir1
#else
431 9fea808a blueswir1
    FD_DOR_SELMASK  = 0x01,
432 78ae820c blueswir1
#endif
433 9fea808a blueswir1
    FD_DOR_nRESET   = 0x04,
434 9fea808a blueswir1
    FD_DOR_DMAEN    = 0x08,
435 9fea808a blueswir1
    FD_DOR_MOTEN0   = 0x10,
436 9fea808a blueswir1
    FD_DOR_MOTEN1   = 0x20,
437 9fea808a blueswir1
    FD_DOR_MOTEN2   = 0x40,
438 9fea808a blueswir1
    FD_DOR_MOTEN3   = 0x80,
439 9fea808a blueswir1
};
440 9fea808a blueswir1
441 9fea808a blueswir1
enum {
442 78ae820c blueswir1
#if MAX_FD == 4
443 9fea808a blueswir1
    FD_TDR_BOOTSEL  = 0x0c,
444 78ae820c blueswir1
#else
445 78ae820c blueswir1
    FD_TDR_BOOTSEL  = 0x04,
446 78ae820c blueswir1
#endif
447 9fea808a blueswir1
};
448 9fea808a blueswir1
449 9fea808a blueswir1
enum {
450 9fea808a blueswir1
    FD_DSR_DRATEMASK= 0x03,
451 9fea808a blueswir1
    FD_DSR_PWRDOWN  = 0x40,
452 9fea808a blueswir1
    FD_DSR_SWRESET  = 0x80,
453 9fea808a blueswir1
};
454 9fea808a blueswir1
455 9fea808a blueswir1
enum {
456 9fea808a blueswir1
    FD_MSR_DRV0BUSY = 0x01,
457 9fea808a blueswir1
    FD_MSR_DRV1BUSY = 0x02,
458 9fea808a blueswir1
    FD_MSR_DRV2BUSY = 0x04,
459 9fea808a blueswir1
    FD_MSR_DRV3BUSY = 0x08,
460 9fea808a blueswir1
    FD_MSR_CMDBUSY  = 0x10,
461 9fea808a blueswir1
    FD_MSR_NONDMA   = 0x20,
462 9fea808a blueswir1
    FD_MSR_DIO      = 0x40,
463 9fea808a blueswir1
    FD_MSR_RQM      = 0x80,
464 9fea808a blueswir1
};
465 9fea808a blueswir1
466 9fea808a blueswir1
enum {
467 9fea808a blueswir1
    FD_DIR_DSKCHG   = 0x80,
468 9fea808a blueswir1
};
469 9fea808a blueswir1
470 8977f3c1 bellard
#define FD_MULTI_TRACK(state) ((state) & FD_STATE_MULTI)
471 8977f3c1 bellard
#define FD_DID_SEEK(state) ((state) & FD_STATE_SEEK)
472 baca51fa bellard
#define FD_FORMAT_CMD(state) ((state) & FD_STATE_FORMAT)
473 8977f3c1 bellard
474 5c02c033 Blue Swirl
struct FDCtrl {
475 4b19ec0c bellard
    /* Controller's identification */
476 8977f3c1 bellard
    uint8_t version;
477 8977f3c1 bellard
    /* HW */
478 d537cf6c pbrook
    qemu_irq irq;
479 8977f3c1 bellard
    int dma_chann;
480 4b19ec0c bellard
    /* Controller state */
481 ed5fd2cc bellard
    QEMUTimer *result_timer;
482 8c6a4d77 blueswir1
    uint8_t sra;
483 8c6a4d77 blueswir1
    uint8_t srb;
484 368df94d blueswir1
    uint8_t dor;
485 d7a6c270 Juan Quintela
    uint8_t dor_vmstate; /* only used as temp during vmstate */
486 46d3233b blueswir1
    uint8_t tdr;
487 b9b3d225 blueswir1
    uint8_t dsr;
488 368df94d blueswir1
    uint8_t msr;
489 8977f3c1 bellard
    uint8_t cur_drv;
490 77370520 blueswir1
    uint8_t status0;
491 77370520 blueswir1
    uint8_t status1;
492 77370520 blueswir1
    uint8_t status2;
493 8977f3c1 bellard
    /* Command FIFO */
494 33f00271 balrog
    uint8_t *fifo;
495 d7a6c270 Juan Quintela
    int32_t fifo_size;
496 8977f3c1 bellard
    uint32_t data_pos;
497 8977f3c1 bellard
    uint32_t data_len;
498 8977f3c1 bellard
    uint8_t data_state;
499 8977f3c1 bellard
    uint8_t data_dir;
500 890fa6be bellard
    uint8_t eot; /* last wanted sector */
501 8977f3c1 bellard
    /* States kept only to be returned back */
502 8977f3c1 bellard
    /* Timers state */
503 8977f3c1 bellard
    uint8_t timer0;
504 8977f3c1 bellard
    uint8_t timer1;
505 8977f3c1 bellard
    /* precompensation */
506 8977f3c1 bellard
    uint8_t precomp_trk;
507 8977f3c1 bellard
    uint8_t config;
508 8977f3c1 bellard
    uint8_t lock;
509 8977f3c1 bellard
    /* Power down config (also with status regB access mode */
510 8977f3c1 bellard
    uint8_t pwrd;
511 741402f9 blueswir1
    /* Sun4m quirks? */
512 a06e5a3c blueswir1
    int sun4m;
513 8977f3c1 bellard
    /* Floppy drives */
514 d7a6c270 Juan Quintela
    uint8_t num_floppies;
515 5c02c033 Blue Swirl
    FDrive drives[MAX_FD];
516 f2d81b33 blueswir1
    int reset_sensei;
517 baca51fa bellard
};
518 baca51fa bellard
519 5c02c033 Blue Swirl
typedef struct FDCtrlSysBus {
520 8baf73ad Gerd Hoffmann
    SysBusDevice busdev;
521 5c02c033 Blue Swirl
    struct FDCtrl state;
522 5c02c033 Blue Swirl
} FDCtrlSysBus;
523 8baf73ad Gerd Hoffmann
524 5c02c033 Blue Swirl
typedef struct FDCtrlISABus {
525 8baf73ad Gerd Hoffmann
    ISADevice busdev;
526 5c02c033 Blue Swirl
    struct FDCtrl state;
527 1ca4d09a Gleb Natapov
    int32_t bootindexA;
528 1ca4d09a Gleb Natapov
    int32_t bootindexB;
529 5c02c033 Blue Swirl
} FDCtrlISABus;
530 8baf73ad Gerd Hoffmann
531 baca51fa bellard
static uint32_t fdctrl_read (void *opaque, uint32_t reg)
532 baca51fa bellard
{
533 5c02c033 Blue Swirl
    FDCtrl *fdctrl = opaque;
534 baca51fa bellard
    uint32_t retval;
535 baca51fa bellard
536 e64d7d59 blueswir1
    switch (reg) {
537 8c6a4d77 blueswir1
    case FD_REG_SRA:
538 8c6a4d77 blueswir1
        retval = fdctrl_read_statusA(fdctrl);
539 4f431960 j_mayer
        break;
540 8c6a4d77 blueswir1
    case FD_REG_SRB:
541 4f431960 j_mayer
        retval = fdctrl_read_statusB(fdctrl);
542 4f431960 j_mayer
        break;
543 9fea808a blueswir1
    case FD_REG_DOR:
544 4f431960 j_mayer
        retval = fdctrl_read_dor(fdctrl);
545 4f431960 j_mayer
        break;
546 9fea808a blueswir1
    case FD_REG_TDR:
547 baca51fa bellard
        retval = fdctrl_read_tape(fdctrl);
548 4f431960 j_mayer
        break;
549 9fea808a blueswir1
    case FD_REG_MSR:
550 baca51fa bellard
        retval = fdctrl_read_main_status(fdctrl);
551 4f431960 j_mayer
        break;
552 9fea808a blueswir1
    case FD_REG_FIFO:
553 baca51fa bellard
        retval = fdctrl_read_data(fdctrl);
554 4f431960 j_mayer
        break;
555 9fea808a blueswir1
    case FD_REG_DIR:
556 baca51fa bellard
        retval = fdctrl_read_dir(fdctrl);
557 4f431960 j_mayer
        break;
558 a541f297 bellard
    default:
559 4f431960 j_mayer
        retval = (uint32_t)(-1);
560 4f431960 j_mayer
        break;
561 a541f297 bellard
    }
562 ed5fd2cc bellard
    FLOPPY_DPRINTF("read reg%d: 0x%02x\n", reg & 7, retval);
563 baca51fa bellard
564 baca51fa bellard
    return retval;
565 baca51fa bellard
}
566 baca51fa bellard
567 baca51fa bellard
static void fdctrl_write (void *opaque, uint32_t reg, uint32_t value)
568 baca51fa bellard
{
569 5c02c033 Blue Swirl
    FDCtrl *fdctrl = opaque;
570 baca51fa bellard
571 ed5fd2cc bellard
    FLOPPY_DPRINTF("write reg%d: 0x%02x\n", reg & 7, value);
572 ed5fd2cc bellard
573 e64d7d59 blueswir1
    switch (reg) {
574 9fea808a blueswir1
    case FD_REG_DOR:
575 4f431960 j_mayer
        fdctrl_write_dor(fdctrl, value);
576 4f431960 j_mayer
        break;
577 9fea808a blueswir1
    case FD_REG_TDR:
578 baca51fa bellard
        fdctrl_write_tape(fdctrl, value);
579 4f431960 j_mayer
        break;
580 9fea808a blueswir1
    case FD_REG_DSR:
581 baca51fa bellard
        fdctrl_write_rate(fdctrl, value);
582 4f431960 j_mayer
        break;
583 9fea808a blueswir1
    case FD_REG_FIFO:
584 baca51fa bellard
        fdctrl_write_data(fdctrl, value);
585 4f431960 j_mayer
        break;
586 a541f297 bellard
    default:
587 4f431960 j_mayer
        break;
588 a541f297 bellard
    }
589 baca51fa bellard
}
590 baca51fa bellard
591 e64d7d59 blueswir1
static uint32_t fdctrl_read_port (void *opaque, uint32_t reg)
592 e64d7d59 blueswir1
{
593 e64d7d59 blueswir1
    return fdctrl_read(opaque, reg & 7);
594 e64d7d59 blueswir1
}
595 e64d7d59 blueswir1
596 e64d7d59 blueswir1
static void fdctrl_write_port (void *opaque, uint32_t reg, uint32_t value)
597 e64d7d59 blueswir1
{
598 e64d7d59 blueswir1
    fdctrl_write(opaque, reg & 7, value);
599 e64d7d59 blueswir1
}
600 e64d7d59 blueswir1
601 c227f099 Anthony Liguori
static uint32_t fdctrl_read_mem (void *opaque, target_phys_addr_t reg)
602 62a46c61 bellard
{
603 5dcb6b91 blueswir1
    return fdctrl_read(opaque, (uint32_t)reg);
604 62a46c61 bellard
}
605 62a46c61 bellard
606 5fafdf24 ths
static void fdctrl_write_mem (void *opaque,
607 c227f099 Anthony Liguori
                              target_phys_addr_t reg, uint32_t value)
608 62a46c61 bellard
{
609 5dcb6b91 blueswir1
    fdctrl_write(opaque, (uint32_t)reg, value);
610 62a46c61 bellard
}
611 62a46c61 bellard
612 d60efc6b Blue Swirl
static CPUReadMemoryFunc * const fdctrl_mem_read[3] = {
613 62a46c61 bellard
    fdctrl_read_mem,
614 62a46c61 bellard
    fdctrl_read_mem,
615 62a46c61 bellard
    fdctrl_read_mem,
616 e80cfcfc bellard
};
617 e80cfcfc bellard
618 d60efc6b Blue Swirl
static CPUWriteMemoryFunc * const fdctrl_mem_write[3] = {
619 62a46c61 bellard
    fdctrl_write_mem,
620 62a46c61 bellard
    fdctrl_write_mem,
621 62a46c61 bellard
    fdctrl_write_mem,
622 e80cfcfc bellard
};
623 e80cfcfc bellard
624 d60efc6b Blue Swirl
static CPUReadMemoryFunc * const fdctrl_mem_read_strict[3] = {
625 7c560456 blueswir1
    fdctrl_read_mem,
626 7c560456 blueswir1
    NULL,
627 7c560456 blueswir1
    NULL,
628 7c560456 blueswir1
};
629 7c560456 blueswir1
630 d60efc6b Blue Swirl
static CPUWriteMemoryFunc * const fdctrl_mem_write_strict[3] = {
631 7c560456 blueswir1
    fdctrl_write_mem,
632 7c560456 blueswir1
    NULL,
633 7c560456 blueswir1
    NULL,
634 7c560456 blueswir1
};
635 7c560456 blueswir1
636 d7a6c270 Juan Quintela
static const VMStateDescription vmstate_fdrive = {
637 d7a6c270 Juan Quintela
    .name = "fdrive",
638 d7a6c270 Juan Quintela
    .version_id = 1,
639 d7a6c270 Juan Quintela
    .minimum_version_id = 1,
640 d7a6c270 Juan Quintela
    .minimum_version_id_old = 1,
641 d7a6c270 Juan Quintela
    .fields      = (VMStateField []) {
642 5c02c033 Blue Swirl
        VMSTATE_UINT8(head, FDrive),
643 5c02c033 Blue Swirl
        VMSTATE_UINT8(track, FDrive),
644 5c02c033 Blue Swirl
        VMSTATE_UINT8(sect, FDrive),
645 d7a6c270 Juan Quintela
        VMSTATE_END_OF_LIST()
646 d7a6c270 Juan Quintela
    }
647 d7a6c270 Juan Quintela
};
648 3ccacc4a blueswir1
649 d4bfa4d7 Juan Quintela
static void fdc_pre_save(void *opaque)
650 3ccacc4a blueswir1
{
651 5c02c033 Blue Swirl
    FDCtrl *s = opaque;
652 3ccacc4a blueswir1
653 d7a6c270 Juan Quintela
    s->dor_vmstate = s->dor | GET_CUR_DRV(s);
654 3ccacc4a blueswir1
}
655 3ccacc4a blueswir1
656 e59fb374 Juan Quintela
static int fdc_post_load(void *opaque, int version_id)
657 3ccacc4a blueswir1
{
658 5c02c033 Blue Swirl
    FDCtrl *s = opaque;
659 3ccacc4a blueswir1
660 d7a6c270 Juan Quintela
    SET_CUR_DRV(s, s->dor_vmstate & FD_DOR_SELMASK);
661 d7a6c270 Juan Quintela
    s->dor = s->dor_vmstate & ~FD_DOR_SELMASK;
662 3ccacc4a blueswir1
    return 0;
663 3ccacc4a blueswir1
}
664 3ccacc4a blueswir1
665 d7a6c270 Juan Quintela
static const VMStateDescription vmstate_fdc = {
666 aef30c3c Juan Quintela
    .name = "fdc",
667 d7a6c270 Juan Quintela
    .version_id = 2,
668 d7a6c270 Juan Quintela
    .minimum_version_id = 2,
669 d7a6c270 Juan Quintela
    .minimum_version_id_old = 2,
670 d7a6c270 Juan Quintela
    .pre_save = fdc_pre_save,
671 d7a6c270 Juan Quintela
    .post_load = fdc_post_load,
672 d7a6c270 Juan Quintela
    .fields      = (VMStateField []) {
673 d7a6c270 Juan Quintela
        /* Controller State */
674 5c02c033 Blue Swirl
        VMSTATE_UINT8(sra, FDCtrl),
675 5c02c033 Blue Swirl
        VMSTATE_UINT8(srb, FDCtrl),
676 5c02c033 Blue Swirl
        VMSTATE_UINT8(dor_vmstate, FDCtrl),
677 5c02c033 Blue Swirl
        VMSTATE_UINT8(tdr, FDCtrl),
678 5c02c033 Blue Swirl
        VMSTATE_UINT8(dsr, FDCtrl),
679 5c02c033 Blue Swirl
        VMSTATE_UINT8(msr, FDCtrl),
680 5c02c033 Blue Swirl
        VMSTATE_UINT8(status0, FDCtrl),
681 5c02c033 Blue Swirl
        VMSTATE_UINT8(status1, FDCtrl),
682 5c02c033 Blue Swirl
        VMSTATE_UINT8(status2, FDCtrl),
683 d7a6c270 Juan Quintela
        /* Command FIFO */
684 8ec68b06 Blue Swirl
        VMSTATE_VARRAY_INT32(fifo, FDCtrl, fifo_size, 0, vmstate_info_uint8,
685 8ec68b06 Blue Swirl
                             uint8_t),
686 5c02c033 Blue Swirl
        VMSTATE_UINT32(data_pos, FDCtrl),
687 5c02c033 Blue Swirl
        VMSTATE_UINT32(data_len, FDCtrl),
688 5c02c033 Blue Swirl
        VMSTATE_UINT8(data_state, FDCtrl),
689 5c02c033 Blue Swirl
        VMSTATE_UINT8(data_dir, FDCtrl),
690 5c02c033 Blue Swirl
        VMSTATE_UINT8(eot, FDCtrl),
691 d7a6c270 Juan Quintela
        /* States kept only to be returned back */
692 5c02c033 Blue Swirl
        VMSTATE_UINT8(timer0, FDCtrl),
693 5c02c033 Blue Swirl
        VMSTATE_UINT8(timer1, FDCtrl),
694 5c02c033 Blue Swirl
        VMSTATE_UINT8(precomp_trk, FDCtrl),
695 5c02c033 Blue Swirl
        VMSTATE_UINT8(config, FDCtrl),
696 5c02c033 Blue Swirl
        VMSTATE_UINT8(lock, FDCtrl),
697 5c02c033 Blue Swirl
        VMSTATE_UINT8(pwrd, FDCtrl),
698 5c02c033 Blue Swirl
        VMSTATE_UINT8_EQUAL(num_floppies, FDCtrl),
699 5c02c033 Blue Swirl
        VMSTATE_STRUCT_ARRAY(drives, FDCtrl, MAX_FD, 1,
700 5c02c033 Blue Swirl
                             vmstate_fdrive, FDrive),
701 d7a6c270 Juan Quintela
        VMSTATE_END_OF_LIST()
702 78ae820c blueswir1
    }
703 d7a6c270 Juan Quintela
};
704 3ccacc4a blueswir1
705 2be37833 Blue Swirl
static void fdctrl_external_reset_sysbus(DeviceState *d)
706 3ccacc4a blueswir1
{
707 5c02c033 Blue Swirl
    FDCtrlSysBus *sys = container_of(d, FDCtrlSysBus, busdev.qdev);
708 5c02c033 Blue Swirl
    FDCtrl *s = &sys->state;
709 2be37833 Blue Swirl
710 2be37833 Blue Swirl
    fdctrl_reset(s, 0);
711 2be37833 Blue Swirl
}
712 2be37833 Blue Swirl
713 2be37833 Blue Swirl
static void fdctrl_external_reset_isa(DeviceState *d)
714 2be37833 Blue Swirl
{
715 5c02c033 Blue Swirl
    FDCtrlISABus *isa = container_of(d, FDCtrlISABus, busdev.qdev);
716 5c02c033 Blue Swirl
    FDCtrl *s = &isa->state;
717 3ccacc4a blueswir1
718 3ccacc4a blueswir1
    fdctrl_reset(s, 0);
719 3ccacc4a blueswir1
}
720 3ccacc4a blueswir1
721 2be17ebd blueswir1
static void fdctrl_handle_tc(void *opaque, int irq, int level)
722 2be17ebd blueswir1
{
723 5c02c033 Blue Swirl
    //FDCtrl *s = opaque;
724 2be17ebd blueswir1
725 2be17ebd blueswir1
    if (level) {
726 2be17ebd blueswir1
        // XXX
727 2be17ebd blueswir1
        FLOPPY_DPRINTF("TC pulsed\n");
728 2be17ebd blueswir1
    }
729 2be17ebd blueswir1
}
730 2be17ebd blueswir1
731 baca51fa bellard
/* XXX: may change if moved to bdrv */
732 5c02c033 Blue Swirl
int fdctrl_get_drive_type(FDCtrl *fdctrl, int drive_num)
733 caed8802 bellard
{
734 baca51fa bellard
    return fdctrl->drives[drive_num].drive;
735 8977f3c1 bellard
}
736 8977f3c1 bellard
737 8977f3c1 bellard
/* Change IRQ state */
738 5c02c033 Blue Swirl
static void fdctrl_reset_irq(FDCtrl *fdctrl)
739 8977f3c1 bellard
{
740 8c6a4d77 blueswir1
    if (!(fdctrl->sra & FD_SRA_INTPEND))
741 8c6a4d77 blueswir1
        return;
742 ed5fd2cc bellard
    FLOPPY_DPRINTF("Reset interrupt\n");
743 d537cf6c pbrook
    qemu_set_irq(fdctrl->irq, 0);
744 8c6a4d77 blueswir1
    fdctrl->sra &= ~FD_SRA_INTPEND;
745 8977f3c1 bellard
}
746 8977f3c1 bellard
747 5c02c033 Blue Swirl
static void fdctrl_raise_irq(FDCtrl *fdctrl, uint8_t status0)
748 8977f3c1 bellard
{
749 b9b3d225 blueswir1
    /* Sparc mutation */
750 b9b3d225 blueswir1
    if (fdctrl->sun4m && (fdctrl->msr & FD_MSR_CMDBUSY)) {
751 b9b3d225 blueswir1
        /* XXX: not sure */
752 b9b3d225 blueswir1
        fdctrl->msr &= ~FD_MSR_CMDBUSY;
753 b9b3d225 blueswir1
        fdctrl->msr |= FD_MSR_RQM | FD_MSR_DIO;
754 77370520 blueswir1
        fdctrl->status0 = status0;
755 4f431960 j_mayer
        return;
756 6f7e9aec bellard
    }
757 8c6a4d77 blueswir1
    if (!(fdctrl->sra & FD_SRA_INTPEND)) {
758 d537cf6c pbrook
        qemu_set_irq(fdctrl->irq, 1);
759 8c6a4d77 blueswir1
        fdctrl->sra |= FD_SRA_INTPEND;
760 8977f3c1 bellard
    }
761 f2d81b33 blueswir1
    fdctrl->reset_sensei = 0;
762 77370520 blueswir1
    fdctrl->status0 = status0;
763 77370520 blueswir1
    FLOPPY_DPRINTF("Set interrupt status to 0x%02x\n", fdctrl->status0);
764 8977f3c1 bellard
}
765 8977f3c1 bellard
766 4b19ec0c bellard
/* Reset controller */
767 5c02c033 Blue Swirl
static void fdctrl_reset(FDCtrl *fdctrl, int do_irq)
768 8977f3c1 bellard
{
769 8977f3c1 bellard
    int i;
770 8977f3c1 bellard
771 4b19ec0c bellard
    FLOPPY_DPRINTF("reset controller\n");
772 baca51fa bellard
    fdctrl_reset_irq(fdctrl);
773 4b19ec0c bellard
    /* Initialise controller */
774 8c6a4d77 blueswir1
    fdctrl->sra = 0;
775 8c6a4d77 blueswir1
    fdctrl->srb = 0xc0;
776 8c6a4d77 blueswir1
    if (!fdctrl->drives[1].bs)
777 8c6a4d77 blueswir1
        fdctrl->sra |= FD_SRA_nDRV2;
778 baca51fa bellard
    fdctrl->cur_drv = 0;
779 1c346df2 blueswir1
    fdctrl->dor = FD_DOR_nRESET;
780 368df94d blueswir1
    fdctrl->dor |= (fdctrl->dma_chann != -1) ? FD_DOR_DMAEN : 0;
781 b9b3d225 blueswir1
    fdctrl->msr = FD_MSR_RQM;
782 8977f3c1 bellard
    /* FIFO state */
783 baca51fa bellard
    fdctrl->data_pos = 0;
784 baca51fa bellard
    fdctrl->data_len = 0;
785 b9b3d225 blueswir1
    fdctrl->data_state = 0;
786 baca51fa bellard
    fdctrl->data_dir = FD_DIR_WRITE;
787 8977f3c1 bellard
    for (i = 0; i < MAX_FD; i++)
788 1c346df2 blueswir1
        fd_recalibrate(&fdctrl->drives[i]);
789 baca51fa bellard
    fdctrl_reset_fifo(fdctrl);
790 77370520 blueswir1
    if (do_irq) {
791 9fea808a blueswir1
        fdctrl_raise_irq(fdctrl, FD_SR0_RDYCHG);
792 f2d81b33 blueswir1
        fdctrl->reset_sensei = FD_RESET_SENSEI_COUNT;
793 77370520 blueswir1
    }
794 baca51fa bellard
}
795 baca51fa bellard
796 5c02c033 Blue Swirl
static inline FDrive *drv0(FDCtrl *fdctrl)
797 baca51fa bellard
{
798 46d3233b blueswir1
    return &fdctrl->drives[(fdctrl->tdr & FD_TDR_BOOTSEL) >> 2];
799 baca51fa bellard
}
800 baca51fa bellard
801 5c02c033 Blue Swirl
static inline FDrive *drv1(FDCtrl *fdctrl)
802 baca51fa bellard
{
803 46d3233b blueswir1
    if ((fdctrl->tdr & FD_TDR_BOOTSEL) < (1 << 2))
804 46d3233b blueswir1
        return &fdctrl->drives[1];
805 46d3233b blueswir1
    else
806 46d3233b blueswir1
        return &fdctrl->drives[0];
807 baca51fa bellard
}
808 baca51fa bellard
809 78ae820c blueswir1
#if MAX_FD == 4
810 5c02c033 Blue Swirl
static inline FDrive *drv2(FDCtrl *fdctrl)
811 78ae820c blueswir1
{
812 78ae820c blueswir1
    if ((fdctrl->tdr & FD_TDR_BOOTSEL) < (2 << 2))
813 78ae820c blueswir1
        return &fdctrl->drives[2];
814 78ae820c blueswir1
    else
815 78ae820c blueswir1
        return &fdctrl->drives[1];
816 78ae820c blueswir1
}
817 78ae820c blueswir1
818 5c02c033 Blue Swirl
static inline FDrive *drv3(FDCtrl *fdctrl)
819 78ae820c blueswir1
{
820 78ae820c blueswir1
    if ((fdctrl->tdr & FD_TDR_BOOTSEL) < (3 << 2))
821 78ae820c blueswir1
        return &fdctrl->drives[3];
822 78ae820c blueswir1
    else
823 78ae820c blueswir1
        return &fdctrl->drives[2];
824 78ae820c blueswir1
}
825 78ae820c blueswir1
#endif
826 78ae820c blueswir1
827 5c02c033 Blue Swirl
static FDrive *get_cur_drv(FDCtrl *fdctrl)
828 baca51fa bellard
{
829 78ae820c blueswir1
    switch (fdctrl->cur_drv) {
830 78ae820c blueswir1
        case 0: return drv0(fdctrl);
831 78ae820c blueswir1
        case 1: return drv1(fdctrl);
832 78ae820c blueswir1
#if MAX_FD == 4
833 78ae820c blueswir1
        case 2: return drv2(fdctrl);
834 78ae820c blueswir1
        case 3: return drv3(fdctrl);
835 78ae820c blueswir1
#endif
836 78ae820c blueswir1
        default: return NULL;
837 78ae820c blueswir1
    }
838 8977f3c1 bellard
}
839 8977f3c1 bellard
840 8c6a4d77 blueswir1
/* Status A register : 0x00 (read-only) */
841 5c02c033 Blue Swirl
static uint32_t fdctrl_read_statusA(FDCtrl *fdctrl)
842 8c6a4d77 blueswir1
{
843 8c6a4d77 blueswir1
    uint32_t retval = fdctrl->sra;
844 8c6a4d77 blueswir1
845 8c6a4d77 blueswir1
    FLOPPY_DPRINTF("status register A: 0x%02x\n", retval);
846 8c6a4d77 blueswir1
847 8c6a4d77 blueswir1
    return retval;
848 8c6a4d77 blueswir1
}
849 8c6a4d77 blueswir1
850 8977f3c1 bellard
/* Status B register : 0x01 (read-only) */
851 5c02c033 Blue Swirl
static uint32_t fdctrl_read_statusB(FDCtrl *fdctrl)
852 8977f3c1 bellard
{
853 8c6a4d77 blueswir1
    uint32_t retval = fdctrl->srb;
854 8c6a4d77 blueswir1
855 8c6a4d77 blueswir1
    FLOPPY_DPRINTF("status register B: 0x%02x\n", retval);
856 8c6a4d77 blueswir1
857 8c6a4d77 blueswir1
    return retval;
858 8977f3c1 bellard
}
859 8977f3c1 bellard
860 8977f3c1 bellard
/* Digital output register : 0x02 */
861 5c02c033 Blue Swirl
static uint32_t fdctrl_read_dor(FDCtrl *fdctrl)
862 8977f3c1 bellard
{
863 1c346df2 blueswir1
    uint32_t retval = fdctrl->dor;
864 8977f3c1 bellard
865 8977f3c1 bellard
    /* Selected drive */
866 baca51fa bellard
    retval |= fdctrl->cur_drv;
867 8977f3c1 bellard
    FLOPPY_DPRINTF("digital output register: 0x%02x\n", retval);
868 8977f3c1 bellard
869 8977f3c1 bellard
    return retval;
870 8977f3c1 bellard
}
871 8977f3c1 bellard
872 5c02c033 Blue Swirl
static void fdctrl_write_dor(FDCtrl *fdctrl, uint32_t value)
873 8977f3c1 bellard
{
874 8977f3c1 bellard
    FLOPPY_DPRINTF("digital output register set to 0x%02x\n", value);
875 8c6a4d77 blueswir1
876 8c6a4d77 blueswir1
    /* Motors */
877 8c6a4d77 blueswir1
    if (value & FD_DOR_MOTEN0)
878 8c6a4d77 blueswir1
        fdctrl->srb |= FD_SRB_MTR0;
879 8c6a4d77 blueswir1
    else
880 8c6a4d77 blueswir1
        fdctrl->srb &= ~FD_SRB_MTR0;
881 8c6a4d77 blueswir1
    if (value & FD_DOR_MOTEN1)
882 8c6a4d77 blueswir1
        fdctrl->srb |= FD_SRB_MTR1;
883 8c6a4d77 blueswir1
    else
884 8c6a4d77 blueswir1
        fdctrl->srb &= ~FD_SRB_MTR1;
885 8c6a4d77 blueswir1
886 8c6a4d77 blueswir1
    /* Drive */
887 8c6a4d77 blueswir1
    if (value & 1)
888 8c6a4d77 blueswir1
        fdctrl->srb |= FD_SRB_DR0;
889 8c6a4d77 blueswir1
    else
890 8c6a4d77 blueswir1
        fdctrl->srb &= ~FD_SRB_DR0;
891 8c6a4d77 blueswir1
892 8977f3c1 bellard
    /* Reset */
893 9fea808a blueswir1
    if (!(value & FD_DOR_nRESET)) {
894 1c346df2 blueswir1
        if (fdctrl->dor & FD_DOR_nRESET) {
895 4b19ec0c bellard
            FLOPPY_DPRINTF("controller enter RESET state\n");
896 8977f3c1 bellard
        }
897 8977f3c1 bellard
    } else {
898 1c346df2 blueswir1
        if (!(fdctrl->dor & FD_DOR_nRESET)) {
899 4b19ec0c bellard
            FLOPPY_DPRINTF("controller out of RESET state\n");
900 fb6cf1d0 bellard
            fdctrl_reset(fdctrl, 1);
901 b9b3d225 blueswir1
            fdctrl->dsr &= ~FD_DSR_PWRDOWN;
902 8977f3c1 bellard
        }
903 8977f3c1 bellard
    }
904 8977f3c1 bellard
    /* Selected drive */
905 9fea808a blueswir1
    fdctrl->cur_drv = value & FD_DOR_SELMASK;
906 368df94d blueswir1
907 368df94d blueswir1
    fdctrl->dor = value;
908 8977f3c1 bellard
}
909 8977f3c1 bellard
910 8977f3c1 bellard
/* Tape drive register : 0x03 */
911 5c02c033 Blue Swirl
static uint32_t fdctrl_read_tape(FDCtrl *fdctrl)
912 8977f3c1 bellard
{
913 46d3233b blueswir1
    uint32_t retval = fdctrl->tdr;
914 8977f3c1 bellard
915 8977f3c1 bellard
    FLOPPY_DPRINTF("tape drive register: 0x%02x\n", retval);
916 8977f3c1 bellard
917 8977f3c1 bellard
    return retval;
918 8977f3c1 bellard
}
919 8977f3c1 bellard
920 5c02c033 Blue Swirl
static void fdctrl_write_tape(FDCtrl *fdctrl, uint32_t value)
921 8977f3c1 bellard
{
922 8977f3c1 bellard
    /* Reset mode */
923 1c346df2 blueswir1
    if (!(fdctrl->dor & FD_DOR_nRESET)) {
924 4b19ec0c bellard
        FLOPPY_DPRINTF("Floppy controller in RESET state !\n");
925 8977f3c1 bellard
        return;
926 8977f3c1 bellard
    }
927 8977f3c1 bellard
    FLOPPY_DPRINTF("tape drive register set to 0x%02x\n", value);
928 8977f3c1 bellard
    /* Disk boot selection indicator */
929 46d3233b blueswir1
    fdctrl->tdr = value & FD_TDR_BOOTSEL;
930 8977f3c1 bellard
    /* Tape indicators: never allow */
931 8977f3c1 bellard
}
932 8977f3c1 bellard
933 8977f3c1 bellard
/* Main status register : 0x04 (read) */
934 5c02c033 Blue Swirl
static uint32_t fdctrl_read_main_status(FDCtrl *fdctrl)
935 8977f3c1 bellard
{
936 b9b3d225 blueswir1
    uint32_t retval = fdctrl->msr;
937 8977f3c1 bellard
938 b9b3d225 blueswir1
    fdctrl->dsr &= ~FD_DSR_PWRDOWN;
939 1c346df2 blueswir1
    fdctrl->dor |= FD_DOR_nRESET;
940 b9b3d225 blueswir1
941 82407d1a Artyom Tarasenko
    /* Sparc mutation */
942 82407d1a Artyom Tarasenko
    if (fdctrl->sun4m) {
943 82407d1a Artyom Tarasenko
        retval |= FD_MSR_DIO;
944 82407d1a Artyom Tarasenko
        fdctrl_reset_irq(fdctrl);
945 82407d1a Artyom Tarasenko
    };
946 82407d1a Artyom Tarasenko
947 8977f3c1 bellard
    FLOPPY_DPRINTF("main status register: 0x%02x\n", retval);
948 8977f3c1 bellard
949 8977f3c1 bellard
    return retval;
950 8977f3c1 bellard
}
951 8977f3c1 bellard
952 8977f3c1 bellard
/* Data select rate register : 0x04 (write) */
953 5c02c033 Blue Swirl
static void fdctrl_write_rate(FDCtrl *fdctrl, uint32_t value)
954 8977f3c1 bellard
{
955 8977f3c1 bellard
    /* Reset mode */
956 1c346df2 blueswir1
    if (!(fdctrl->dor & FD_DOR_nRESET)) {
957 4f431960 j_mayer
        FLOPPY_DPRINTF("Floppy controller in RESET state !\n");
958 4f431960 j_mayer
        return;
959 4f431960 j_mayer
    }
960 8977f3c1 bellard
    FLOPPY_DPRINTF("select rate register set to 0x%02x\n", value);
961 8977f3c1 bellard
    /* Reset: autoclear */
962 9fea808a blueswir1
    if (value & FD_DSR_SWRESET) {
963 1c346df2 blueswir1
        fdctrl->dor &= ~FD_DOR_nRESET;
964 baca51fa bellard
        fdctrl_reset(fdctrl, 1);
965 1c346df2 blueswir1
        fdctrl->dor |= FD_DOR_nRESET;
966 8977f3c1 bellard
    }
967 9fea808a blueswir1
    if (value & FD_DSR_PWRDOWN) {
968 baca51fa bellard
        fdctrl_reset(fdctrl, 1);
969 8977f3c1 bellard
    }
970 b9b3d225 blueswir1
    fdctrl->dsr = value;
971 8977f3c1 bellard
}
972 8977f3c1 bellard
973 5c02c033 Blue Swirl
static int fdctrl_media_changed(FDrive *drv)
974 ea185bbd bellard
{
975 ea185bbd bellard
    int ret;
976 4f431960 j_mayer
977 5fafdf24 ths
    if (!drv->bs)
978 ea185bbd bellard
        return 0;
979 ea185bbd bellard
    ret = bdrv_media_changed(drv->bs);
980 ea185bbd bellard
    if (ret) {
981 ea185bbd bellard
        fd_revalidate(drv);
982 ea185bbd bellard
    }
983 ea185bbd bellard
    return ret;
984 ea185bbd bellard
}
985 ea185bbd bellard
986 8977f3c1 bellard
/* Digital input register : 0x07 (read-only) */
987 5c02c033 Blue Swirl
static uint32_t fdctrl_read_dir(FDCtrl *fdctrl)
988 8977f3c1 bellard
{
989 8977f3c1 bellard
    uint32_t retval = 0;
990 8977f3c1 bellard
991 78ae820c blueswir1
    if (fdctrl_media_changed(drv0(fdctrl))
992 78ae820c blueswir1
     || fdctrl_media_changed(drv1(fdctrl))
993 78ae820c blueswir1
#if MAX_FD == 4
994 78ae820c blueswir1
     || fdctrl_media_changed(drv2(fdctrl))
995 78ae820c blueswir1
     || fdctrl_media_changed(drv3(fdctrl))
996 78ae820c blueswir1
#endif
997 78ae820c blueswir1
        )
998 9fea808a blueswir1
        retval |= FD_DIR_DSKCHG;
999 3c83eb4f Blue Swirl
    if (retval != 0) {
1000 baca51fa bellard
        FLOPPY_DPRINTF("Floppy digital input register: 0x%02x\n", retval);
1001 3c83eb4f Blue Swirl
    }
1002 8977f3c1 bellard
1003 8977f3c1 bellard
    return retval;
1004 8977f3c1 bellard
}
1005 8977f3c1 bellard
1006 8977f3c1 bellard
/* FIFO state control */
1007 5c02c033 Blue Swirl
static void fdctrl_reset_fifo(FDCtrl *fdctrl)
1008 8977f3c1 bellard
{
1009 baca51fa bellard
    fdctrl->data_dir = FD_DIR_WRITE;
1010 baca51fa bellard
    fdctrl->data_pos = 0;
1011 b9b3d225 blueswir1
    fdctrl->msr &= ~(FD_MSR_CMDBUSY | FD_MSR_DIO);
1012 8977f3c1 bellard
}
1013 8977f3c1 bellard
1014 8977f3c1 bellard
/* Set FIFO status for the host to read */
1015 5c02c033 Blue Swirl
static void fdctrl_set_fifo(FDCtrl *fdctrl, int fifo_len, int do_irq)
1016 8977f3c1 bellard
{
1017 baca51fa bellard
    fdctrl->data_dir = FD_DIR_READ;
1018 baca51fa bellard
    fdctrl->data_len = fifo_len;
1019 baca51fa bellard
    fdctrl->data_pos = 0;
1020 b9b3d225 blueswir1
    fdctrl->msr |= FD_MSR_CMDBUSY | FD_MSR_RQM | FD_MSR_DIO;
1021 8977f3c1 bellard
    if (do_irq)
1022 baca51fa bellard
        fdctrl_raise_irq(fdctrl, 0x00);
1023 8977f3c1 bellard
}
1024 8977f3c1 bellard
1025 8977f3c1 bellard
/* Set an error: unimplemented/unknown command */
1026 5c02c033 Blue Swirl
static void fdctrl_unimplemented(FDCtrl *fdctrl, int direction)
1027 8977f3c1 bellard
{
1028 77370520 blueswir1
    FLOPPY_ERROR("unimplemented command 0x%02x\n", fdctrl->fifo[0]);
1029 9fea808a blueswir1
    fdctrl->fifo[0] = FD_SR0_INVCMD;
1030 baca51fa bellard
    fdctrl_set_fifo(fdctrl, 1, 0);
1031 8977f3c1 bellard
}
1032 8977f3c1 bellard
1033 746d6de7 blueswir1
/* Seek to next sector */
1034 5c02c033 Blue Swirl
static int fdctrl_seek_to_next_sect(FDCtrl *fdctrl, FDrive *cur_drv)
1035 746d6de7 blueswir1
{
1036 746d6de7 blueswir1
    FLOPPY_DPRINTF("seek to next sector (%d %02x %02x => %d)\n",
1037 746d6de7 blueswir1
                   cur_drv->head, cur_drv->track, cur_drv->sect,
1038 746d6de7 blueswir1
                   fd_sector(cur_drv));
1039 746d6de7 blueswir1
    /* XXX: cur_drv->sect >= cur_drv->last_sect should be an
1040 746d6de7 blueswir1
       error in fact */
1041 746d6de7 blueswir1
    if (cur_drv->sect >= cur_drv->last_sect ||
1042 746d6de7 blueswir1
        cur_drv->sect == fdctrl->eot) {
1043 746d6de7 blueswir1
        cur_drv->sect = 1;
1044 746d6de7 blueswir1
        if (FD_MULTI_TRACK(fdctrl->data_state)) {
1045 746d6de7 blueswir1
            if (cur_drv->head == 0 &&
1046 746d6de7 blueswir1
                (cur_drv->flags & FDISK_DBL_SIDES) != 0) {
1047 746d6de7 blueswir1
                cur_drv->head = 1;
1048 746d6de7 blueswir1
            } else {
1049 746d6de7 blueswir1
                cur_drv->head = 0;
1050 746d6de7 blueswir1
                cur_drv->track++;
1051 746d6de7 blueswir1
                if ((cur_drv->flags & FDISK_DBL_SIDES) == 0)
1052 746d6de7 blueswir1
                    return 0;
1053 746d6de7 blueswir1
            }
1054 746d6de7 blueswir1
        } else {
1055 746d6de7 blueswir1
            cur_drv->track++;
1056 746d6de7 blueswir1
            return 0;
1057 746d6de7 blueswir1
        }
1058 746d6de7 blueswir1
        FLOPPY_DPRINTF("seek to next track (%d %02x %02x => %d)\n",
1059 746d6de7 blueswir1
                       cur_drv->head, cur_drv->track,
1060 746d6de7 blueswir1
                       cur_drv->sect, fd_sector(cur_drv));
1061 746d6de7 blueswir1
    } else {
1062 746d6de7 blueswir1
        cur_drv->sect++;
1063 746d6de7 blueswir1
    }
1064 746d6de7 blueswir1
    return 1;
1065 746d6de7 blueswir1
}
1066 746d6de7 blueswir1
1067 8977f3c1 bellard
/* Callback for transfer end (stop or abort) */
1068 5c02c033 Blue Swirl
static void fdctrl_stop_transfer(FDCtrl *fdctrl, uint8_t status0,
1069 5c02c033 Blue Swirl
                                 uint8_t status1, uint8_t status2)
1070 8977f3c1 bellard
{
1071 5c02c033 Blue Swirl
    FDrive *cur_drv;
1072 8977f3c1 bellard
1073 baca51fa bellard
    cur_drv = get_cur_drv(fdctrl);
1074 8977f3c1 bellard
    FLOPPY_DPRINTF("transfer status: %02x %02x %02x (%02x)\n",
1075 8977f3c1 bellard
                   status0, status1, status2,
1076 cefec4f5 blueswir1
                   status0 | (cur_drv->head << 2) | GET_CUR_DRV(fdctrl));
1077 cefec4f5 blueswir1
    fdctrl->fifo[0] = status0 | (cur_drv->head << 2) | GET_CUR_DRV(fdctrl);
1078 baca51fa bellard
    fdctrl->fifo[1] = status1;
1079 baca51fa bellard
    fdctrl->fifo[2] = status2;
1080 baca51fa bellard
    fdctrl->fifo[3] = cur_drv->track;
1081 baca51fa bellard
    fdctrl->fifo[4] = cur_drv->head;
1082 baca51fa bellard
    fdctrl->fifo[5] = cur_drv->sect;
1083 baca51fa bellard
    fdctrl->fifo[6] = FD_SECTOR_SC;
1084 baca51fa bellard
    fdctrl->data_dir = FD_DIR_READ;
1085 368df94d blueswir1
    if (!(fdctrl->msr & FD_MSR_NONDMA)) {
1086 baca51fa bellard
        DMA_release_DREQ(fdctrl->dma_chann);
1087 ed5fd2cc bellard
    }
1088 b9b3d225 blueswir1
    fdctrl->msr |= FD_MSR_RQM | FD_MSR_DIO;
1089 368df94d blueswir1
    fdctrl->msr &= ~FD_MSR_NONDMA;
1090 baca51fa bellard
    fdctrl_set_fifo(fdctrl, 7, 1);
1091 8977f3c1 bellard
}
1092 8977f3c1 bellard
1093 8977f3c1 bellard
/* Prepare a data transfer (either DMA or FIFO) */
1094 5c02c033 Blue Swirl
static void fdctrl_start_transfer(FDCtrl *fdctrl, int direction)
1095 8977f3c1 bellard
{
1096 5c02c033 Blue Swirl
    FDrive *cur_drv;
1097 8977f3c1 bellard
    uint8_t kh, kt, ks;
1098 77370520 blueswir1
    int did_seek = 0;
1099 8977f3c1 bellard
1100 cefec4f5 blueswir1
    SET_CUR_DRV(fdctrl, fdctrl->fifo[1] & FD_DOR_SELMASK);
1101 baca51fa bellard
    cur_drv = get_cur_drv(fdctrl);
1102 baca51fa bellard
    kt = fdctrl->fifo[2];
1103 baca51fa bellard
    kh = fdctrl->fifo[3];
1104 baca51fa bellard
    ks = fdctrl->fifo[4];
1105 4b19ec0c bellard
    FLOPPY_DPRINTF("Start transfer at %d %d %02x %02x (%d)\n",
1106 cefec4f5 blueswir1
                   GET_CUR_DRV(fdctrl), kh, kt, ks,
1107 7859cb98 Blue Swirl
                   fd_sector_calc(kh, kt, ks, cur_drv->last_sect));
1108 77370520 blueswir1
    switch (fd_seek(cur_drv, kh, kt, ks, fdctrl->config & FD_CONFIG_EIS)) {
1109 8977f3c1 bellard
    case 2:
1110 8977f3c1 bellard
        /* sect too big */
1111 9fea808a blueswir1
        fdctrl_stop_transfer(fdctrl, FD_SR0_ABNTERM, 0x00, 0x00);
1112 baca51fa bellard
        fdctrl->fifo[3] = kt;
1113 baca51fa bellard
        fdctrl->fifo[4] = kh;
1114 baca51fa bellard
        fdctrl->fifo[5] = ks;
1115 8977f3c1 bellard
        return;
1116 8977f3c1 bellard
    case 3:
1117 8977f3c1 bellard
        /* track too big */
1118 77370520 blueswir1
        fdctrl_stop_transfer(fdctrl, FD_SR0_ABNTERM, FD_SR1_EC, 0x00);
1119 baca51fa bellard
        fdctrl->fifo[3] = kt;
1120 baca51fa bellard
        fdctrl->fifo[4] = kh;
1121 baca51fa bellard
        fdctrl->fifo[5] = ks;
1122 8977f3c1 bellard
        return;
1123 8977f3c1 bellard
    case 4:
1124 8977f3c1 bellard
        /* No seek enabled */
1125 9fea808a blueswir1
        fdctrl_stop_transfer(fdctrl, FD_SR0_ABNTERM, 0x00, 0x00);
1126 baca51fa bellard
        fdctrl->fifo[3] = kt;
1127 baca51fa bellard
        fdctrl->fifo[4] = kh;
1128 baca51fa bellard
        fdctrl->fifo[5] = ks;
1129 8977f3c1 bellard
        return;
1130 8977f3c1 bellard
    case 1:
1131 8977f3c1 bellard
        did_seek = 1;
1132 8977f3c1 bellard
        break;
1133 8977f3c1 bellard
    default:
1134 8977f3c1 bellard
        break;
1135 8977f3c1 bellard
    }
1136 b9b3d225 blueswir1
1137 8977f3c1 bellard
    /* Set the FIFO state */
1138 baca51fa bellard
    fdctrl->data_dir = direction;
1139 baca51fa bellard
    fdctrl->data_pos = 0;
1140 b9b3d225 blueswir1
    fdctrl->msr |= FD_MSR_CMDBUSY;
1141 baca51fa bellard
    if (fdctrl->fifo[0] & 0x80)
1142 baca51fa bellard
        fdctrl->data_state |= FD_STATE_MULTI;
1143 baca51fa bellard
    else
1144 baca51fa bellard
        fdctrl->data_state &= ~FD_STATE_MULTI;
1145 8977f3c1 bellard
    if (did_seek)
1146 baca51fa bellard
        fdctrl->data_state |= FD_STATE_SEEK;
1147 baca51fa bellard
    else
1148 baca51fa bellard
        fdctrl->data_state &= ~FD_STATE_SEEK;
1149 baca51fa bellard
    if (fdctrl->fifo[5] == 00) {
1150 baca51fa bellard
        fdctrl->data_len = fdctrl->fifo[8];
1151 baca51fa bellard
    } else {
1152 4f431960 j_mayer
        int tmp;
1153 3bcb80f1 ths
        fdctrl->data_len = 128 << (fdctrl->fifo[5] > 7 ? 7 : fdctrl->fifo[5]);
1154 771effeb blueswir1
        tmp = (fdctrl->fifo[6] - ks + 1);
1155 baca51fa bellard
        if (fdctrl->fifo[0] & 0x80)
1156 771effeb blueswir1
            tmp += fdctrl->fifo[6];
1157 4f431960 j_mayer
        fdctrl->data_len *= tmp;
1158 baca51fa bellard
    }
1159 890fa6be bellard
    fdctrl->eot = fdctrl->fifo[6];
1160 368df94d blueswir1
    if (fdctrl->dor & FD_DOR_DMAEN) {
1161 8977f3c1 bellard
        int dma_mode;
1162 8977f3c1 bellard
        /* DMA transfer are enabled. Check if DMA channel is well programmed */
1163 baca51fa bellard
        dma_mode = DMA_get_channel_mode(fdctrl->dma_chann);
1164 8977f3c1 bellard
        dma_mode = (dma_mode >> 2) & 3;
1165 baca51fa bellard
        FLOPPY_DPRINTF("dma_mode=%d direction=%d (%d - %d)\n",
1166 4f431960 j_mayer
                       dma_mode, direction,
1167 baca51fa bellard
                       (128 << fdctrl->fifo[5]) *
1168 4f431960 j_mayer
                       (cur_drv->last_sect - ks + 1), fdctrl->data_len);
1169 8977f3c1 bellard
        if (((direction == FD_DIR_SCANE || direction == FD_DIR_SCANL ||
1170 8977f3c1 bellard
              direction == FD_DIR_SCANH) && dma_mode == 0) ||
1171 8977f3c1 bellard
            (direction == FD_DIR_WRITE && dma_mode == 2) ||
1172 8977f3c1 bellard
            (direction == FD_DIR_READ && dma_mode == 1)) {
1173 8977f3c1 bellard
            /* No access is allowed until DMA transfer has completed */
1174 b9b3d225 blueswir1
            fdctrl->msr &= ~FD_MSR_RQM;
1175 4b19ec0c bellard
            /* Now, we just have to wait for the DMA controller to
1176 8977f3c1 bellard
             * recall us...
1177 8977f3c1 bellard
             */
1178 baca51fa bellard
            DMA_hold_DREQ(fdctrl->dma_chann);
1179 baca51fa bellard
            DMA_schedule(fdctrl->dma_chann);
1180 8977f3c1 bellard
            return;
1181 baca51fa bellard
        } else {
1182 4f431960 j_mayer
            FLOPPY_ERROR("dma_mode=%d direction=%d\n", dma_mode, direction);
1183 8977f3c1 bellard
        }
1184 8977f3c1 bellard
    }
1185 8977f3c1 bellard
    FLOPPY_DPRINTF("start non-DMA transfer\n");
1186 368df94d blueswir1
    fdctrl->msr |= FD_MSR_NONDMA;
1187 b9b3d225 blueswir1
    if (direction != FD_DIR_WRITE)
1188 b9b3d225 blueswir1
        fdctrl->msr |= FD_MSR_DIO;
1189 8977f3c1 bellard
    /* IO based transfer: calculate len */
1190 baca51fa bellard
    fdctrl_raise_irq(fdctrl, 0x00);
1191 8977f3c1 bellard
1192 8977f3c1 bellard
    return;
1193 8977f3c1 bellard
}
1194 8977f3c1 bellard
1195 8977f3c1 bellard
/* Prepare a transfer of deleted data */
1196 5c02c033 Blue Swirl
static void fdctrl_start_transfer_del(FDCtrl *fdctrl, int direction)
1197 8977f3c1 bellard
{
1198 77370520 blueswir1
    FLOPPY_ERROR("fdctrl_start_transfer_del() unimplemented\n");
1199 77370520 blueswir1
1200 8977f3c1 bellard
    /* We don't handle deleted data,
1201 8977f3c1 bellard
     * so we don't return *ANYTHING*
1202 8977f3c1 bellard
     */
1203 9fea808a blueswir1
    fdctrl_stop_transfer(fdctrl, FD_SR0_ABNTERM | FD_SR0_SEEK, 0x00, 0x00);
1204 8977f3c1 bellard
}
1205 8977f3c1 bellard
1206 8977f3c1 bellard
/* handlers for DMA transfers */
1207 85571bc7 bellard
static int fdctrl_transfer_handler (void *opaque, int nchan,
1208 85571bc7 bellard
                                    int dma_pos, int dma_len)
1209 8977f3c1 bellard
{
1210 5c02c033 Blue Swirl
    FDCtrl *fdctrl;
1211 5c02c033 Blue Swirl
    FDrive *cur_drv;
1212 baca51fa bellard
    int len, start_pos, rel_pos;
1213 8977f3c1 bellard
    uint8_t status0 = 0x00, status1 = 0x00, status2 = 0x00;
1214 8977f3c1 bellard
1215 baca51fa bellard
    fdctrl = opaque;
1216 b9b3d225 blueswir1
    if (fdctrl->msr & FD_MSR_RQM) {
1217 8977f3c1 bellard
        FLOPPY_DPRINTF("Not in DMA transfer mode !\n");
1218 8977f3c1 bellard
        return 0;
1219 8977f3c1 bellard
    }
1220 baca51fa bellard
    cur_drv = get_cur_drv(fdctrl);
1221 baca51fa bellard
    if (fdctrl->data_dir == FD_DIR_SCANE || fdctrl->data_dir == FD_DIR_SCANL ||
1222 baca51fa bellard
        fdctrl->data_dir == FD_DIR_SCANH)
1223 77370520 blueswir1
        status2 = FD_SR2_SNS;
1224 85571bc7 bellard
    if (dma_len > fdctrl->data_len)
1225 85571bc7 bellard
        dma_len = fdctrl->data_len;
1226 890fa6be bellard
    if (cur_drv->bs == NULL) {
1227 4f431960 j_mayer
        if (fdctrl->data_dir == FD_DIR_WRITE)
1228 9fea808a blueswir1
            fdctrl_stop_transfer(fdctrl, FD_SR0_ABNTERM | FD_SR0_SEEK, 0x00, 0x00);
1229 4f431960 j_mayer
        else
1230 9fea808a blueswir1
            fdctrl_stop_transfer(fdctrl, FD_SR0_ABNTERM, 0x00, 0x00);
1231 4f431960 j_mayer
        len = 0;
1232 890fa6be bellard
        goto transfer_error;
1233 890fa6be bellard
    }
1234 baca51fa bellard
    rel_pos = fdctrl->data_pos % FD_SECTOR_LEN;
1235 85571bc7 bellard
    for (start_pos = fdctrl->data_pos; fdctrl->data_pos < dma_len;) {
1236 85571bc7 bellard
        len = dma_len - fdctrl->data_pos;
1237 baca51fa bellard
        if (len + rel_pos > FD_SECTOR_LEN)
1238 baca51fa bellard
            len = FD_SECTOR_LEN - rel_pos;
1239 6f7e9aec bellard
        FLOPPY_DPRINTF("copy %d bytes (%d %d %d) %d pos %d %02x "
1240 6f7e9aec bellard
                       "(%d-0x%08x 0x%08x)\n", len, dma_len, fdctrl->data_pos,
1241 cefec4f5 blueswir1
                       fdctrl->data_len, GET_CUR_DRV(fdctrl), cur_drv->head,
1242 baca51fa bellard
                       cur_drv->track, cur_drv->sect, fd_sector(cur_drv),
1243 9fea808a blueswir1
                       fd_sector(cur_drv) * FD_SECTOR_LEN);
1244 baca51fa bellard
        if (fdctrl->data_dir != FD_DIR_WRITE ||
1245 4f431960 j_mayer
            len < FD_SECTOR_LEN || rel_pos != 0) {
1246 baca51fa bellard
            /* READ & SCAN commands and realign to a sector for WRITE */
1247 baca51fa bellard
            if (bdrv_read(cur_drv->bs, fd_sector(cur_drv),
1248 4f431960 j_mayer
                          fdctrl->fifo, 1) < 0) {
1249 8977f3c1 bellard
                FLOPPY_DPRINTF("Floppy: error getting sector %d\n",
1250 8977f3c1 bellard
                               fd_sector(cur_drv));
1251 8977f3c1 bellard
                /* Sure, image size is too small... */
1252 baca51fa bellard
                memset(fdctrl->fifo, 0, FD_SECTOR_LEN);
1253 8977f3c1 bellard
            }
1254 890fa6be bellard
        }
1255 4f431960 j_mayer
        switch (fdctrl->data_dir) {
1256 4f431960 j_mayer
        case FD_DIR_READ:
1257 4f431960 j_mayer
            /* READ commands */
1258 85571bc7 bellard
            DMA_write_memory (nchan, fdctrl->fifo + rel_pos,
1259 85571bc7 bellard
                              fdctrl->data_pos, len);
1260 4f431960 j_mayer
            break;
1261 4f431960 j_mayer
        case FD_DIR_WRITE:
1262 baca51fa bellard
            /* WRITE commands */
1263 85571bc7 bellard
            DMA_read_memory (nchan, fdctrl->fifo + rel_pos,
1264 85571bc7 bellard
                             fdctrl->data_pos, len);
1265 baca51fa bellard
            if (bdrv_write(cur_drv->bs, fd_sector(cur_drv),
1266 4f431960 j_mayer
                           fdctrl->fifo, 1) < 0) {
1267 77370520 blueswir1
                FLOPPY_ERROR("writing sector %d\n", fd_sector(cur_drv));
1268 9fea808a blueswir1
                fdctrl_stop_transfer(fdctrl, FD_SR0_ABNTERM | FD_SR0_SEEK, 0x00, 0x00);
1269 baca51fa bellard
                goto transfer_error;
1270 890fa6be bellard
            }
1271 4f431960 j_mayer
            break;
1272 4f431960 j_mayer
        default:
1273 4f431960 j_mayer
            /* SCAN commands */
1274 baca51fa bellard
            {
1275 4f431960 j_mayer
                uint8_t tmpbuf[FD_SECTOR_LEN];
1276 baca51fa bellard
                int ret;
1277 85571bc7 bellard
                DMA_read_memory (nchan, tmpbuf, fdctrl->data_pos, len);
1278 baca51fa bellard
                ret = memcmp(tmpbuf, fdctrl->fifo + rel_pos, len);
1279 8977f3c1 bellard
                if (ret == 0) {
1280 77370520 blueswir1
                    status2 = FD_SR2_SEH;
1281 8977f3c1 bellard
                    goto end_transfer;
1282 8977f3c1 bellard
                }
1283 baca51fa bellard
                if ((ret < 0 && fdctrl->data_dir == FD_DIR_SCANL) ||
1284 baca51fa bellard
                    (ret > 0 && fdctrl->data_dir == FD_DIR_SCANH)) {
1285 8977f3c1 bellard
                    status2 = 0x00;
1286 8977f3c1 bellard
                    goto end_transfer;
1287 8977f3c1 bellard
                }
1288 8977f3c1 bellard
            }
1289 4f431960 j_mayer
            break;
1290 8977f3c1 bellard
        }
1291 4f431960 j_mayer
        fdctrl->data_pos += len;
1292 4f431960 j_mayer
        rel_pos = fdctrl->data_pos % FD_SECTOR_LEN;
1293 baca51fa bellard
        if (rel_pos == 0) {
1294 8977f3c1 bellard
            /* Seek to next sector */
1295 746d6de7 blueswir1
            if (!fdctrl_seek_to_next_sect(fdctrl, cur_drv))
1296 746d6de7 blueswir1
                break;
1297 8977f3c1 bellard
        }
1298 8977f3c1 bellard
    }
1299 4f431960 j_mayer
 end_transfer:
1300 baca51fa bellard
    len = fdctrl->data_pos - start_pos;
1301 baca51fa bellard
    FLOPPY_DPRINTF("end transfer %d %d %d\n",
1302 4f431960 j_mayer
                   fdctrl->data_pos, len, fdctrl->data_len);
1303 baca51fa bellard
    if (fdctrl->data_dir == FD_DIR_SCANE ||
1304 baca51fa bellard
        fdctrl->data_dir == FD_DIR_SCANL ||
1305 baca51fa bellard
        fdctrl->data_dir == FD_DIR_SCANH)
1306 77370520 blueswir1
        status2 = FD_SR2_SEH;
1307 baca51fa bellard
    if (FD_DID_SEEK(fdctrl->data_state))
1308 9fea808a blueswir1
        status0 |= FD_SR0_SEEK;
1309 baca51fa bellard
    fdctrl->data_len -= len;
1310 890fa6be bellard
    fdctrl_stop_transfer(fdctrl, status0, status1, status2);
1311 4f431960 j_mayer
 transfer_error:
1312 8977f3c1 bellard
1313 baca51fa bellard
    return len;
1314 8977f3c1 bellard
}
1315 8977f3c1 bellard
1316 8977f3c1 bellard
/* Data register : 0x05 */
1317 5c02c033 Blue Swirl
static uint32_t fdctrl_read_data(FDCtrl *fdctrl)
1318 8977f3c1 bellard
{
1319 5c02c033 Blue Swirl
    FDrive *cur_drv;
1320 8977f3c1 bellard
    uint32_t retval = 0;
1321 746d6de7 blueswir1
    int pos;
1322 8977f3c1 bellard
1323 baca51fa bellard
    cur_drv = get_cur_drv(fdctrl);
1324 b9b3d225 blueswir1
    fdctrl->dsr &= ~FD_DSR_PWRDOWN;
1325 b9b3d225 blueswir1
    if (!(fdctrl->msr & FD_MSR_RQM) || !(fdctrl->msr & FD_MSR_DIO)) {
1326 b9b3d225 blueswir1
        FLOPPY_ERROR("controller not ready for reading\n");
1327 8977f3c1 bellard
        return 0;
1328 8977f3c1 bellard
    }
1329 baca51fa bellard
    pos = fdctrl->data_pos;
1330 368df94d blueswir1
    if (fdctrl->msr & FD_MSR_NONDMA) {
1331 8977f3c1 bellard
        pos %= FD_SECTOR_LEN;
1332 8977f3c1 bellard
        if (pos == 0) {
1333 746d6de7 blueswir1
            if (fdctrl->data_pos != 0)
1334 746d6de7 blueswir1
                if (!fdctrl_seek_to_next_sect(fdctrl, cur_drv)) {
1335 746d6de7 blueswir1
                    FLOPPY_DPRINTF("error seeking to next sector %d\n",
1336 746d6de7 blueswir1
                                   fd_sector(cur_drv));
1337 746d6de7 blueswir1
                    return 0;
1338 746d6de7 blueswir1
                }
1339 77370520 blueswir1
            if (bdrv_read(cur_drv->bs, fd_sector(cur_drv), fdctrl->fifo, 1) < 0) {
1340 77370520 blueswir1
                FLOPPY_DPRINTF("error getting sector %d\n",
1341 77370520 blueswir1
                               fd_sector(cur_drv));
1342 77370520 blueswir1
                /* Sure, image size is too small... */
1343 77370520 blueswir1
                memset(fdctrl->fifo, 0, FD_SECTOR_LEN);
1344 77370520 blueswir1
            }
1345 8977f3c1 bellard
        }
1346 8977f3c1 bellard
    }
1347 baca51fa bellard
    retval = fdctrl->fifo[pos];
1348 baca51fa bellard
    if (++fdctrl->data_pos == fdctrl->data_len) {
1349 baca51fa bellard
        fdctrl->data_pos = 0;
1350 890fa6be bellard
        /* Switch from transfer mode to status mode
1351 8977f3c1 bellard
         * then from status mode to command mode
1352 8977f3c1 bellard
         */
1353 368df94d blueswir1
        if (fdctrl->msr & FD_MSR_NONDMA) {
1354 9fea808a blueswir1
            fdctrl_stop_transfer(fdctrl, FD_SR0_SEEK, 0x00, 0x00);
1355 ed5fd2cc bellard
        } else {
1356 baca51fa bellard
            fdctrl_reset_fifo(fdctrl);
1357 ed5fd2cc bellard
            fdctrl_reset_irq(fdctrl);
1358 ed5fd2cc bellard
        }
1359 8977f3c1 bellard
    }
1360 8977f3c1 bellard
    FLOPPY_DPRINTF("data register: 0x%02x\n", retval);
1361 8977f3c1 bellard
1362 8977f3c1 bellard
    return retval;
1363 8977f3c1 bellard
}
1364 8977f3c1 bellard
1365 5c02c033 Blue Swirl
static void fdctrl_format_sector(FDCtrl *fdctrl)
1366 8977f3c1 bellard
{
1367 5c02c033 Blue Swirl
    FDrive *cur_drv;
1368 baca51fa bellard
    uint8_t kh, kt, ks;
1369 8977f3c1 bellard
1370 cefec4f5 blueswir1
    SET_CUR_DRV(fdctrl, fdctrl->fifo[1] & FD_DOR_SELMASK);
1371 baca51fa bellard
    cur_drv = get_cur_drv(fdctrl);
1372 baca51fa bellard
    kt = fdctrl->fifo[6];
1373 baca51fa bellard
    kh = fdctrl->fifo[7];
1374 baca51fa bellard
    ks = fdctrl->fifo[8];
1375 baca51fa bellard
    FLOPPY_DPRINTF("format sector at %d %d %02x %02x (%d)\n",
1376 cefec4f5 blueswir1
                   GET_CUR_DRV(fdctrl), kh, kt, ks,
1377 7859cb98 Blue Swirl
                   fd_sector_calc(kh, kt, ks, cur_drv->last_sect));
1378 9fea808a blueswir1
    switch (fd_seek(cur_drv, kh, kt, ks, fdctrl->config & FD_CONFIG_EIS)) {
1379 baca51fa bellard
    case 2:
1380 baca51fa bellard
        /* sect too big */
1381 9fea808a blueswir1
        fdctrl_stop_transfer(fdctrl, FD_SR0_ABNTERM, 0x00, 0x00);
1382 baca51fa bellard
        fdctrl->fifo[3] = kt;
1383 baca51fa bellard
        fdctrl->fifo[4] = kh;
1384 baca51fa bellard
        fdctrl->fifo[5] = ks;
1385 baca51fa bellard
        return;
1386 baca51fa bellard
    case 3:
1387 baca51fa bellard
        /* track too big */
1388 77370520 blueswir1
        fdctrl_stop_transfer(fdctrl, FD_SR0_ABNTERM, FD_SR1_EC, 0x00);
1389 baca51fa bellard
        fdctrl->fifo[3] = kt;
1390 baca51fa bellard
        fdctrl->fifo[4] = kh;
1391 baca51fa bellard
        fdctrl->fifo[5] = ks;
1392 baca51fa bellard
        return;
1393 baca51fa bellard
    case 4:
1394 baca51fa bellard
        /* No seek enabled */
1395 9fea808a blueswir1
        fdctrl_stop_transfer(fdctrl, FD_SR0_ABNTERM, 0x00, 0x00);
1396 baca51fa bellard
        fdctrl->fifo[3] = kt;
1397 baca51fa bellard
        fdctrl->fifo[4] = kh;
1398 baca51fa bellard
        fdctrl->fifo[5] = ks;
1399 baca51fa bellard
        return;
1400 baca51fa bellard
    case 1:
1401 baca51fa bellard
        fdctrl->data_state |= FD_STATE_SEEK;
1402 baca51fa bellard
        break;
1403 baca51fa bellard
    default:
1404 baca51fa bellard
        break;
1405 baca51fa bellard
    }
1406 baca51fa bellard
    memset(fdctrl->fifo, 0, FD_SECTOR_LEN);
1407 baca51fa bellard
    if (cur_drv->bs == NULL ||
1408 baca51fa bellard
        bdrv_write(cur_drv->bs, fd_sector(cur_drv), fdctrl->fifo, 1) < 0) {
1409 37a4c539 ths
        FLOPPY_ERROR("formatting sector %d\n", fd_sector(cur_drv));
1410 9fea808a blueswir1
        fdctrl_stop_transfer(fdctrl, FD_SR0_ABNTERM | FD_SR0_SEEK, 0x00, 0x00);
1411 baca51fa bellard
    } else {
1412 4f431960 j_mayer
        if (cur_drv->sect == cur_drv->last_sect) {
1413 4f431960 j_mayer
            fdctrl->data_state &= ~FD_STATE_FORMAT;
1414 4f431960 j_mayer
            /* Last sector done */
1415 4f431960 j_mayer
            if (FD_DID_SEEK(fdctrl->data_state))
1416 9fea808a blueswir1
                fdctrl_stop_transfer(fdctrl, FD_SR0_SEEK, 0x00, 0x00);
1417 4f431960 j_mayer
            else
1418 4f431960 j_mayer
                fdctrl_stop_transfer(fdctrl, 0x00, 0x00, 0x00);
1419 4f431960 j_mayer
        } else {
1420 4f431960 j_mayer
            /* More to do */
1421 4f431960 j_mayer
            fdctrl->data_pos = 0;
1422 4f431960 j_mayer
            fdctrl->data_len = 4;
1423 4f431960 j_mayer
        }
1424 baca51fa bellard
    }
1425 baca51fa bellard
}
1426 baca51fa bellard
1427 5c02c033 Blue Swirl
static void fdctrl_handle_lock(FDCtrl *fdctrl, int direction)
1428 65cef780 blueswir1
{
1429 65cef780 blueswir1
    fdctrl->lock = (fdctrl->fifo[0] & 0x80) ? 1 : 0;
1430 65cef780 blueswir1
    fdctrl->fifo[0] = fdctrl->lock << 4;
1431 65cef780 blueswir1
    fdctrl_set_fifo(fdctrl, 1, fdctrl->lock);
1432 65cef780 blueswir1
}
1433 65cef780 blueswir1
1434 5c02c033 Blue Swirl
static void fdctrl_handle_dumpreg(FDCtrl *fdctrl, int direction)
1435 65cef780 blueswir1
{
1436 5c02c033 Blue Swirl
    FDrive *cur_drv = get_cur_drv(fdctrl);
1437 65cef780 blueswir1
1438 65cef780 blueswir1
    /* Drives position */
1439 65cef780 blueswir1
    fdctrl->fifo[0] = drv0(fdctrl)->track;
1440 65cef780 blueswir1
    fdctrl->fifo[1] = drv1(fdctrl)->track;
1441 78ae820c blueswir1
#if MAX_FD == 4
1442 78ae820c blueswir1
    fdctrl->fifo[2] = drv2(fdctrl)->track;
1443 78ae820c blueswir1
    fdctrl->fifo[3] = drv3(fdctrl)->track;
1444 78ae820c blueswir1
#else
1445 65cef780 blueswir1
    fdctrl->fifo[2] = 0;
1446 65cef780 blueswir1
    fdctrl->fifo[3] = 0;
1447 78ae820c blueswir1
#endif
1448 65cef780 blueswir1
    /* timers */
1449 65cef780 blueswir1
    fdctrl->fifo[4] = fdctrl->timer0;
1450 368df94d blueswir1
    fdctrl->fifo[5] = (fdctrl->timer1 << 1) | (fdctrl->dor & FD_DOR_DMAEN ? 1 : 0);
1451 65cef780 blueswir1
    fdctrl->fifo[6] = cur_drv->last_sect;
1452 65cef780 blueswir1
    fdctrl->fifo[7] = (fdctrl->lock << 7) |
1453 65cef780 blueswir1
        (cur_drv->perpendicular << 2);
1454 65cef780 blueswir1
    fdctrl->fifo[8] = fdctrl->config;
1455 65cef780 blueswir1
    fdctrl->fifo[9] = fdctrl->precomp_trk;
1456 65cef780 blueswir1
    fdctrl_set_fifo(fdctrl, 10, 0);
1457 65cef780 blueswir1
}
1458 65cef780 blueswir1
1459 5c02c033 Blue Swirl
static void fdctrl_handle_version(FDCtrl *fdctrl, int direction)
1460 65cef780 blueswir1
{
1461 65cef780 blueswir1
    /* Controller's version */
1462 65cef780 blueswir1
    fdctrl->fifo[0] = fdctrl->version;
1463 65cef780 blueswir1
    fdctrl_set_fifo(fdctrl, 1, 1);
1464 65cef780 blueswir1
}
1465 65cef780 blueswir1
1466 5c02c033 Blue Swirl
static void fdctrl_handle_partid(FDCtrl *fdctrl, int direction)
1467 65cef780 blueswir1
{
1468 65cef780 blueswir1
    fdctrl->fifo[0] = 0x41; /* Stepping 1 */
1469 65cef780 blueswir1
    fdctrl_set_fifo(fdctrl, 1, 0);
1470 65cef780 blueswir1
}
1471 65cef780 blueswir1
1472 5c02c033 Blue Swirl
static void fdctrl_handle_restore(FDCtrl *fdctrl, int direction)
1473 65cef780 blueswir1
{
1474 5c02c033 Blue Swirl
    FDrive *cur_drv = get_cur_drv(fdctrl);
1475 65cef780 blueswir1
1476 65cef780 blueswir1
    /* Drives position */
1477 65cef780 blueswir1
    drv0(fdctrl)->track = fdctrl->fifo[3];
1478 65cef780 blueswir1
    drv1(fdctrl)->track = fdctrl->fifo[4];
1479 78ae820c blueswir1
#if MAX_FD == 4
1480 78ae820c blueswir1
    drv2(fdctrl)->track = fdctrl->fifo[5];
1481 78ae820c blueswir1
    drv3(fdctrl)->track = fdctrl->fifo[6];
1482 78ae820c blueswir1
#endif
1483 65cef780 blueswir1
    /* timers */
1484 65cef780 blueswir1
    fdctrl->timer0 = fdctrl->fifo[7];
1485 65cef780 blueswir1
    fdctrl->timer1 = fdctrl->fifo[8];
1486 65cef780 blueswir1
    cur_drv->last_sect = fdctrl->fifo[9];
1487 65cef780 blueswir1
    fdctrl->lock = fdctrl->fifo[10] >> 7;
1488 65cef780 blueswir1
    cur_drv->perpendicular = (fdctrl->fifo[10] >> 2) & 0xF;
1489 65cef780 blueswir1
    fdctrl->config = fdctrl->fifo[11];
1490 65cef780 blueswir1
    fdctrl->precomp_trk = fdctrl->fifo[12];
1491 65cef780 blueswir1
    fdctrl->pwrd = fdctrl->fifo[13];
1492 65cef780 blueswir1
    fdctrl_reset_fifo(fdctrl);
1493 65cef780 blueswir1
}
1494 65cef780 blueswir1
1495 5c02c033 Blue Swirl
static void fdctrl_handle_save(FDCtrl *fdctrl, int direction)
1496 65cef780 blueswir1
{
1497 5c02c033 Blue Swirl
    FDrive *cur_drv = get_cur_drv(fdctrl);
1498 65cef780 blueswir1
1499 65cef780 blueswir1
    fdctrl->fifo[0] = 0;
1500 65cef780 blueswir1
    fdctrl->fifo[1] = 0;
1501 65cef780 blueswir1
    /* Drives position */
1502 65cef780 blueswir1
    fdctrl->fifo[2] = drv0(fdctrl)->track;
1503 65cef780 blueswir1
    fdctrl->fifo[3] = drv1(fdctrl)->track;
1504 78ae820c blueswir1
#if MAX_FD == 4
1505 78ae820c blueswir1
    fdctrl->fifo[4] = drv2(fdctrl)->track;
1506 78ae820c blueswir1
    fdctrl->fifo[5] = drv3(fdctrl)->track;
1507 78ae820c blueswir1
#else
1508 65cef780 blueswir1
    fdctrl->fifo[4] = 0;
1509 65cef780 blueswir1
    fdctrl->fifo[5] = 0;
1510 78ae820c blueswir1
#endif
1511 65cef780 blueswir1
    /* timers */
1512 65cef780 blueswir1
    fdctrl->fifo[6] = fdctrl->timer0;
1513 65cef780 blueswir1
    fdctrl->fifo[7] = fdctrl->timer1;
1514 65cef780 blueswir1
    fdctrl->fifo[8] = cur_drv->last_sect;
1515 65cef780 blueswir1
    fdctrl->fifo[9] = (fdctrl->lock << 7) |
1516 65cef780 blueswir1
        (cur_drv->perpendicular << 2);
1517 65cef780 blueswir1
    fdctrl->fifo[10] = fdctrl->config;
1518 65cef780 blueswir1
    fdctrl->fifo[11] = fdctrl->precomp_trk;
1519 65cef780 blueswir1
    fdctrl->fifo[12] = fdctrl->pwrd;
1520 65cef780 blueswir1
    fdctrl->fifo[13] = 0;
1521 65cef780 blueswir1
    fdctrl->fifo[14] = 0;
1522 65cef780 blueswir1
    fdctrl_set_fifo(fdctrl, 15, 1);
1523 65cef780 blueswir1
}
1524 65cef780 blueswir1
1525 5c02c033 Blue Swirl
static void fdctrl_handle_readid(FDCtrl *fdctrl, int direction)
1526 65cef780 blueswir1
{
1527 5c02c033 Blue Swirl
    FDrive *cur_drv = get_cur_drv(fdctrl);
1528 65cef780 blueswir1
1529 65cef780 blueswir1
    /* XXX: should set main status register to busy */
1530 65cef780 blueswir1
    cur_drv->head = (fdctrl->fifo[1] >> 2) & 1;
1531 65cef780 blueswir1
    qemu_mod_timer(fdctrl->result_timer,
1532 6ee093c9 Juan Quintela
                   qemu_get_clock(vm_clock) + (get_ticks_per_sec() / 50));
1533 65cef780 blueswir1
}
1534 65cef780 blueswir1
1535 5c02c033 Blue Swirl
static void fdctrl_handle_format_track(FDCtrl *fdctrl, int direction)
1536 65cef780 blueswir1
{
1537 5c02c033 Blue Swirl
    FDrive *cur_drv;
1538 65cef780 blueswir1
1539 cefec4f5 blueswir1
    SET_CUR_DRV(fdctrl, fdctrl->fifo[1] & FD_DOR_SELMASK);
1540 65cef780 blueswir1
    cur_drv = get_cur_drv(fdctrl);
1541 65cef780 blueswir1
    fdctrl->data_state |= FD_STATE_FORMAT;
1542 65cef780 blueswir1
    if (fdctrl->fifo[0] & 0x80)
1543 65cef780 blueswir1
        fdctrl->data_state |= FD_STATE_MULTI;
1544 65cef780 blueswir1
    else
1545 65cef780 blueswir1
        fdctrl->data_state &= ~FD_STATE_MULTI;
1546 65cef780 blueswir1
    fdctrl->data_state &= ~FD_STATE_SEEK;
1547 65cef780 blueswir1
    cur_drv->bps =
1548 65cef780 blueswir1
        fdctrl->fifo[2] > 7 ? 16384 : 128 << fdctrl->fifo[2];
1549 65cef780 blueswir1
#if 0
1550 65cef780 blueswir1
    cur_drv->last_sect =
1551 65cef780 blueswir1
        cur_drv->flags & FDISK_DBL_SIDES ? fdctrl->fifo[3] :
1552 65cef780 blueswir1
        fdctrl->fifo[3] / 2;
1553 65cef780 blueswir1
#else
1554 65cef780 blueswir1
    cur_drv->last_sect = fdctrl->fifo[3];
1555 65cef780 blueswir1
#endif
1556 65cef780 blueswir1
    /* TODO: implement format using DMA expected by the Bochs BIOS
1557 65cef780 blueswir1
     * and Linux fdformat (read 3 bytes per sector via DMA and fill
1558 65cef780 blueswir1
     * the sector with the specified fill byte
1559 65cef780 blueswir1
     */
1560 65cef780 blueswir1
    fdctrl->data_state &= ~FD_STATE_FORMAT;
1561 65cef780 blueswir1
    fdctrl_stop_transfer(fdctrl, 0x00, 0x00, 0x00);
1562 65cef780 blueswir1
}
1563 65cef780 blueswir1
1564 5c02c033 Blue Swirl
static void fdctrl_handle_specify(FDCtrl *fdctrl, int direction)
1565 65cef780 blueswir1
{
1566 65cef780 blueswir1
    fdctrl->timer0 = (fdctrl->fifo[1] >> 4) & 0xF;
1567 65cef780 blueswir1
    fdctrl->timer1 = fdctrl->fifo[2] >> 1;
1568 368df94d blueswir1
    if (fdctrl->fifo[2] & 1)
1569 368df94d blueswir1
        fdctrl->dor &= ~FD_DOR_DMAEN;
1570 368df94d blueswir1
    else
1571 368df94d blueswir1
        fdctrl->dor |= FD_DOR_DMAEN;
1572 65cef780 blueswir1
    /* No result back */
1573 65cef780 blueswir1
    fdctrl_reset_fifo(fdctrl);
1574 65cef780 blueswir1
}
1575 65cef780 blueswir1
1576 5c02c033 Blue Swirl
static void fdctrl_handle_sense_drive_status(FDCtrl *fdctrl, int direction)
1577 65cef780 blueswir1
{
1578 5c02c033 Blue Swirl
    FDrive *cur_drv;
1579 65cef780 blueswir1
1580 cefec4f5 blueswir1
    SET_CUR_DRV(fdctrl, fdctrl->fifo[1] & FD_DOR_SELMASK);
1581 65cef780 blueswir1
    cur_drv = get_cur_drv(fdctrl);
1582 65cef780 blueswir1
    cur_drv->head = (fdctrl->fifo[1] >> 2) & 1;
1583 65cef780 blueswir1
    /* 1 Byte status back */
1584 65cef780 blueswir1
    fdctrl->fifo[0] = (cur_drv->ro << 6) |
1585 65cef780 blueswir1
        (cur_drv->track == 0 ? 0x10 : 0x00) |
1586 65cef780 blueswir1
        (cur_drv->head << 2) |
1587 cefec4f5 blueswir1
        GET_CUR_DRV(fdctrl) |
1588 65cef780 blueswir1
        0x28;
1589 65cef780 blueswir1
    fdctrl_set_fifo(fdctrl, 1, 0);
1590 65cef780 blueswir1
}
1591 65cef780 blueswir1
1592 5c02c033 Blue Swirl
static void fdctrl_handle_recalibrate(FDCtrl *fdctrl, int direction)
1593 65cef780 blueswir1
{
1594 5c02c033 Blue Swirl
    FDrive *cur_drv;
1595 65cef780 blueswir1
1596 cefec4f5 blueswir1
    SET_CUR_DRV(fdctrl, fdctrl->fifo[1] & FD_DOR_SELMASK);
1597 65cef780 blueswir1
    cur_drv = get_cur_drv(fdctrl);
1598 65cef780 blueswir1
    fd_recalibrate(cur_drv);
1599 65cef780 blueswir1
    fdctrl_reset_fifo(fdctrl);
1600 65cef780 blueswir1
    /* Raise Interrupt */
1601 65cef780 blueswir1
    fdctrl_raise_irq(fdctrl, FD_SR0_SEEK);
1602 65cef780 blueswir1
}
1603 65cef780 blueswir1
1604 5c02c033 Blue Swirl
static void fdctrl_handle_sense_interrupt_status(FDCtrl *fdctrl, int direction)
1605 65cef780 blueswir1
{
1606 5c02c033 Blue Swirl
    FDrive *cur_drv = get_cur_drv(fdctrl);
1607 65cef780 blueswir1
1608 f2d81b33 blueswir1
    if(fdctrl->reset_sensei > 0) {
1609 f2d81b33 blueswir1
        fdctrl->fifo[0] =
1610 f2d81b33 blueswir1
            FD_SR0_RDYCHG + FD_RESET_SENSEI_COUNT - fdctrl->reset_sensei;
1611 f2d81b33 blueswir1
        fdctrl->reset_sensei--;
1612 f2d81b33 blueswir1
    } else {
1613 f2d81b33 blueswir1
        /* XXX: status0 handling is broken for read/write
1614 f2d81b33 blueswir1
           commands, so we do this hack. It should be suppressed
1615 f2d81b33 blueswir1
           ASAP */
1616 f2d81b33 blueswir1
        fdctrl->fifo[0] =
1617 f2d81b33 blueswir1
            FD_SR0_SEEK | (cur_drv->head << 2) | GET_CUR_DRV(fdctrl);
1618 f2d81b33 blueswir1
    }
1619 f2d81b33 blueswir1
1620 65cef780 blueswir1
    fdctrl->fifo[1] = cur_drv->track;
1621 65cef780 blueswir1
    fdctrl_set_fifo(fdctrl, 2, 0);
1622 65cef780 blueswir1
    fdctrl_reset_irq(fdctrl);
1623 77370520 blueswir1
    fdctrl->status0 = FD_SR0_RDYCHG;
1624 65cef780 blueswir1
}
1625 65cef780 blueswir1
1626 5c02c033 Blue Swirl
static void fdctrl_handle_seek(FDCtrl *fdctrl, int direction)
1627 65cef780 blueswir1
{
1628 5c02c033 Blue Swirl
    FDrive *cur_drv;
1629 65cef780 blueswir1
1630 cefec4f5 blueswir1
    SET_CUR_DRV(fdctrl, fdctrl->fifo[1] & FD_DOR_SELMASK);
1631 65cef780 blueswir1
    cur_drv = get_cur_drv(fdctrl);
1632 65cef780 blueswir1
    fdctrl_reset_fifo(fdctrl);
1633 65cef780 blueswir1
    if (fdctrl->fifo[2] > cur_drv->max_track) {
1634 65cef780 blueswir1
        fdctrl_raise_irq(fdctrl, FD_SR0_ABNTERM | FD_SR0_SEEK);
1635 65cef780 blueswir1
    } else {
1636 65cef780 blueswir1
        cur_drv->track = fdctrl->fifo[2];
1637 65cef780 blueswir1
        /* Raise Interrupt */
1638 65cef780 blueswir1
        fdctrl_raise_irq(fdctrl, FD_SR0_SEEK);
1639 65cef780 blueswir1
    }
1640 65cef780 blueswir1
}
1641 65cef780 blueswir1
1642 5c02c033 Blue Swirl
static void fdctrl_handle_perpendicular_mode(FDCtrl *fdctrl, int direction)
1643 65cef780 blueswir1
{
1644 5c02c033 Blue Swirl
    FDrive *cur_drv = get_cur_drv(fdctrl);
1645 65cef780 blueswir1
1646 65cef780 blueswir1
    if (fdctrl->fifo[1] & 0x80)
1647 65cef780 blueswir1
        cur_drv->perpendicular = fdctrl->fifo[1] & 0x7;
1648 65cef780 blueswir1
    /* No result back */
1649 1c346df2 blueswir1
    fdctrl_reset_fifo(fdctrl);
1650 65cef780 blueswir1
}
1651 65cef780 blueswir1
1652 5c02c033 Blue Swirl
static void fdctrl_handle_configure(FDCtrl *fdctrl, int direction)
1653 65cef780 blueswir1
{
1654 65cef780 blueswir1
    fdctrl->config = fdctrl->fifo[2];
1655 65cef780 blueswir1
    fdctrl->precomp_trk =  fdctrl->fifo[3];
1656 65cef780 blueswir1
    /* No result back */
1657 65cef780 blueswir1
    fdctrl_reset_fifo(fdctrl);
1658 65cef780 blueswir1
}
1659 65cef780 blueswir1
1660 5c02c033 Blue Swirl
static void fdctrl_handle_powerdown_mode(FDCtrl *fdctrl, int direction)
1661 65cef780 blueswir1
{
1662 65cef780 blueswir1
    fdctrl->pwrd = fdctrl->fifo[1];
1663 65cef780 blueswir1
    fdctrl->fifo[0] = fdctrl->fifo[1];
1664 65cef780 blueswir1
    fdctrl_set_fifo(fdctrl, 1, 1);
1665 65cef780 blueswir1
}
1666 65cef780 blueswir1
1667 5c02c033 Blue Swirl
static void fdctrl_handle_option(FDCtrl *fdctrl, int direction)
1668 65cef780 blueswir1
{
1669 65cef780 blueswir1
    /* No result back */
1670 65cef780 blueswir1
    fdctrl_reset_fifo(fdctrl);
1671 65cef780 blueswir1
}
1672 65cef780 blueswir1
1673 5c02c033 Blue Swirl
static void fdctrl_handle_drive_specification_command(FDCtrl *fdctrl, int direction)
1674 65cef780 blueswir1
{
1675 5c02c033 Blue Swirl
    FDrive *cur_drv = get_cur_drv(fdctrl);
1676 65cef780 blueswir1
1677 65cef780 blueswir1
    if (fdctrl->fifo[fdctrl->data_pos - 1] & 0x80) {
1678 65cef780 blueswir1
        /* Command parameters done */
1679 65cef780 blueswir1
        if (fdctrl->fifo[fdctrl->data_pos - 1] & 0x40) {
1680 65cef780 blueswir1
            fdctrl->fifo[0] = fdctrl->fifo[1];
1681 65cef780 blueswir1
            fdctrl->fifo[2] = 0;
1682 65cef780 blueswir1
            fdctrl->fifo[3] = 0;
1683 65cef780 blueswir1
            fdctrl_set_fifo(fdctrl, 4, 1);
1684 65cef780 blueswir1
        } else {
1685 65cef780 blueswir1
            fdctrl_reset_fifo(fdctrl);
1686 65cef780 blueswir1
        }
1687 65cef780 blueswir1
    } else if (fdctrl->data_len > 7) {
1688 65cef780 blueswir1
        /* ERROR */
1689 65cef780 blueswir1
        fdctrl->fifo[0] = 0x80 |
1690 cefec4f5 blueswir1
            (cur_drv->head << 2) | GET_CUR_DRV(fdctrl);
1691 65cef780 blueswir1
        fdctrl_set_fifo(fdctrl, 1, 1);
1692 65cef780 blueswir1
    }
1693 65cef780 blueswir1
}
1694 65cef780 blueswir1
1695 5c02c033 Blue Swirl
static void fdctrl_handle_relative_seek_out(FDCtrl *fdctrl, int direction)
1696 65cef780 blueswir1
{
1697 5c02c033 Blue Swirl
    FDrive *cur_drv;
1698 65cef780 blueswir1
1699 cefec4f5 blueswir1
    SET_CUR_DRV(fdctrl, fdctrl->fifo[1] & FD_DOR_SELMASK);
1700 65cef780 blueswir1
    cur_drv = get_cur_drv(fdctrl);
1701 65cef780 blueswir1
    if (fdctrl->fifo[2] + cur_drv->track >= cur_drv->max_track) {
1702 65cef780 blueswir1
        cur_drv->track = cur_drv->max_track - 1;
1703 65cef780 blueswir1
    } else {
1704 65cef780 blueswir1
        cur_drv->track += fdctrl->fifo[2];
1705 65cef780 blueswir1
    }
1706 65cef780 blueswir1
    fdctrl_reset_fifo(fdctrl);
1707 77370520 blueswir1
    /* Raise Interrupt */
1708 65cef780 blueswir1
    fdctrl_raise_irq(fdctrl, FD_SR0_SEEK);
1709 65cef780 blueswir1
}
1710 65cef780 blueswir1
1711 5c02c033 Blue Swirl
static void fdctrl_handle_relative_seek_in(FDCtrl *fdctrl, int direction)
1712 65cef780 blueswir1
{
1713 5c02c033 Blue Swirl
    FDrive *cur_drv;
1714 65cef780 blueswir1
1715 cefec4f5 blueswir1
    SET_CUR_DRV(fdctrl, fdctrl->fifo[1] & FD_DOR_SELMASK);
1716 65cef780 blueswir1
    cur_drv = get_cur_drv(fdctrl);
1717 65cef780 blueswir1
    if (fdctrl->fifo[2] > cur_drv->track) {
1718 65cef780 blueswir1
        cur_drv->track = 0;
1719 65cef780 blueswir1
    } else {
1720 65cef780 blueswir1
        cur_drv->track -= fdctrl->fifo[2];
1721 65cef780 blueswir1
    }
1722 65cef780 blueswir1
    fdctrl_reset_fifo(fdctrl);
1723 65cef780 blueswir1
    /* Raise Interrupt */
1724 65cef780 blueswir1
    fdctrl_raise_irq(fdctrl, FD_SR0_SEEK);
1725 65cef780 blueswir1
}
1726 65cef780 blueswir1
1727 678803ab blueswir1
static const struct {
1728 678803ab blueswir1
    uint8_t value;
1729 678803ab blueswir1
    uint8_t mask;
1730 678803ab blueswir1
    const char* name;
1731 678803ab blueswir1
    int parameters;
1732 5c02c033 Blue Swirl
    void (*handler)(FDCtrl *fdctrl, int direction);
1733 678803ab blueswir1
    int direction;
1734 678803ab blueswir1
} handlers[] = {
1735 678803ab blueswir1
    { FD_CMD_READ, 0x1f, "READ", 8, fdctrl_start_transfer, FD_DIR_READ },
1736 678803ab blueswir1
    { FD_CMD_WRITE, 0x3f, "WRITE", 8, fdctrl_start_transfer, FD_DIR_WRITE },
1737 678803ab blueswir1
    { FD_CMD_SEEK, 0xff, "SEEK", 2, fdctrl_handle_seek },
1738 678803ab blueswir1
    { FD_CMD_SENSE_INTERRUPT_STATUS, 0xff, "SENSE INTERRUPT STATUS", 0, fdctrl_handle_sense_interrupt_status },
1739 678803ab blueswir1
    { FD_CMD_RECALIBRATE, 0xff, "RECALIBRATE", 1, fdctrl_handle_recalibrate },
1740 678803ab blueswir1
    { FD_CMD_FORMAT_TRACK, 0xbf, "FORMAT TRACK", 5, fdctrl_handle_format_track },
1741 678803ab blueswir1
    { FD_CMD_READ_TRACK, 0xbf, "READ TRACK", 8, fdctrl_start_transfer, FD_DIR_READ },
1742 678803ab blueswir1
    { FD_CMD_RESTORE, 0xff, "RESTORE", 17, fdctrl_handle_restore }, /* part of READ DELETED DATA */
1743 678803ab blueswir1
    { FD_CMD_SAVE, 0xff, "SAVE", 0, fdctrl_handle_save }, /* part of READ DELETED DATA */
1744 678803ab blueswir1
    { FD_CMD_READ_DELETED, 0x1f, "READ DELETED DATA", 8, fdctrl_start_transfer_del, FD_DIR_READ },
1745 678803ab blueswir1
    { FD_CMD_SCAN_EQUAL, 0x1f, "SCAN EQUAL", 8, fdctrl_start_transfer, FD_DIR_SCANE },
1746 678803ab blueswir1
    { FD_CMD_VERIFY, 0x1f, "VERIFY", 8, fdctrl_unimplemented },
1747 678803ab blueswir1
    { FD_CMD_SCAN_LOW_OR_EQUAL, 0x1f, "SCAN LOW OR EQUAL", 8, fdctrl_start_transfer, FD_DIR_SCANL },
1748 678803ab blueswir1
    { FD_CMD_SCAN_HIGH_OR_EQUAL, 0x1f, "SCAN HIGH OR EQUAL", 8, fdctrl_start_transfer, FD_DIR_SCANH },
1749 678803ab blueswir1
    { FD_CMD_WRITE_DELETED, 0x3f, "WRITE DELETED DATA", 8, fdctrl_start_transfer_del, FD_DIR_WRITE },
1750 678803ab blueswir1
    { FD_CMD_READ_ID, 0xbf, "READ ID", 1, fdctrl_handle_readid },
1751 678803ab blueswir1
    { FD_CMD_SPECIFY, 0xff, "SPECIFY", 2, fdctrl_handle_specify },
1752 678803ab blueswir1
    { FD_CMD_SENSE_DRIVE_STATUS, 0xff, "SENSE DRIVE STATUS", 1, fdctrl_handle_sense_drive_status },
1753 678803ab blueswir1
    { FD_CMD_PERPENDICULAR_MODE, 0xff, "PERPENDICULAR MODE", 1, fdctrl_handle_perpendicular_mode },
1754 678803ab blueswir1
    { FD_CMD_CONFIGURE, 0xff, "CONFIGURE", 3, fdctrl_handle_configure },
1755 678803ab blueswir1
    { FD_CMD_POWERDOWN_MODE, 0xff, "POWERDOWN MODE", 2, fdctrl_handle_powerdown_mode },
1756 678803ab blueswir1
    { FD_CMD_OPTION, 0xff, "OPTION", 1, fdctrl_handle_option },
1757 678803ab blueswir1
    { FD_CMD_DRIVE_SPECIFICATION_COMMAND, 0xff, "DRIVE SPECIFICATION COMMAND", 5, fdctrl_handle_drive_specification_command },
1758 678803ab blueswir1
    { FD_CMD_RELATIVE_SEEK_OUT, 0xff, "RELATIVE SEEK OUT", 2, fdctrl_handle_relative_seek_out },
1759 678803ab blueswir1
    { FD_CMD_FORMAT_AND_WRITE, 0xff, "FORMAT AND WRITE", 10, fdctrl_unimplemented },
1760 678803ab blueswir1
    { FD_CMD_RELATIVE_SEEK_IN, 0xff, "RELATIVE SEEK IN", 2, fdctrl_handle_relative_seek_in },
1761 678803ab blueswir1
    { FD_CMD_LOCK, 0x7f, "LOCK", 0, fdctrl_handle_lock },
1762 678803ab blueswir1
    { FD_CMD_DUMPREG, 0xff, "DUMPREG", 0, fdctrl_handle_dumpreg },
1763 678803ab blueswir1
    { FD_CMD_VERSION, 0xff, "VERSION", 0, fdctrl_handle_version },
1764 678803ab blueswir1
    { FD_CMD_PART_ID, 0xff, "PART ID", 0, fdctrl_handle_partid },
1765 678803ab blueswir1
    { FD_CMD_WRITE, 0x1f, "WRITE (BeOS)", 8, fdctrl_start_transfer, FD_DIR_WRITE }, /* not in specification ; BeOS 4.5 bug */
1766 678803ab blueswir1
    { 0, 0, "unknown", 0, fdctrl_unimplemented }, /* default handler */
1767 678803ab blueswir1
};
1768 678803ab blueswir1
/* Associate command to an index in the 'handlers' array */
1769 678803ab blueswir1
static uint8_t command_to_handler[256];
1770 678803ab blueswir1
1771 5c02c033 Blue Swirl
static void fdctrl_write_data(FDCtrl *fdctrl, uint32_t value)
1772 baca51fa bellard
{
1773 5c02c033 Blue Swirl
    FDrive *cur_drv;
1774 65cef780 blueswir1
    int pos;
1775 baca51fa bellard
1776 8977f3c1 bellard
    /* Reset mode */
1777 1c346df2 blueswir1
    if (!(fdctrl->dor & FD_DOR_nRESET)) {
1778 4b19ec0c bellard
        FLOPPY_DPRINTF("Floppy controller in RESET state !\n");
1779 8977f3c1 bellard
        return;
1780 8977f3c1 bellard
    }
1781 b9b3d225 blueswir1
    if (!(fdctrl->msr & FD_MSR_RQM) || (fdctrl->msr & FD_MSR_DIO)) {
1782 b9b3d225 blueswir1
        FLOPPY_ERROR("controller not ready for writing\n");
1783 8977f3c1 bellard
        return;
1784 8977f3c1 bellard
    }
1785 b9b3d225 blueswir1
    fdctrl->dsr &= ~FD_DSR_PWRDOWN;
1786 8977f3c1 bellard
    /* Is it write command time ? */
1787 368df94d blueswir1
    if (fdctrl->msr & FD_MSR_NONDMA) {
1788 8977f3c1 bellard
        /* FIFO data write */
1789 b3bc1540 blueswir1
        pos = fdctrl->data_pos++;
1790 b3bc1540 blueswir1
        pos %= FD_SECTOR_LEN;
1791 b3bc1540 blueswir1
        fdctrl->fifo[pos] = value;
1792 b3bc1540 blueswir1
        if (pos == FD_SECTOR_LEN - 1 ||
1793 baca51fa bellard
            fdctrl->data_pos == fdctrl->data_len) {
1794 77370520 blueswir1
            cur_drv = get_cur_drv(fdctrl);
1795 77370520 blueswir1
            if (bdrv_write(cur_drv->bs, fd_sector(cur_drv), fdctrl->fifo, 1) < 0) {
1796 77370520 blueswir1
                FLOPPY_ERROR("writing sector %d\n", fd_sector(cur_drv));
1797 77370520 blueswir1
                return;
1798 77370520 blueswir1
            }
1799 746d6de7 blueswir1
            if (!fdctrl_seek_to_next_sect(fdctrl, cur_drv)) {
1800 746d6de7 blueswir1
                FLOPPY_DPRINTF("error seeking to next sector %d\n",
1801 746d6de7 blueswir1
                               fd_sector(cur_drv));
1802 746d6de7 blueswir1
                return;
1803 746d6de7 blueswir1
            }
1804 8977f3c1 bellard
        }
1805 890fa6be bellard
        /* Switch from transfer mode to status mode
1806 8977f3c1 bellard
         * then from status mode to command mode
1807 8977f3c1 bellard
         */
1808 b9b3d225 blueswir1
        if (fdctrl->data_pos == fdctrl->data_len)
1809 9fea808a blueswir1
            fdctrl_stop_transfer(fdctrl, FD_SR0_SEEK, 0x00, 0x00);
1810 8977f3c1 bellard
        return;
1811 8977f3c1 bellard
    }
1812 baca51fa bellard
    if (fdctrl->data_pos == 0) {
1813 8977f3c1 bellard
        /* Command */
1814 678803ab blueswir1
        pos = command_to_handler[value & 0xff];
1815 678803ab blueswir1
        FLOPPY_DPRINTF("%s command\n", handlers[pos].name);
1816 678803ab blueswir1
        fdctrl->data_len = handlers[pos].parameters + 1;
1817 8977f3c1 bellard
    }
1818 678803ab blueswir1
1819 baca51fa bellard
    FLOPPY_DPRINTF("%s: %02x\n", __func__, value);
1820 77370520 blueswir1
    fdctrl->fifo[fdctrl->data_pos++] = value;
1821 77370520 blueswir1
    if (fdctrl->data_pos == fdctrl->data_len) {
1822 8977f3c1 bellard
        /* We now have all parameters
1823 8977f3c1 bellard
         * and will be able to treat the command
1824 8977f3c1 bellard
         */
1825 4f431960 j_mayer
        if (fdctrl->data_state & FD_STATE_FORMAT) {
1826 4f431960 j_mayer
            fdctrl_format_sector(fdctrl);
1827 8977f3c1 bellard
            return;
1828 8977f3c1 bellard
        }
1829 65cef780 blueswir1
1830 678803ab blueswir1
        pos = command_to_handler[fdctrl->fifo[0] & 0xff];
1831 678803ab blueswir1
        FLOPPY_DPRINTF("treat %s command\n", handlers[pos].name);
1832 678803ab blueswir1
        (*handlers[pos].handler)(fdctrl, handlers[pos].direction);
1833 8977f3c1 bellard
    }
1834 8977f3c1 bellard
}
1835 ed5fd2cc bellard
1836 ed5fd2cc bellard
static void fdctrl_result_timer(void *opaque)
1837 ed5fd2cc bellard
{
1838 5c02c033 Blue Swirl
    FDCtrl *fdctrl = opaque;
1839 5c02c033 Blue Swirl
    FDrive *cur_drv = get_cur_drv(fdctrl);
1840 4f431960 j_mayer
1841 b7ffa3b1 ths
    /* Pretend we are spinning.
1842 b7ffa3b1 ths
     * This is needed for Coherent, which uses READ ID to check for
1843 b7ffa3b1 ths
     * sector interleaving.
1844 b7ffa3b1 ths
     */
1845 b7ffa3b1 ths
    if (cur_drv->last_sect != 0) {
1846 b7ffa3b1 ths
        cur_drv->sect = (cur_drv->sect % cur_drv->last_sect) + 1;
1847 b7ffa3b1 ths
    }
1848 ed5fd2cc bellard
    fdctrl_stop_transfer(fdctrl, 0x00, 0x00, 0x00);
1849 ed5fd2cc bellard
}
1850 678803ab blueswir1
1851 678803ab blueswir1
/* Init functions */
1852 b47b3525 Markus Armbruster
static int fdctrl_connect_drives(FDCtrl *fdctrl)
1853 678803ab blueswir1
{
1854 12a71a02 Blue Swirl
    unsigned int i;
1855 7d0d6950 Markus Armbruster
    FDrive *drive;
1856 678803ab blueswir1
1857 678803ab blueswir1
    for (i = 0; i < MAX_FD; i++) {
1858 7d0d6950 Markus Armbruster
        drive = &fdctrl->drives[i];
1859 7d0d6950 Markus Armbruster
1860 b47b3525 Markus Armbruster
        if (drive->bs) {
1861 b47b3525 Markus Armbruster
            if (bdrv_get_on_error(drive->bs, 0) != BLOCK_ERR_STOP_ENOSPC) {
1862 b47b3525 Markus Armbruster
                error_report("fdc doesn't support drive option werror");
1863 b47b3525 Markus Armbruster
                return -1;
1864 b47b3525 Markus Armbruster
            }
1865 b47b3525 Markus Armbruster
            if (bdrv_get_on_error(drive->bs, 1) != BLOCK_ERR_REPORT) {
1866 b47b3525 Markus Armbruster
                error_report("fdc doesn't support drive option rerror");
1867 b47b3525 Markus Armbruster
                return -1;
1868 b47b3525 Markus Armbruster
            }
1869 b47b3525 Markus Armbruster
        }
1870 b47b3525 Markus Armbruster
1871 7d0d6950 Markus Armbruster
        fd_init(drive);
1872 7d0d6950 Markus Armbruster
        fd_revalidate(drive);
1873 7d0d6950 Markus Armbruster
        if (drive->bs) {
1874 7d0d6950 Markus Armbruster
            bdrv_set_removable(drive->bs, 1);
1875 7d0d6950 Markus Armbruster
        }
1876 678803ab blueswir1
    }
1877 b47b3525 Markus Armbruster
    return 0;
1878 678803ab blueswir1
}
1879 678803ab blueswir1
1880 5c02c033 Blue Swirl
FDCtrl *fdctrl_init_isa(DriveInfo **fds)
1881 678803ab blueswir1
{
1882 2091ba23 Gerd Hoffmann
    ISADevice *dev;
1883 678803ab blueswir1
1884 fd8014e1 Gerd Hoffmann
    dev = isa_create("isa-fdc");
1885 995bf0ca Gerd Hoffmann
    if (fds[0]) {
1886 18846dee Markus Armbruster
        qdev_prop_set_drive_nofail(&dev->qdev, "driveA", fds[0]->bdrv);
1887 995bf0ca Gerd Hoffmann
    }
1888 995bf0ca Gerd Hoffmann
    if (fds[1]) {
1889 18846dee Markus Armbruster
        qdev_prop_set_drive_nofail(&dev->qdev, "driveB", fds[1]->bdrv);
1890 995bf0ca Gerd Hoffmann
    }
1891 b47b3525 Markus Armbruster
    qdev_init_nofail(&dev->qdev);
1892 5c02c033 Blue Swirl
    return &(DO_UPCAST(FDCtrlISABus, busdev, dev)->state);
1893 2091ba23 Gerd Hoffmann
}
1894 2091ba23 Gerd Hoffmann
1895 5c02c033 Blue Swirl
FDCtrl *fdctrl_init_sysbus(qemu_irq irq, int dma_chann,
1896 5c02c033 Blue Swirl
                           target_phys_addr_t mmio_base, DriveInfo **fds)
1897 2091ba23 Gerd Hoffmann
{
1898 5c02c033 Blue Swirl
    FDCtrl *fdctrl;
1899 2091ba23 Gerd Hoffmann
    DeviceState *dev;
1900 5c02c033 Blue Swirl
    FDCtrlSysBus *sys;
1901 2091ba23 Gerd Hoffmann
1902 2091ba23 Gerd Hoffmann
    dev = qdev_create(NULL, "sysbus-fdc");
1903 5c02c033 Blue Swirl
    sys = DO_UPCAST(FDCtrlSysBus, busdev.qdev, dev);
1904 99244fa1 Gerd Hoffmann
    fdctrl = &sys->state;
1905 99244fa1 Gerd Hoffmann
    fdctrl->dma_chann = dma_chann; /* FIXME */
1906 995bf0ca Gerd Hoffmann
    if (fds[0]) {
1907 18846dee Markus Armbruster
        qdev_prop_set_drive_nofail(dev, "driveA", fds[0]->bdrv);
1908 995bf0ca Gerd Hoffmann
    }
1909 995bf0ca Gerd Hoffmann
    if (fds[1]) {
1910 18846dee Markus Armbruster
        qdev_prop_set_drive_nofail(dev, "driveB", fds[1]->bdrv);
1911 995bf0ca Gerd Hoffmann
    }
1912 e23a1b33 Markus Armbruster
    qdev_init_nofail(dev);
1913 2091ba23 Gerd Hoffmann
    sysbus_connect_irq(&sys->busdev, 0, irq);
1914 2091ba23 Gerd Hoffmann
    sysbus_mmio_map(&sys->busdev, 0, mmio_base);
1915 8baf73ad Gerd Hoffmann
1916 678803ab blueswir1
    return fdctrl;
1917 678803ab blueswir1
}
1918 678803ab blueswir1
1919 5c02c033 Blue Swirl
FDCtrl *sun4m_fdctrl_init(qemu_irq irq, target_phys_addr_t io_base,
1920 5c02c033 Blue Swirl
                          DriveInfo **fds, qemu_irq *fdc_tc)
1921 678803ab blueswir1
{
1922 f64ab228 Blue Swirl
    DeviceState *dev;
1923 5c02c033 Blue Swirl
    FDCtrlSysBus *sys;
1924 5c02c033 Blue Swirl
    FDCtrl *fdctrl;
1925 678803ab blueswir1
1926 12a71a02 Blue Swirl
    dev = qdev_create(NULL, "SUNW,fdtwo");
1927 995bf0ca Gerd Hoffmann
    if (fds[0]) {
1928 18846dee Markus Armbruster
        qdev_prop_set_drive_nofail(dev, "drive", fds[0]->bdrv);
1929 995bf0ca Gerd Hoffmann
    }
1930 e23a1b33 Markus Armbruster
    qdev_init_nofail(dev);
1931 5c02c033 Blue Swirl
    sys = DO_UPCAST(FDCtrlSysBus, busdev.qdev, dev);
1932 8baf73ad Gerd Hoffmann
    fdctrl = &sys->state;
1933 8baf73ad Gerd Hoffmann
    sysbus_connect_irq(&sys->busdev, 0, irq);
1934 8baf73ad Gerd Hoffmann
    sysbus_mmio_map(&sys->busdev, 0, io_base);
1935 f64ab228 Blue Swirl
    *fdc_tc = qdev_get_gpio_in(dev, 0);
1936 f64ab228 Blue Swirl
1937 678803ab blueswir1
    return fdctrl;
1938 678803ab blueswir1
}
1939 f64ab228 Blue Swirl
1940 a64405d1 Jan Kiszka
static int fdctrl_init_common(FDCtrl *fdctrl)
1941 f64ab228 Blue Swirl
{
1942 12a71a02 Blue Swirl
    int i, j;
1943 12a71a02 Blue Swirl
    static int command_tables_inited = 0;
1944 f64ab228 Blue Swirl
1945 12a71a02 Blue Swirl
    /* Fill 'command_to_handler' lookup table */
1946 12a71a02 Blue Swirl
    if (!command_tables_inited) {
1947 12a71a02 Blue Swirl
        command_tables_inited = 1;
1948 12a71a02 Blue Swirl
        for (i = ARRAY_SIZE(handlers) - 1; i >= 0; i--) {
1949 12a71a02 Blue Swirl
            for (j = 0; j < sizeof(command_to_handler); j++) {
1950 12a71a02 Blue Swirl
                if ((j & handlers[i].mask) == handlers[i].value) {
1951 12a71a02 Blue Swirl
                    command_to_handler[j] = i;
1952 12a71a02 Blue Swirl
                }
1953 12a71a02 Blue Swirl
            }
1954 12a71a02 Blue Swirl
        }
1955 12a71a02 Blue Swirl
    }
1956 12a71a02 Blue Swirl
1957 12a71a02 Blue Swirl
    FLOPPY_DPRINTF("init controller\n");
1958 12a71a02 Blue Swirl
    fdctrl->fifo = qemu_memalign(512, FD_SECTOR_LEN);
1959 d7a6c270 Juan Quintela
    fdctrl->fifo_size = 512;
1960 12a71a02 Blue Swirl
    fdctrl->result_timer = qemu_new_timer(vm_clock,
1961 12a71a02 Blue Swirl
                                          fdctrl_result_timer, fdctrl);
1962 12a71a02 Blue Swirl
1963 12a71a02 Blue Swirl
    fdctrl->version = 0x90; /* Intel 82078 controller */
1964 12a71a02 Blue Swirl
    fdctrl->config = FD_CONFIG_EIS | FD_CONFIG_EFIFO; /* Implicit seek, polling & FIFO enabled */
1965 d7a6c270 Juan Quintela
    fdctrl->num_floppies = MAX_FD;
1966 12a71a02 Blue Swirl
1967 99244fa1 Gerd Hoffmann
    if (fdctrl->dma_chann != -1)
1968 99244fa1 Gerd Hoffmann
        DMA_register_channel(fdctrl->dma_chann, &fdctrl_transfer_handler, fdctrl);
1969 b47b3525 Markus Armbruster
    return fdctrl_connect_drives(fdctrl);
1970 f64ab228 Blue Swirl
}
1971 f64ab228 Blue Swirl
1972 81a322d4 Gerd Hoffmann
static int isabus_fdc_init1(ISADevice *dev)
1973 8baf73ad Gerd Hoffmann
{
1974 5c02c033 Blue Swirl
    FDCtrlISABus *isa = DO_UPCAST(FDCtrlISABus, busdev, dev);
1975 5c02c033 Blue Swirl
    FDCtrl *fdctrl = &isa->state;
1976 86c86157 Gerd Hoffmann
    int iobase = 0x3f0;
1977 2e15e23b Gerd Hoffmann
    int isairq = 6;
1978 99244fa1 Gerd Hoffmann
    int dma_chann = 2;
1979 2be37833 Blue Swirl
    int ret;
1980 8baf73ad Gerd Hoffmann
1981 86c86157 Gerd Hoffmann
    register_ioport_read(iobase + 0x01, 5, 1,
1982 8baf73ad Gerd Hoffmann
                         &fdctrl_read_port, fdctrl);
1983 86c86157 Gerd Hoffmann
    register_ioport_read(iobase + 0x07, 1, 1,
1984 8baf73ad Gerd Hoffmann
                         &fdctrl_read_port, fdctrl);
1985 86c86157 Gerd Hoffmann
    register_ioport_write(iobase + 0x01, 5, 1,
1986 8baf73ad Gerd Hoffmann
                          &fdctrl_write_port, fdctrl);
1987 86c86157 Gerd Hoffmann
    register_ioport_write(iobase + 0x07, 1, 1,
1988 8baf73ad Gerd Hoffmann
                          &fdctrl_write_port, fdctrl);
1989 dee41d58 Gleb Natapov
    isa_init_ioport_range(dev, iobase, 6);
1990 dee41d58 Gleb Natapov
    isa_init_ioport(dev, iobase + 7);
1991 dee41d58 Gleb Natapov
1992 2e15e23b Gerd Hoffmann
    isa_init_irq(&isa->busdev, &fdctrl->irq, isairq);
1993 99244fa1 Gerd Hoffmann
    fdctrl->dma_chann = dma_chann;
1994 8baf73ad Gerd Hoffmann
1995 a64405d1 Jan Kiszka
    qdev_set_legacy_instance_id(&dev->qdev, iobase, 2);
1996 a64405d1 Jan Kiszka
    ret = fdctrl_init_common(fdctrl);
1997 2be37833 Blue Swirl
1998 1ca4d09a Gleb Natapov
    add_boot_device_path(isa->bootindexA, &dev->qdev, "/floppy@0");
1999 1ca4d09a Gleb Natapov
    add_boot_device_path(isa->bootindexB, &dev->qdev, "/floppy@1");
2000 1ca4d09a Gleb Natapov
2001 2be37833 Blue Swirl
    return ret;
2002 8baf73ad Gerd Hoffmann
}
2003 8baf73ad Gerd Hoffmann
2004 81a322d4 Gerd Hoffmann
static int sysbus_fdc_init1(SysBusDevice *dev)
2005 12a71a02 Blue Swirl
{
2006 5c02c033 Blue Swirl
    FDCtrlSysBus *sys = DO_UPCAST(FDCtrlSysBus, busdev, dev);
2007 5c02c033 Blue Swirl
    FDCtrl *fdctrl = &sys->state;
2008 12a71a02 Blue Swirl
    int io;
2009 2be37833 Blue Swirl
    int ret;
2010 12a71a02 Blue Swirl
2011 2507c12a Alexander Graf
    io = cpu_register_io_memory(fdctrl_mem_read, fdctrl_mem_write, fdctrl,
2012 2507c12a Alexander Graf
                                DEVICE_NATIVE_ENDIAN);
2013 8baf73ad Gerd Hoffmann
    sysbus_init_mmio(dev, 0x08, io);
2014 8baf73ad Gerd Hoffmann
    sysbus_init_irq(dev, &fdctrl->irq);
2015 8baf73ad Gerd Hoffmann
    qdev_init_gpio_in(&dev->qdev, fdctrl_handle_tc, 1);
2016 99244fa1 Gerd Hoffmann
    fdctrl->dma_chann = -1;
2017 8baf73ad Gerd Hoffmann
2018 a64405d1 Jan Kiszka
    qdev_set_legacy_instance_id(&dev->qdev, io, 2);
2019 a64405d1 Jan Kiszka
    ret = fdctrl_init_common(fdctrl);
2020 2be37833 Blue Swirl
2021 2be37833 Blue Swirl
    return ret;
2022 12a71a02 Blue Swirl
}
2023 12a71a02 Blue Swirl
2024 81a322d4 Gerd Hoffmann
static int sun4m_fdc_init1(SysBusDevice *dev)
2025 12a71a02 Blue Swirl
{
2026 5c02c033 Blue Swirl
    FDCtrl *fdctrl = &(FROM_SYSBUS(FDCtrlSysBus, dev)->state);
2027 12a71a02 Blue Swirl
    int io;
2028 12a71a02 Blue Swirl
2029 12a71a02 Blue Swirl
    io = cpu_register_io_memory(fdctrl_mem_read_strict,
2030 2507c12a Alexander Graf
                                fdctrl_mem_write_strict, fdctrl,
2031 2507c12a Alexander Graf
                                DEVICE_NATIVE_ENDIAN);
2032 8baf73ad Gerd Hoffmann
    sysbus_init_mmio(dev, 0x08, io);
2033 8baf73ad Gerd Hoffmann
    sysbus_init_irq(dev, &fdctrl->irq);
2034 8baf73ad Gerd Hoffmann
    qdev_init_gpio_in(&dev->qdev, fdctrl_handle_tc, 1);
2035 8baf73ad Gerd Hoffmann
2036 8baf73ad Gerd Hoffmann
    fdctrl->sun4m = 1;
2037 a64405d1 Jan Kiszka
    qdev_set_legacy_instance_id(&dev->qdev, io, 2);
2038 a64405d1 Jan Kiszka
    return fdctrl_init_common(fdctrl);
2039 12a71a02 Blue Swirl
}
2040 f64ab228 Blue Swirl
2041 a64405d1 Jan Kiszka
static const VMStateDescription vmstate_isa_fdc ={
2042 a64405d1 Jan Kiszka
    .name = "fdc",
2043 a64405d1 Jan Kiszka
    .version_id = 2,
2044 a64405d1 Jan Kiszka
    .minimum_version_id = 2,
2045 a64405d1 Jan Kiszka
    .fields = (VMStateField []) {
2046 a64405d1 Jan Kiszka
        VMSTATE_STRUCT(state, FDCtrlISABus, 0, vmstate_fdc, FDCtrl),
2047 a64405d1 Jan Kiszka
        VMSTATE_END_OF_LIST()
2048 a64405d1 Jan Kiszka
    }
2049 a64405d1 Jan Kiszka
};
2050 a64405d1 Jan Kiszka
2051 8baf73ad Gerd Hoffmann
static ISADeviceInfo isa_fdc_info = {
2052 8baf73ad Gerd Hoffmann
    .init = isabus_fdc_init1,
2053 8baf73ad Gerd Hoffmann
    .qdev.name  = "isa-fdc",
2054 779206de Gleb Natapov
    .qdev.fw_name  = "fdc",
2055 5c02c033 Blue Swirl
    .qdev.size  = sizeof(FDCtrlISABus),
2056 39a51dfd Markus Armbruster
    .qdev.no_user = 1,
2057 a64405d1 Jan Kiszka
    .qdev.vmsd  = &vmstate_isa_fdc,
2058 2be37833 Blue Swirl
    .qdev.reset = fdctrl_external_reset_isa,
2059 fd8014e1 Gerd Hoffmann
    .qdev.props = (Property[]) {
2060 f8b6cc00 Markus Armbruster
        DEFINE_PROP_DRIVE("driveA", FDCtrlISABus, state.drives[0].bs),
2061 f8b6cc00 Markus Armbruster
        DEFINE_PROP_DRIVE("driveB", FDCtrlISABus, state.drives[1].bs),
2062 1ca4d09a Gleb Natapov
        DEFINE_PROP_INT32("bootindexA", FDCtrlISABus, bootindexA, -1),
2063 1ca4d09a Gleb Natapov
        DEFINE_PROP_INT32("bootindexB", FDCtrlISABus, bootindexB, -1),
2064 fd8014e1 Gerd Hoffmann
        DEFINE_PROP_END_OF_LIST(),
2065 fd8014e1 Gerd Hoffmann
    },
2066 8baf73ad Gerd Hoffmann
};
2067 8baf73ad Gerd Hoffmann
2068 a64405d1 Jan Kiszka
static const VMStateDescription vmstate_sysbus_fdc ={
2069 a64405d1 Jan Kiszka
    .name = "fdc",
2070 a64405d1 Jan Kiszka
    .version_id = 2,
2071 a64405d1 Jan Kiszka
    .minimum_version_id = 2,
2072 a64405d1 Jan Kiszka
    .fields = (VMStateField []) {
2073 a64405d1 Jan Kiszka
        VMSTATE_STRUCT(state, FDCtrlSysBus, 0, vmstate_fdc, FDCtrl),
2074 a64405d1 Jan Kiszka
        VMSTATE_END_OF_LIST()
2075 a64405d1 Jan Kiszka
    }
2076 a64405d1 Jan Kiszka
};
2077 a64405d1 Jan Kiszka
2078 8baf73ad Gerd Hoffmann
static SysBusDeviceInfo sysbus_fdc_info = {
2079 8baf73ad Gerd Hoffmann
    .init = sysbus_fdc_init1,
2080 8baf73ad Gerd Hoffmann
    .qdev.name  = "sysbus-fdc",
2081 5c02c033 Blue Swirl
    .qdev.size  = sizeof(FDCtrlSysBus),
2082 a64405d1 Jan Kiszka
    .qdev.vmsd  = &vmstate_sysbus_fdc,
2083 2be37833 Blue Swirl
    .qdev.reset = fdctrl_external_reset_sysbus,
2084 fd8014e1 Gerd Hoffmann
    .qdev.props = (Property[]) {
2085 f8b6cc00 Markus Armbruster
        DEFINE_PROP_DRIVE("driveA", FDCtrlSysBus, state.drives[0].bs),
2086 f8b6cc00 Markus Armbruster
        DEFINE_PROP_DRIVE("driveB", FDCtrlSysBus, state.drives[1].bs),
2087 fd8014e1 Gerd Hoffmann
        DEFINE_PROP_END_OF_LIST(),
2088 fd8014e1 Gerd Hoffmann
    },
2089 12a71a02 Blue Swirl
};
2090 12a71a02 Blue Swirl
2091 12a71a02 Blue Swirl
static SysBusDeviceInfo sun4m_fdc_info = {
2092 12a71a02 Blue Swirl
    .init = sun4m_fdc_init1,
2093 12a71a02 Blue Swirl
    .qdev.name  = "SUNW,fdtwo",
2094 5c02c033 Blue Swirl
    .qdev.size  = sizeof(FDCtrlSysBus),
2095 a64405d1 Jan Kiszka
    .qdev.vmsd  = &vmstate_sysbus_fdc,
2096 2be37833 Blue Swirl
    .qdev.reset = fdctrl_external_reset_sysbus,
2097 fd8014e1 Gerd Hoffmann
    .qdev.props = (Property[]) {
2098 f8b6cc00 Markus Armbruster
        DEFINE_PROP_DRIVE("drive", FDCtrlSysBus, state.drives[0].bs),
2099 fd8014e1 Gerd Hoffmann
        DEFINE_PROP_END_OF_LIST(),
2100 fd8014e1 Gerd Hoffmann
    },
2101 f64ab228 Blue Swirl
};
2102 f64ab228 Blue Swirl
2103 f64ab228 Blue Swirl
static void fdc_register_devices(void)
2104 f64ab228 Blue Swirl
{
2105 8baf73ad Gerd Hoffmann
    isa_qdev_register(&isa_fdc_info);
2106 8baf73ad Gerd Hoffmann
    sysbus_register_withprop(&sysbus_fdc_info);
2107 12a71a02 Blue Swirl
    sysbus_register_withprop(&sun4m_fdc_info);
2108 f64ab228 Blue Swirl
}
2109 f64ab228 Blue Swirl
2110 f64ab228 Blue Swirl
device_init(fdc_register_devices)