root / hw / ppc / ppc4xx_devs.c @ cba933b2
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1 | 008ff9d7 | j_mayer | /*
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2 | 008ff9d7 | j_mayer | * QEMU PowerPC 4xx embedded processors shared devices emulation
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3 | 008ff9d7 | j_mayer | *
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4 | 008ff9d7 | j_mayer | * Copyright (c) 2007 Jocelyn Mayer
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5 | 008ff9d7 | j_mayer | *
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6 | 008ff9d7 | j_mayer | * Permission is hereby granted, free of charge, to any person obtaining a copy
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7 | 008ff9d7 | j_mayer | * of this software and associated documentation files (the "Software"), to deal
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8 | 008ff9d7 | j_mayer | * in the Software without restriction, including without limitation the rights
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9 | 008ff9d7 | j_mayer | * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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10 | 008ff9d7 | j_mayer | * copies of the Software, and to permit persons to whom the Software is
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11 | 008ff9d7 | j_mayer | * furnished to do so, subject to the following conditions:
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12 | 008ff9d7 | j_mayer | *
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13 | 008ff9d7 | j_mayer | * The above copyright notice and this permission notice shall be included in
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14 | 008ff9d7 | j_mayer | * all copies or substantial portions of the Software.
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15 | 008ff9d7 | j_mayer | *
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16 | 008ff9d7 | j_mayer | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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17 | 008ff9d7 | j_mayer | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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18 | 008ff9d7 | j_mayer | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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19 | 008ff9d7 | j_mayer | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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20 | 008ff9d7 | j_mayer | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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21 | 008ff9d7 | j_mayer | * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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22 | 008ff9d7 | j_mayer | * THE SOFTWARE.
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23 | 008ff9d7 | j_mayer | */
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24 | 83c9f4ca | Paolo Bonzini | #include "hw/hw.h" |
25 | 0d09e41a | Paolo Bonzini | #include "hw/ppc/ppc.h" |
26 | 0d09e41a | Paolo Bonzini | #include "hw/ppc/ppc4xx.h" |
27 | 1de7afc9 | Paolo Bonzini | #include "qemu/log.h" |
28 | 022c62cb | Paolo Bonzini | #include "exec/address-spaces.h" |
29 | 008ff9d7 | j_mayer | |
30 | 008ff9d7 | j_mayer | #define DEBUG_UIC
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31 | 008ff9d7 | j_mayer | |
32 | d12d51d5 | aliguori | |
33 | d12d51d5 | aliguori | #ifdef DEBUG_UIC
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34 | 93fcfe39 | aliguori | # define LOG_UIC(...) qemu_log_mask(CPU_LOG_INT, ## __VA_ARGS__) |
35 | d12d51d5 | aliguori | #else
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36 | d12d51d5 | aliguori | # define LOG_UIC(...) do { } while (0) |
37 | d12d51d5 | aliguori | #endif
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38 | d12d51d5 | aliguori | |
39 | 1bba0dc9 | Andreas Färber | static void ppc4xx_reset(void *opaque) |
40 | 1bba0dc9 | Andreas Färber | { |
41 | 90cb09d9 | Andreas Färber | PowerPCCPU *cpu = opaque; |
42 | 1bba0dc9 | Andreas Färber | |
43 | 90cb09d9 | Andreas Färber | cpu_reset(CPU(cpu)); |
44 | 1bba0dc9 | Andreas Färber | } |
45 | 1bba0dc9 | Andreas Färber | |
46 | 008ff9d7 | j_mayer | /*****************************************************************************/
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47 | 60b14d95 | Stefan Weil | /* Generic PowerPC 4xx processor instantiation */
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48 | 2f9859fb | Andreas Färber | PowerPCCPU *ppc4xx_init(const char *cpu_model, |
49 | 2f9859fb | Andreas Färber | clk_setup_t *cpu_clk, clk_setup_t *tb_clk, |
50 | 2f9859fb | Andreas Färber | uint32_t sysclk) |
51 | 008ff9d7 | j_mayer | { |
52 | 57274713 | Andreas Färber | PowerPCCPU *cpu; |
53 | e2684c0b | Andreas Färber | CPUPPCState *env; |
54 | 008ff9d7 | j_mayer | |
55 | 008ff9d7 | j_mayer | /* init CPUs */
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56 | 57274713 | Andreas Färber | cpu = cpu_ppc_init(cpu_model); |
57 | 57274713 | Andreas Färber | if (cpu == NULL) { |
58 | aaed909a | bellard | fprintf(stderr, "Unable to find PowerPC %s CPU definition\n",
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59 | aaed909a | bellard | cpu_model); |
60 | aaed909a | bellard | exit(1);
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61 | 008ff9d7 | j_mayer | } |
62 | 57274713 | Andreas Färber | env = &cpu->env; |
63 | 57274713 | Andreas Färber | |
64 | 008ff9d7 | j_mayer | cpu_clk->cb = NULL; /* We don't care about CPU clock frequency changes */ |
65 | 008ff9d7 | j_mayer | cpu_clk->opaque = env; |
66 | 008ff9d7 | j_mayer | /* Set time-base frequency to sysclk */
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67 | ddd1055b | Fabien Chouteau | tb_clk->cb = ppc_40x_timers_init(env, sysclk, PPC_INTERRUPT_PIT); |
68 | 008ff9d7 | j_mayer | tb_clk->opaque = env; |
69 | 008ff9d7 | j_mayer | ppc_dcr_init(env, NULL, NULL); |
70 | 008ff9d7 | j_mayer | /* Register qemu callbacks */
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71 | 90cb09d9 | Andreas Färber | qemu_register_reset(ppc4xx_reset, cpu); |
72 | 008ff9d7 | j_mayer | |
73 | 2f9859fb | Andreas Färber | return cpu;
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74 | 008ff9d7 | j_mayer | } |
75 | 008ff9d7 | j_mayer | |
76 | 008ff9d7 | j_mayer | /*****************************************************************************/
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77 | 008ff9d7 | j_mayer | /* "Universal" Interrupt controller */
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78 | 008ff9d7 | j_mayer | enum {
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79 | 008ff9d7 | j_mayer | DCR_UICSR = 0x000,
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80 | 008ff9d7 | j_mayer | DCR_UICSRS = 0x001,
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81 | 008ff9d7 | j_mayer | DCR_UICER = 0x002,
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82 | 008ff9d7 | j_mayer | DCR_UICCR = 0x003,
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83 | 008ff9d7 | j_mayer | DCR_UICPR = 0x004,
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84 | 008ff9d7 | j_mayer | DCR_UICTR = 0x005,
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85 | 008ff9d7 | j_mayer | DCR_UICMSR = 0x006,
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86 | 008ff9d7 | j_mayer | DCR_UICVR = 0x007,
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87 | 008ff9d7 | j_mayer | DCR_UICVCR = 0x008,
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88 | 008ff9d7 | j_mayer | DCR_UICMAX = 0x009,
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89 | 008ff9d7 | j_mayer | }; |
90 | 008ff9d7 | j_mayer | |
91 | 008ff9d7 | j_mayer | #define UIC_MAX_IRQ 32 |
92 | c227f099 | Anthony Liguori | typedef struct ppcuic_t ppcuic_t; |
93 | c227f099 | Anthony Liguori | struct ppcuic_t {
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94 | 008ff9d7 | j_mayer | uint32_t dcr_base; |
95 | 008ff9d7 | j_mayer | int use_vectors;
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96 | 4c54e875 | aurel32 | uint32_t level; /* Remembers the state of level-triggered interrupts. */
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97 | 008ff9d7 | j_mayer | uint32_t uicsr; /* Status register */
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98 | 008ff9d7 | j_mayer | uint32_t uicer; /* Enable register */
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99 | 008ff9d7 | j_mayer | uint32_t uiccr; /* Critical register */
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100 | 008ff9d7 | j_mayer | uint32_t uicpr; /* Polarity register */
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101 | 008ff9d7 | j_mayer | uint32_t uictr; /* Triggering register */
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102 | 008ff9d7 | j_mayer | uint32_t uicvcr; /* Vector configuration register */
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103 | 008ff9d7 | j_mayer | uint32_t uicvr; |
104 | 008ff9d7 | j_mayer | qemu_irq *irqs; |
105 | 008ff9d7 | j_mayer | }; |
106 | 008ff9d7 | j_mayer | |
107 | c227f099 | Anthony Liguori | static void ppcuic_trigger_irq (ppcuic_t *uic) |
108 | 008ff9d7 | j_mayer | { |
109 | 008ff9d7 | j_mayer | uint32_t ir, cr; |
110 | 008ff9d7 | j_mayer | int start, end, inc, i;
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111 | 008ff9d7 | j_mayer | |
112 | 008ff9d7 | j_mayer | /* Trigger interrupt if any is pending */
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113 | 008ff9d7 | j_mayer | ir = uic->uicsr & uic->uicer & (~uic->uiccr); |
114 | 008ff9d7 | j_mayer | cr = uic->uicsr & uic->uicer & uic->uiccr; |
115 | d12d51d5 | aliguori | LOG_UIC("%s: uicsr %08" PRIx32 " uicer %08" PRIx32 |
116 | aae9366a | j_mayer | " uiccr %08" PRIx32 "\n" |
117 | aae9366a | j_mayer | " %08" PRIx32 " ir %08" PRIx32 " cr %08" PRIx32 "\n", |
118 | aae9366a | j_mayer | __func__, uic->uicsr, uic->uicer, uic->uiccr, |
119 | 008ff9d7 | j_mayer | uic->uicsr & uic->uicer, ir, cr); |
120 | 008ff9d7 | j_mayer | if (ir != 0x0000000) { |
121 | d12d51d5 | aliguori | LOG_UIC("Raise UIC interrupt\n");
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122 | 008ff9d7 | j_mayer | qemu_irq_raise(uic->irqs[PPCUIC_OUTPUT_INT]); |
123 | 008ff9d7 | j_mayer | } else {
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124 | d12d51d5 | aliguori | LOG_UIC("Lower UIC interrupt\n");
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125 | 008ff9d7 | j_mayer | qemu_irq_lower(uic->irqs[PPCUIC_OUTPUT_INT]); |
126 | 008ff9d7 | j_mayer | } |
127 | 008ff9d7 | j_mayer | /* Trigger critical interrupt if any is pending and update vector */
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128 | 008ff9d7 | j_mayer | if (cr != 0x0000000) { |
129 | 008ff9d7 | j_mayer | qemu_irq_raise(uic->irqs[PPCUIC_OUTPUT_CINT]); |
130 | 008ff9d7 | j_mayer | if (uic->use_vectors) {
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131 | 008ff9d7 | j_mayer | /* Compute critical IRQ vector */
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132 | 008ff9d7 | j_mayer | if (uic->uicvcr & 1) { |
133 | 008ff9d7 | j_mayer | start = 31;
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134 | 008ff9d7 | j_mayer | end = 0;
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135 | 008ff9d7 | j_mayer | inc = -1;
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136 | 008ff9d7 | j_mayer | } else {
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137 | 008ff9d7 | j_mayer | start = 0;
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138 | 008ff9d7 | j_mayer | end = 31;
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139 | 008ff9d7 | j_mayer | inc = 1;
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140 | 008ff9d7 | j_mayer | } |
141 | 008ff9d7 | j_mayer | uic->uicvr = uic->uicvcr & 0xFFFFFFFC;
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142 | 008ff9d7 | j_mayer | for (i = start; i <= end; i += inc) {
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143 | 008ff9d7 | j_mayer | if (cr & (1 << i)) { |
144 | 008ff9d7 | j_mayer | uic->uicvr += (i - start) * 512 * inc;
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145 | 008ff9d7 | j_mayer | break;
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146 | 008ff9d7 | j_mayer | } |
147 | 008ff9d7 | j_mayer | } |
148 | 008ff9d7 | j_mayer | } |
149 | d12d51d5 | aliguori | LOG_UIC("Raise UIC critical interrupt - "
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150 | aae9366a | j_mayer | "vector %08" PRIx32 "\n", uic->uicvr); |
151 | 008ff9d7 | j_mayer | } else {
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152 | d12d51d5 | aliguori | LOG_UIC("Lower UIC critical interrupt\n");
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153 | 008ff9d7 | j_mayer | qemu_irq_lower(uic->irqs[PPCUIC_OUTPUT_CINT]); |
154 | 008ff9d7 | j_mayer | uic->uicvr = 0x00000000;
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155 | 008ff9d7 | j_mayer | } |
156 | 008ff9d7 | j_mayer | } |
157 | 008ff9d7 | j_mayer | |
158 | 008ff9d7 | j_mayer | static void ppcuic_set_irq (void *opaque, int irq_num, int level) |
159 | 008ff9d7 | j_mayer | { |
160 | c227f099 | Anthony Liguori | ppcuic_t *uic; |
161 | 008ff9d7 | j_mayer | uint32_t mask, sr; |
162 | 008ff9d7 | j_mayer | |
163 | 008ff9d7 | j_mayer | uic = opaque; |
164 | 923e5e33 | aurel32 | mask = 1 << (31-irq_num); |
165 | d12d51d5 | aliguori | LOG_UIC("%s: irq %d level %d uicsr %08" PRIx32
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166 | aae9366a | j_mayer | " mask %08" PRIx32 " => %08" PRIx32 " %08" PRIx32 "\n", |
167 | aae9366a | j_mayer | __func__, irq_num, level, |
168 | 008ff9d7 | j_mayer | uic->uicsr, mask, uic->uicsr & mask, level << irq_num); |
169 | 008ff9d7 | j_mayer | if (irq_num < 0 || irq_num > 31) |
170 | 008ff9d7 | j_mayer | return;
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171 | 008ff9d7 | j_mayer | sr = uic->uicsr; |
172 | 50bf72b3 | aurel32 | |
173 | 008ff9d7 | j_mayer | /* Update status register */
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174 | 008ff9d7 | j_mayer | if (uic->uictr & mask) {
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175 | 008ff9d7 | j_mayer | /* Edge sensitive interrupt */
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176 | 008ff9d7 | j_mayer | if (level == 1) |
177 | 008ff9d7 | j_mayer | uic->uicsr |= mask; |
178 | 008ff9d7 | j_mayer | } else {
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179 | 008ff9d7 | j_mayer | /* Level sensitive interrupt */
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180 | 4c54e875 | aurel32 | if (level == 1) { |
181 | 008ff9d7 | j_mayer | uic->uicsr |= mask; |
182 | 4c54e875 | aurel32 | uic->level |= mask; |
183 | 4c54e875 | aurel32 | } else {
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184 | 008ff9d7 | j_mayer | uic->uicsr &= ~mask; |
185 | 4c54e875 | aurel32 | uic->level &= ~mask; |
186 | 4c54e875 | aurel32 | } |
187 | 008ff9d7 | j_mayer | } |
188 | d12d51d5 | aliguori | LOG_UIC("%s: irq %d level %d sr %" PRIx32 " => " |
189 | aae9366a | j_mayer | "%08" PRIx32 "\n", __func__, irq_num, level, uic->uicsr, sr); |
190 | 008ff9d7 | j_mayer | if (sr != uic->uicsr)
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191 | 008ff9d7 | j_mayer | ppcuic_trigger_irq(uic); |
192 | 008ff9d7 | j_mayer | } |
193 | 008ff9d7 | j_mayer | |
194 | 73b01960 | Alexander Graf | static uint32_t dcr_read_uic (void *opaque, int dcrn) |
195 | 008ff9d7 | j_mayer | { |
196 | c227f099 | Anthony Liguori | ppcuic_t *uic; |
197 | 73b01960 | Alexander Graf | uint32_t ret; |
198 | 008ff9d7 | j_mayer | |
199 | 008ff9d7 | j_mayer | uic = opaque; |
200 | 008ff9d7 | j_mayer | dcrn -= uic->dcr_base; |
201 | 008ff9d7 | j_mayer | switch (dcrn) {
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202 | 008ff9d7 | j_mayer | case DCR_UICSR:
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203 | 008ff9d7 | j_mayer | case DCR_UICSRS:
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204 | 008ff9d7 | j_mayer | ret = uic->uicsr; |
205 | 008ff9d7 | j_mayer | break;
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206 | 008ff9d7 | j_mayer | case DCR_UICER:
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207 | 008ff9d7 | j_mayer | ret = uic->uicer; |
208 | 008ff9d7 | j_mayer | break;
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209 | 008ff9d7 | j_mayer | case DCR_UICCR:
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210 | 008ff9d7 | j_mayer | ret = uic->uiccr; |
211 | 008ff9d7 | j_mayer | break;
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212 | 008ff9d7 | j_mayer | case DCR_UICPR:
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213 | 008ff9d7 | j_mayer | ret = uic->uicpr; |
214 | 008ff9d7 | j_mayer | break;
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215 | 008ff9d7 | j_mayer | case DCR_UICTR:
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216 | 008ff9d7 | j_mayer | ret = uic->uictr; |
217 | 008ff9d7 | j_mayer | break;
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218 | 008ff9d7 | j_mayer | case DCR_UICMSR:
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219 | 008ff9d7 | j_mayer | ret = uic->uicsr & uic->uicer; |
220 | 008ff9d7 | j_mayer | break;
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221 | 008ff9d7 | j_mayer | case DCR_UICVR:
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222 | 008ff9d7 | j_mayer | if (!uic->use_vectors)
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223 | 008ff9d7 | j_mayer | goto no_read;
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224 | 008ff9d7 | j_mayer | ret = uic->uicvr; |
225 | 008ff9d7 | j_mayer | break;
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226 | 008ff9d7 | j_mayer | case DCR_UICVCR:
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227 | 008ff9d7 | j_mayer | if (!uic->use_vectors)
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228 | 008ff9d7 | j_mayer | goto no_read;
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229 | 008ff9d7 | j_mayer | ret = uic->uicvcr; |
230 | 008ff9d7 | j_mayer | break;
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231 | 008ff9d7 | j_mayer | default:
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232 | 008ff9d7 | j_mayer | no_read:
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233 | 008ff9d7 | j_mayer | ret = 0x00000000;
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234 | 008ff9d7 | j_mayer | break;
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235 | 008ff9d7 | j_mayer | } |
236 | 008ff9d7 | j_mayer | |
237 | 008ff9d7 | j_mayer | return ret;
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238 | 008ff9d7 | j_mayer | } |
239 | 008ff9d7 | j_mayer | |
240 | 73b01960 | Alexander Graf | static void dcr_write_uic (void *opaque, int dcrn, uint32_t val) |
241 | 008ff9d7 | j_mayer | { |
242 | c227f099 | Anthony Liguori | ppcuic_t *uic; |
243 | 008ff9d7 | j_mayer | |
244 | 008ff9d7 | j_mayer | uic = opaque; |
245 | 008ff9d7 | j_mayer | dcrn -= uic->dcr_base; |
246 | 73b01960 | Alexander Graf | LOG_UIC("%s: dcr %d val 0x%x\n", __func__, dcrn, val);
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247 | 008ff9d7 | j_mayer | switch (dcrn) {
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248 | 008ff9d7 | j_mayer | case DCR_UICSR:
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249 | 008ff9d7 | j_mayer | uic->uicsr &= ~val; |
250 | 4c54e875 | aurel32 | uic->uicsr |= uic->level; |
251 | 008ff9d7 | j_mayer | ppcuic_trigger_irq(uic); |
252 | 008ff9d7 | j_mayer | break;
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253 | 008ff9d7 | j_mayer | case DCR_UICSRS:
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254 | 008ff9d7 | j_mayer | uic->uicsr |= val; |
255 | 008ff9d7 | j_mayer | ppcuic_trigger_irq(uic); |
256 | 008ff9d7 | j_mayer | break;
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257 | 008ff9d7 | j_mayer | case DCR_UICER:
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258 | 008ff9d7 | j_mayer | uic->uicer = val; |
259 | 008ff9d7 | j_mayer | ppcuic_trigger_irq(uic); |
260 | 008ff9d7 | j_mayer | break;
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261 | 008ff9d7 | j_mayer | case DCR_UICCR:
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262 | 008ff9d7 | j_mayer | uic->uiccr = val; |
263 | 008ff9d7 | j_mayer | ppcuic_trigger_irq(uic); |
264 | 008ff9d7 | j_mayer | break;
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265 | 008ff9d7 | j_mayer | case DCR_UICPR:
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266 | 008ff9d7 | j_mayer | uic->uicpr = val; |
267 | 008ff9d7 | j_mayer | break;
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268 | 008ff9d7 | j_mayer | case DCR_UICTR:
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269 | 008ff9d7 | j_mayer | uic->uictr = val; |
270 | 008ff9d7 | j_mayer | ppcuic_trigger_irq(uic); |
271 | 008ff9d7 | j_mayer | break;
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272 | 008ff9d7 | j_mayer | case DCR_UICMSR:
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273 | 008ff9d7 | j_mayer | break;
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274 | 008ff9d7 | j_mayer | case DCR_UICVR:
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275 | 008ff9d7 | j_mayer | break;
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276 | 008ff9d7 | j_mayer | case DCR_UICVCR:
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277 | 008ff9d7 | j_mayer | uic->uicvcr = val & 0xFFFFFFFD;
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278 | 008ff9d7 | j_mayer | ppcuic_trigger_irq(uic); |
279 | 008ff9d7 | j_mayer | break;
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280 | 008ff9d7 | j_mayer | } |
281 | 008ff9d7 | j_mayer | } |
282 | 008ff9d7 | j_mayer | |
283 | 008ff9d7 | j_mayer | static void ppcuic_reset (void *opaque) |
284 | 008ff9d7 | j_mayer | { |
285 | c227f099 | Anthony Liguori | ppcuic_t *uic; |
286 | 008ff9d7 | j_mayer | |
287 | 008ff9d7 | j_mayer | uic = opaque; |
288 | 008ff9d7 | j_mayer | uic->uiccr = 0x00000000;
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289 | 008ff9d7 | j_mayer | uic->uicer = 0x00000000;
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290 | 008ff9d7 | j_mayer | uic->uicpr = 0x00000000;
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291 | 008ff9d7 | j_mayer | uic->uicsr = 0x00000000;
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292 | 008ff9d7 | j_mayer | uic->uictr = 0x00000000;
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293 | 008ff9d7 | j_mayer | if (uic->use_vectors) {
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294 | 008ff9d7 | j_mayer | uic->uicvcr = 0x00000000;
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295 | 008ff9d7 | j_mayer | uic->uicvr = 0x0000000;
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296 | 008ff9d7 | j_mayer | } |
297 | 008ff9d7 | j_mayer | } |
298 | 008ff9d7 | j_mayer | |
299 | e2684c0b | Andreas Färber | qemu_irq *ppcuic_init (CPUPPCState *env, qemu_irq *irqs, |
300 | 008ff9d7 | j_mayer | uint32_t dcr_base, int has_ssr, int has_vr) |
301 | 008ff9d7 | j_mayer | { |
302 | c227f099 | Anthony Liguori | ppcuic_t *uic; |
303 | 008ff9d7 | j_mayer | int i;
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304 | 008ff9d7 | j_mayer | |
305 | 7267c094 | Anthony Liguori | uic = g_malloc0(sizeof(ppcuic_t));
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306 | 487414f1 | aliguori | uic->dcr_base = dcr_base; |
307 | 487414f1 | aliguori | uic->irqs = irqs; |
308 | 487414f1 | aliguori | if (has_vr)
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309 | 487414f1 | aliguori | uic->use_vectors = 1;
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310 | 487414f1 | aliguori | for (i = 0; i < DCR_UICMAX; i++) { |
311 | 487414f1 | aliguori | ppc_dcr_register(env, dcr_base + i, uic, |
312 | 487414f1 | aliguori | &dcr_read_uic, &dcr_write_uic); |
313 | 008ff9d7 | j_mayer | } |
314 | a08d4367 | Jan Kiszka | qemu_register_reset(ppcuic_reset, uic); |
315 | 008ff9d7 | j_mayer | |
316 | 008ff9d7 | j_mayer | return qemu_allocate_irqs(&ppcuic_set_irq, uic, UIC_MAX_IRQ);
|
317 | 008ff9d7 | j_mayer | } |
318 | 61b24405 | aurel32 | |
319 | 61b24405 | aurel32 | /*****************************************************************************/
|
320 | 61b24405 | aurel32 | /* SDRAM controller */
|
321 | c227f099 | Anthony Liguori | typedef struct ppc4xx_sdram_t ppc4xx_sdram_t; |
322 | c227f099 | Anthony Liguori | struct ppc4xx_sdram_t {
|
323 | 61b24405 | aurel32 | uint32_t addr; |
324 | 61b24405 | aurel32 | int nbanks;
|
325 | b6dcbe08 | Avi Kivity | MemoryRegion containers[4]; /* used for clipping */ |
326 | b6dcbe08 | Avi Kivity | MemoryRegion *ram_memories; |
327 | a8170e5e | Avi Kivity | hwaddr ram_bases[4];
|
328 | a8170e5e | Avi Kivity | hwaddr ram_sizes[4];
|
329 | 61b24405 | aurel32 | uint32_t besr0; |
330 | 61b24405 | aurel32 | uint32_t besr1; |
331 | 61b24405 | aurel32 | uint32_t bear; |
332 | 61b24405 | aurel32 | uint32_t cfg; |
333 | 61b24405 | aurel32 | uint32_t status; |
334 | 61b24405 | aurel32 | uint32_t rtr; |
335 | 61b24405 | aurel32 | uint32_t pmit; |
336 | 61b24405 | aurel32 | uint32_t bcr[4];
|
337 | 61b24405 | aurel32 | uint32_t tr; |
338 | 61b24405 | aurel32 | uint32_t ecccfg; |
339 | 61b24405 | aurel32 | uint32_t eccesr; |
340 | 61b24405 | aurel32 | qemu_irq irq; |
341 | 61b24405 | aurel32 | }; |
342 | 61b24405 | aurel32 | |
343 | 61b24405 | aurel32 | enum {
|
344 | 61b24405 | aurel32 | SDRAM0_CFGADDR = 0x010,
|
345 | 61b24405 | aurel32 | SDRAM0_CFGDATA = 0x011,
|
346 | 61b24405 | aurel32 | }; |
347 | 61b24405 | aurel32 | |
348 | 61b24405 | aurel32 | /* XXX: TOFIX: some patches have made this code become inconsistent:
|
349 | a8170e5e | Avi Kivity | * there are type inconsistencies, mixing hwaddr, target_ulong
|
350 | 61b24405 | aurel32 | * and uint32_t
|
351 | 61b24405 | aurel32 | */
|
352 | a8170e5e | Avi Kivity | static uint32_t sdram_bcr (hwaddr ram_base,
|
353 | a8170e5e | Avi Kivity | hwaddr ram_size) |
354 | 61b24405 | aurel32 | { |
355 | 61b24405 | aurel32 | uint32_t bcr; |
356 | 61b24405 | aurel32 | |
357 | 61b24405 | aurel32 | switch (ram_size) {
|
358 | 61b24405 | aurel32 | case (4 * 1024 * 1024): |
359 | 61b24405 | aurel32 | bcr = 0x00000000;
|
360 | 61b24405 | aurel32 | break;
|
361 | 61b24405 | aurel32 | case (8 * 1024 * 1024): |
362 | 61b24405 | aurel32 | bcr = 0x00020000;
|
363 | 61b24405 | aurel32 | break;
|
364 | 61b24405 | aurel32 | case (16 * 1024 * 1024): |
365 | 61b24405 | aurel32 | bcr = 0x00040000;
|
366 | 61b24405 | aurel32 | break;
|
367 | 61b24405 | aurel32 | case (32 * 1024 * 1024): |
368 | 61b24405 | aurel32 | bcr = 0x00060000;
|
369 | 61b24405 | aurel32 | break;
|
370 | 61b24405 | aurel32 | case (64 * 1024 * 1024): |
371 | 61b24405 | aurel32 | bcr = 0x00080000;
|
372 | 61b24405 | aurel32 | break;
|
373 | 61b24405 | aurel32 | case (128 * 1024 * 1024): |
374 | 61b24405 | aurel32 | bcr = 0x000A0000;
|
375 | 61b24405 | aurel32 | break;
|
376 | 61b24405 | aurel32 | case (256 * 1024 * 1024): |
377 | 61b24405 | aurel32 | bcr = 0x000C0000;
|
378 | 61b24405 | aurel32 | break;
|
379 | 61b24405 | aurel32 | default:
|
380 | 90e189ec | Blue Swirl | printf("%s: invalid RAM size " TARGET_FMT_plx "\n", __func__, |
381 | 90e189ec | Blue Swirl | ram_size); |
382 | 61b24405 | aurel32 | return 0x00000000; |
383 | 61b24405 | aurel32 | } |
384 | 61b24405 | aurel32 | bcr |= ram_base & 0xFF800000;
|
385 | 61b24405 | aurel32 | bcr |= 1;
|
386 | 61b24405 | aurel32 | |
387 | 61b24405 | aurel32 | return bcr;
|
388 | 61b24405 | aurel32 | } |
389 | 61b24405 | aurel32 | |
390 | a8170e5e | Avi Kivity | static inline hwaddr sdram_base(uint32_t bcr) |
391 | 61b24405 | aurel32 | { |
392 | 61b24405 | aurel32 | return bcr & 0xFF800000; |
393 | 61b24405 | aurel32 | } |
394 | 61b24405 | aurel32 | |
395 | 61b24405 | aurel32 | static target_ulong sdram_size (uint32_t bcr)
|
396 | 61b24405 | aurel32 | { |
397 | 61b24405 | aurel32 | target_ulong size; |
398 | 61b24405 | aurel32 | int sh;
|
399 | 61b24405 | aurel32 | |
400 | 61b24405 | aurel32 | sh = (bcr >> 17) & 0x7; |
401 | 61b24405 | aurel32 | if (sh == 7) |
402 | 61b24405 | aurel32 | size = -1;
|
403 | 61b24405 | aurel32 | else
|
404 | 61b24405 | aurel32 | size = (4 * 1024 * 1024) << sh; |
405 | 61b24405 | aurel32 | |
406 | 61b24405 | aurel32 | return size;
|
407 | 61b24405 | aurel32 | } |
408 | 61b24405 | aurel32 | |
409 | b6dcbe08 | Avi Kivity | static void sdram_set_bcr(ppc4xx_sdram_t *sdram, |
410 | b6dcbe08 | Avi Kivity | uint32_t *bcrp, uint32_t bcr, int enabled)
|
411 | 61b24405 | aurel32 | { |
412 | b6dcbe08 | Avi Kivity | unsigned n = bcrp - sdram->bcr;
|
413 | b6dcbe08 | Avi Kivity | |
414 | 61b24405 | aurel32 | if (*bcrp & 0x00000001) { |
415 | 61b24405 | aurel32 | /* Unmap RAM */
|
416 | 61b24405 | aurel32 | #ifdef DEBUG_SDRAM
|
417 | 90e189ec | Blue Swirl | printf("%s: unmap RAM area " TARGET_FMT_plx " " TARGET_FMT_lx "\n", |
418 | 61b24405 | aurel32 | __func__, sdram_base(*bcrp), sdram_size(*bcrp)); |
419 | 61b24405 | aurel32 | #endif
|
420 | b6dcbe08 | Avi Kivity | memory_region_del_subregion(get_system_memory(), |
421 | b6dcbe08 | Avi Kivity | &sdram->containers[n]); |
422 | b6dcbe08 | Avi Kivity | memory_region_del_subregion(&sdram->containers[n], |
423 | b6dcbe08 | Avi Kivity | &sdram->ram_memories[n]); |
424 | b6dcbe08 | Avi Kivity | memory_region_destroy(&sdram->containers[n]); |
425 | 61b24405 | aurel32 | } |
426 | 61b24405 | aurel32 | *bcrp = bcr & 0xFFDEE001;
|
427 | 61b24405 | aurel32 | if (enabled && (bcr & 0x00000001)) { |
428 | 61b24405 | aurel32 | #ifdef DEBUG_SDRAM
|
429 | 90e189ec | Blue Swirl | printf("%s: Map RAM area " TARGET_FMT_plx " " TARGET_FMT_lx "\n", |
430 | 61b24405 | aurel32 | __func__, sdram_base(bcr), sdram_size(bcr)); |
431 | 61b24405 | aurel32 | #endif
|
432 | 2c9b15ca | Paolo Bonzini | memory_region_init(&sdram->containers[n], NULL, "sdram-containers", |
433 | b6dcbe08 | Avi Kivity | sdram_size(bcr)); |
434 | b6dcbe08 | Avi Kivity | memory_region_add_subregion(&sdram->containers[n], 0,
|
435 | b6dcbe08 | Avi Kivity | &sdram->ram_memories[n]); |
436 | b6dcbe08 | Avi Kivity | memory_region_add_subregion(get_system_memory(), |
437 | b6dcbe08 | Avi Kivity | sdram_base(bcr), |
438 | b6dcbe08 | Avi Kivity | &sdram->containers[n]); |
439 | 61b24405 | aurel32 | } |
440 | 61b24405 | aurel32 | } |
441 | 61b24405 | aurel32 | |
442 | c227f099 | Anthony Liguori | static void sdram_map_bcr (ppc4xx_sdram_t *sdram) |
443 | 61b24405 | aurel32 | { |
444 | 61b24405 | aurel32 | int i;
|
445 | 61b24405 | aurel32 | |
446 | 61b24405 | aurel32 | for (i = 0; i < sdram->nbanks; i++) { |
447 | 61b24405 | aurel32 | if (sdram->ram_sizes[i] != 0) { |
448 | b6dcbe08 | Avi Kivity | sdram_set_bcr(sdram, |
449 | b6dcbe08 | Avi Kivity | &sdram->bcr[i], |
450 | 61b24405 | aurel32 | sdram_bcr(sdram->ram_bases[i], sdram->ram_sizes[i]), |
451 | 61b24405 | aurel32 | 1);
|
452 | 61b24405 | aurel32 | } else {
|
453 | b6dcbe08 | Avi Kivity | sdram_set_bcr(sdram, &sdram->bcr[i], 0x00000000, 0); |
454 | 61b24405 | aurel32 | } |
455 | 61b24405 | aurel32 | } |
456 | 61b24405 | aurel32 | } |
457 | 61b24405 | aurel32 | |
458 | c227f099 | Anthony Liguori | static void sdram_unmap_bcr (ppc4xx_sdram_t *sdram) |
459 | 61b24405 | aurel32 | { |
460 | 61b24405 | aurel32 | int i;
|
461 | 61b24405 | aurel32 | |
462 | 61b24405 | aurel32 | for (i = 0; i < sdram->nbanks; i++) { |
463 | 61b24405 | aurel32 | #ifdef DEBUG_SDRAM
|
464 | 90e189ec | Blue Swirl | printf("%s: Unmap RAM area " TARGET_FMT_plx " " TARGET_FMT_lx "\n", |
465 | 61b24405 | aurel32 | __func__, sdram_base(sdram->bcr[i]), sdram_size(sdram->bcr[i])); |
466 | 61b24405 | aurel32 | #endif
|
467 | b6dcbe08 | Avi Kivity | memory_region_del_subregion(get_system_memory(), |
468 | b6dcbe08 | Avi Kivity | &sdram->ram_memories[i]); |
469 | 61b24405 | aurel32 | } |
470 | 61b24405 | aurel32 | } |
471 | 61b24405 | aurel32 | |
472 | 73b01960 | Alexander Graf | static uint32_t dcr_read_sdram (void *opaque, int dcrn) |
473 | 61b24405 | aurel32 | { |
474 | c227f099 | Anthony Liguori | ppc4xx_sdram_t *sdram; |
475 | 73b01960 | Alexander Graf | uint32_t ret; |
476 | 61b24405 | aurel32 | |
477 | 61b24405 | aurel32 | sdram = opaque; |
478 | 61b24405 | aurel32 | switch (dcrn) {
|
479 | 61b24405 | aurel32 | case SDRAM0_CFGADDR:
|
480 | 61b24405 | aurel32 | ret = sdram->addr; |
481 | 61b24405 | aurel32 | break;
|
482 | 61b24405 | aurel32 | case SDRAM0_CFGDATA:
|
483 | 61b24405 | aurel32 | switch (sdram->addr) {
|
484 | 61b24405 | aurel32 | case 0x00: /* SDRAM_BESR0 */ |
485 | 61b24405 | aurel32 | ret = sdram->besr0; |
486 | 61b24405 | aurel32 | break;
|
487 | 61b24405 | aurel32 | case 0x08: /* SDRAM_BESR1 */ |
488 | 61b24405 | aurel32 | ret = sdram->besr1; |
489 | 61b24405 | aurel32 | break;
|
490 | 61b24405 | aurel32 | case 0x10: /* SDRAM_BEAR */ |
491 | 61b24405 | aurel32 | ret = sdram->bear; |
492 | 61b24405 | aurel32 | break;
|
493 | 61b24405 | aurel32 | case 0x20: /* SDRAM_CFG */ |
494 | 61b24405 | aurel32 | ret = sdram->cfg; |
495 | 61b24405 | aurel32 | break;
|
496 | 61b24405 | aurel32 | case 0x24: /* SDRAM_STATUS */ |
497 | 61b24405 | aurel32 | ret = sdram->status; |
498 | 61b24405 | aurel32 | break;
|
499 | 61b24405 | aurel32 | case 0x30: /* SDRAM_RTR */ |
500 | 61b24405 | aurel32 | ret = sdram->rtr; |
501 | 61b24405 | aurel32 | break;
|
502 | 61b24405 | aurel32 | case 0x34: /* SDRAM_PMIT */ |
503 | 61b24405 | aurel32 | ret = sdram->pmit; |
504 | 61b24405 | aurel32 | break;
|
505 | 61b24405 | aurel32 | case 0x40: /* SDRAM_B0CR */ |
506 | 61b24405 | aurel32 | ret = sdram->bcr[0];
|
507 | 61b24405 | aurel32 | break;
|
508 | 61b24405 | aurel32 | case 0x44: /* SDRAM_B1CR */ |
509 | 61b24405 | aurel32 | ret = sdram->bcr[1];
|
510 | 61b24405 | aurel32 | break;
|
511 | 61b24405 | aurel32 | case 0x48: /* SDRAM_B2CR */ |
512 | 61b24405 | aurel32 | ret = sdram->bcr[2];
|
513 | 61b24405 | aurel32 | break;
|
514 | 61b24405 | aurel32 | case 0x4C: /* SDRAM_B3CR */ |
515 | 61b24405 | aurel32 | ret = sdram->bcr[3];
|
516 | 61b24405 | aurel32 | break;
|
517 | 61b24405 | aurel32 | case 0x80: /* SDRAM_TR */ |
518 | 61b24405 | aurel32 | ret = -1; /* ? */ |
519 | 61b24405 | aurel32 | break;
|
520 | 61b24405 | aurel32 | case 0x94: /* SDRAM_ECCCFG */ |
521 | 61b24405 | aurel32 | ret = sdram->ecccfg; |
522 | 61b24405 | aurel32 | break;
|
523 | 61b24405 | aurel32 | case 0x98: /* SDRAM_ECCESR */ |
524 | 61b24405 | aurel32 | ret = sdram->eccesr; |
525 | 61b24405 | aurel32 | break;
|
526 | 61b24405 | aurel32 | default: /* Error */ |
527 | 61b24405 | aurel32 | ret = -1;
|
528 | 61b24405 | aurel32 | break;
|
529 | 61b24405 | aurel32 | } |
530 | 61b24405 | aurel32 | break;
|
531 | 61b24405 | aurel32 | default:
|
532 | 61b24405 | aurel32 | /* Avoid gcc warning */
|
533 | 61b24405 | aurel32 | ret = 0x00000000;
|
534 | 61b24405 | aurel32 | break;
|
535 | 61b24405 | aurel32 | } |
536 | 61b24405 | aurel32 | |
537 | 61b24405 | aurel32 | return ret;
|
538 | 61b24405 | aurel32 | } |
539 | 61b24405 | aurel32 | |
540 | 73b01960 | Alexander Graf | static void dcr_write_sdram (void *opaque, int dcrn, uint32_t val) |
541 | 61b24405 | aurel32 | { |
542 | c227f099 | Anthony Liguori | ppc4xx_sdram_t *sdram; |
543 | 61b24405 | aurel32 | |
544 | 61b24405 | aurel32 | sdram = opaque; |
545 | 61b24405 | aurel32 | switch (dcrn) {
|
546 | 61b24405 | aurel32 | case SDRAM0_CFGADDR:
|
547 | 61b24405 | aurel32 | sdram->addr = val; |
548 | 61b24405 | aurel32 | break;
|
549 | 61b24405 | aurel32 | case SDRAM0_CFGDATA:
|
550 | 61b24405 | aurel32 | switch (sdram->addr) {
|
551 | 61b24405 | aurel32 | case 0x00: /* SDRAM_BESR0 */ |
552 | 61b24405 | aurel32 | sdram->besr0 &= ~val; |
553 | 61b24405 | aurel32 | break;
|
554 | 61b24405 | aurel32 | case 0x08: /* SDRAM_BESR1 */ |
555 | 61b24405 | aurel32 | sdram->besr1 &= ~val; |
556 | 61b24405 | aurel32 | break;
|
557 | 61b24405 | aurel32 | case 0x10: /* SDRAM_BEAR */ |
558 | 61b24405 | aurel32 | sdram->bear = val; |
559 | 61b24405 | aurel32 | break;
|
560 | 61b24405 | aurel32 | case 0x20: /* SDRAM_CFG */ |
561 | 61b24405 | aurel32 | val &= 0xFFE00000;
|
562 | 61b24405 | aurel32 | if (!(sdram->cfg & 0x80000000) && (val & 0x80000000)) { |
563 | 61b24405 | aurel32 | #ifdef DEBUG_SDRAM
|
564 | 61b24405 | aurel32 | printf("%s: enable SDRAM controller\n", __func__);
|
565 | 61b24405 | aurel32 | #endif
|
566 | 61b24405 | aurel32 | /* validate all RAM mappings */
|
567 | 61b24405 | aurel32 | sdram_map_bcr(sdram); |
568 | 61b24405 | aurel32 | sdram->status &= ~0x80000000;
|
569 | 61b24405 | aurel32 | } else if ((sdram->cfg & 0x80000000) && !(val & 0x80000000)) { |
570 | 61b24405 | aurel32 | #ifdef DEBUG_SDRAM
|
571 | 61b24405 | aurel32 | printf("%s: disable SDRAM controller\n", __func__);
|
572 | 61b24405 | aurel32 | #endif
|
573 | 61b24405 | aurel32 | /* invalidate all RAM mappings */
|
574 | 61b24405 | aurel32 | sdram_unmap_bcr(sdram); |
575 | 61b24405 | aurel32 | sdram->status |= 0x80000000;
|
576 | 61b24405 | aurel32 | } |
577 | 61b24405 | aurel32 | if (!(sdram->cfg & 0x40000000) && (val & 0x40000000)) |
578 | 61b24405 | aurel32 | sdram->status |= 0x40000000;
|
579 | 61b24405 | aurel32 | else if ((sdram->cfg & 0x40000000) && !(val & 0x40000000)) |
580 | 61b24405 | aurel32 | sdram->status &= ~0x40000000;
|
581 | 61b24405 | aurel32 | sdram->cfg = val; |
582 | 61b24405 | aurel32 | break;
|
583 | 61b24405 | aurel32 | case 0x24: /* SDRAM_STATUS */ |
584 | 61b24405 | aurel32 | /* Read-only register */
|
585 | 61b24405 | aurel32 | break;
|
586 | 61b24405 | aurel32 | case 0x30: /* SDRAM_RTR */ |
587 | 61b24405 | aurel32 | sdram->rtr = val & 0x3FF80000;
|
588 | 61b24405 | aurel32 | break;
|
589 | 61b24405 | aurel32 | case 0x34: /* SDRAM_PMIT */ |
590 | 61b24405 | aurel32 | sdram->pmit = (val & 0xF8000000) | 0x07C00000; |
591 | 61b24405 | aurel32 | break;
|
592 | 61b24405 | aurel32 | case 0x40: /* SDRAM_B0CR */ |
593 | b6dcbe08 | Avi Kivity | sdram_set_bcr(sdram, &sdram->bcr[0], val, sdram->cfg & 0x80000000); |
594 | 61b24405 | aurel32 | break;
|
595 | 61b24405 | aurel32 | case 0x44: /* SDRAM_B1CR */ |
596 | b6dcbe08 | Avi Kivity | sdram_set_bcr(sdram, &sdram->bcr[1], val, sdram->cfg & 0x80000000); |
597 | 61b24405 | aurel32 | break;
|
598 | 61b24405 | aurel32 | case 0x48: /* SDRAM_B2CR */ |
599 | b6dcbe08 | Avi Kivity | sdram_set_bcr(sdram, &sdram->bcr[2], val, sdram->cfg & 0x80000000); |
600 | 61b24405 | aurel32 | break;
|
601 | 61b24405 | aurel32 | case 0x4C: /* SDRAM_B3CR */ |
602 | b6dcbe08 | Avi Kivity | sdram_set_bcr(sdram, &sdram->bcr[3], val, sdram->cfg & 0x80000000); |
603 | 61b24405 | aurel32 | break;
|
604 | 61b24405 | aurel32 | case 0x80: /* SDRAM_TR */ |
605 | 61b24405 | aurel32 | sdram->tr = val & 0x018FC01F;
|
606 | 61b24405 | aurel32 | break;
|
607 | 61b24405 | aurel32 | case 0x94: /* SDRAM_ECCCFG */ |
608 | 61b24405 | aurel32 | sdram->ecccfg = val & 0x00F00000;
|
609 | 61b24405 | aurel32 | break;
|
610 | 61b24405 | aurel32 | case 0x98: /* SDRAM_ECCESR */ |
611 | 61b24405 | aurel32 | val &= 0xFFF0F000;
|
612 | 61b24405 | aurel32 | if (sdram->eccesr == 0 && val != 0) |
613 | 61b24405 | aurel32 | qemu_irq_raise(sdram->irq); |
614 | 61b24405 | aurel32 | else if (sdram->eccesr != 0 && val == 0) |
615 | 61b24405 | aurel32 | qemu_irq_lower(sdram->irq); |
616 | 61b24405 | aurel32 | sdram->eccesr = val; |
617 | 61b24405 | aurel32 | break;
|
618 | 61b24405 | aurel32 | default: /* Error */ |
619 | 61b24405 | aurel32 | break;
|
620 | 61b24405 | aurel32 | } |
621 | 61b24405 | aurel32 | break;
|
622 | 61b24405 | aurel32 | } |
623 | 61b24405 | aurel32 | } |
624 | 61b24405 | aurel32 | |
625 | 61b24405 | aurel32 | static void sdram_reset (void *opaque) |
626 | 61b24405 | aurel32 | { |
627 | c227f099 | Anthony Liguori | ppc4xx_sdram_t *sdram; |
628 | 61b24405 | aurel32 | |
629 | 61b24405 | aurel32 | sdram = opaque; |
630 | 61b24405 | aurel32 | sdram->addr = 0x00000000;
|
631 | 61b24405 | aurel32 | sdram->bear = 0x00000000;
|
632 | 61b24405 | aurel32 | sdram->besr0 = 0x00000000; /* No error */ |
633 | 61b24405 | aurel32 | sdram->besr1 = 0x00000000; /* No error */ |
634 | 61b24405 | aurel32 | sdram->cfg = 0x00000000;
|
635 | 61b24405 | aurel32 | sdram->ecccfg = 0x00000000; /* No ECC */ |
636 | 61b24405 | aurel32 | sdram->eccesr = 0x00000000; /* No error */ |
637 | 61b24405 | aurel32 | sdram->pmit = 0x07C00000;
|
638 | 61b24405 | aurel32 | sdram->rtr = 0x05F00000;
|
639 | 61b24405 | aurel32 | sdram->tr = 0x00854009;
|
640 | 61b24405 | aurel32 | /* We pre-initialize RAM banks */
|
641 | 61b24405 | aurel32 | sdram->status = 0x00000000;
|
642 | 61b24405 | aurel32 | sdram->cfg = 0x00800000;
|
643 | 61b24405 | aurel32 | } |
644 | 61b24405 | aurel32 | |
645 | e2684c0b | Andreas Färber | void ppc4xx_sdram_init (CPUPPCState *env, qemu_irq irq, int nbanks, |
646 | b6dcbe08 | Avi Kivity | MemoryRegion *ram_memories, |
647 | a8170e5e | Avi Kivity | hwaddr *ram_bases, |
648 | a8170e5e | Avi Kivity | hwaddr *ram_sizes, |
649 | 61b24405 | aurel32 | int do_init)
|
650 | 61b24405 | aurel32 | { |
651 | c227f099 | Anthony Liguori | ppc4xx_sdram_t *sdram; |
652 | 61b24405 | aurel32 | |
653 | 7267c094 | Anthony Liguori | sdram = g_malloc0(sizeof(ppc4xx_sdram_t));
|
654 | 487414f1 | aliguori | sdram->irq = irq; |
655 | 487414f1 | aliguori | sdram->nbanks = nbanks; |
656 | b6dcbe08 | Avi Kivity | sdram->ram_memories = ram_memories; |
657 | a8170e5e | Avi Kivity | memset(sdram->ram_bases, 0, 4 * sizeof(hwaddr)); |
658 | 487414f1 | aliguori | memcpy(sdram->ram_bases, ram_bases, |
659 | a8170e5e | Avi Kivity | nbanks * sizeof(hwaddr));
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660 | a8170e5e | Avi Kivity | memset(sdram->ram_sizes, 0, 4 * sizeof(hwaddr)); |
661 | 487414f1 | aliguori | memcpy(sdram->ram_sizes, ram_sizes, |
662 | a8170e5e | Avi Kivity | nbanks * sizeof(hwaddr));
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663 | a08d4367 | Jan Kiszka | qemu_register_reset(&sdram_reset, sdram); |
664 | 487414f1 | aliguori | ppc_dcr_register(env, SDRAM0_CFGADDR, |
665 | 487414f1 | aliguori | sdram, &dcr_read_sdram, &dcr_write_sdram); |
666 | 487414f1 | aliguori | ppc_dcr_register(env, SDRAM0_CFGDATA, |
667 | 487414f1 | aliguori | sdram, &dcr_read_sdram, &dcr_write_sdram); |
668 | 487414f1 | aliguori | if (do_init)
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669 | 487414f1 | aliguori | sdram_map_bcr(sdram); |
670 | 61b24405 | aurel32 | } |
671 | b7da58fd | aurel32 | |
672 | b7da58fd | aurel32 | /* Fill in consecutive SDRAM banks with 'ram_size' bytes of memory.
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673 | b7da58fd | aurel32 | *
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674 | b7da58fd | aurel32 | * sdram_bank_sizes[] must be 0-terminated.
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675 | b7da58fd | aurel32 | *
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676 | b7da58fd | aurel32 | * The 4xx SDRAM controller supports a small number of banks, and each bank
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677 | b7da58fd | aurel32 | * must be one of a small set of sizes. The number of banks and the supported
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678 | b7da58fd | aurel32 | * sizes varies by SoC. */
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679 | c227f099 | Anthony Liguori | ram_addr_t ppc4xx_sdram_adjust(ram_addr_t ram_size, int nr_banks,
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680 | b6dcbe08 | Avi Kivity | MemoryRegion ram_memories[], |
681 | a8170e5e | Avi Kivity | hwaddr ram_bases[], |
682 | a8170e5e | Avi Kivity | hwaddr ram_sizes[], |
683 | b7da58fd | aurel32 | const unsigned int sdram_bank_sizes[]) |
684 | b7da58fd | aurel32 | { |
685 | c227f099 | Anthony Liguori | ram_addr_t size_left = ram_size; |
686 | b6dcbe08 | Avi Kivity | ram_addr_t base = 0;
|
687 | b7da58fd | aurel32 | int i;
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688 | b7da58fd | aurel32 | int j;
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689 | b7da58fd | aurel32 | |
690 | b7da58fd | aurel32 | for (i = 0; i < nr_banks; i++) { |
691 | b7da58fd | aurel32 | for (j = 0; sdram_bank_sizes[j] != 0; j++) { |
692 | b7da58fd | aurel32 | unsigned int bank_size = sdram_bank_sizes[j]; |
693 | b7da58fd | aurel32 | |
694 | 5c130f65 | pbrook | if (bank_size <= size_left) {
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695 | 1724f049 | Alex Williamson | char name[32]; |
696 | 1724f049 | Alex Williamson | snprintf(name, sizeof(name), "ppc4xx.sdram%d", i); |
697 | 2c9b15ca | Paolo Bonzini | memory_region_init_ram(&ram_memories[i], NULL, name, bank_size);
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698 | c5705a77 | Avi Kivity | vmstate_register_ram_global(&ram_memories[i]); |
699 | b6dcbe08 | Avi Kivity | ram_bases[i] = base; |
700 | b7da58fd | aurel32 | ram_sizes[i] = bank_size; |
701 | 11e5d738 | Alin Tomescu | base += bank_size; |
702 | 5c130f65 | pbrook | size_left -= bank_size; |
703 | b7da58fd | aurel32 | break;
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704 | b7da58fd | aurel32 | } |
705 | b7da58fd | aurel32 | } |
706 | b7da58fd | aurel32 | |
707 | 5c130f65 | pbrook | if (!size_left) {
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708 | b7da58fd | aurel32 | /* No need to use the remaining banks. */
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709 | b7da58fd | aurel32 | break;
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710 | b7da58fd | aurel32 | } |
711 | b7da58fd | aurel32 | } |
712 | b7da58fd | aurel32 | |
713 | 5c130f65 | pbrook | ram_size -= size_left; |
714 | d23ab920 | Hollis Blanchard | if (size_left)
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715 | b7da58fd | aurel32 | printf("Truncating memory to %d MiB to fit SDRAM controller limits.\n",
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716 | 5c130f65 | pbrook | (int)(ram_size >> 20)); |
717 | b7da58fd | aurel32 | |
718 | 5c130f65 | pbrook | return ram_size;
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719 | b7da58fd | aurel32 | } |