Revision cbd2d434
b/hw/ide/ich.c | ||
---|---|---|
88 | 88 |
{ |
89 | 89 |
struct AHCIPCIState *d = DO_UPCAST(struct AHCIPCIState, card.qdev, dev); |
90 | 90 |
|
91 |
msi_reset(&d->card); |
|
92 | 91 |
ahci_reset(&d->ahci); |
93 | 92 |
} |
94 | 93 |
|
b/hw/intel-hda.c | ||
---|---|---|
1107 | 1107 |
DeviceState *qdev; |
1108 | 1108 |
HDACodecDevice *cdev; |
1109 | 1109 |
|
1110 |
if (d->msi) { |
|
1111 |
msi_reset(&d->pci); |
|
1112 |
} |
|
1113 | 1110 |
intel_hda_regs_reset(d); |
1114 | 1111 |
d->wall_base_ns = qemu_get_clock_ns(vm_clock); |
1115 | 1112 |
|
b/hw/ioh3420.c | ||
---|---|---|
81 | 81 |
static void ioh3420_reset(DeviceState *qdev) |
82 | 82 |
{ |
83 | 83 |
PCIDevice *d = PCI_DEVICE(qdev); |
84 |
msi_reset(d); |
|
84 |
|
|
85 | 85 |
ioh3420_aer_vector_update(d); |
86 | 86 |
pcie_cap_root_reset(d); |
87 | 87 |
pcie_cap_deverr_reset(d); |
b/hw/ivshmem.c | ||
---|---|---|
530 | 530 |
IVShmemState *s = DO_UPCAST(IVShmemState, dev.qdev, d); |
531 | 531 |
|
532 | 532 |
s->intrstatus = 0; |
533 |
msix_reset(&s->dev); |
|
534 | 533 |
ivshmem_use_msix(s); |
535 | 534 |
return; |
536 | 535 |
} |
b/hw/pci.c | ||
---|---|---|
31 | 31 |
#include "loader.h" |
32 | 32 |
#include "range.h" |
33 | 33 |
#include "qmp-commands.h" |
34 |
#include "msi.h" |
|
35 |
#include "msix.h" |
|
34 | 36 |
|
35 | 37 |
//#define DEBUG_PCI |
36 | 38 |
#ifdef DEBUG_PCI |
... | ... | |
188 | 190 |
} |
189 | 191 |
} |
190 | 192 |
pci_update_mappings(dev); |
193 |
|
|
194 |
msi_reset(dev); |
|
195 |
msix_reset(dev); |
|
191 | 196 |
} |
192 | 197 |
|
193 | 198 |
/* |
b/hw/pci_bridge.c | ||
---|---|---|
254 | 254 |
} |
255 | 255 |
|
256 | 256 |
/* reset bridge specific configuration registers */ |
257 |
void pci_bridge_reset_reg(PCIDevice *dev)
|
|
257 |
void pci_bridge_reset(DeviceState *qdev)
|
|
258 | 258 |
{ |
259 |
PCIDevice *dev = PCI_DEVICE(qdev); |
|
259 | 260 |
uint8_t *conf = dev->config; |
260 | 261 |
|
261 | 262 |
conf[PCI_PRIMARY_BUS] = 0; |
... | ... | |
291 | 292 |
pci_set_word(conf + PCI_BRIDGE_CONTROL, 0); |
292 | 293 |
} |
293 | 294 |
|
294 |
/* default reset function for PCI-to-PCI bridge */ |
|
295 |
void pci_bridge_reset(DeviceState *qdev) |
|
296 |
{ |
|
297 |
PCIDevice *dev = PCI_DEVICE(qdev); |
|
298 |
pci_bridge_reset_reg(dev); |
|
299 |
} |
|
300 |
|
|
301 | 295 |
/* default qdev initialization function for PCI-to-PCI bridge */ |
302 | 296 |
int pci_bridge_initfn(PCIDevice *dev) |
303 | 297 |
{ |
b/hw/pci_bridge_dev.c | ||
---|---|---|
119 | 119 |
static void qdev_pci_bridge_dev_reset(DeviceState *qdev) |
120 | 120 |
{ |
121 | 121 |
PCIDevice *dev = DO_UPCAST(PCIDevice, qdev, qdev); |
122 |
|
|
122 | 123 |
pci_bridge_reset(qdev); |
123 |
if (msi_present(dev)) { |
|
124 |
msi_reset(dev); |
|
125 |
} |
|
126 | 124 |
shpc_reset(dev); |
127 | 125 |
} |
128 | 126 |
|
b/hw/virtio-pci.c | ||
---|---|---|
278 | 278 |
VirtIOPCIProxy *proxy = container_of(d, VirtIOPCIProxy, pci_dev.qdev); |
279 | 279 |
virtio_pci_stop_ioeventfd(proxy); |
280 | 280 |
virtio_reset(proxy->vdev); |
281 |
msix_reset(&proxy->pci_dev); |
|
282 | 281 |
proxy->flags &= ~VIRTIO_PCI_FLAG_BUS_MASTER_BUG; |
283 | 282 |
} |
284 | 283 |
|
b/hw/xio3130_downstream.c | ||
---|---|---|
48 | 48 |
static void xio3130_downstream_reset(DeviceState *qdev) |
49 | 49 |
{ |
50 | 50 |
PCIDevice *d = PCI_DEVICE(qdev); |
51 |
msi_reset(d); |
|
51 |
|
|
52 | 52 |
pcie_cap_deverr_reset(d); |
53 | 53 |
pcie_cap_slot_reset(d); |
54 | 54 |
pcie_cap_ari_reset(d); |
b/hw/xio3130_upstream.c | ||
---|---|---|
47 | 47 |
static void xio3130_upstream_reset(DeviceState *qdev) |
48 | 48 |
{ |
49 | 49 |
PCIDevice *d = PCI_DEVICE(qdev); |
50 |
msi_reset(d); |
|
50 |
|
|
51 | 51 |
pci_bridge_reset(qdev); |
52 | 52 |
pcie_cap_deverr_reset(d); |
53 | 53 |
} |
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