Revision cc01cc8e tcg/mips/tcg-target.c
b/tcg/mips/tcg-target.c | ||
---|---|---|
222 | 222 |
case 'S': /* qemu_st constraint */ |
223 | 223 |
ct->ct |= TCG_CT_REG; |
224 | 224 |
tcg_regset_set(ct->u.regs, 0xffffffff); |
225 |
#if defined(CONFIG_SOFTMMU) |
|
226 | 225 |
tcg_regset_reset_reg(ct->u.regs, TCG_REG_A0); |
226 |
#if defined(CONFIG_SOFTMMU) |
|
227 | 227 |
# if TARGET_LONG_BITS == 64 |
228 | 228 |
tcg_regset_reset_reg(ct->u.regs, TCG_REG_A1); |
229 | 229 |
# endif |
... | ... | |
858 | 858 |
tcg_out_opc_imm(s, OPC_LW, TCG_REG_A0, TCG_REG_A0, |
859 | 859 |
offsetof(CPUState, tlb_table[mem_index][0].addend) + addr_meml); |
860 | 860 |
tcg_out_opc_reg(s, OPC_ADDU, TCG_REG_V0, TCG_REG_A0, addr_regl); |
861 |
|
|
862 |
addr_reg1 = TCG_REG_V0; |
|
861 |
#else |
|
862 |
if (GUEST_BASE == (int16_t)GUEST_BASE) { |
|
863 |
tcg_out_opc_imm(s, OPC_ADDIU, TCG_REG_V0, addr_reg1, GUEST_BASE); |
|
864 |
} else { |
|
865 |
tcg_out_movi(s, TCG_TYPE_PTR, TCG_REG_V0, GUEST_BASE); |
|
866 |
tcg_out_opc_reg(s, OPC_ADDU, TCG_REG_V0, TCG_REG_V0, addr_reg1); |
|
867 |
} |
|
863 | 868 |
#endif |
864 | 869 |
|
865 | 870 |
switch(opc) { |
866 | 871 |
case 0: |
867 |
tcg_out_opc_imm(s, OPC_LBU, data_reg1, addr_reg1, 0);
|
|
872 |
tcg_out_opc_imm(s, OPC_LBU, data_reg1, TCG_REG_V0, 0);
|
|
868 | 873 |
break; |
869 | 874 |
case 0 | 4: |
870 |
tcg_out_opc_imm(s, OPC_LB, data_reg1, addr_reg1, 0);
|
|
875 |
tcg_out_opc_imm(s, OPC_LB, data_reg1, TCG_REG_V0, 0);
|
|
871 | 876 |
break; |
872 | 877 |
case 1: |
873 | 878 |
if (TCG_NEED_BSWAP) { |
874 |
tcg_out_opc_imm(s, OPC_LHU, TCG_REG_T0, addr_reg1, 0);
|
|
879 |
tcg_out_opc_imm(s, OPC_LHU, TCG_REG_T0, TCG_REG_V0, 0);
|
|
875 | 880 |
tcg_out_bswap16(s, data_reg1, TCG_REG_T0); |
876 | 881 |
} else { |
877 |
tcg_out_opc_imm(s, OPC_LHU, data_reg1, addr_reg1, 0);
|
|
882 |
tcg_out_opc_imm(s, OPC_LHU, data_reg1, TCG_REG_V0, 0);
|
|
878 | 883 |
} |
879 | 884 |
break; |
880 | 885 |
case 1 | 4: |
881 | 886 |
if (TCG_NEED_BSWAP) { |
882 |
tcg_out_opc_imm(s, OPC_LHU, TCG_REG_T0, addr_reg1, 0);
|
|
887 |
tcg_out_opc_imm(s, OPC_LHU, TCG_REG_T0, TCG_REG_V0, 0);
|
|
883 | 888 |
tcg_out_bswap16s(s, data_reg1, TCG_REG_T0); |
884 | 889 |
} else { |
885 |
tcg_out_opc_imm(s, OPC_LH, data_reg1, addr_reg1, 0);
|
|
890 |
tcg_out_opc_imm(s, OPC_LH, data_reg1, TCG_REG_V0, 0);
|
|
886 | 891 |
} |
887 | 892 |
break; |
888 | 893 |
case 2: |
889 | 894 |
if (TCG_NEED_BSWAP) { |
890 |
tcg_out_opc_imm(s, OPC_LW, TCG_REG_T0, addr_reg1, 0);
|
|
895 |
tcg_out_opc_imm(s, OPC_LW, TCG_REG_T0, TCG_REG_V0, 0);
|
|
891 | 896 |
tcg_out_bswap32(s, data_reg1, TCG_REG_T0); |
892 | 897 |
} else { |
893 |
tcg_out_opc_imm(s, OPC_LW, data_reg1, addr_reg1, 0);
|
|
898 |
tcg_out_opc_imm(s, OPC_LW, data_reg1, TCG_REG_V0, 0);
|
|
894 | 899 |
} |
895 | 900 |
break; |
896 | 901 |
case 3: |
897 |
#if !defined(CONFIG_SOFTMMU) |
|
898 |
tcg_out_mov(s, TCG_REG_V0, addr_reg1); |
|
899 |
addr_reg1 = TCG_REG_V0; |
|
900 |
#endif |
|
901 | 902 |
if (TCG_NEED_BSWAP) { |
902 |
tcg_out_opc_imm(s, OPC_LW, TCG_REG_T0, addr_reg1, 4);
|
|
903 |
tcg_out_opc_imm(s, OPC_LW, TCG_REG_T0, TCG_REG_V0, 4);
|
|
903 | 904 |
tcg_out_bswap32(s, data_reg1, TCG_REG_T0); |
904 |
tcg_out_opc_imm(s, OPC_LW, TCG_REG_T0, addr_reg1, 0);
|
|
905 |
tcg_out_opc_imm(s, OPC_LW, TCG_REG_T0, TCG_REG_V0, 0);
|
|
905 | 906 |
tcg_out_bswap32(s, data_reg2, TCG_REG_T0); |
906 | 907 |
} else { |
907 |
tcg_out_opc_imm(s, OPC_LW, data_reg1, addr_reg1, 0);
|
|
908 |
tcg_out_opc_imm(s, OPC_LW, data_reg2, addr_reg1, 4);
|
|
908 |
tcg_out_opc_imm(s, OPC_LW, data_reg1, TCG_REG_V0, 0);
|
|
909 |
tcg_out_opc_imm(s, OPC_LW, data_reg2, TCG_REG_V0, 4);
|
|
909 | 910 |
} |
910 | 911 |
break; |
911 | 912 |
default: |
... | ... | |
1044 | 1045 |
tcg_out_opc_imm(s, OPC_LW, TCG_REG_A0, TCG_REG_A0, |
1045 | 1046 |
offsetof(CPUState, tlb_table[mem_index][0].addend) + addr_meml); |
1046 | 1047 |
tcg_out_opc_reg(s, OPC_ADDU, TCG_REG_A0, TCG_REG_A0, addr_regl); |
1048 |
#else |
|
1049 |
if (GUEST_BASE == (int16_t)GUEST_BASE) { |
|
1050 |
tcg_out_opc_imm(s, OPC_ADDIU, TCG_REG_A0, addr_reg1, GUEST_BASE); |
|
1051 |
} else { |
|
1052 |
tcg_out_movi(s, TCG_TYPE_PTR, TCG_REG_A0, GUEST_BASE); |
|
1053 |
tcg_out_opc_reg(s, OPC_ADDU, TCG_REG_A0, TCG_REG_A0, addr_reg1); |
|
1054 |
} |
|
1047 | 1055 |
|
1048 |
addr_reg1 = TCG_REG_A0; |
|
1049 | 1056 |
#endif |
1050 | 1057 |
|
1051 | 1058 |
switch(opc) { |
1052 | 1059 |
case 0: |
1053 |
tcg_out_opc_imm(s, OPC_SB, data_reg1, addr_reg1, 0);
|
|
1060 |
tcg_out_opc_imm(s, OPC_SB, data_reg1, TCG_REG_A0, 0);
|
|
1054 | 1061 |
break; |
1055 | 1062 |
case 1: |
1056 | 1063 |
if (TCG_NEED_BSWAP) { |
1057 | 1064 |
tcg_out_bswap16(s, TCG_REG_T0, data_reg1); |
1058 |
tcg_out_opc_imm(s, OPC_SH, TCG_REG_T0, addr_reg1, 0);
|
|
1065 |
tcg_out_opc_imm(s, OPC_SH, TCG_REG_T0, TCG_REG_A0, 0);
|
|
1059 | 1066 |
} else { |
1060 |
tcg_out_opc_imm(s, OPC_SH, data_reg1, addr_reg1, 0);
|
|
1067 |
tcg_out_opc_imm(s, OPC_SH, data_reg1, TCG_REG_A0, 0);
|
|
1061 | 1068 |
} |
1062 | 1069 |
break; |
1063 | 1070 |
case 2: |
1064 | 1071 |
if (TCG_NEED_BSWAP) { |
1065 | 1072 |
tcg_out_bswap32(s, TCG_REG_T0, data_reg1); |
1066 |
tcg_out_opc_imm(s, OPC_SW, TCG_REG_T0, addr_reg1, 0);
|
|
1073 |
tcg_out_opc_imm(s, OPC_SW, TCG_REG_T0, TCG_REG_A0, 0);
|
|
1067 | 1074 |
} else { |
1068 |
tcg_out_opc_imm(s, OPC_SW, data_reg1, addr_reg1, 0);
|
|
1075 |
tcg_out_opc_imm(s, OPC_SW, data_reg1, TCG_REG_A0, 0);
|
|
1069 | 1076 |
} |
1070 | 1077 |
break; |
1071 | 1078 |
case 3: |
1072 | 1079 |
if (TCG_NEED_BSWAP) { |
1073 | 1080 |
tcg_out_bswap32(s, TCG_REG_T0, data_reg2); |
1074 |
tcg_out_opc_imm(s, OPC_SW, TCG_REG_T0, addr_reg1, 0);
|
|
1081 |
tcg_out_opc_imm(s, OPC_SW, TCG_REG_T0, TCG_REG_A0, 0);
|
|
1075 | 1082 |
tcg_out_bswap32(s, TCG_REG_T0, data_reg1); |
1076 |
tcg_out_opc_imm(s, OPC_SW, TCG_REG_T0, addr_reg1, 4);
|
|
1083 |
tcg_out_opc_imm(s, OPC_SW, TCG_REG_T0, TCG_REG_A0, 4);
|
|
1077 | 1084 |
} else { |
1078 |
tcg_out_opc_imm(s, OPC_SW, data_reg1, addr_reg1, 0);
|
|
1079 |
tcg_out_opc_imm(s, OPC_SW, data_reg2, addr_reg1, 4);
|
|
1085 |
tcg_out_opc_imm(s, OPC_SW, data_reg1, TCG_REG_A0, 0);
|
|
1086 |
tcg_out_opc_imm(s, OPC_SW, data_reg2, TCG_REG_A0, 4);
|
|
1080 | 1087 |
} |
1081 | 1088 |
break; |
1082 | 1089 |
default: |
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