root / hw / slavio_timer.c @ cc02c66c
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1 | e80cfcfc | bellard | /*
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2 | e80cfcfc | bellard | * QEMU Sparc SLAVIO timer controller emulation
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3 | e80cfcfc | bellard | *
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4 | 66321a11 | bellard | * Copyright (c) 2003-2005 Fabrice Bellard
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5 | 5fafdf24 | ths | *
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6 | e80cfcfc | bellard | * Permission is hereby granted, free of charge, to any person obtaining a copy
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7 | e80cfcfc | bellard | * of this software and associated documentation files (the "Software"), to deal
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8 | e80cfcfc | bellard | * in the Software without restriction, including without limitation the rights
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9 | e80cfcfc | bellard | * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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10 | e80cfcfc | bellard | * copies of the Software, and to permit persons to whom the Software is
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11 | e80cfcfc | bellard | * furnished to do so, subject to the following conditions:
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12 | e80cfcfc | bellard | *
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13 | e80cfcfc | bellard | * The above copyright notice and this permission notice shall be included in
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14 | e80cfcfc | bellard | * all copies or substantial portions of the Software.
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15 | e80cfcfc | bellard | *
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16 | e80cfcfc | bellard | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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17 | e80cfcfc | bellard | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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18 | e80cfcfc | bellard | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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19 | e80cfcfc | bellard | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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20 | e80cfcfc | bellard | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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21 | e80cfcfc | bellard | * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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22 | e80cfcfc | bellard | * THE SOFTWARE.
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23 | e80cfcfc | bellard | */
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24 | c70c59ee | Blue Swirl | |
25 | 87ecb68b | pbrook | #include "sun4m.h" |
26 | 87ecb68b | pbrook | #include "qemu-timer.h" |
27 | c70c59ee | Blue Swirl | #include "sysbus.h" |
28 | e80cfcfc | bellard | |
29 | e80cfcfc | bellard | //#define DEBUG_TIMER
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30 | e80cfcfc | bellard | |
31 | 66321a11 | bellard | #ifdef DEBUG_TIMER
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32 | 001faf32 | Blue Swirl | #define DPRINTF(fmt, ...) \
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33 | 001faf32 | Blue Swirl | do { printf("TIMER: " fmt , ## __VA_ARGS__); } while (0) |
34 | 66321a11 | bellard | #else
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35 | 001faf32 | Blue Swirl | #define DPRINTF(fmt, ...) do {} while (0) |
36 | 66321a11 | bellard | #endif
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37 | 66321a11 | bellard | |
38 | e80cfcfc | bellard | /*
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39 | e80cfcfc | bellard | * Registers of hardware timer in sun4m.
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40 | e80cfcfc | bellard | *
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41 | e80cfcfc | bellard | * This is the timer/counter part of chip STP2001 (Slave I/O), also
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42 | e80cfcfc | bellard | * produced as NCR89C105. See
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43 | e80cfcfc | bellard | * http://www.ibiblio.org/pub/historic-linux/early-ports/Sparc/NCR/NCR89C105.txt
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44 | 5fafdf24 | ths | *
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45 | e80cfcfc | bellard | * The 31-bit counter is incremented every 500ns by bit 9. Bits 8..0
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46 | e80cfcfc | bellard | * are zero. Bit 31 is 1 when count has been reached.
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47 | e80cfcfc | bellard | *
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48 | ba3c64fb | bellard | * Per-CPU timers interrupt local CPU, system timer uses normal
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49 | ba3c64fb | bellard | * interrupt routing.
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50 | ba3c64fb | bellard | *
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51 | e80cfcfc | bellard | */
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52 | e80cfcfc | bellard | |
53 | 81732d19 | blueswir1 | #define MAX_CPUS 16 |
54 | 81732d19 | blueswir1 | |
55 | 7204ff9c | Blue Swirl | typedef struct CPUTimerState { |
56 | d7edfd27 | blueswir1 | qemu_irq irq; |
57 | 8d05ea8a | blueswir1 | ptimer_state *timer; |
58 | 8d05ea8a | blueswir1 | uint32_t count, counthigh, reached; |
59 | 8d05ea8a | blueswir1 | uint64_t limit; |
60 | 115646b6 | blueswir1 | // processor only
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61 | 22548760 | blueswir1 | uint32_t running; |
62 | 7204ff9c | Blue Swirl | } CPUTimerState; |
63 | 7204ff9c | Blue Swirl | |
64 | 7204ff9c | Blue Swirl | typedef struct SLAVIO_TIMERState { |
65 | 7204ff9c | Blue Swirl | SysBusDevice busdev; |
66 | 7204ff9c | Blue Swirl | uint32_t num_cpus; |
67 | 7204ff9c | Blue Swirl | CPUTimerState cputimer[MAX_CPUS + 1];
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68 | 7204ff9c | Blue Swirl | uint32_t cputimer_mode; |
69 | e80cfcfc | bellard | } SLAVIO_TIMERState; |
70 | e80cfcfc | bellard | |
71 | 7204ff9c | Blue Swirl | typedef struct TimerContext { |
72 | 7204ff9c | Blue Swirl | SLAVIO_TIMERState *s; |
73 | 7204ff9c | Blue Swirl | unsigned int timer_index; /* 0 for system, 1 ... MAX_CPUS for CPU timers */ |
74 | 7204ff9c | Blue Swirl | } TimerContext; |
75 | 7204ff9c | Blue Swirl | |
76 | 115646b6 | blueswir1 | #define SYS_TIMER_SIZE 0x14 |
77 | 81732d19 | blueswir1 | #define CPU_TIMER_SIZE 0x10 |
78 | e80cfcfc | bellard | |
79 | d2c38b24 | blueswir1 | #define TIMER_LIMIT 0 |
80 | d2c38b24 | blueswir1 | #define TIMER_COUNTER 1 |
81 | d2c38b24 | blueswir1 | #define TIMER_COUNTER_NORST 2 |
82 | d2c38b24 | blueswir1 | #define TIMER_STATUS 3 |
83 | d2c38b24 | blueswir1 | #define TIMER_MODE 4 |
84 | d2c38b24 | blueswir1 | |
85 | d2c38b24 | blueswir1 | #define TIMER_COUNT_MASK32 0xfffffe00 |
86 | d2c38b24 | blueswir1 | #define TIMER_LIMIT_MASK32 0x7fffffff |
87 | d2c38b24 | blueswir1 | #define TIMER_MAX_COUNT64 0x7ffffffffffffe00ULL |
88 | d2c38b24 | blueswir1 | #define TIMER_MAX_COUNT32 0x7ffffe00ULL |
89 | d2c38b24 | blueswir1 | #define TIMER_REACHED 0x80000000 |
90 | d2c38b24 | blueswir1 | #define TIMER_PERIOD 500ULL // 500ns |
91 | d2c38b24 | blueswir1 | #define LIMIT_TO_PERIODS(l) ((l) >> 9) |
92 | d2c38b24 | blueswir1 | #define PERIODS_TO_LIMIT(l) ((l) << 9) |
93 | d2c38b24 | blueswir1 | |
94 | 7204ff9c | Blue Swirl | static int slavio_timer_is_user(TimerContext *tc) |
95 | 115646b6 | blueswir1 | { |
96 | 7204ff9c | Blue Swirl | SLAVIO_TIMERState *s = tc->s; |
97 | 7204ff9c | Blue Swirl | unsigned int timer_index = tc->timer_index; |
98 | 7204ff9c | Blue Swirl | |
99 | 7204ff9c | Blue Swirl | return timer_index != 0 && (s->cputimer_mode & (1 << (timer_index - 1))); |
100 | 115646b6 | blueswir1 | } |
101 | 115646b6 | blueswir1 | |
102 | e80cfcfc | bellard | // Update count, set irq, update expire_time
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103 | 8d05ea8a | blueswir1 | // Convert from ptimer countdown units
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104 | 7204ff9c | Blue Swirl | static void slavio_timer_get_out(CPUTimerState *t) |
105 | e80cfcfc | bellard | { |
106 | bd7e2875 | blueswir1 | uint64_t count, limit; |
107 | e80cfcfc | bellard | |
108 | 7204ff9c | Blue Swirl | if (t->limit == 0) { /* free-run system or processor counter */ |
109 | bd7e2875 | blueswir1 | limit = TIMER_MAX_COUNT32; |
110 | 7204ff9c | Blue Swirl | } else {
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111 | 7204ff9c | Blue Swirl | limit = t->limit; |
112 | 7204ff9c | Blue Swirl | } |
113 | 9ebec28b | Blue Swirl | count = limit - PERIODS_TO_LIMIT(ptimer_get_count(t->timer)); |
114 | 9ebec28b | Blue Swirl | |
115 | 7204ff9c | Blue Swirl | DPRINTF("get_out: limit %" PRIx64 " count %x%08x\n", t->limit, t->counthigh, |
116 | 7204ff9c | Blue Swirl | t->count); |
117 | 7204ff9c | Blue Swirl | t->count = count & TIMER_COUNT_MASK32; |
118 | 7204ff9c | Blue Swirl | t->counthigh = count >> 32;
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119 | e80cfcfc | bellard | } |
120 | e80cfcfc | bellard | |
121 | e80cfcfc | bellard | // timer callback
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122 | e80cfcfc | bellard | static void slavio_timer_irq(void *opaque) |
123 | e80cfcfc | bellard | { |
124 | 7204ff9c | Blue Swirl | TimerContext *tc = opaque; |
125 | 7204ff9c | Blue Swirl | SLAVIO_TIMERState *s = tc->s; |
126 | 7204ff9c | Blue Swirl | CPUTimerState *t = &s->cputimer[tc->timer_index]; |
127 | 7204ff9c | Blue Swirl | |
128 | 7204ff9c | Blue Swirl | slavio_timer_get_out(t); |
129 | 7204ff9c | Blue Swirl | DPRINTF("callback: count %x%08x\n", t->counthigh, t->count);
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130 | 7204ff9c | Blue Swirl | t->reached = TIMER_REACHED; |
131 | 452efba6 | Blue Swirl | /* there is no interrupt if user timer or free-run */
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132 | 452efba6 | Blue Swirl | if (!slavio_timer_is_user(tc) && t->limit != 0) { |
133 | 7204ff9c | Blue Swirl | qemu_irq_raise(t->irq); |
134 | 7204ff9c | Blue Swirl | } |
135 | e80cfcfc | bellard | } |
136 | e80cfcfc | bellard | |
137 | c227f099 | Anthony Liguori | static uint32_t slavio_timer_mem_readl(void *opaque, target_phys_addr_t addr) |
138 | e80cfcfc | bellard | { |
139 | 7204ff9c | Blue Swirl | TimerContext *tc = opaque; |
140 | 7204ff9c | Blue Swirl | SLAVIO_TIMERState *s = tc->s; |
141 | 8d05ea8a | blueswir1 | uint32_t saddr, ret; |
142 | 7204ff9c | Blue Swirl | unsigned int timer_index = tc->timer_index; |
143 | 7204ff9c | Blue Swirl | CPUTimerState *t = &s->cputimer[timer_index]; |
144 | e80cfcfc | bellard | |
145 | e64d7d59 | blueswir1 | saddr = addr >> 2;
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146 | e80cfcfc | bellard | switch (saddr) {
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147 | d2c38b24 | blueswir1 | case TIMER_LIMIT:
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148 | f930d07e | blueswir1 | // read limit (system counter mode) or read most signifying
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149 | f930d07e | blueswir1 | // part of counter (user mode)
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150 | 7204ff9c | Blue Swirl | if (slavio_timer_is_user(tc)) {
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151 | 115646b6 | blueswir1 | // read user timer MSW
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152 | 7204ff9c | Blue Swirl | slavio_timer_get_out(t); |
153 | 7204ff9c | Blue Swirl | ret = t->counthigh | t->reached; |
154 | 115646b6 | blueswir1 | } else {
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155 | 115646b6 | blueswir1 | // read limit
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156 | f930d07e | blueswir1 | // clear irq
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157 | 7204ff9c | Blue Swirl | qemu_irq_lower(t->irq); |
158 | 7204ff9c | Blue Swirl | t->reached = 0;
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159 | 7204ff9c | Blue Swirl | ret = t->limit & TIMER_LIMIT_MASK32; |
160 | f930d07e | blueswir1 | } |
161 | 8d05ea8a | blueswir1 | break;
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162 | d2c38b24 | blueswir1 | case TIMER_COUNTER:
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163 | f930d07e | blueswir1 | // read counter and reached bit (system mode) or read lsbits
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164 | f930d07e | blueswir1 | // of counter (user mode)
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165 | 7204ff9c | Blue Swirl | slavio_timer_get_out(t); |
166 | 7204ff9c | Blue Swirl | if (slavio_timer_is_user(tc)) { // read user timer LSW |
167 | 7204ff9c | Blue Swirl | ret = t->count & TIMER_MAX_COUNT64; |
168 | 7204ff9c | Blue Swirl | } else { // read limit |
169 | 7204ff9c | Blue Swirl | ret = (t->count & TIMER_MAX_COUNT32) | |
170 | 7204ff9c | Blue Swirl | t->reached; |
171 | 7204ff9c | Blue Swirl | } |
172 | 8d05ea8a | blueswir1 | break;
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173 | d2c38b24 | blueswir1 | case TIMER_STATUS:
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174 | 115646b6 | blueswir1 | // only available in processor counter/timer
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175 | f930d07e | blueswir1 | // read start/stop status
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176 | 7204ff9c | Blue Swirl | if (timer_index > 0) { |
177 | 7204ff9c | Blue Swirl | ret = t->running; |
178 | 7204ff9c | Blue Swirl | } else {
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179 | 7204ff9c | Blue Swirl | ret = 0;
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180 | 7204ff9c | Blue Swirl | } |
181 | 8d05ea8a | blueswir1 | break;
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182 | d2c38b24 | blueswir1 | case TIMER_MODE:
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183 | 115646b6 | blueswir1 | // only available in system counter
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184 | f930d07e | blueswir1 | // read user/system mode
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185 | 7204ff9c | Blue Swirl | ret = s->cputimer_mode; |
186 | 8d05ea8a | blueswir1 | break;
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187 | e80cfcfc | bellard | default:
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188 | 115646b6 | blueswir1 | DPRINTF("invalid read address " TARGET_FMT_plx "\n", addr); |
189 | 8d05ea8a | blueswir1 | ret = 0;
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190 | 8d05ea8a | blueswir1 | break;
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191 | e80cfcfc | bellard | } |
192 | 8d05ea8a | blueswir1 | DPRINTF("read " TARGET_FMT_plx " = %08x\n", addr, ret); |
193 | 8d05ea8a | blueswir1 | |
194 | 8d05ea8a | blueswir1 | return ret;
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195 | e80cfcfc | bellard | } |
196 | e80cfcfc | bellard | |
197 | c227f099 | Anthony Liguori | static void slavio_timer_mem_writel(void *opaque, target_phys_addr_t addr, |
198 | d2c38b24 | blueswir1 | uint32_t val) |
199 | e80cfcfc | bellard | { |
200 | 7204ff9c | Blue Swirl | TimerContext *tc = opaque; |
201 | 7204ff9c | Blue Swirl | SLAVIO_TIMERState *s = tc->s; |
202 | e80cfcfc | bellard | uint32_t saddr; |
203 | 7204ff9c | Blue Swirl | unsigned int timer_index = tc->timer_index; |
204 | 7204ff9c | Blue Swirl | CPUTimerState *t = &s->cputimer[timer_index]; |
205 | e80cfcfc | bellard | |
206 | 8d05ea8a | blueswir1 | DPRINTF("write " TARGET_FMT_plx " %08x\n", addr, val); |
207 | e64d7d59 | blueswir1 | saddr = addr >> 2;
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208 | e80cfcfc | bellard | switch (saddr) {
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209 | d2c38b24 | blueswir1 | case TIMER_LIMIT:
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210 | 7204ff9c | Blue Swirl | if (slavio_timer_is_user(tc)) {
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211 | e1cb9502 | blueswir1 | uint64_t count; |
212 | e1cb9502 | blueswir1 | |
213 | 115646b6 | blueswir1 | // set user counter MSW, reset counter
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214 | 7204ff9c | Blue Swirl | t->limit = TIMER_MAX_COUNT64; |
215 | 7204ff9c | Blue Swirl | t->counthigh = val & (TIMER_MAX_COUNT64 >> 32);
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216 | 7204ff9c | Blue Swirl | t->reached = 0;
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217 | 7204ff9c | Blue Swirl | count = ((uint64_t)t->counthigh << 32) | t->count;
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218 | 0bf9e31a | Blue Swirl | DPRINTF("processor %d user timer set to %016" PRIx64 "\n", |
219 | 7204ff9c | Blue Swirl | timer_index, count); |
220 | 9ebec28b | Blue Swirl | ptimer_set_count(t->timer, LIMIT_TO_PERIODS(t->limit - count)); |
221 | 115646b6 | blueswir1 | } else {
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222 | 115646b6 | blueswir1 | // set limit, reset counter
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223 | 7204ff9c | Blue Swirl | qemu_irq_lower(t->irq); |
224 | 7204ff9c | Blue Swirl | t->limit = val & TIMER_MAX_COUNT32; |
225 | 7204ff9c | Blue Swirl | if (t->timer) {
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226 | 7204ff9c | Blue Swirl | if (t->limit == 0) { /* free-run */ |
227 | 7204ff9c | Blue Swirl | ptimer_set_limit(t->timer, |
228 | 77f193da | blueswir1 | LIMIT_TO_PERIODS(TIMER_MAX_COUNT32), 1);
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229 | 7204ff9c | Blue Swirl | } else {
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230 | 7204ff9c | Blue Swirl | ptimer_set_limit(t->timer, LIMIT_TO_PERIODS(t->limit), 1);
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231 | 7204ff9c | Blue Swirl | } |
232 | 85e3023e | blueswir1 | } |
233 | 81732d19 | blueswir1 | } |
234 | 115646b6 | blueswir1 | break;
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235 | d2c38b24 | blueswir1 | case TIMER_COUNTER:
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236 | 7204ff9c | Blue Swirl | if (slavio_timer_is_user(tc)) {
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237 | e1cb9502 | blueswir1 | uint64_t count; |
238 | e1cb9502 | blueswir1 | |
239 | 115646b6 | blueswir1 | // set user counter LSW, reset counter
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240 | 7204ff9c | Blue Swirl | t->limit = TIMER_MAX_COUNT64; |
241 | 7204ff9c | Blue Swirl | t->count = val & TIMER_MAX_COUNT64; |
242 | 7204ff9c | Blue Swirl | t->reached = 0;
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243 | 7204ff9c | Blue Swirl | count = ((uint64_t)t->counthigh) << 32 | t->count;
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244 | 0bf9e31a | Blue Swirl | DPRINTF("processor %d user timer set to %016" PRIx64 "\n", |
245 | 7204ff9c | Blue Swirl | timer_index, count); |
246 | 9ebec28b | Blue Swirl | ptimer_set_count(t->timer, LIMIT_TO_PERIODS(t->limit - count)); |
247 | 115646b6 | blueswir1 | } else
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248 | 115646b6 | blueswir1 | DPRINTF("not user timer\n");
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249 | 115646b6 | blueswir1 | break;
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250 | d2c38b24 | blueswir1 | case TIMER_COUNTER_NORST:
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251 | f930d07e | blueswir1 | // set limit without resetting counter
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252 | 7204ff9c | Blue Swirl | t->limit = val & TIMER_MAX_COUNT32; |
253 | 9ebec28b | Blue Swirl | if (t->limit == 0) { /* free-run */ |
254 | 9ebec28b | Blue Swirl | ptimer_set_limit(t->timer, LIMIT_TO_PERIODS(TIMER_MAX_COUNT32), 0);
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255 | 9ebec28b | Blue Swirl | } else {
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256 | 9ebec28b | Blue Swirl | ptimer_set_limit(t->timer, LIMIT_TO_PERIODS(t->limit), 0);
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257 | 85e3023e | blueswir1 | } |
258 | f930d07e | blueswir1 | break;
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259 | d2c38b24 | blueswir1 | case TIMER_STATUS:
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260 | 7204ff9c | Blue Swirl | if (slavio_timer_is_user(tc)) {
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261 | 115646b6 | blueswir1 | // start/stop user counter
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262 | 7204ff9c | Blue Swirl | if ((val & 1) && !t->running) { |
263 | 7204ff9c | Blue Swirl | DPRINTF("processor %d user timer started\n",
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264 | 7204ff9c | Blue Swirl | timer_index); |
265 | 9ebec28b | Blue Swirl | ptimer_run(t->timer, 0);
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266 | 7204ff9c | Blue Swirl | t->running = 1;
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267 | 7204ff9c | Blue Swirl | } else if (!(val & 1) && t->running) { |
268 | 7204ff9c | Blue Swirl | DPRINTF("processor %d user timer stopped\n",
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269 | 7204ff9c | Blue Swirl | timer_index); |
270 | 9ebec28b | Blue Swirl | ptimer_stop(t->timer); |
271 | 7204ff9c | Blue Swirl | t->running = 0;
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272 | f930d07e | blueswir1 | } |
273 | f930d07e | blueswir1 | } |
274 | f930d07e | blueswir1 | break;
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275 | d2c38b24 | blueswir1 | case TIMER_MODE:
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276 | 7204ff9c | Blue Swirl | if (timer_index == 0) { |
277 | 81732d19 | blueswir1 | unsigned int i; |
278 | 81732d19 | blueswir1 | |
279 | 7204ff9c | Blue Swirl | for (i = 0; i < s->num_cpus; i++) { |
280 | 67e42751 | blueswir1 | unsigned int processor = 1 << i; |
281 | 7204ff9c | Blue Swirl | CPUTimerState *curr_timer = &s->cputimer[i + 1];
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282 | 67e42751 | blueswir1 | |
283 | 67e42751 | blueswir1 | // check for a change in timer mode for this processor
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284 | 7204ff9c | Blue Swirl | if ((val & processor) != (s->cputimer_mode & processor)) {
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285 | 67e42751 | blueswir1 | if (val & processor) { // counter -> user timer |
286 | 7204ff9c | Blue Swirl | qemu_irq_lower(curr_timer->irq); |
287 | 67e42751 | blueswir1 | // counters are always running
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288 | 7204ff9c | Blue Swirl | ptimer_stop(curr_timer->timer); |
289 | 7204ff9c | Blue Swirl | curr_timer->running = 0;
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290 | 67e42751 | blueswir1 | // user timer limit is always the same
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291 | 7204ff9c | Blue Swirl | curr_timer->limit = TIMER_MAX_COUNT64; |
292 | 7204ff9c | Blue Swirl | ptimer_set_limit(curr_timer->timer, |
293 | 7204ff9c | Blue Swirl | LIMIT_TO_PERIODS(curr_timer->limit), |
294 | 77f193da | blueswir1 | 1);
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295 | 67e42751 | blueswir1 | // set this processors user timer bit in config
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296 | 67e42751 | blueswir1 | // register
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297 | 7204ff9c | Blue Swirl | s->cputimer_mode |= processor; |
298 | 67e42751 | blueswir1 | DPRINTF("processor %d changed from counter to user "
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299 | 7204ff9c | Blue Swirl | "timer\n", timer_index);
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300 | 67e42751 | blueswir1 | } else { // user timer -> counter |
301 | 67e42751 | blueswir1 | // stop the user timer if it is running
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302 | 7204ff9c | Blue Swirl | if (curr_timer->running) {
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303 | 7204ff9c | Blue Swirl | ptimer_stop(curr_timer->timer); |
304 | 7204ff9c | Blue Swirl | } |
305 | 67e42751 | blueswir1 | // start the counter
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306 | 7204ff9c | Blue Swirl | ptimer_run(curr_timer->timer, 0);
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307 | 7204ff9c | Blue Swirl | curr_timer->running = 1;
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308 | 67e42751 | blueswir1 | // clear this processors user timer bit in config
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309 | 67e42751 | blueswir1 | // register
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310 | 7204ff9c | Blue Swirl | s->cputimer_mode &= ~processor; |
311 | 67e42751 | blueswir1 | DPRINTF("processor %d changed from user timer to "
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312 | 7204ff9c | Blue Swirl | "counter\n", timer_index);
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313 | 67e42751 | blueswir1 | } |
314 | 115646b6 | blueswir1 | } |
315 | 81732d19 | blueswir1 | } |
316 | 7204ff9c | Blue Swirl | } else {
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317 | 115646b6 | blueswir1 | DPRINTF("not system timer\n");
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318 | 7204ff9c | Blue Swirl | } |
319 | f930d07e | blueswir1 | break;
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320 | e80cfcfc | bellard | default:
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321 | 115646b6 | blueswir1 | DPRINTF("invalid write address " TARGET_FMT_plx "\n", addr); |
322 | f930d07e | blueswir1 | break;
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323 | e80cfcfc | bellard | } |
324 | e80cfcfc | bellard | } |
325 | e80cfcfc | bellard | |
326 | d60efc6b | Blue Swirl | static CPUReadMemoryFunc * const slavio_timer_mem_read[3] = { |
327 | 7c560456 | blueswir1 | NULL,
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328 | 7c560456 | blueswir1 | NULL,
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329 | e80cfcfc | bellard | slavio_timer_mem_readl, |
330 | e80cfcfc | bellard | }; |
331 | e80cfcfc | bellard | |
332 | d60efc6b | Blue Swirl | static CPUWriteMemoryFunc * const slavio_timer_mem_write[3] = { |
333 | 7c560456 | blueswir1 | NULL,
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334 | 7c560456 | blueswir1 | NULL,
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335 | e80cfcfc | bellard | slavio_timer_mem_writel, |
336 | e80cfcfc | bellard | }; |
337 | e80cfcfc | bellard | |
338 | f4b19cd0 | Blue Swirl | static const VMStateDescription vmstate_timer = { |
339 | f4b19cd0 | Blue Swirl | .name ="timer",
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340 | f4b19cd0 | Blue Swirl | .version_id = 3,
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341 | f4b19cd0 | Blue Swirl | .minimum_version_id = 3,
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342 | f4b19cd0 | Blue Swirl | .minimum_version_id_old = 3,
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343 | f4b19cd0 | Blue Swirl | .fields = (VMStateField []) { |
344 | f4b19cd0 | Blue Swirl | VMSTATE_UINT64(limit, CPUTimerState), |
345 | f4b19cd0 | Blue Swirl | VMSTATE_UINT32(count, CPUTimerState), |
346 | f4b19cd0 | Blue Swirl | VMSTATE_UINT32(counthigh, CPUTimerState), |
347 | f4b19cd0 | Blue Swirl | VMSTATE_UINT32(reached, CPUTimerState), |
348 | f4b19cd0 | Blue Swirl | VMSTATE_UINT32(running, CPUTimerState), |
349 | f4b19cd0 | Blue Swirl | VMSTATE_PTIMER(timer, CPUTimerState), |
350 | f4b19cd0 | Blue Swirl | VMSTATE_END_OF_LIST() |
351 | 7204ff9c | Blue Swirl | } |
352 | f4b19cd0 | Blue Swirl | }; |
353 | e80cfcfc | bellard | |
354 | f4b19cd0 | Blue Swirl | static const VMStateDescription vmstate_slavio_timer = { |
355 | f4b19cd0 | Blue Swirl | .name ="slavio_timer",
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356 | f4b19cd0 | Blue Swirl | .version_id = 3,
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357 | f4b19cd0 | Blue Swirl | .minimum_version_id = 3,
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358 | f4b19cd0 | Blue Swirl | .minimum_version_id_old = 3,
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359 | f4b19cd0 | Blue Swirl | .fields = (VMStateField []) { |
360 | f4b19cd0 | Blue Swirl | VMSTATE_STRUCT_ARRAY(cputimer, SLAVIO_TIMERState, MAX_CPUS + 1, 3, |
361 | f4b19cd0 | Blue Swirl | vmstate_timer, CPUTimerState), |
362 | f4b19cd0 | Blue Swirl | VMSTATE_END_OF_LIST() |
363 | 7204ff9c | Blue Swirl | } |
364 | f4b19cd0 | Blue Swirl | }; |
365 | e80cfcfc | bellard | |
366 | 0e0bfeea | Blue Swirl | static void slavio_timer_reset(DeviceState *d) |
367 | e80cfcfc | bellard | { |
368 | 0e0bfeea | Blue Swirl | SLAVIO_TIMERState *s = container_of(d, SLAVIO_TIMERState, busdev.qdev); |
369 | 7204ff9c | Blue Swirl | unsigned int i; |
370 | 7204ff9c | Blue Swirl | CPUTimerState *curr_timer; |
371 | 7204ff9c | Blue Swirl | |
372 | 7204ff9c | Blue Swirl | for (i = 0; i <= MAX_CPUS; i++) { |
373 | 7204ff9c | Blue Swirl | curr_timer = &s->cputimer[i]; |
374 | 7204ff9c | Blue Swirl | curr_timer->limit = 0;
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375 | 7204ff9c | Blue Swirl | curr_timer->count = 0;
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376 | 7204ff9c | Blue Swirl | curr_timer->reached = 0;
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377 | 7204ff9c | Blue Swirl | if (i < s->num_cpus) {
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378 | 7204ff9c | Blue Swirl | ptimer_set_limit(curr_timer->timer, |
379 | 7204ff9c | Blue Swirl | LIMIT_TO_PERIODS(TIMER_MAX_COUNT32), 1);
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380 | 7204ff9c | Blue Swirl | ptimer_run(curr_timer->timer, 0);
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381 | 7204ff9c | Blue Swirl | } |
382 | 7204ff9c | Blue Swirl | curr_timer->running = 1;
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383 | 85e3023e | blueswir1 | } |
384 | 7204ff9c | Blue Swirl | s->cputimer_mode = 0;
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385 | e80cfcfc | bellard | } |
386 | e80cfcfc | bellard | |
387 | 81a322d4 | Gerd Hoffmann | static int slavio_timer_init1(SysBusDevice *dev) |
388 | c70c59ee | Blue Swirl | { |
389 | c70c59ee | Blue Swirl | int io;
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390 | c70c59ee | Blue Swirl | SLAVIO_TIMERState *s = FROM_SYSBUS(SLAVIO_TIMERState, dev); |
391 | 8d05ea8a | blueswir1 | QEMUBH *bh; |
392 | 7204ff9c | Blue Swirl | unsigned int i; |
393 | 7204ff9c | Blue Swirl | TimerContext *tc; |
394 | e80cfcfc | bellard | |
395 | 7204ff9c | Blue Swirl | for (i = 0; i <= MAX_CPUS; i++) { |
396 | 7204ff9c | Blue Swirl | tc = qemu_mallocz(sizeof(TimerContext));
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397 | 7204ff9c | Blue Swirl | tc->s = s; |
398 | 7204ff9c | Blue Swirl | tc->timer_index = i; |
399 | c70c59ee | Blue Swirl | |
400 | 7204ff9c | Blue Swirl | bh = qemu_bh_new(slavio_timer_irq, tc); |
401 | 7204ff9c | Blue Swirl | s->cputimer[i].timer = ptimer_init(bh); |
402 | 7204ff9c | Blue Swirl | ptimer_set_period(s->cputimer[i].timer, TIMER_PERIOD); |
403 | e80cfcfc | bellard | |
404 | 7204ff9c | Blue Swirl | io = cpu_register_io_memory(slavio_timer_mem_read, |
405 | 7204ff9c | Blue Swirl | slavio_timer_mem_write, tc); |
406 | 7204ff9c | Blue Swirl | if (i == 0) { |
407 | 7204ff9c | Blue Swirl | sysbus_init_mmio(dev, SYS_TIMER_SIZE, io); |
408 | 7204ff9c | Blue Swirl | } else {
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409 | 7204ff9c | Blue Swirl | sysbus_init_mmio(dev, CPU_TIMER_SIZE, io); |
410 | 7204ff9c | Blue Swirl | } |
411 | 7204ff9c | Blue Swirl | |
412 | 7204ff9c | Blue Swirl | sysbus_init_irq(dev, &s->cputimer[i].irq); |
413 | c70c59ee | Blue Swirl | } |
414 | c70c59ee | Blue Swirl | |
415 | 81a322d4 | Gerd Hoffmann | return 0; |
416 | 81732d19 | blueswir1 | } |
417 | 81732d19 | blueswir1 | |
418 | c70c59ee | Blue Swirl | static SysBusDeviceInfo slavio_timer_info = {
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419 | c70c59ee | Blue Swirl | .init = slavio_timer_init1, |
420 | c70c59ee | Blue Swirl | .qdev.name = "slavio_timer",
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421 | c70c59ee | Blue Swirl | .qdev.size = sizeof(SLAVIO_TIMERState),
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422 | 0e0bfeea | Blue Swirl | .qdev.vmsd = &vmstate_slavio_timer, |
423 | 0e0bfeea | Blue Swirl | .qdev.reset = slavio_timer_reset, |
424 | ee6847d1 | Gerd Hoffmann | .qdev.props = (Property[]) { |
425 | 18c637dc | Gerd Hoffmann | DEFINE_PROP_UINT32("num_cpus", SLAVIO_TIMERState, num_cpus, 0), |
426 | 18c637dc | Gerd Hoffmann | DEFINE_PROP_END_OF_LIST(), |
427 | c70c59ee | Blue Swirl | } |
428 | c70c59ee | Blue Swirl | }; |
429 | c70c59ee | Blue Swirl | |
430 | c70c59ee | Blue Swirl | static void slavio_timer_register_devices(void) |
431 | c70c59ee | Blue Swirl | { |
432 | c70c59ee | Blue Swirl | sysbus_register_withprop(&slavio_timer_info); |
433 | c70c59ee | Blue Swirl | } |
434 | c70c59ee | Blue Swirl | |
435 | c70c59ee | Blue Swirl | device_init(slavio_timer_register_devices) |