root / hw / arm_gic.c @ cc9f28bc
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1 | 5fafdf24 | ths | /*
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2 | 9ee6e8bb | pbrook | * ARM Generic/Distributed Interrupt Controller
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3 | e69954b9 | pbrook | *
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4 | 9ee6e8bb | pbrook | * Copyright (c) 2006-2007 CodeSourcery.
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5 | e69954b9 | pbrook | * Written by Paul Brook
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6 | e69954b9 | pbrook | *
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7 | e69954b9 | pbrook | * This code is licenced under the GPL.
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8 | e69954b9 | pbrook | */
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9 | e69954b9 | pbrook | |
10 | 9ee6e8bb | pbrook | /* This file contains implementation code for the RealView EB interrupt
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11 | 9ee6e8bb | pbrook | controller, MPCore distributed interrupt controller and ARMv7-M
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12 | 9ee6e8bb | pbrook | Nested Vectored Interrupt Controller. */
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13 | e69954b9 | pbrook | |
14 | e69954b9 | pbrook | //#define DEBUG_GIC
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15 | e69954b9 | pbrook | |
16 | e69954b9 | pbrook | #ifdef DEBUG_GIC
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17 | 001faf32 | Blue Swirl | #define DPRINTF(fmt, ...) \
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18 | 001faf32 | Blue Swirl | do { printf("arm_gic: " fmt , ## __VA_ARGS__); } while (0) |
19 | e69954b9 | pbrook | #else
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20 | 001faf32 | Blue Swirl | #define DPRINTF(fmt, ...) do {} while(0) |
21 | e69954b9 | pbrook | #endif
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22 | e69954b9 | pbrook | |
23 | 9ee6e8bb | pbrook | #ifdef NVIC
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24 | 9ee6e8bb | pbrook | static const uint8_t gic_id[] = |
25 | 9ee6e8bb | pbrook | { 0x00, 0xb0, 0x1b, 0x00, 0x0d, 0xe0, 0x05, 0xb1 }; |
26 | 9ee6e8bb | pbrook | /* The NVIC has 16 internal vectors. However these are not exposed
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27 | 9ee6e8bb | pbrook | through the normal GIC interface. */
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28 | 9ee6e8bb | pbrook | #define GIC_BASE_IRQ 32 |
29 | 9ee6e8bb | pbrook | #else
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30 | e69954b9 | pbrook | static const uint8_t gic_id[] = |
31 | e69954b9 | pbrook | { 0x90, 0x13, 0x04, 0x00, 0x0d, 0xf0, 0x05, 0xb1 }; |
32 | 9ee6e8bb | pbrook | #define GIC_BASE_IRQ 0 |
33 | 9ee6e8bb | pbrook | #endif
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34 | e69954b9 | pbrook | |
35 | fe7e8758 | Paul Brook | #define FROM_SYSBUSGIC(type, dev) \
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36 | fe7e8758 | Paul Brook | DO_UPCAST(type, gic, FROM_SYSBUS(gic_state, dev)) |
37 | fe7e8758 | Paul Brook | |
38 | e69954b9 | pbrook | typedef struct gic_irq_state |
39 | e69954b9 | pbrook | { |
40 | 9ee6e8bb | pbrook | /* ??? The documentation seems to imply the enable bits are global, even
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41 | 9ee6e8bb | pbrook | for per-cpu interrupts. This seems strange. */
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42 | e69954b9 | pbrook | unsigned enabled:1; |
43 | 9ee6e8bb | pbrook | unsigned pending:NCPU;
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44 | 9ee6e8bb | pbrook | unsigned active:NCPU;
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45 | a45db6c6 | aurel32 | unsigned level:NCPU;
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46 | 9ee6e8bb | pbrook | unsigned model:1; /* 0 = N:N, 1 = 1:N */ |
47 | e69954b9 | pbrook | unsigned trigger:1; /* nonzero = edge triggered. */ |
48 | e69954b9 | pbrook | } gic_irq_state; |
49 | e69954b9 | pbrook | |
50 | 9ee6e8bb | pbrook | #define ALL_CPU_MASK ((1 << NCPU) - 1) |
51 | c988bfad | Paul Brook | #if NCPU > 1 |
52 | c988bfad | Paul Brook | #define NUM_CPU(s) ((s)->num_cpu)
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53 | c988bfad | Paul Brook | #else
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54 | c988bfad | Paul Brook | #define NUM_CPU(s) 1 |
55 | c988bfad | Paul Brook | #endif
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56 | 9ee6e8bb | pbrook | |
57 | e69954b9 | pbrook | #define GIC_SET_ENABLED(irq) s->irq_state[irq].enabled = 1 |
58 | e69954b9 | pbrook | #define GIC_CLEAR_ENABLED(irq) s->irq_state[irq].enabled = 0 |
59 | e69954b9 | pbrook | #define GIC_TEST_ENABLED(irq) s->irq_state[irq].enabled
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60 | 9ee6e8bb | pbrook | #define GIC_SET_PENDING(irq, cm) s->irq_state[irq].pending |= (cm)
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61 | 9ee6e8bb | pbrook | #define GIC_CLEAR_PENDING(irq, cm) s->irq_state[irq].pending &= ~(cm)
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62 | 9ee6e8bb | pbrook | #define GIC_TEST_PENDING(irq, cm) ((s->irq_state[irq].pending & (cm)) != 0) |
63 | 9ee6e8bb | pbrook | #define GIC_SET_ACTIVE(irq, cm) s->irq_state[irq].active |= (cm)
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64 | 9ee6e8bb | pbrook | #define GIC_CLEAR_ACTIVE(irq, cm) s->irq_state[irq].active &= ~(cm)
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65 | 9ee6e8bb | pbrook | #define GIC_TEST_ACTIVE(irq, cm) ((s->irq_state[irq].active & (cm)) != 0) |
66 | e69954b9 | pbrook | #define GIC_SET_MODEL(irq) s->irq_state[irq].model = 1 |
67 | e69954b9 | pbrook | #define GIC_CLEAR_MODEL(irq) s->irq_state[irq].model = 0 |
68 | e69954b9 | pbrook | #define GIC_TEST_MODEL(irq) s->irq_state[irq].model
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69 | 9ee6e8bb | pbrook | #define GIC_SET_LEVEL(irq, cm) s->irq_state[irq].level = (cm)
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70 | 9ee6e8bb | pbrook | #define GIC_CLEAR_LEVEL(irq, cm) s->irq_state[irq].level &= ~(cm)
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71 | 57d69a91 | balrog | #define GIC_TEST_LEVEL(irq, cm) ((s->irq_state[irq].level & (cm)) != 0) |
72 | e69954b9 | pbrook | #define GIC_SET_TRIGGER(irq) s->irq_state[irq].trigger = 1 |
73 | e69954b9 | pbrook | #define GIC_CLEAR_TRIGGER(irq) s->irq_state[irq].trigger = 0 |
74 | e69954b9 | pbrook | #define GIC_TEST_TRIGGER(irq) s->irq_state[irq].trigger
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75 | 9ee6e8bb | pbrook | #define GIC_GET_PRIORITY(irq, cpu) \
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76 | 9ee6e8bb | pbrook | (((irq) < 32) ? s->priority1[irq][cpu] : s->priority2[(irq) - 32]) |
77 | 9ee6e8bb | pbrook | #ifdef NVIC
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78 | 9ee6e8bb | pbrook | #define GIC_TARGET(irq) 1 |
79 | 9ee6e8bb | pbrook | #else
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80 | 9ee6e8bb | pbrook | #define GIC_TARGET(irq) s->irq_target[irq]
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81 | 9ee6e8bb | pbrook | #endif
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82 | e69954b9 | pbrook | |
83 | e69954b9 | pbrook | typedef struct gic_state |
84 | e69954b9 | pbrook | { |
85 | fe7e8758 | Paul Brook | SysBusDevice busdev; |
86 | 9ee6e8bb | pbrook | qemu_irq parent_irq[NCPU]; |
87 | e69954b9 | pbrook | int enabled;
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88 | 9ee6e8bb | pbrook | int cpu_enabled[NCPU];
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89 | e69954b9 | pbrook | |
90 | e69954b9 | pbrook | gic_irq_state irq_state[GIC_NIRQ]; |
91 | 9ee6e8bb | pbrook | #ifndef NVIC
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92 | e69954b9 | pbrook | int irq_target[GIC_NIRQ];
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93 | 9ee6e8bb | pbrook | #endif
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94 | 9ee6e8bb | pbrook | int priority1[32][NCPU]; |
95 | 9ee6e8bb | pbrook | int priority2[GIC_NIRQ - 32]; |
96 | 9ee6e8bb | pbrook | int last_active[GIC_NIRQ][NCPU];
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97 | 9ee6e8bb | pbrook | |
98 | 9ee6e8bb | pbrook | int priority_mask[NCPU];
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99 | 9ee6e8bb | pbrook | int running_irq[NCPU];
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100 | 9ee6e8bb | pbrook | int running_priority[NCPU];
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101 | 9ee6e8bb | pbrook | int current_pending[NCPU];
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102 | 9ee6e8bb | pbrook | |
103 | c988bfad | Paul Brook | #if NCPU > 1 |
104 | c988bfad | Paul Brook | int num_cpu;
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105 | c988bfad | Paul Brook | #endif
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106 | c988bfad | Paul Brook | |
107 | fe7e8758 | Paul Brook | int iomemtype;
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108 | e69954b9 | pbrook | } gic_state; |
109 | e69954b9 | pbrook | |
110 | e69954b9 | pbrook | /* TODO: Many places that call this routine could be optimized. */
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111 | e69954b9 | pbrook | /* Update interrupt status after enabled or pending bits have been changed. */
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112 | e69954b9 | pbrook | static void gic_update(gic_state *s) |
113 | e69954b9 | pbrook | { |
114 | e69954b9 | pbrook | int best_irq;
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115 | e69954b9 | pbrook | int best_prio;
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116 | e69954b9 | pbrook | int irq;
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117 | 9ee6e8bb | pbrook | int level;
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118 | 9ee6e8bb | pbrook | int cpu;
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119 | 9ee6e8bb | pbrook | int cm;
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120 | 9ee6e8bb | pbrook | |
121 | c988bfad | Paul Brook | for (cpu = 0; cpu < NUM_CPU(s); cpu++) { |
122 | 9ee6e8bb | pbrook | cm = 1 << cpu;
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123 | 9ee6e8bb | pbrook | s->current_pending[cpu] = 1023;
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124 | 9ee6e8bb | pbrook | if (!s->enabled || !s->cpu_enabled[cpu]) {
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125 | 9ee6e8bb | pbrook | qemu_irq_lower(s->parent_irq[cpu]); |
126 | 9ee6e8bb | pbrook | return;
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127 | 9ee6e8bb | pbrook | } |
128 | 9ee6e8bb | pbrook | best_prio = 0x100;
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129 | 9ee6e8bb | pbrook | best_irq = 1023;
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130 | 9ee6e8bb | pbrook | for (irq = 0; irq < GIC_NIRQ; irq++) { |
131 | 9ee6e8bb | pbrook | if (GIC_TEST_ENABLED(irq) && GIC_TEST_PENDING(irq, cm)) {
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132 | 9ee6e8bb | pbrook | if (GIC_GET_PRIORITY(irq, cpu) < best_prio) {
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133 | 9ee6e8bb | pbrook | best_prio = GIC_GET_PRIORITY(irq, cpu); |
134 | 9ee6e8bb | pbrook | best_irq = irq; |
135 | 9ee6e8bb | pbrook | } |
136 | e69954b9 | pbrook | } |
137 | e69954b9 | pbrook | } |
138 | 9ee6e8bb | pbrook | level = 0;
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139 | 9ee6e8bb | pbrook | if (best_prio <= s->priority_mask[cpu]) {
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140 | 9ee6e8bb | pbrook | s->current_pending[cpu] = best_irq; |
141 | 9ee6e8bb | pbrook | if (best_prio < s->running_priority[cpu]) {
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142 | 9ee6e8bb | pbrook | DPRINTF("Raised pending IRQ %d\n", best_irq);
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143 | 9ee6e8bb | pbrook | level = 1;
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144 | 9ee6e8bb | pbrook | } |
145 | e69954b9 | pbrook | } |
146 | 9ee6e8bb | pbrook | qemu_set_irq(s->parent_irq[cpu], level); |
147 | e69954b9 | pbrook | } |
148 | e69954b9 | pbrook | } |
149 | e69954b9 | pbrook | |
150 | 9ee6e8bb | pbrook | static void __attribute__((unused)) |
151 | 9ee6e8bb | pbrook | gic_set_pending_private(gic_state *s, int cpu, int irq) |
152 | 9ee6e8bb | pbrook | { |
153 | 9ee6e8bb | pbrook | int cm = 1 << cpu; |
154 | 9ee6e8bb | pbrook | |
155 | 9ee6e8bb | pbrook | if (GIC_TEST_PENDING(irq, cm))
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156 | 9ee6e8bb | pbrook | return;
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157 | 9ee6e8bb | pbrook | |
158 | 9ee6e8bb | pbrook | DPRINTF("Set %d pending cpu %d\n", irq, cpu);
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159 | 9ee6e8bb | pbrook | GIC_SET_PENDING(irq, cm); |
160 | 9ee6e8bb | pbrook | gic_update(s); |
161 | 9ee6e8bb | pbrook | } |
162 | 9ee6e8bb | pbrook | |
163 | 9ee6e8bb | pbrook | /* Process a change in an external IRQ input. */
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164 | e69954b9 | pbrook | static void gic_set_irq(void *opaque, int irq, int level) |
165 | e69954b9 | pbrook | { |
166 | e69954b9 | pbrook | gic_state *s = (gic_state *)opaque; |
167 | e69954b9 | pbrook | /* The first external input line is internal interrupt 32. */
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168 | e69954b9 | pbrook | irq += 32;
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169 | 9ee6e8bb | pbrook | if (level == GIC_TEST_LEVEL(irq, ALL_CPU_MASK))
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170 | e69954b9 | pbrook | return;
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171 | e69954b9 | pbrook | |
172 | e69954b9 | pbrook | if (level) {
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173 | 9ee6e8bb | pbrook | GIC_SET_LEVEL(irq, ALL_CPU_MASK); |
174 | e69954b9 | pbrook | if (GIC_TEST_TRIGGER(irq) || GIC_TEST_ENABLED(irq)) {
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175 | 9ee6e8bb | pbrook | DPRINTF("Set %d pending mask %x\n", irq, GIC_TARGET(irq));
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176 | 9ee6e8bb | pbrook | GIC_SET_PENDING(irq, GIC_TARGET(irq)); |
177 | e69954b9 | pbrook | } |
178 | e69954b9 | pbrook | } else {
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179 | 9ee6e8bb | pbrook | GIC_CLEAR_LEVEL(irq, ALL_CPU_MASK); |
180 | e69954b9 | pbrook | } |
181 | e69954b9 | pbrook | gic_update(s); |
182 | e69954b9 | pbrook | } |
183 | e69954b9 | pbrook | |
184 | 9ee6e8bb | pbrook | static void gic_set_running_irq(gic_state *s, int cpu, int irq) |
185 | e69954b9 | pbrook | { |
186 | 9ee6e8bb | pbrook | s->running_irq[cpu] = irq; |
187 | 9ee6e8bb | pbrook | if (irq == 1023) { |
188 | 9ee6e8bb | pbrook | s->running_priority[cpu] = 0x100;
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189 | 9ee6e8bb | pbrook | } else {
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190 | 9ee6e8bb | pbrook | s->running_priority[cpu] = GIC_GET_PRIORITY(irq, cpu); |
191 | 9ee6e8bb | pbrook | } |
192 | e69954b9 | pbrook | gic_update(s); |
193 | e69954b9 | pbrook | } |
194 | e69954b9 | pbrook | |
195 | 9ee6e8bb | pbrook | static uint32_t gic_acknowledge_irq(gic_state *s, int cpu) |
196 | e69954b9 | pbrook | { |
197 | e69954b9 | pbrook | int new_irq;
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198 | 9ee6e8bb | pbrook | int cm = 1 << cpu; |
199 | 9ee6e8bb | pbrook | new_irq = s->current_pending[cpu]; |
200 | 9ee6e8bb | pbrook | if (new_irq == 1023 |
201 | 9ee6e8bb | pbrook | || GIC_GET_PRIORITY(new_irq, cpu) >= s->running_priority[cpu]) { |
202 | e69954b9 | pbrook | DPRINTF("ACK no pending IRQ\n");
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203 | e69954b9 | pbrook | return 1023; |
204 | e69954b9 | pbrook | } |
205 | 9ee6e8bb | pbrook | s->last_active[new_irq][cpu] = s->running_irq[cpu]; |
206 | 9ee6e8bb | pbrook | /* Clear pending flags for both level and edge triggered interrupts.
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207 | 9ee6e8bb | pbrook | Level triggered IRQs will be reasserted once they become inactive. */
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208 | 9ee6e8bb | pbrook | GIC_CLEAR_PENDING(new_irq, GIC_TEST_MODEL(new_irq) ? ALL_CPU_MASK : cm); |
209 | 9ee6e8bb | pbrook | gic_set_running_irq(s, cpu, new_irq); |
210 | e69954b9 | pbrook | DPRINTF("ACK %d\n", new_irq);
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211 | e69954b9 | pbrook | return new_irq;
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212 | e69954b9 | pbrook | } |
213 | e69954b9 | pbrook | |
214 | 9ee6e8bb | pbrook | static void gic_complete_irq(gic_state * s, int cpu, int irq) |
215 | e69954b9 | pbrook | { |
216 | e69954b9 | pbrook | int update = 0; |
217 | 9ee6e8bb | pbrook | int cm = 1 << cpu; |
218 | df628ff1 | pbrook | DPRINTF("EOI %d\n", irq);
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219 | 9ee6e8bb | pbrook | if (s->running_irq[cpu] == 1023) |
220 | e69954b9 | pbrook | return; /* No active IRQ. */ |
221 | e69954b9 | pbrook | if (irq != 1023) { |
222 | e69954b9 | pbrook | /* Mark level triggered interrupts as pending if they are still
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223 | e69954b9 | pbrook | raised. */
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224 | e69954b9 | pbrook | if (!GIC_TEST_TRIGGER(irq) && GIC_TEST_ENABLED(irq)
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225 | 9ee6e8bb | pbrook | && GIC_TEST_LEVEL(irq, cm) && (GIC_TARGET(irq) & cm) != 0) {
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226 | 9ee6e8bb | pbrook | DPRINTF("Set %d pending mask %x\n", irq, cm);
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227 | 9ee6e8bb | pbrook | GIC_SET_PENDING(irq, cm); |
228 | e69954b9 | pbrook | update = 1;
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229 | e69954b9 | pbrook | } |
230 | e69954b9 | pbrook | } |
231 | 9ee6e8bb | pbrook | if (irq != s->running_irq[cpu]) {
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232 | e69954b9 | pbrook | /* Complete an IRQ that is not currently running. */
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233 | 9ee6e8bb | pbrook | int tmp = s->running_irq[cpu];
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234 | 9ee6e8bb | pbrook | while (s->last_active[tmp][cpu] != 1023) { |
235 | 9ee6e8bb | pbrook | if (s->last_active[tmp][cpu] == irq) {
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236 | 9ee6e8bb | pbrook | s->last_active[tmp][cpu] = s->last_active[irq][cpu]; |
237 | e69954b9 | pbrook | break;
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238 | e69954b9 | pbrook | } |
239 | 9ee6e8bb | pbrook | tmp = s->last_active[tmp][cpu]; |
240 | e69954b9 | pbrook | } |
241 | e69954b9 | pbrook | if (update) {
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242 | e69954b9 | pbrook | gic_update(s); |
243 | e69954b9 | pbrook | } |
244 | e69954b9 | pbrook | } else {
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245 | e69954b9 | pbrook | /* Complete the current running IRQ. */
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246 | 9ee6e8bb | pbrook | gic_set_running_irq(s, cpu, s->last_active[s->running_irq[cpu]][cpu]); |
247 | e69954b9 | pbrook | } |
248 | e69954b9 | pbrook | } |
249 | e69954b9 | pbrook | |
250 | c227f099 | Anthony Liguori | static uint32_t gic_dist_readb(void *opaque, target_phys_addr_t offset) |
251 | e69954b9 | pbrook | { |
252 | e69954b9 | pbrook | gic_state *s = (gic_state *)opaque; |
253 | e69954b9 | pbrook | uint32_t res; |
254 | e69954b9 | pbrook | int irq;
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255 | e69954b9 | pbrook | int i;
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256 | 9ee6e8bb | pbrook | int cpu;
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257 | 9ee6e8bb | pbrook | int cm;
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258 | 9ee6e8bb | pbrook | int mask;
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259 | e69954b9 | pbrook | |
260 | 9ee6e8bb | pbrook | cpu = gic_get_current_cpu(); |
261 | 9ee6e8bb | pbrook | cm = 1 << cpu;
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262 | e69954b9 | pbrook | if (offset < 0x100) { |
263 | 9ee6e8bb | pbrook | #ifndef NVIC
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264 | e69954b9 | pbrook | if (offset == 0) |
265 | e69954b9 | pbrook | return s->enabled;
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266 | e69954b9 | pbrook | if (offset == 4) |
267 | c988bfad | Paul Brook | return ((GIC_NIRQ / 32) - 1) | ((NUM_CPU(s) - 1) << 5); |
268 | e69954b9 | pbrook | if (offset < 0x08) |
269 | e69954b9 | pbrook | return 0; |
270 | 9ee6e8bb | pbrook | #endif
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271 | e69954b9 | pbrook | goto bad_reg;
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272 | e69954b9 | pbrook | } else if (offset < 0x200) { |
273 | e69954b9 | pbrook | /* Interrupt Set/Clear Enable. */
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274 | e69954b9 | pbrook | if (offset < 0x180) |
275 | e69954b9 | pbrook | irq = (offset - 0x100) * 8; |
276 | e69954b9 | pbrook | else
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277 | e69954b9 | pbrook | irq = (offset - 0x180) * 8; |
278 | 9ee6e8bb | pbrook | irq += GIC_BASE_IRQ; |
279 | e69954b9 | pbrook | if (irq >= GIC_NIRQ)
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280 | e69954b9 | pbrook | goto bad_reg;
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281 | e69954b9 | pbrook | res = 0;
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282 | e69954b9 | pbrook | for (i = 0; i < 8; i++) { |
283 | e69954b9 | pbrook | if (GIC_TEST_ENABLED(irq + i)) {
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284 | e69954b9 | pbrook | res |= (1 << i);
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285 | e69954b9 | pbrook | } |
286 | e69954b9 | pbrook | } |
287 | e69954b9 | pbrook | } else if (offset < 0x300) { |
288 | e69954b9 | pbrook | /* Interrupt Set/Clear Pending. */
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289 | e69954b9 | pbrook | if (offset < 0x280) |
290 | e69954b9 | pbrook | irq = (offset - 0x200) * 8; |
291 | e69954b9 | pbrook | else
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292 | e69954b9 | pbrook | irq = (offset - 0x280) * 8; |
293 | 9ee6e8bb | pbrook | irq += GIC_BASE_IRQ; |
294 | e69954b9 | pbrook | if (irq >= GIC_NIRQ)
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295 | e69954b9 | pbrook | goto bad_reg;
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296 | e69954b9 | pbrook | res = 0;
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297 | 9ee6e8bb | pbrook | mask = (irq < 32) ? cm : ALL_CPU_MASK;
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298 | e69954b9 | pbrook | for (i = 0; i < 8; i++) { |
299 | 9ee6e8bb | pbrook | if (GIC_TEST_PENDING(irq + i, mask)) {
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300 | e69954b9 | pbrook | res |= (1 << i);
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301 | e69954b9 | pbrook | } |
302 | e69954b9 | pbrook | } |
303 | e69954b9 | pbrook | } else if (offset < 0x400) { |
304 | e69954b9 | pbrook | /* Interrupt Active. */
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305 | 9ee6e8bb | pbrook | irq = (offset - 0x300) * 8 + GIC_BASE_IRQ; |
306 | e69954b9 | pbrook | if (irq >= GIC_NIRQ)
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307 | e69954b9 | pbrook | goto bad_reg;
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308 | e69954b9 | pbrook | res = 0;
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309 | 9ee6e8bb | pbrook | mask = (irq < 32) ? cm : ALL_CPU_MASK;
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310 | e69954b9 | pbrook | for (i = 0; i < 8; i++) { |
311 | 9ee6e8bb | pbrook | if (GIC_TEST_ACTIVE(irq + i, mask)) {
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312 | e69954b9 | pbrook | res |= (1 << i);
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313 | e69954b9 | pbrook | } |
314 | e69954b9 | pbrook | } |
315 | e69954b9 | pbrook | } else if (offset < 0x800) { |
316 | e69954b9 | pbrook | /* Interrupt Priority. */
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317 | 9ee6e8bb | pbrook | irq = (offset - 0x400) + GIC_BASE_IRQ;
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318 | e69954b9 | pbrook | if (irq >= GIC_NIRQ)
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319 | e69954b9 | pbrook | goto bad_reg;
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320 | 9ee6e8bb | pbrook | res = GIC_GET_PRIORITY(irq, cpu); |
321 | 9ee6e8bb | pbrook | #ifndef NVIC
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322 | e69954b9 | pbrook | } else if (offset < 0xc00) { |
323 | e69954b9 | pbrook | /* Interrupt CPU Target. */
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324 | 9ee6e8bb | pbrook | irq = (offset - 0x800) + GIC_BASE_IRQ;
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325 | e69954b9 | pbrook | if (irq >= GIC_NIRQ)
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326 | e69954b9 | pbrook | goto bad_reg;
|
327 | 9ee6e8bb | pbrook | if (irq >= 29 && irq <= 31) { |
328 | 9ee6e8bb | pbrook | res = cm; |
329 | 9ee6e8bb | pbrook | } else {
|
330 | 9ee6e8bb | pbrook | res = GIC_TARGET(irq); |
331 | 9ee6e8bb | pbrook | } |
332 | e69954b9 | pbrook | } else if (offset < 0xf00) { |
333 | e69954b9 | pbrook | /* Interrupt Configuration. */
|
334 | 9ee6e8bb | pbrook | irq = (offset - 0xc00) * 2 + GIC_BASE_IRQ; |
335 | e69954b9 | pbrook | if (irq >= GIC_NIRQ)
|
336 | e69954b9 | pbrook | goto bad_reg;
|
337 | e69954b9 | pbrook | res = 0;
|
338 | e69954b9 | pbrook | for (i = 0; i < 4; i++) { |
339 | e69954b9 | pbrook | if (GIC_TEST_MODEL(irq + i))
|
340 | e69954b9 | pbrook | res |= (1 << (i * 2)); |
341 | e69954b9 | pbrook | if (GIC_TEST_TRIGGER(irq + i))
|
342 | e69954b9 | pbrook | res |= (2 << (i * 2)); |
343 | e69954b9 | pbrook | } |
344 | 9ee6e8bb | pbrook | #endif
|
345 | e69954b9 | pbrook | } else if (offset < 0xfe0) { |
346 | e69954b9 | pbrook | goto bad_reg;
|
347 | e69954b9 | pbrook | } else /* offset >= 0xfe0 */ { |
348 | e69954b9 | pbrook | if (offset & 3) { |
349 | e69954b9 | pbrook | res = 0;
|
350 | e69954b9 | pbrook | } else {
|
351 | e69954b9 | pbrook | res = gic_id[(offset - 0xfe0) >> 2]; |
352 | e69954b9 | pbrook | } |
353 | e69954b9 | pbrook | } |
354 | e69954b9 | pbrook | return res;
|
355 | e69954b9 | pbrook | bad_reg:
|
356 | 2ac71179 | Paul Brook | hw_error("gic_dist_readb: Bad offset %x\n", (int)offset); |
357 | e69954b9 | pbrook | return 0; |
358 | e69954b9 | pbrook | } |
359 | e69954b9 | pbrook | |
360 | c227f099 | Anthony Liguori | static uint32_t gic_dist_readw(void *opaque, target_phys_addr_t offset) |
361 | e69954b9 | pbrook | { |
362 | e69954b9 | pbrook | uint32_t val; |
363 | e69954b9 | pbrook | val = gic_dist_readb(opaque, offset); |
364 | e69954b9 | pbrook | val |= gic_dist_readb(opaque, offset + 1) << 8; |
365 | e69954b9 | pbrook | return val;
|
366 | e69954b9 | pbrook | } |
367 | e69954b9 | pbrook | |
368 | c227f099 | Anthony Liguori | static uint32_t gic_dist_readl(void *opaque, target_phys_addr_t offset) |
369 | e69954b9 | pbrook | { |
370 | e69954b9 | pbrook | uint32_t val; |
371 | 9ee6e8bb | pbrook | #ifdef NVIC
|
372 | 9ee6e8bb | pbrook | gic_state *s = (gic_state *)opaque; |
373 | 9ee6e8bb | pbrook | uint32_t addr; |
374 | 8da3ff18 | pbrook | addr = offset; |
375 | 9ee6e8bb | pbrook | if (addr < 0x100 || addr > 0xd00) |
376 | fe7e8758 | Paul Brook | return nvic_readl(s, addr);
|
377 | 9ee6e8bb | pbrook | #endif
|
378 | e69954b9 | pbrook | val = gic_dist_readw(opaque, offset); |
379 | e69954b9 | pbrook | val |= gic_dist_readw(opaque, offset + 2) << 16; |
380 | e69954b9 | pbrook | return val;
|
381 | e69954b9 | pbrook | } |
382 | e69954b9 | pbrook | |
383 | c227f099 | Anthony Liguori | static void gic_dist_writeb(void *opaque, target_phys_addr_t offset, |
384 | e69954b9 | pbrook | uint32_t value) |
385 | e69954b9 | pbrook | { |
386 | e69954b9 | pbrook | gic_state *s = (gic_state *)opaque; |
387 | e69954b9 | pbrook | int irq;
|
388 | e69954b9 | pbrook | int i;
|
389 | 9ee6e8bb | pbrook | int cpu;
|
390 | e69954b9 | pbrook | |
391 | 9ee6e8bb | pbrook | cpu = gic_get_current_cpu(); |
392 | e69954b9 | pbrook | if (offset < 0x100) { |
393 | 9ee6e8bb | pbrook | #ifdef NVIC
|
394 | 9ee6e8bb | pbrook | goto bad_reg;
|
395 | 9ee6e8bb | pbrook | #else
|
396 | e69954b9 | pbrook | if (offset == 0) { |
397 | e69954b9 | pbrook | s->enabled = (value & 1);
|
398 | e69954b9 | pbrook | DPRINTF("Distribution %sabled\n", s->enabled ? "En" : "Dis"); |
399 | e69954b9 | pbrook | } else if (offset < 4) { |
400 | e69954b9 | pbrook | /* ignored. */
|
401 | e69954b9 | pbrook | } else {
|
402 | e69954b9 | pbrook | goto bad_reg;
|
403 | e69954b9 | pbrook | } |
404 | 9ee6e8bb | pbrook | #endif
|
405 | e69954b9 | pbrook | } else if (offset < 0x180) { |
406 | e69954b9 | pbrook | /* Interrupt Set Enable. */
|
407 | 9ee6e8bb | pbrook | irq = (offset - 0x100) * 8 + GIC_BASE_IRQ; |
408 | e69954b9 | pbrook | if (irq >= GIC_NIRQ)
|
409 | e69954b9 | pbrook | goto bad_reg;
|
410 | 9ee6e8bb | pbrook | if (irq < 16) |
411 | 9ee6e8bb | pbrook | value = 0xff;
|
412 | e69954b9 | pbrook | for (i = 0; i < 8; i++) { |
413 | e69954b9 | pbrook | if (value & (1 << i)) { |
414 | 9ee6e8bb | pbrook | int mask = (irq < 32) ? (1 << cpu) : GIC_TARGET(irq); |
415 | e69954b9 | pbrook | if (!GIC_TEST_ENABLED(irq + i))
|
416 | e69954b9 | pbrook | DPRINTF("Enabled IRQ %d\n", irq + i);
|
417 | e69954b9 | pbrook | GIC_SET_ENABLED(irq + i); |
418 | e69954b9 | pbrook | /* If a raised level triggered IRQ enabled then mark
|
419 | e69954b9 | pbrook | is as pending. */
|
420 | 9ee6e8bb | pbrook | if (GIC_TEST_LEVEL(irq + i, mask)
|
421 | 9ee6e8bb | pbrook | && !GIC_TEST_TRIGGER(irq + i)) { |
422 | 9ee6e8bb | pbrook | DPRINTF("Set %d pending mask %x\n", irq + i, mask);
|
423 | 9ee6e8bb | pbrook | GIC_SET_PENDING(irq + i, mask); |
424 | 9ee6e8bb | pbrook | } |
425 | e69954b9 | pbrook | } |
426 | e69954b9 | pbrook | } |
427 | e69954b9 | pbrook | } else if (offset < 0x200) { |
428 | e69954b9 | pbrook | /* Interrupt Clear Enable. */
|
429 | 9ee6e8bb | pbrook | irq = (offset - 0x180) * 8 + GIC_BASE_IRQ; |
430 | e69954b9 | pbrook | if (irq >= GIC_NIRQ)
|
431 | e69954b9 | pbrook | goto bad_reg;
|
432 | 9ee6e8bb | pbrook | if (irq < 16) |
433 | 9ee6e8bb | pbrook | value = 0;
|
434 | e69954b9 | pbrook | for (i = 0; i < 8; i++) { |
435 | e69954b9 | pbrook | if (value & (1 << i)) { |
436 | e69954b9 | pbrook | if (GIC_TEST_ENABLED(irq + i))
|
437 | e69954b9 | pbrook | DPRINTF("Disabled IRQ %d\n", irq + i);
|
438 | e69954b9 | pbrook | GIC_CLEAR_ENABLED(irq + i); |
439 | e69954b9 | pbrook | } |
440 | e69954b9 | pbrook | } |
441 | e69954b9 | pbrook | } else if (offset < 0x280) { |
442 | e69954b9 | pbrook | /* Interrupt Set Pending. */
|
443 | 9ee6e8bb | pbrook | irq = (offset - 0x200) * 8 + GIC_BASE_IRQ; |
444 | e69954b9 | pbrook | if (irq >= GIC_NIRQ)
|
445 | e69954b9 | pbrook | goto bad_reg;
|
446 | 9ee6e8bb | pbrook | if (irq < 16) |
447 | 9ee6e8bb | pbrook | irq = 0;
|
448 | 9ee6e8bb | pbrook | |
449 | e69954b9 | pbrook | for (i = 0; i < 8; i++) { |
450 | e69954b9 | pbrook | if (value & (1 << i)) { |
451 | 9ee6e8bb | pbrook | GIC_SET_PENDING(irq + i, GIC_TARGET(irq)); |
452 | e69954b9 | pbrook | } |
453 | e69954b9 | pbrook | } |
454 | e69954b9 | pbrook | } else if (offset < 0x300) { |
455 | e69954b9 | pbrook | /* Interrupt Clear Pending. */
|
456 | 9ee6e8bb | pbrook | irq = (offset - 0x280) * 8 + GIC_BASE_IRQ; |
457 | e69954b9 | pbrook | if (irq >= GIC_NIRQ)
|
458 | e69954b9 | pbrook | goto bad_reg;
|
459 | e69954b9 | pbrook | for (i = 0; i < 8; i++) { |
460 | 9ee6e8bb | pbrook | /* ??? This currently clears the pending bit for all CPUs, even
|
461 | 9ee6e8bb | pbrook | for per-CPU interrupts. It's unclear whether this is the
|
462 | 9ee6e8bb | pbrook | corect behavior. */
|
463 | e69954b9 | pbrook | if (value & (1 << i)) { |
464 | 9ee6e8bb | pbrook | GIC_CLEAR_PENDING(irq + i, ALL_CPU_MASK); |
465 | e69954b9 | pbrook | } |
466 | e69954b9 | pbrook | } |
467 | e69954b9 | pbrook | } else if (offset < 0x400) { |
468 | e69954b9 | pbrook | /* Interrupt Active. */
|
469 | e69954b9 | pbrook | goto bad_reg;
|
470 | e69954b9 | pbrook | } else if (offset < 0x800) { |
471 | e69954b9 | pbrook | /* Interrupt Priority. */
|
472 | 9ee6e8bb | pbrook | irq = (offset - 0x400) + GIC_BASE_IRQ;
|
473 | e69954b9 | pbrook | if (irq >= GIC_NIRQ)
|
474 | e69954b9 | pbrook | goto bad_reg;
|
475 | 9ee6e8bb | pbrook | if (irq < 32) { |
476 | 9ee6e8bb | pbrook | s->priority1[irq][cpu] = value; |
477 | 9ee6e8bb | pbrook | } else {
|
478 | 9ee6e8bb | pbrook | s->priority2[irq - 32] = value;
|
479 | 9ee6e8bb | pbrook | } |
480 | 9ee6e8bb | pbrook | #ifndef NVIC
|
481 | e69954b9 | pbrook | } else if (offset < 0xc00) { |
482 | e69954b9 | pbrook | /* Interrupt CPU Target. */
|
483 | 9ee6e8bb | pbrook | irq = (offset - 0x800) + GIC_BASE_IRQ;
|
484 | e69954b9 | pbrook | if (irq >= GIC_NIRQ)
|
485 | e69954b9 | pbrook | goto bad_reg;
|
486 | 9ee6e8bb | pbrook | if (irq < 29) |
487 | 9ee6e8bb | pbrook | value = 0;
|
488 | 9ee6e8bb | pbrook | else if (irq < 32) |
489 | 9ee6e8bb | pbrook | value = ALL_CPU_MASK; |
490 | 9ee6e8bb | pbrook | s->irq_target[irq] = value & ALL_CPU_MASK; |
491 | e69954b9 | pbrook | } else if (offset < 0xf00) { |
492 | e69954b9 | pbrook | /* Interrupt Configuration. */
|
493 | 9ee6e8bb | pbrook | irq = (offset - 0xc00) * 4 + GIC_BASE_IRQ; |
494 | e69954b9 | pbrook | if (irq >= GIC_NIRQ)
|
495 | e69954b9 | pbrook | goto bad_reg;
|
496 | 9ee6e8bb | pbrook | if (irq < 32) |
497 | 9ee6e8bb | pbrook | value |= 0xaa;
|
498 | e69954b9 | pbrook | for (i = 0; i < 4; i++) { |
499 | e69954b9 | pbrook | if (value & (1 << (i * 2))) { |
500 | e69954b9 | pbrook | GIC_SET_MODEL(irq + i); |
501 | e69954b9 | pbrook | } else {
|
502 | e69954b9 | pbrook | GIC_CLEAR_MODEL(irq + i); |
503 | e69954b9 | pbrook | } |
504 | e69954b9 | pbrook | if (value & (2 << (i * 2))) { |
505 | e69954b9 | pbrook | GIC_SET_TRIGGER(irq + i); |
506 | e69954b9 | pbrook | } else {
|
507 | e69954b9 | pbrook | GIC_CLEAR_TRIGGER(irq + i); |
508 | e69954b9 | pbrook | } |
509 | e69954b9 | pbrook | } |
510 | 9ee6e8bb | pbrook | #endif
|
511 | e69954b9 | pbrook | } else {
|
512 | 9ee6e8bb | pbrook | /* 0xf00 is only handled for 32-bit writes. */
|
513 | e69954b9 | pbrook | goto bad_reg;
|
514 | e69954b9 | pbrook | } |
515 | e69954b9 | pbrook | gic_update(s); |
516 | e69954b9 | pbrook | return;
|
517 | e69954b9 | pbrook | bad_reg:
|
518 | 2ac71179 | Paul Brook | hw_error("gic_dist_writeb: Bad offset %x\n", (int)offset); |
519 | e69954b9 | pbrook | } |
520 | e69954b9 | pbrook | |
521 | c227f099 | Anthony Liguori | static void gic_dist_writew(void *opaque, target_phys_addr_t offset, |
522 | e69954b9 | pbrook | uint32_t value) |
523 | e69954b9 | pbrook | { |
524 | e69954b9 | pbrook | gic_dist_writeb(opaque, offset, value & 0xff);
|
525 | e69954b9 | pbrook | gic_dist_writeb(opaque, offset + 1, value >> 8); |
526 | e69954b9 | pbrook | } |
527 | e69954b9 | pbrook | |
528 | c227f099 | Anthony Liguori | static void gic_dist_writel(void *opaque, target_phys_addr_t offset, |
529 | e69954b9 | pbrook | uint32_t value) |
530 | e69954b9 | pbrook | { |
531 | 9ee6e8bb | pbrook | gic_state *s = (gic_state *)opaque; |
532 | 9ee6e8bb | pbrook | #ifdef NVIC
|
533 | 9ee6e8bb | pbrook | uint32_t addr; |
534 | 8da3ff18 | pbrook | addr = offset; |
535 | 9ee6e8bb | pbrook | if (addr < 0x100 || (addr > 0xd00 && addr != 0xf00)) { |
536 | fe7e8758 | Paul Brook | nvic_writel(s, addr, value); |
537 | 9ee6e8bb | pbrook | return;
|
538 | 9ee6e8bb | pbrook | } |
539 | 9ee6e8bb | pbrook | #endif
|
540 | 8da3ff18 | pbrook | if (offset == 0xf00) { |
541 | 9ee6e8bb | pbrook | int cpu;
|
542 | 9ee6e8bb | pbrook | int irq;
|
543 | 9ee6e8bb | pbrook | int mask;
|
544 | 9ee6e8bb | pbrook | |
545 | 9ee6e8bb | pbrook | cpu = gic_get_current_cpu(); |
546 | 9ee6e8bb | pbrook | irq = value & 0x3ff;
|
547 | 9ee6e8bb | pbrook | switch ((value >> 24) & 3) { |
548 | 9ee6e8bb | pbrook | case 0: |
549 | 9ee6e8bb | pbrook | mask = (value >> 16) & ALL_CPU_MASK;
|
550 | 9ee6e8bb | pbrook | break;
|
551 | 9ee6e8bb | pbrook | case 1: |
552 | 9ee6e8bb | pbrook | mask = 1 << cpu;
|
553 | 9ee6e8bb | pbrook | break;
|
554 | 9ee6e8bb | pbrook | case 2: |
555 | 9ee6e8bb | pbrook | mask = ALL_CPU_MASK ^ (1 << cpu);
|
556 | 9ee6e8bb | pbrook | break;
|
557 | 9ee6e8bb | pbrook | default:
|
558 | 9ee6e8bb | pbrook | DPRINTF("Bad Soft Int target filter\n");
|
559 | 9ee6e8bb | pbrook | mask = ALL_CPU_MASK; |
560 | 9ee6e8bb | pbrook | break;
|
561 | 9ee6e8bb | pbrook | } |
562 | 9ee6e8bb | pbrook | GIC_SET_PENDING(irq, mask); |
563 | 9ee6e8bb | pbrook | gic_update(s); |
564 | 9ee6e8bb | pbrook | return;
|
565 | 9ee6e8bb | pbrook | } |
566 | e69954b9 | pbrook | gic_dist_writew(opaque, offset, value & 0xffff);
|
567 | e69954b9 | pbrook | gic_dist_writew(opaque, offset + 2, value >> 16); |
568 | e69954b9 | pbrook | } |
569 | e69954b9 | pbrook | |
570 | d60efc6b | Blue Swirl | static CPUReadMemoryFunc * const gic_dist_readfn[] = { |
571 | e69954b9 | pbrook | gic_dist_readb, |
572 | e69954b9 | pbrook | gic_dist_readw, |
573 | e69954b9 | pbrook | gic_dist_readl |
574 | e69954b9 | pbrook | }; |
575 | e69954b9 | pbrook | |
576 | d60efc6b | Blue Swirl | static CPUWriteMemoryFunc * const gic_dist_writefn[] = { |
577 | e69954b9 | pbrook | gic_dist_writeb, |
578 | e69954b9 | pbrook | gic_dist_writew, |
579 | e69954b9 | pbrook | gic_dist_writel |
580 | e69954b9 | pbrook | }; |
581 | e69954b9 | pbrook | |
582 | 9ee6e8bb | pbrook | #ifndef NVIC
|
583 | 9ee6e8bb | pbrook | static uint32_t gic_cpu_read(gic_state *s, int cpu, int offset) |
584 | e69954b9 | pbrook | { |
585 | e69954b9 | pbrook | switch (offset) {
|
586 | e69954b9 | pbrook | case 0x00: /* Control */ |
587 | 9ee6e8bb | pbrook | return s->cpu_enabled[cpu];
|
588 | e69954b9 | pbrook | case 0x04: /* Priority mask */ |
589 | 9ee6e8bb | pbrook | return s->priority_mask[cpu];
|
590 | e69954b9 | pbrook | case 0x08: /* Binary Point */ |
591 | e69954b9 | pbrook | /* ??? Not implemented. */
|
592 | e69954b9 | pbrook | return 0; |
593 | e69954b9 | pbrook | case 0x0c: /* Acknowledge */ |
594 | 9ee6e8bb | pbrook | return gic_acknowledge_irq(s, cpu);
|
595 | e69954b9 | pbrook | case 0x14: /* Runing Priority */ |
596 | 9ee6e8bb | pbrook | return s->running_priority[cpu];
|
597 | e69954b9 | pbrook | case 0x18: /* Highest Pending Interrupt */ |
598 | 9ee6e8bb | pbrook | return s->current_pending[cpu];
|
599 | e69954b9 | pbrook | default:
|
600 | 2ac71179 | Paul Brook | hw_error("gic_cpu_read: Bad offset %x\n", (int)offset); |
601 | e69954b9 | pbrook | return 0; |
602 | e69954b9 | pbrook | } |
603 | e69954b9 | pbrook | } |
604 | e69954b9 | pbrook | |
605 | 9ee6e8bb | pbrook | static void gic_cpu_write(gic_state *s, int cpu, int offset, uint32_t value) |
606 | e69954b9 | pbrook | { |
607 | e69954b9 | pbrook | switch (offset) {
|
608 | e69954b9 | pbrook | case 0x00: /* Control */ |
609 | 9ee6e8bb | pbrook | s->cpu_enabled[cpu] = (value & 1);
|
610 | f7c70325 | Paul Brook | DPRINTF("CPU %d %sabled\n", cpu, s->cpu_enabled ? "En" : "Dis"); |
611 | e69954b9 | pbrook | break;
|
612 | e69954b9 | pbrook | case 0x04: /* Priority mask */ |
613 | 9ee6e8bb | pbrook | s->priority_mask[cpu] = (value & 0xff);
|
614 | e69954b9 | pbrook | break;
|
615 | e69954b9 | pbrook | case 0x08: /* Binary Point */ |
616 | e69954b9 | pbrook | /* ??? Not implemented. */
|
617 | e69954b9 | pbrook | break;
|
618 | e69954b9 | pbrook | case 0x10: /* End Of Interrupt */ |
619 | 9ee6e8bb | pbrook | return gic_complete_irq(s, cpu, value & 0x3ff); |
620 | e69954b9 | pbrook | default:
|
621 | 2ac71179 | Paul Brook | hw_error("gic_cpu_write: Bad offset %x\n", (int)offset); |
622 | e69954b9 | pbrook | return;
|
623 | e69954b9 | pbrook | } |
624 | e69954b9 | pbrook | gic_update(s); |
625 | e69954b9 | pbrook | } |
626 | 9ee6e8bb | pbrook | #endif
|
627 | e69954b9 | pbrook | |
628 | e69954b9 | pbrook | static void gic_reset(gic_state *s) |
629 | e69954b9 | pbrook | { |
630 | e69954b9 | pbrook | int i;
|
631 | e69954b9 | pbrook | memset(s->irq_state, 0, GIC_NIRQ * sizeof(gic_irq_state)); |
632 | c988bfad | Paul Brook | for (i = 0 ; i < NUM_CPU(s); i++) { |
633 | 9ee6e8bb | pbrook | s->priority_mask[i] = 0xf0;
|
634 | 9ee6e8bb | pbrook | s->current_pending[i] = 1023;
|
635 | 9ee6e8bb | pbrook | s->running_irq[i] = 1023;
|
636 | 9ee6e8bb | pbrook | s->running_priority[i] = 0x100;
|
637 | 9ee6e8bb | pbrook | #ifdef NVIC
|
638 | 9ee6e8bb | pbrook | /* The NVIC doesn't have per-cpu interfaces, so enable by default. */
|
639 | 9ee6e8bb | pbrook | s->cpu_enabled[i] = 1;
|
640 | 9ee6e8bb | pbrook | #else
|
641 | 9ee6e8bb | pbrook | s->cpu_enabled[i] = 0;
|
642 | 9ee6e8bb | pbrook | #endif
|
643 | 9ee6e8bb | pbrook | } |
644 | e57ec016 | pbrook | for (i = 0; i < 16; i++) { |
645 | e69954b9 | pbrook | GIC_SET_ENABLED(i); |
646 | e69954b9 | pbrook | GIC_SET_TRIGGER(i); |
647 | e69954b9 | pbrook | } |
648 | 9ee6e8bb | pbrook | #ifdef NVIC
|
649 | 9ee6e8bb | pbrook | /* The NVIC is always enabled. */
|
650 | 9ee6e8bb | pbrook | s->enabled = 1;
|
651 | 9ee6e8bb | pbrook | #else
|
652 | e69954b9 | pbrook | s->enabled = 0;
|
653 | 9ee6e8bb | pbrook | #endif
|
654 | e69954b9 | pbrook | } |
655 | e69954b9 | pbrook | |
656 | 23e39294 | pbrook | static void gic_save(QEMUFile *f, void *opaque) |
657 | 23e39294 | pbrook | { |
658 | 23e39294 | pbrook | gic_state *s = (gic_state *)opaque; |
659 | 23e39294 | pbrook | int i;
|
660 | 23e39294 | pbrook | int j;
|
661 | 23e39294 | pbrook | |
662 | 23e39294 | pbrook | qemu_put_be32(f, s->enabled); |
663 | c988bfad | Paul Brook | for (i = 0; i < NUM_CPU(s); i++) { |
664 | 23e39294 | pbrook | qemu_put_be32(f, s->cpu_enabled[i]); |
665 | 23e39294 | pbrook | #ifndef NVIC
|
666 | 23e39294 | pbrook | qemu_put_be32(f, s->irq_target[i]); |
667 | 23e39294 | pbrook | #endif
|
668 | 23e39294 | pbrook | for (j = 0; j < 32; j++) |
669 | 23e39294 | pbrook | qemu_put_be32(f, s->priority1[j][i]); |
670 | 23e39294 | pbrook | for (j = 0; j < GIC_NIRQ; j++) |
671 | 23e39294 | pbrook | qemu_put_be32(f, s->last_active[j][i]); |
672 | 23e39294 | pbrook | qemu_put_be32(f, s->priority_mask[i]); |
673 | 23e39294 | pbrook | qemu_put_be32(f, s->running_irq[i]); |
674 | 23e39294 | pbrook | qemu_put_be32(f, s->running_priority[i]); |
675 | 23e39294 | pbrook | qemu_put_be32(f, s->current_pending[i]); |
676 | 23e39294 | pbrook | } |
677 | 23e39294 | pbrook | for (i = 0; i < GIC_NIRQ - 32; i++) { |
678 | 23e39294 | pbrook | qemu_put_be32(f, s->priority2[i]); |
679 | 23e39294 | pbrook | } |
680 | 23e39294 | pbrook | for (i = 0; i < GIC_NIRQ; i++) { |
681 | 23e39294 | pbrook | qemu_put_byte(f, s->irq_state[i].enabled); |
682 | 23e39294 | pbrook | qemu_put_byte(f, s->irq_state[i].pending); |
683 | 23e39294 | pbrook | qemu_put_byte(f, s->irq_state[i].active); |
684 | 23e39294 | pbrook | qemu_put_byte(f, s->irq_state[i].level); |
685 | 23e39294 | pbrook | qemu_put_byte(f, s->irq_state[i].model); |
686 | 23e39294 | pbrook | qemu_put_byte(f, s->irq_state[i].trigger); |
687 | 23e39294 | pbrook | } |
688 | 23e39294 | pbrook | } |
689 | 23e39294 | pbrook | |
690 | 23e39294 | pbrook | static int gic_load(QEMUFile *f, void *opaque, int version_id) |
691 | 23e39294 | pbrook | { |
692 | 23e39294 | pbrook | gic_state *s = (gic_state *)opaque; |
693 | 23e39294 | pbrook | int i;
|
694 | 23e39294 | pbrook | int j;
|
695 | 23e39294 | pbrook | |
696 | 23e39294 | pbrook | if (version_id != 1) |
697 | 23e39294 | pbrook | return -EINVAL;
|
698 | 23e39294 | pbrook | |
699 | 23e39294 | pbrook | s->enabled = qemu_get_be32(f); |
700 | c988bfad | Paul Brook | for (i = 0; i < NUM_CPU(s); i++) { |
701 | 23e39294 | pbrook | s->cpu_enabled[i] = qemu_get_be32(f); |
702 | 23e39294 | pbrook | #ifndef NVIC
|
703 | 23e39294 | pbrook | s->irq_target[i] = qemu_get_be32(f); |
704 | 23e39294 | pbrook | #endif
|
705 | 23e39294 | pbrook | for (j = 0; j < 32; j++) |
706 | 23e39294 | pbrook | s->priority1[j][i] = qemu_get_be32(f); |
707 | 23e39294 | pbrook | for (j = 0; j < GIC_NIRQ; j++) |
708 | 23e39294 | pbrook | s->last_active[j][i] = qemu_get_be32(f); |
709 | 23e39294 | pbrook | s->priority_mask[i] = qemu_get_be32(f); |
710 | 23e39294 | pbrook | s->running_irq[i] = qemu_get_be32(f); |
711 | 23e39294 | pbrook | s->running_priority[i] = qemu_get_be32(f); |
712 | 23e39294 | pbrook | s->current_pending[i] = qemu_get_be32(f); |
713 | 23e39294 | pbrook | } |
714 | 23e39294 | pbrook | for (i = 0; i < GIC_NIRQ - 32; i++) { |
715 | 23e39294 | pbrook | s->priority2[i] = qemu_get_be32(f); |
716 | 23e39294 | pbrook | } |
717 | 23e39294 | pbrook | for (i = 0; i < GIC_NIRQ; i++) { |
718 | 23e39294 | pbrook | s->irq_state[i].enabled = qemu_get_byte(f); |
719 | 23e39294 | pbrook | s->irq_state[i].pending = qemu_get_byte(f); |
720 | 23e39294 | pbrook | s->irq_state[i].active = qemu_get_byte(f); |
721 | 23e39294 | pbrook | s->irq_state[i].level = qemu_get_byte(f); |
722 | 23e39294 | pbrook | s->irq_state[i].model = qemu_get_byte(f); |
723 | 23e39294 | pbrook | s->irq_state[i].trigger = qemu_get_byte(f); |
724 | 23e39294 | pbrook | } |
725 | 23e39294 | pbrook | |
726 | 23e39294 | pbrook | return 0; |
727 | 23e39294 | pbrook | } |
728 | 23e39294 | pbrook | |
729 | c988bfad | Paul Brook | #if NCPU > 1 |
730 | c988bfad | Paul Brook | static void gic_init(gic_state *s, int num_cpu) |
731 | c988bfad | Paul Brook | #else
|
732 | fe7e8758 | Paul Brook | static void gic_init(gic_state *s) |
733 | c988bfad | Paul Brook | #endif
|
734 | e69954b9 | pbrook | { |
735 | 9ee6e8bb | pbrook | int i;
|
736 | e69954b9 | pbrook | |
737 | c988bfad | Paul Brook | #if NCPU > 1 |
738 | c988bfad | Paul Brook | s->num_cpu = num_cpu; |
739 | c988bfad | Paul Brook | #endif
|
740 | 067a3ddc | Paul Brook | qdev_init_gpio_in(&s->busdev.qdev, gic_set_irq, GIC_NIRQ - 32);
|
741 | c988bfad | Paul Brook | for (i = 0; i < NUM_CPU(s); i++) { |
742 | fe7e8758 | Paul Brook | sysbus_init_irq(&s->busdev, &s->parent_irq[i]); |
743 | e69954b9 | pbrook | } |
744 | 1eed09cb | Avi Kivity | s->iomemtype = cpu_register_io_memory(gic_dist_readfn, |
745 | fe7e8758 | Paul Brook | gic_dist_writefn, s); |
746 | e69954b9 | pbrook | gic_reset(s); |
747 | 23e39294 | pbrook | register_savevm("arm_gic", -1, 1, gic_save, gic_load, s); |
748 | e69954b9 | pbrook | } |