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1 | ab93bbe2 | bellard | /*
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2 | ab93bbe2 | bellard | * common defines for all CPUs
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3 | 5fafdf24 | ths | *
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4 | ab93bbe2 | bellard | * Copyright (c) 2003 Fabrice Bellard
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5 | ab93bbe2 | bellard | *
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6 | ab93bbe2 | bellard | * This library is free software; you can redistribute it and/or
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7 | ab93bbe2 | bellard | * modify it under the terms of the GNU Lesser General Public
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8 | ab93bbe2 | bellard | * License as published by the Free Software Foundation; either
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9 | ab93bbe2 | bellard | * version 2 of the License, or (at your option) any later version.
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10 | ab93bbe2 | bellard | *
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11 | ab93bbe2 | bellard | * This library is distributed in the hope that it will be useful,
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12 | ab93bbe2 | bellard | * but WITHOUT ANY WARRANTY; without even the implied warranty of
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13 | ab93bbe2 | bellard | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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14 | ab93bbe2 | bellard | * Lesser General Public License for more details.
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15 | ab93bbe2 | bellard | *
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16 | ab93bbe2 | bellard | * You should have received a copy of the GNU Lesser General Public
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17 | 8167ee88 | Blue Swirl | * License along with this library; if not, see <http://www.gnu.org/licenses/>.
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18 | ab93bbe2 | bellard | */
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19 | ab93bbe2 | bellard | #ifndef CPU_DEFS_H
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20 | ab93bbe2 | bellard | #define CPU_DEFS_H
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21 | ab93bbe2 | bellard | |
22 | 87ecb68b | pbrook | #ifndef NEED_CPU_H
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23 | 87ecb68b | pbrook | #error cpu.h included from common code
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24 | 87ecb68b | pbrook | #endif
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25 | 87ecb68b | pbrook | |
26 | ab93bbe2 | bellard | #include "config.h" |
27 | ab93bbe2 | bellard | #include <setjmp.h> |
28 | ed1c0bcb | bellard | #include <inttypes.h> |
29 | be214e6c | aurel32 | #include <signal.h> |
30 | ed1c0bcb | bellard | #include "osdep.h" |
31 | 72cf2d4f | Blue Swirl | #include "qemu-queue.h" |
32 | 1ad2134f | Paul Brook | #include "targphys.h" |
33 | ab93bbe2 | bellard | |
34 | 35b66fc4 | bellard | #ifndef TARGET_LONG_BITS
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35 | 35b66fc4 | bellard | #error TARGET_LONG_BITS must be defined before including this header
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36 | 35b66fc4 | bellard | #endif
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37 | 35b66fc4 | bellard | |
38 | 35b66fc4 | bellard | #define TARGET_LONG_SIZE (TARGET_LONG_BITS / 8) |
39 | 35b66fc4 | bellard | |
40 | ab6d960f | bellard | /* target_ulong is the type of a virtual address */
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41 | 35b66fc4 | bellard | #if TARGET_LONG_SIZE == 4 |
42 | 35b66fc4 | bellard | typedef int32_t target_long;
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43 | 35b66fc4 | bellard | typedef uint32_t target_ulong;
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44 | c27004ec | bellard | #define TARGET_FMT_lx "%08x" |
45 | b62b461b | j_mayer | #define TARGET_FMT_ld "%d" |
46 | 71c8b8fd | j_mayer | #define TARGET_FMT_lu "%u" |
47 | 35b66fc4 | bellard | #elif TARGET_LONG_SIZE == 8 |
48 | 35b66fc4 | bellard | typedef int64_t target_long;
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49 | 35b66fc4 | bellard | typedef uint64_t target_ulong;
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50 | 26a76461 | bellard | #define TARGET_FMT_lx "%016" PRIx64 |
51 | b62b461b | j_mayer | #define TARGET_FMT_ld "%" PRId64 |
52 | 71c8b8fd | j_mayer | #define TARGET_FMT_lu "%" PRIu64 |
53 | 35b66fc4 | bellard | #else
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54 | 35b66fc4 | bellard | #error TARGET_LONG_SIZE undefined
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55 | 35b66fc4 | bellard | #endif
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56 | 35b66fc4 | bellard | |
57 | f193c797 | bellard | #define HOST_LONG_SIZE (HOST_LONG_BITS / 8) |
58 | f193c797 | bellard | |
59 | 2be0071f | bellard | #define EXCP_INTERRUPT 0x10000 /* async interruption */ |
60 | 2be0071f | bellard | #define EXCP_HLT 0x10001 /* hlt instruction reached */ |
61 | 2be0071f | bellard | #define EXCP_DEBUG 0x10002 /* cpu stopped after a breakpoint or singlestep */ |
62 | 5a1e3cfc | bellard | #define EXCP_HALTED 0x10003 /* cpu is halted (waiting for external event) */ |
63 | ab93bbe2 | bellard | |
64 | a316d335 | bellard | #define TB_JMP_CACHE_BITS 12 |
65 | a316d335 | bellard | #define TB_JMP_CACHE_SIZE (1 << TB_JMP_CACHE_BITS) |
66 | a316d335 | bellard | |
67 | b362e5e0 | pbrook | /* Only the bottom TB_JMP_PAGE_BITS of the jump cache hash bits vary for
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68 | b362e5e0 | pbrook | addresses on the same page. The top bits are the same. This allows
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69 | b362e5e0 | pbrook | TLB invalidation to quickly clear a subset of the hash table. */
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70 | b362e5e0 | pbrook | #define TB_JMP_PAGE_BITS (TB_JMP_CACHE_BITS / 2) |
71 | b362e5e0 | pbrook | #define TB_JMP_PAGE_SIZE (1 << TB_JMP_PAGE_BITS) |
72 | b362e5e0 | pbrook | #define TB_JMP_ADDR_MASK (TB_JMP_PAGE_SIZE - 1) |
73 | b362e5e0 | pbrook | #define TB_JMP_PAGE_MASK (TB_JMP_CACHE_SIZE - TB_JMP_PAGE_SIZE)
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74 | b362e5e0 | pbrook | |
75 | 84b7b8e7 | bellard | #define CPU_TLB_BITS 8 |
76 | 84b7b8e7 | bellard | #define CPU_TLB_SIZE (1 << CPU_TLB_BITS) |
77 | ab93bbe2 | bellard | |
78 | d656469f | bellard | #if TARGET_PHYS_ADDR_BITS == 32 && TARGET_LONG_BITS == 32 |
79 | d656469f | bellard | #define CPU_TLB_ENTRY_BITS 4 |
80 | d656469f | bellard | #else
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81 | d656469f | bellard | #define CPU_TLB_ENTRY_BITS 5 |
82 | d656469f | bellard | #endif
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83 | d656469f | bellard | |
84 | ab93bbe2 | bellard | typedef struct CPUTLBEntry { |
85 | 0f459d16 | pbrook | /* bit TARGET_LONG_BITS to TARGET_PAGE_BITS : virtual address
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86 | 0f459d16 | pbrook | bit TARGET_PAGE_BITS-1..4 : Nonzero for accesses that should not
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87 | 0f459d16 | pbrook | go directly to ram.
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88 | db8d7466 | bellard | bit 3 : indicates that the entry is invalid
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89 | db8d7466 | bellard | bit 2..0 : zero
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90 | db8d7466 | bellard | */
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91 | 5fafdf24 | ths | target_ulong addr_read; |
92 | 5fafdf24 | ths | target_ulong addr_write; |
93 | 5fafdf24 | ths | target_ulong addr_code; |
94 | 0f459d16 | pbrook | /* Addend to virtual address to get physical address. IO accesses
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95 | ee50add9 | pbrook | use the corresponding iotlb value. */
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96 | d656469f | bellard | #if TARGET_PHYS_ADDR_BITS == 64 |
97 | d656469f | bellard | /* on i386 Linux make sure it is aligned */
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98 | c227f099 | Anthony Liguori | target_phys_addr_t addend __attribute__((aligned(8)));
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99 | d656469f | bellard | #else
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100 | c227f099 | Anthony Liguori | target_phys_addr_t addend; |
101 | d656469f | bellard | #endif
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102 | d656469f | bellard | /* padding to get a power of two size */
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103 | d656469f | bellard | uint8_t dummy[(1 << CPU_TLB_ENTRY_BITS) -
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104 | d656469f | bellard | (sizeof(target_ulong) * 3 + |
105 | c227f099 | Anthony Liguori | ((-sizeof(target_ulong) * 3) & (sizeof(target_phys_addr_t) - 1)) + |
106 | c227f099 | Anthony Liguori | sizeof(target_phys_addr_t))];
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107 | ab93bbe2 | bellard | } CPUTLBEntry; |
108 | ab93bbe2 | bellard | |
109 | e2542fe2 | Juan Quintela | #ifdef HOST_WORDS_BIGENDIAN
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110 | 2e70f6ef | pbrook | typedef struct icount_decr_u16 { |
111 | 2e70f6ef | pbrook | uint16_t high; |
112 | 2e70f6ef | pbrook | uint16_t low; |
113 | 2e70f6ef | pbrook | } icount_decr_u16; |
114 | 2e70f6ef | pbrook | #else
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115 | 2e70f6ef | pbrook | typedef struct icount_decr_u16 { |
116 | 2e70f6ef | pbrook | uint16_t low; |
117 | 2e70f6ef | pbrook | uint16_t high; |
118 | 2e70f6ef | pbrook | } icount_decr_u16; |
119 | 2e70f6ef | pbrook | #endif
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120 | 2e70f6ef | pbrook | |
121 | 7ba1e619 | aliguori | struct kvm_run;
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122 | 7ba1e619 | aliguori | struct KVMState;
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123 | 7ba1e619 | aliguori | |
124 | a1d1bb31 | aliguori | typedef struct CPUBreakpoint { |
125 | a1d1bb31 | aliguori | target_ulong pc; |
126 | a1d1bb31 | aliguori | int flags; /* BP_* */ |
127 | 72cf2d4f | Blue Swirl | QTAILQ_ENTRY(CPUBreakpoint) entry; |
128 | a1d1bb31 | aliguori | } CPUBreakpoint; |
129 | a1d1bb31 | aliguori | |
130 | a1d1bb31 | aliguori | typedef struct CPUWatchpoint { |
131 | a1d1bb31 | aliguori | target_ulong vaddr; |
132 | a1d1bb31 | aliguori | target_ulong len_mask; |
133 | a1d1bb31 | aliguori | int flags; /* BP_* */ |
134 | 72cf2d4f | Blue Swirl | QTAILQ_ENTRY(CPUWatchpoint) entry; |
135 | a1d1bb31 | aliguori | } CPUWatchpoint; |
136 | a1d1bb31 | aliguori | |
137 | a20e31dc | blueswir1 | #define CPU_TEMP_BUF_NLONGS 128 |
138 | a316d335 | bellard | #define CPU_COMMON \
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139 | a316d335 | bellard | struct TranslationBlock *current_tb; /* currently executing TB */ \ |
140 | a316d335 | bellard | /* soft mmu support */ \
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141 | 2e70f6ef | pbrook | /* in order to avoid passing too many arguments to the MMIO \
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142 | 2e70f6ef | pbrook | helpers, we store some rarely used information in the CPU \
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143 | a316d335 | bellard | context) */ \
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144 | 2e70f6ef | pbrook | unsigned long mem_io_pc; /* host pc at which the memory was \ |
145 | 2e70f6ef | pbrook | accessed */ \
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146 | 2e70f6ef | pbrook | target_ulong mem_io_vaddr; /* target virtual addr at which the \
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147 | 2e70f6ef | pbrook | memory was accessed */ \
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148 | 9656f324 | pbrook | uint32_t halted; /* Nonzero if the CPU is in suspend state */ \
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149 | d6dc3d42 | aliguori | uint32_t stop; /* Stop request */ \
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150 | d6dc3d42 | aliguori | uint32_t stopped; /* Artificially stopped */ \
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151 | 9656f324 | pbrook | uint32_t interrupt_request; \ |
152 | be214e6c | aurel32 | volatile sig_atomic_t exit_request; \
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153 | 623a930e | ths | /* The meaning of the MMU modes is defined in the target code. */ \
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154 | 6fa4cea9 | j_mayer | CPUTLBEntry tlb_table[NB_MMU_MODES][CPU_TLB_SIZE]; \ |
155 | c227f099 | Anthony Liguori | target_phys_addr_t iotlb[NB_MMU_MODES][CPU_TLB_SIZE]; \ |
156 | a316d335 | bellard | struct TranslationBlock *tb_jmp_cache[TB_JMP_CACHE_SIZE]; \
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157 | a20e31dc | blueswir1 | /* buffer for temporaries in the code generator */ \
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158 | a20e31dc | blueswir1 | long temp_buf[CPU_TEMP_BUF_NLONGS]; \
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159 | a316d335 | bellard | \ |
160 | 2e70f6ef | pbrook | int64_t icount_extra; /* Instructions until next timer event. */ \
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161 | 2e70f6ef | pbrook | /* Number of cycles left, with interrupt flag in high bit. \
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162 | 2e70f6ef | pbrook | This allows a single read-compare-cbranch-write sequence to test \
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163 | 2e70f6ef | pbrook | for both decrementer underflow and exceptions. */ \
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164 | 2e70f6ef | pbrook | union { \
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165 | 2e70f6ef | pbrook | uint32_t u32; \ |
166 | 2e70f6ef | pbrook | icount_decr_u16 u16; \ |
167 | 2e70f6ef | pbrook | } icount_decr; \ |
168 | 2e70f6ef | pbrook | uint32_t can_do_io; /* nonzero if memory mapped IO is safe. */ \
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169 | 2e70f6ef | pbrook | \ |
170 | a316d335 | bellard | /* from this point: preserved by CPU reset */ \
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171 | a316d335 | bellard | /* ice debug support */ \
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172 | 72cf2d4f | Blue Swirl | QTAILQ_HEAD(breakpoints_head, CPUBreakpoint) breakpoints; \ |
173 | a316d335 | bellard | int singlestep_enabled; \
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174 | a316d335 | bellard | \ |
175 | 72cf2d4f | Blue Swirl | QTAILQ_HEAD(watchpoints_head, CPUWatchpoint) watchpoints; \ |
176 | a1d1bb31 | aliguori | CPUWatchpoint *watchpoint_hit; \ |
177 | 56aebc89 | pbrook | \ |
178 | 56aebc89 | pbrook | struct GDBRegisterState *gdb_regs; \
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179 | 6658ffb8 | pbrook | \ |
180 | 9133e39b | bellard | /* Core interrupt code */ \
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181 | 9133e39b | bellard | jmp_buf jmp_env; \ |
182 | 9133e39b | bellard | int exception_index; \
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183 | 9133e39b | bellard | \ |
184 | c2764719 | pbrook | CPUState *next_cpu; /* next CPU sharing TB cache */ \
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185 | 6a00d601 | bellard | int cpu_index; /* CPU index (informative) */ \ |
186 | 1e9fa730 | Nathan Froyd | uint32_t host_tid; /* host thread ID */ \
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187 | 268a362c | aliguori | int numa_node; /* NUMA node this cpu is belonging to */ \ |
188 | dc6b1c09 | Andre Przywara | int nr_cores; /* number of cores within this CPU package */ \ |
189 | dc6b1c09 | Andre Przywara | int nr_threads;/* number of threads within this CPU */ \ |
190 | d5975363 | pbrook | int running; /* Nonzero if cpu is currently running(usermode). */ \ |
191 | a316d335 | bellard | /* user data */ \
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192 | 01ba9816 | ths | void *opaque; \
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193 | 01ba9816 | ths | \ |
194 | d6dc3d42 | aliguori | uint32_t created; \ |
195 | d6dc3d42 | aliguori | struct QemuThread *thread; \
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196 | d6dc3d42 | aliguori | struct QemuCond *halt_cond; \
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197 | 7ba1e619 | aliguori | const char *cpu_model_str; \ |
198 | 7ba1e619 | aliguori | struct KVMState *kvm_state; \
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199 | 7ba1e619 | aliguori | struct kvm_run *kvm_run; \
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200 | 7ba1e619 | aliguori | int kvm_fd;
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201 | a316d335 | bellard | |
202 | ab93bbe2 | bellard | #endif |