Revision cd629de1
| b/include/elf.h | ||
|---|---|---|
| 411 | 411 |
#define R_SPARC_5 44 |
| 412 | 412 |
#define R_SPARC_6 45 |
| 413 | 413 |
|
| 414 |
/* Bits present in AT_HWCAP for PowerPC. */ |
|
| 415 |
|
|
| 416 |
#define PPC_FEATURE_32 0x80000000 |
|
| 417 |
#define PPC_FEATURE_64 0x40000000 |
|
| 418 |
#define PPC_FEATURE_601_INSTR 0x20000000 |
|
| 419 |
#define PPC_FEATURE_HAS_ALTIVEC 0x10000000 |
|
| 420 |
#define PPC_FEATURE_HAS_FPU 0x08000000 |
|
| 421 |
#define PPC_FEATURE_HAS_MMU 0x04000000 |
|
| 422 |
#define PPC_FEATURE_HAS_4xxMAC 0x02000000 |
|
| 423 |
#define PPC_FEATURE_UNIFIED_CACHE 0x01000000 |
|
| 424 |
#define PPC_FEATURE_HAS_SPE 0x00800000 |
|
| 425 |
#define PPC_FEATURE_HAS_EFP_SINGLE 0x00400000 |
|
| 426 |
#define PPC_FEATURE_HAS_EFP_DOUBLE 0x00200000 |
|
| 427 |
#define PPC_FEATURE_NO_TB 0x00100000 |
|
| 428 |
#define PPC_FEATURE_POWER4 0x00080000 |
|
| 429 |
#define PPC_FEATURE_POWER5 0x00040000 |
|
| 430 |
#define PPC_FEATURE_POWER5_PLUS 0x00020000 |
|
| 431 |
#define PPC_FEATURE_CELL 0x00010000 |
|
| 432 |
#define PPC_FEATURE_BOOKE 0x00008000 |
|
| 433 |
#define PPC_FEATURE_SMT 0x00004000 |
|
| 434 |
#define PPC_FEATURE_ICACHE_SNOOP 0x00002000 |
|
| 435 |
#define PPC_FEATURE_ARCH_2_05 0x00001000 |
|
| 436 |
#define PPC_FEATURE_PA6T 0x00000800 |
|
| 437 |
#define PPC_FEATURE_HAS_DFP 0x00000400 |
|
| 438 |
#define PPC_FEATURE_POWER6_EXT 0x00000200 |
|
| 439 |
#define PPC_FEATURE_ARCH_2_06 0x00000100 |
|
| 440 |
#define PPC_FEATURE_HAS_VSX 0x00000080 |
|
| 441 |
|
|
| 442 |
#define PPC_FEATURE_PSERIES_PERFMON_COMPAT \ |
|
| 443 |
0x00000040 |
|
| 444 |
|
|
| 445 |
#define PPC_FEATURE_TRUE_LE 0x00000002 |
|
| 446 |
#define PPC_FEATURE_PPC_LE 0x00000001 |
|
| 447 |
|
|
| 414 | 448 |
/* Bits present in AT_HWCAP, primarily for Sparc32. */ |
| 415 | 449 |
|
| 416 | 450 |
#define HWCAP_SPARC_FLUSH 1 /* CPU supports flush instruction. */ |
| b/tcg/ppc64/tcg-target.c | ||
|---|---|---|
| 45 | 45 |
#define GUEST_BASE 0 |
| 46 | 46 |
#endif |
| 47 | 47 |
|
| 48 |
#ifdef CONFIG_GETAUXVAL |
|
| 49 |
#include <sys/auxv.h> |
|
| 48 |
#include "elf.h" |
|
| 50 | 49 |
static bool have_isa_2_06; |
| 51 | 50 |
#define HAVE_ISA_2_06 have_isa_2_06 |
| 52 | 51 |
#define HAVE_ISEL have_isa_2_06 |
| 53 |
#else |
|
| 54 |
#define HAVE_ISA_2_06 0 |
|
| 55 |
#define HAVE_ISEL 0 |
|
| 56 |
#endif |
|
| 57 | 52 |
|
| 58 | 53 |
#ifdef CONFIG_USE_GUEST_BASE |
| 59 | 54 |
#define TCG_GUEST_BASE_REG 30 |
| ... | ... | |
| 2132 | 2127 |
|
| 2133 | 2128 |
static void tcg_target_init(TCGContext *s) |
| 2134 | 2129 |
{
|
| 2135 |
#ifdef CONFIG_GETAUXVAL |
|
| 2136 |
unsigned long hwcap = getauxval(AT_HWCAP); |
|
| 2130 |
unsigned long hwcap = qemu_getauxval(AT_HWCAP); |
|
| 2137 | 2131 |
if (hwcap & PPC_FEATURE_ARCH_2_06) {
|
| 2138 | 2132 |
have_isa_2_06 = true; |
| 2139 | 2133 |
} |
| 2140 |
#endif |
|
| 2141 | 2134 |
|
| 2142 | 2135 |
tcg_regset_set32(tcg_target_available_regs[TCG_TYPE_I32], 0, 0xffffffff); |
| 2143 | 2136 |
tcg_regset_set32(tcg_target_available_regs[TCG_TYPE_I64], 0, 0xffffffff); |
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