root / hw / g364fb.c @ cd7a45c9
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/*
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* QEMU G364 framebuffer Emulator.
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*
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* Copyright (c) 2007-2011 Herve Poussineau
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License along
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* with this program; if not, see <http://www.gnu.org/licenses/>.
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*/
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#include "hw.h" |
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#include "console.h" |
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#include "pixel_ops.h" |
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#include "trace.h" |
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#include "sysbus.h" |
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|
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typedef struct G364State { |
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/* hardware */
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uint8_t *vram; |
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uint32_t vram_size; |
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qemu_irq irq; |
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MemoryRegion mem_vram; |
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MemoryRegion mem_ctrl; |
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/* registers */
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uint8_t color_palette[256][3]; |
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uint8_t cursor_palette[3][3]; |
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uint16_t cursor[512];
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uint32_t cursor_position; |
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uint32_t ctla; |
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uint32_t top_of_screen; |
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uint32_t width, height; /* in pixels */
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/* display refresh support */
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DisplayState *ds; |
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int depth;
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int blanked;
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} G364State; |
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|
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#define REG_BOOT 0x000000 |
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#define REG_DISPLAY 0x000118 |
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#define REG_VDISPLAY 0x000150 |
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#define REG_CTLA 0x000300 |
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#define REG_TOP 0x000400 |
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#define REG_CURS_PAL 0x000508 |
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#define REG_CURS_POS 0x000638 |
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#define REG_CLR_PAL 0x000800 |
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#define REG_CURS_PAT 0x001000 |
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#define REG_RESET 0x100000 |
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|
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#define CTLA_FORCE_BLANK 0x00000400 |
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#define CTLA_NO_CURSOR 0x00800000 |
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|
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#define G364_PAGE_SIZE 4096 |
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|
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static inline int check_dirty(G364State *s, ram_addr_t page) |
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{
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return memory_region_get_dirty(&s->mem_vram, page, G364_PAGE_SIZE,
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DIRTY_MEMORY_VGA); |
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} |
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|
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static inline void reset_dirty(G364State *s, |
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ram_addr_t page_min, ram_addr_t page_max) |
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{
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memory_region_reset_dirty(&s->mem_vram, |
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page_min, |
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page_max + G364_PAGE_SIZE - page_min - 1,
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DIRTY_MEMORY_VGA); |
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} |
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static void g364fb_draw_graphic8(G364State *s) |
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{
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int i, w;
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uint8_t *vram; |
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uint8_t *data_display, *dd; |
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ram_addr_t page, page_min, page_max; |
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int x, y;
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int xmin, xmax;
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int ymin, ymax;
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int xcursor, ycursor;
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unsigned int (*rgb_to_pixel)(unsigned int r, unsigned int g, unsigned int b); |
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switch (ds_get_bits_per_pixel(s->ds)) {
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case 8: |
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rgb_to_pixel = rgb_to_pixel8; |
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w = 1;
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break;
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case 15: |
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rgb_to_pixel = rgb_to_pixel15; |
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w = 2;
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break;
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case 16: |
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rgb_to_pixel = rgb_to_pixel16; |
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w = 2;
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break;
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case 32: |
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rgb_to_pixel = rgb_to_pixel32; |
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w = 4;
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break;
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default:
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hw_error("g364: unknown host depth %d",
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ds_get_bits_per_pixel(s->ds)); |
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return;
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} |
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page = 0;
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page_min = (ram_addr_t)-1;
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page_max = 0;
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x = y = 0;
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xmin = s->width; |
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xmax = 0;
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ymin = s->height; |
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ymax = 0;
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if (!(s->ctla & CTLA_NO_CURSOR)) {
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xcursor = s->cursor_position >> 12;
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ycursor = s->cursor_position & 0xfff;
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} else {
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xcursor = ycursor = -65;
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} |
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vram = s->vram + s->top_of_screen; |
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/* XXX: out of range in vram? */
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data_display = dd = ds_get_data(s->ds); |
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while (y < s->height) {
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if (check_dirty(s, page)) {
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if (y < ymin)
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ymin = ymax = y; |
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if (page_min == (ram_addr_t)-1) |
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page_min = page; |
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page_max = page; |
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if (x < xmin)
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xmin = x; |
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for (i = 0; i < G364_PAGE_SIZE; i++) { |
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uint8_t index; |
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unsigned int color; |
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if (unlikely((y >= ycursor && y < ycursor + 64) && |
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(x >= xcursor && x < xcursor + 64))) {
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/* pointer area */
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int xdiff = x - xcursor;
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uint16_t curs = s->cursor[(y - ycursor) * 8 + xdiff / 8]; |
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int op = (curs >> ((xdiff & 7) * 2)) & 3; |
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if (likely(op == 0)) { |
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/* transparent */
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index = *vram; |
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color = (*rgb_to_pixel)( |
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s->color_palette[index][0],
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s->color_palette[index][1],
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s->color_palette[index][2]);
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} else {
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/* get cursor color */
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index = op - 1;
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color = (*rgb_to_pixel)( |
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s->cursor_palette[index][0],
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s->cursor_palette[index][1],
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s->cursor_palette[index][2]);
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} |
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} else {
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/* normal area */
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index = *vram; |
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color = (*rgb_to_pixel)( |
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s->color_palette[index][0],
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s->color_palette[index][1],
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s->color_palette[index][2]);
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} |
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memcpy(dd, &color, w); |
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dd += w; |
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x++; |
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vram++; |
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if (x == s->width) {
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xmax = s->width - 1;
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y++; |
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if (y == s->height) {
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ymax = s->height - 1;
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goto done;
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} |
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data_display = dd = data_display + ds_get_linesize(s->ds); |
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xmin = 0;
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x = 0;
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} |
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} |
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if (x > xmax)
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xmax = x; |
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if (y > ymax)
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ymax = y; |
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} else {
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int dy;
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if (page_min != (ram_addr_t)-1) { |
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reset_dirty(s, page_min, page_max); |
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page_min = (ram_addr_t)-1;
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page_max = 0;
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dpy_update(s->ds, xmin, ymin, xmax - xmin + 1, ymax - ymin + 1); |
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xmin = s->width; |
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xmax = 0;
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ymin = s->height; |
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ymax = 0;
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} |
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x += G364_PAGE_SIZE; |
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dy = x / s->width; |
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x = x % s->width; |
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y += dy; |
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vram += G364_PAGE_SIZE; |
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data_display += dy * ds_get_linesize(s->ds); |
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dd = data_display + x * w; |
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} |
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page += G364_PAGE_SIZE; |
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} |
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done:
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if (page_min != (ram_addr_t)-1) { |
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dpy_update(s->ds, xmin, ymin, xmax - xmin + 1, ymax - ymin + 1); |
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reset_dirty(s, page_min, page_max); |
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} |
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} |
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static void g364fb_draw_blank(G364State *s) |
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{
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int i, w;
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uint8_t *d; |
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if (s->blanked) {
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/* Screen is already blank. No need to redraw it */
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return;
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} |
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w = s->width * ((ds_get_bits_per_pixel(s->ds) + 7) >> 3); |
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d = ds_get_data(s->ds); |
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for (i = 0; i < s->height; i++) { |
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memset(d, 0, w);
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d += ds_get_linesize(s->ds); |
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} |
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dpy_update(s->ds, 0, 0, s->width, s->height); |
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s->blanked = 1;
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} |
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|
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static void g364fb_update_display(void *opaque) |
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{
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G364State *s = opaque; |
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qemu_flush_coalesced_mmio_buffer(); |
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if (s->width == 0 || s->height == 0) |
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return;
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if (s->width != ds_get_width(s->ds) || s->height != ds_get_height(s->ds)) {
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qemu_console_resize(s->ds, s->width, s->height); |
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} |
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|
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if (s->ctla & CTLA_FORCE_BLANK) {
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g364fb_draw_blank(s); |
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} else if (s->depth == 8) { |
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g364fb_draw_graphic8(s); |
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} else {
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error_report("g364: unknown guest depth %d", s->depth);
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} |
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qemu_irq_raise(s->irq); |
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} |
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|
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static inline void g364fb_invalidate_display(void *opaque) |
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{
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G364State *s = opaque; |
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|
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s->blanked = 0;
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memory_region_set_dirty(&s->mem_vram, 0, s->vram_size);
|
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} |
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|
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static void g364fb_reset(G364State *s) |
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{
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qemu_irq_lower(s->irq); |
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|
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memset(s->color_palette, 0, sizeof(s->color_palette)); |
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memset(s->cursor_palette, 0, sizeof(s->cursor_palette)); |
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memset(s->cursor, 0, sizeof(s->cursor)); |
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s->cursor_position = 0;
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s->ctla = 0;
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s->top_of_screen = 0;
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s->width = s->height = 0;
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memset(s->vram, 0, s->vram_size);
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g364fb_invalidate_display(s); |
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} |
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|
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static void g364fb_screen_dump(void *opaque, const char *filename) |
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{
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G364State *s = opaque; |
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int y, x;
|
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uint8_t index; |
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uint8_t *data_buffer; |
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FILE *f; |
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|
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qemu_flush_coalesced_mmio_buffer(); |
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|
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if (s->depth != 8) { |
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error_report("g364: unknown guest depth %d", s->depth);
|
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return;
|
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} |
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|
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f = fopen(filename, "wb");
|
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if (!f)
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return;
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|
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if (s->ctla & CTLA_FORCE_BLANK) {
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/* blank screen */
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fprintf(f, "P4\n%d %d\n",
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s->width, s->height); |
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for (y = 0; y < s->height; y++) |
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for (x = 0; x < s->width; x++) |
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fputc(0, f);
|
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} else {
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data_buffer = s->vram + s->top_of_screen; |
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fprintf(f, "P6\n%d %d\n%d\n",
|
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s->width, s->height, 255);
|
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for (y = 0; y < s->height; y++) |
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for (x = 0; x < s->width; x++, data_buffer++) { |
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index = *data_buffer; |
| 325 |
fputc(s->color_palette[index][0], f);
|
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fputc(s->color_palette[index][1], f);
|
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fputc(s->color_palette[index][2], f);
|
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} |
| 329 |
} |
| 330 |
|
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fclose(f); |
| 332 |
} |
| 333 |
|
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/* called for accesses to io ports */
|
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static uint64_t g364fb_ctrl_read(void *opaque, |
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target_phys_addr_t addr, |
| 337 |
unsigned int size) |
| 338 |
{
|
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G364State *s = opaque; |
| 340 |
uint32_t val; |
| 341 |
|
| 342 |
if (addr >= REG_CURS_PAT && addr < REG_CURS_PAT + 0x1000) { |
| 343 |
/* cursor pattern */
|
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int idx = (addr - REG_CURS_PAT) >> 3; |
| 345 |
val = s->cursor[idx]; |
| 346 |
} else if (addr >= REG_CURS_PAL && addr < REG_CURS_PAL + 0x18) { |
| 347 |
/* cursor palette */
|
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int idx = (addr - REG_CURS_PAL) >> 3; |
| 349 |
val = ((uint32_t)s->cursor_palette[idx][0] << 16); |
| 350 |
val |= ((uint32_t)s->cursor_palette[idx][1] << 8); |
| 351 |
val |= ((uint32_t)s->cursor_palette[idx][2] << 0); |
| 352 |
} else {
|
| 353 |
switch (addr) {
|
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case REG_DISPLAY:
|
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val = s->width / 4;
|
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break;
|
| 357 |
case REG_VDISPLAY:
|
| 358 |
val = s->height * 2;
|
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break;
|
| 360 |
case REG_CTLA:
|
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val = s->ctla; |
| 362 |
break;
|
| 363 |
default:
|
| 364 |
{
|
| 365 |
error_report("g364: invalid read at [" TARGET_FMT_plx "]", |
| 366 |
addr); |
| 367 |
val = 0;
|
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break;
|
| 369 |
} |
| 370 |
} |
| 371 |
} |
| 372 |
|
| 373 |
trace_g364fb_read(addr, val); |
| 374 |
|
| 375 |
return val;
|
| 376 |
} |
| 377 |
|
| 378 |
static void g364fb_update_depth(G364State *s) |
| 379 |
{
|
| 380 |
static const int depths[8] = { 1, 2, 4, 8, 15, 16, 0 }; |
| 381 |
s->depth = depths[(s->ctla & 0x00700000) >> 20]; |
| 382 |
} |
| 383 |
|
| 384 |
static void g364_invalidate_cursor_position(G364State *s) |
| 385 |
{
|
| 386 |
int ymin, ymax, start, end;
|
| 387 |
|
| 388 |
/* invalidate only near the cursor */
|
| 389 |
ymin = s->cursor_position & 0xfff;
|
| 390 |
ymax = MIN(s->height, ymin + 64);
|
| 391 |
start = ymin * ds_get_linesize(s->ds); |
| 392 |
end = (ymax + 1) * ds_get_linesize(s->ds);
|
| 393 |
|
| 394 |
memory_region_set_dirty(&s->mem_vram, start, end - start); |
| 395 |
} |
| 396 |
|
| 397 |
static void g364fb_ctrl_write(void *opaque, |
| 398 |
target_phys_addr_t addr, |
| 399 |
uint64_t val, |
| 400 |
unsigned int size) |
| 401 |
{
|
| 402 |
G364State *s = opaque; |
| 403 |
|
| 404 |
trace_g364fb_write(addr, val); |
| 405 |
|
| 406 |
if (addr >= REG_CLR_PAL && addr < REG_CLR_PAL + 0x800) { |
| 407 |
/* color palette */
|
| 408 |
int idx = (addr - REG_CLR_PAL) >> 3; |
| 409 |
s->color_palette[idx][0] = (val >> 16) & 0xff; |
| 410 |
s->color_palette[idx][1] = (val >> 8) & 0xff; |
| 411 |
s->color_palette[idx][2] = val & 0xff; |
| 412 |
g364fb_invalidate_display(s); |
| 413 |
} else if (addr >= REG_CURS_PAT && addr < REG_CURS_PAT + 0x1000) { |
| 414 |
/* cursor pattern */
|
| 415 |
int idx = (addr - REG_CURS_PAT) >> 3; |
| 416 |
s->cursor[idx] = val; |
| 417 |
g364fb_invalidate_display(s); |
| 418 |
} else if (addr >= REG_CURS_PAL && addr < REG_CURS_PAL + 0x18) { |
| 419 |
/* cursor palette */
|
| 420 |
int idx = (addr - REG_CURS_PAL) >> 3; |
| 421 |
s->cursor_palette[idx][0] = (val >> 16) & 0xff; |
| 422 |
s->cursor_palette[idx][1] = (val >> 8) & 0xff; |
| 423 |
s->cursor_palette[idx][2] = val & 0xff; |
| 424 |
g364fb_invalidate_display(s); |
| 425 |
} else {
|
| 426 |
switch (addr) {
|
| 427 |
case REG_BOOT: /* Boot timing */ |
| 428 |
case 0x00108: /* Line timing: half sync */ |
| 429 |
case 0x00110: /* Line timing: back porch */ |
| 430 |
case 0x00120: /* Line timing: short display */ |
| 431 |
case 0x00128: /* Frame timing: broad pulse */ |
| 432 |
case 0x00130: /* Frame timing: v sync */ |
| 433 |
case 0x00138: /* Frame timing: v preequalise */ |
| 434 |
case 0x00140: /* Frame timing: v postequalise */ |
| 435 |
case 0x00148: /* Frame timing: v blank */ |
| 436 |
case 0x00158: /* Line timing: line time */ |
| 437 |
case 0x00160: /* Frame store: line start */ |
| 438 |
case 0x00168: /* vram cycle: mem init */ |
| 439 |
case 0x00170: /* vram cycle: transfer delay */ |
| 440 |
case 0x00200: /* vram cycle: mask register */ |
| 441 |
/* ignore */
|
| 442 |
break;
|
| 443 |
case REG_TOP:
|
| 444 |
s->top_of_screen = val; |
| 445 |
g364fb_invalidate_display(s); |
| 446 |
break;
|
| 447 |
case REG_DISPLAY:
|
| 448 |
s->width = val * 4;
|
| 449 |
break;
|
| 450 |
case REG_VDISPLAY:
|
| 451 |
s->height = val / 2;
|
| 452 |
break;
|
| 453 |
case REG_CTLA:
|
| 454 |
s->ctla = val; |
| 455 |
g364fb_update_depth(s); |
| 456 |
g364fb_invalidate_display(s); |
| 457 |
break;
|
| 458 |
case REG_CURS_POS:
|
| 459 |
g364_invalidate_cursor_position(s); |
| 460 |
s->cursor_position = val; |
| 461 |
g364_invalidate_cursor_position(s); |
| 462 |
break;
|
| 463 |
case REG_RESET:
|
| 464 |
g364fb_reset(s); |
| 465 |
break;
|
| 466 |
default:
|
| 467 |
error_report("g364: invalid write of 0x%" PRIx64
|
| 468 |
" at [" TARGET_FMT_plx "]", val, addr); |
| 469 |
break;
|
| 470 |
} |
| 471 |
} |
| 472 |
qemu_irq_lower(s->irq); |
| 473 |
} |
| 474 |
|
| 475 |
static const MemoryRegionOps g364fb_ctrl_ops = { |
| 476 |
.read = g364fb_ctrl_read, |
| 477 |
.write = g364fb_ctrl_write, |
| 478 |
.endianness = DEVICE_LITTLE_ENDIAN, |
| 479 |
.impl.min_access_size = 4,
|
| 480 |
.impl.max_access_size = 4,
|
| 481 |
}; |
| 482 |
|
| 483 |
static int g364fb_post_load(void *opaque, int version_id) |
| 484 |
{
|
| 485 |
G364State *s = opaque; |
| 486 |
|
| 487 |
/* force refresh */
|
| 488 |
g364fb_update_depth(s); |
| 489 |
g364fb_invalidate_display(s); |
| 490 |
|
| 491 |
return 0; |
| 492 |
} |
| 493 |
|
| 494 |
static const VMStateDescription vmstate_g364fb = { |
| 495 |
.name = "g364fb",
|
| 496 |
.version_id = 1,
|
| 497 |
.minimum_version_id = 1,
|
| 498 |
.minimum_version_id_old = 1,
|
| 499 |
.post_load = g364fb_post_load, |
| 500 |
.fields = (VMStateField[]) {
|
| 501 |
VMSTATE_VBUFFER_UINT32(vram, G364State, 1, NULL, 0, vram_size), |
| 502 |
VMSTATE_BUFFER_UNSAFE(color_palette, G364State, 0, 256 * 3), |
| 503 |
VMSTATE_BUFFER_UNSAFE(cursor_palette, G364State, 0, 9), |
| 504 |
VMSTATE_UINT16_ARRAY(cursor, G364State, 512),
|
| 505 |
VMSTATE_UINT32(cursor_position, G364State), |
| 506 |
VMSTATE_UINT32(ctla, G364State), |
| 507 |
VMSTATE_UINT32(top_of_screen, G364State), |
| 508 |
VMSTATE_UINT32(width, G364State), |
| 509 |
VMSTATE_UINT32(height, G364State), |
| 510 |
VMSTATE_END_OF_LIST() |
| 511 |
} |
| 512 |
}; |
| 513 |
|
| 514 |
static void g364fb_init(DeviceState *dev, G364State *s) |
| 515 |
{
|
| 516 |
s->vram = g_malloc0(s->vram_size); |
| 517 |
|
| 518 |
s->ds = graphic_console_init(g364fb_update_display, |
| 519 |
g364fb_invalidate_display, |
| 520 |
g364fb_screen_dump, NULL, s);
|
| 521 |
|
| 522 |
memory_region_init_io(&s->mem_ctrl, &g364fb_ctrl_ops, s, "ctrl", 0x180000); |
| 523 |
memory_region_init_ram_ptr(&s->mem_vram, "vram",
|
| 524 |
s->vram_size, s->vram); |
| 525 |
vmstate_register_ram(&s->mem_vram, dev); |
| 526 |
memory_region_set_coalescing(&s->mem_vram); |
| 527 |
} |
| 528 |
|
| 529 |
typedef struct { |
| 530 |
SysBusDevice busdev; |
| 531 |
G364State g364; |
| 532 |
} G364SysBusState; |
| 533 |
|
| 534 |
static int g364fb_sysbus_init(SysBusDevice *dev) |
| 535 |
{
|
| 536 |
G364State *s = &FROM_SYSBUS(G364SysBusState, dev)->g364; |
| 537 |
|
| 538 |
g364fb_init(&dev->qdev, s); |
| 539 |
sysbus_init_irq(dev, &s->irq); |
| 540 |
sysbus_init_mmio(dev, &s->mem_ctrl); |
| 541 |
sysbus_init_mmio(dev, &s->mem_vram); |
| 542 |
|
| 543 |
return 0; |
| 544 |
} |
| 545 |
|
| 546 |
static void g364fb_sysbus_reset(DeviceState *d) |
| 547 |
{
|
| 548 |
G364SysBusState *s = DO_UPCAST(G364SysBusState, busdev.qdev, d); |
| 549 |
g364fb_reset(&s->g364); |
| 550 |
} |
| 551 |
|
| 552 |
static Property g364fb_sysbus_properties[] = {
|
| 553 |
DEFINE_PROP_HEX32("vram_size", G364SysBusState, g364.vram_size,
|
| 554 |
8 * 1024 * 1024), |
| 555 |
DEFINE_PROP_END_OF_LIST(), |
| 556 |
}; |
| 557 |
|
| 558 |
static void g364fb_sysbus_class_init(ObjectClass *klass, void *data) |
| 559 |
{
|
| 560 |
DeviceClass *dc = DEVICE_CLASS(klass); |
| 561 |
SysBusDeviceClass *k = SYS_BUS_DEVICE_CLASS(klass); |
| 562 |
|
| 563 |
k->init = g364fb_sysbus_init; |
| 564 |
dc->desc = "G364 framebuffer";
|
| 565 |
dc->reset = g364fb_sysbus_reset; |
| 566 |
dc->vmsd = &vmstate_g364fb; |
| 567 |
dc->props = g364fb_sysbus_properties; |
| 568 |
} |
| 569 |
|
| 570 |
static TypeInfo g364fb_sysbus_info = {
|
| 571 |
.name = "sysbus-g364",
|
| 572 |
.parent = TYPE_SYS_BUS_DEVICE, |
| 573 |
.instance_size = sizeof(G364SysBusState),
|
| 574 |
.class_init = g364fb_sysbus_class_init, |
| 575 |
}; |
| 576 |
|
| 577 |
static void g364fb_register(void) |
| 578 |
{
|
| 579 |
type_register_static(&g364fb_sysbus_info); |
| 580 |
} |
| 581 |
|
| 582 |
device_init(g364fb_register); |