root / hw / milkymist-minimac2.c @ cde844fa
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1 | 07424544 | Michael Walle | /*
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2 | 57aa265d | Michael Walle | * QEMU model of the Milkymist minimac2 block.
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3 | 07424544 | Michael Walle | *
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4 | 57aa265d | Michael Walle | * Copyright (c) 2011 Michael Walle <michael@walle.cc>
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5 | 07424544 | Michael Walle | *
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6 | 07424544 | Michael Walle | * This library is free software; you can redistribute it and/or
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7 | 07424544 | Michael Walle | * modify it under the terms of the GNU Lesser General Public
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8 | 07424544 | Michael Walle | * License as published by the Free Software Foundation; either
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9 | 07424544 | Michael Walle | * version 2 of the License, or (at your option) any later version.
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10 | 07424544 | Michael Walle | *
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11 | 07424544 | Michael Walle | * This library is distributed in the hope that it will be useful,
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12 | 07424544 | Michael Walle | * but WITHOUT ANY WARRANTY; without even the implied warranty of
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13 | 07424544 | Michael Walle | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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14 | 07424544 | Michael Walle | * Lesser General Public License for more details.
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15 | 07424544 | Michael Walle | *
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16 | 07424544 | Michael Walle | * You should have received a copy of the GNU Lesser General Public
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17 | 07424544 | Michael Walle | * License along with this library; if not, see <http://www.gnu.org/licenses/>.
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18 | 07424544 | Michael Walle | *
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19 | 07424544 | Michael Walle | *
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20 | 07424544 | Michael Walle | * Specification available at:
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21 | 57aa265d | Michael Walle | * not available yet
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22 | 07424544 | Michael Walle | *
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23 | 07424544 | Michael Walle | */
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24 | 07424544 | Michael Walle | |
25 | 07424544 | Michael Walle | #include "hw.h" |
26 | 07424544 | Michael Walle | #include "sysbus.h" |
27 | 07424544 | Michael Walle | #include "trace.h" |
28 | 07424544 | Michael Walle | #include "net.h" |
29 | 07424544 | Michael Walle | #include "qemu-error.h" |
30 | 57aa265d | Michael Walle | #include "qdev-addr.h" |
31 | 07424544 | Michael Walle | |
32 | 07424544 | Michael Walle | #include <zlib.h> |
33 | 07424544 | Michael Walle | |
34 | 07424544 | Michael Walle | enum {
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35 | 07424544 | Michael Walle | R_SETUP = 0,
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36 | 07424544 | Michael Walle | R_MDIO, |
37 | 07424544 | Michael Walle | R_STATE0, |
38 | 07424544 | Michael Walle | R_COUNT0, |
39 | 07424544 | Michael Walle | R_STATE1, |
40 | 07424544 | Michael Walle | R_COUNT1, |
41 | 07424544 | Michael Walle | R_TXCOUNT, |
42 | 07424544 | Michael Walle | R_MAX |
43 | 07424544 | Michael Walle | }; |
44 | 07424544 | Michael Walle | |
45 | 07424544 | Michael Walle | enum {
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46 | 57aa265d | Michael Walle | SETUP_PHY_RST = (1<<0), |
47 | 07424544 | Michael Walle | }; |
48 | 07424544 | Michael Walle | |
49 | 07424544 | Michael Walle | enum {
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50 | 07424544 | Michael Walle | MDIO_DO = (1<<0), |
51 | 07424544 | Michael Walle | MDIO_DI = (1<<1), |
52 | 07424544 | Michael Walle | MDIO_OE = (1<<2), |
53 | 07424544 | Michael Walle | MDIO_CLK = (1<<3), |
54 | 07424544 | Michael Walle | }; |
55 | 07424544 | Michael Walle | |
56 | 07424544 | Michael Walle | enum {
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57 | 07424544 | Michael Walle | STATE_EMPTY = 0,
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58 | 07424544 | Michael Walle | STATE_LOADED = 1,
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59 | 07424544 | Michael Walle | STATE_PENDING = 2,
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60 | 07424544 | Michael Walle | }; |
61 | 07424544 | Michael Walle | |
62 | 07424544 | Michael Walle | enum {
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63 | 07424544 | Michael Walle | MDIO_OP_WRITE = 1,
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64 | 07424544 | Michael Walle | MDIO_OP_READ = 2,
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65 | 07424544 | Michael Walle | }; |
66 | 07424544 | Michael Walle | |
67 | 07424544 | Michael Walle | enum mdio_state {
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68 | 07424544 | Michael Walle | MDIO_STATE_IDLE, |
69 | 07424544 | Michael Walle | MDIO_STATE_READING, |
70 | 07424544 | Michael Walle | MDIO_STATE_WRITING, |
71 | 07424544 | Michael Walle | }; |
72 | 07424544 | Michael Walle | |
73 | 07424544 | Michael Walle | enum {
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74 | 07424544 | Michael Walle | R_PHY_ID1 = 2,
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75 | 07424544 | Michael Walle | R_PHY_ID2 = 3,
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76 | 07424544 | Michael Walle | R_PHY_MAX = 32
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77 | 07424544 | Michael Walle | }; |
78 | 07424544 | Michael Walle | |
79 | 57aa265d | Michael Walle | #define MINIMAC2_MTU 1530 |
80 | 57aa265d | Michael Walle | #define MINIMAC2_BUFFER_SIZE 2048 |
81 | 07424544 | Michael Walle | |
82 | 57aa265d | Michael Walle | struct MilkymistMinimac2MdioState {
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83 | 07424544 | Michael Walle | int last_clk;
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84 | 07424544 | Michael Walle | int count;
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85 | 07424544 | Michael Walle | uint32_t data; |
86 | 07424544 | Michael Walle | uint16_t data_out; |
87 | 07424544 | Michael Walle | int state;
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88 | 07424544 | Michael Walle | |
89 | 07424544 | Michael Walle | uint8_t phy_addr; |
90 | 07424544 | Michael Walle | uint8_t reg_addr; |
91 | 07424544 | Michael Walle | }; |
92 | 57aa265d | Michael Walle | typedef struct MilkymistMinimac2MdioState MilkymistMinimac2MdioState; |
93 | 07424544 | Michael Walle | |
94 | 57aa265d | Michael Walle | struct MilkymistMinimac2State {
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95 | 07424544 | Michael Walle | SysBusDevice busdev; |
96 | 07424544 | Michael Walle | NICState *nic; |
97 | 07424544 | Michael Walle | NICConf conf; |
98 | 07424544 | Michael Walle | char *phy_model;
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99 | 57aa265d | Michael Walle | target_phys_addr_t buffers_base; |
100 | 8a53d56f | Avi Kivity | MemoryRegion buffers; |
101 | 8a53d56f | Avi Kivity | MemoryRegion regs_region; |
102 | 07424544 | Michael Walle | |
103 | 07424544 | Michael Walle | qemu_irq rx_irq; |
104 | 07424544 | Michael Walle | qemu_irq tx_irq; |
105 | 07424544 | Michael Walle | |
106 | 07424544 | Michael Walle | uint32_t regs[R_MAX]; |
107 | 07424544 | Michael Walle | |
108 | 57aa265d | Michael Walle | MilkymistMinimac2MdioState mdio; |
109 | 07424544 | Michael Walle | |
110 | 07424544 | Michael Walle | uint16_t phy_regs[R_PHY_MAX]; |
111 | 57aa265d | Michael Walle | |
112 | 57aa265d | Michael Walle | uint8_t *rx0_buf; |
113 | 57aa265d | Michael Walle | uint8_t *rx1_buf; |
114 | 57aa265d | Michael Walle | uint8_t *tx_buf; |
115 | 07424544 | Michael Walle | }; |
116 | 57aa265d | Michael Walle | typedef struct MilkymistMinimac2State MilkymistMinimac2State; |
117 | 07424544 | Michael Walle | |
118 | 07424544 | Michael Walle | static const uint8_t preamble_sfd[] = { |
119 | 07424544 | Michael Walle | 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0xd5 |
120 | 07424544 | Michael Walle | }; |
121 | 07424544 | Michael Walle | |
122 | 57aa265d | Michael Walle | static void minimac2_mdio_write_reg(MilkymistMinimac2State *s, |
123 | 07424544 | Michael Walle | uint8_t phy_addr, uint8_t reg_addr, uint16_t value) |
124 | 07424544 | Michael Walle | { |
125 | 57aa265d | Michael Walle | trace_milkymist_minimac2_mdio_write(phy_addr, reg_addr, value); |
126 | 07424544 | Michael Walle | |
127 | 07424544 | Michael Walle | /* nop */
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128 | 07424544 | Michael Walle | } |
129 | 07424544 | Michael Walle | |
130 | 57aa265d | Michael Walle | static uint16_t minimac2_mdio_read_reg(MilkymistMinimac2State *s,
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131 | 07424544 | Michael Walle | uint8_t phy_addr, uint8_t reg_addr) |
132 | 07424544 | Michael Walle | { |
133 | 07424544 | Michael Walle | uint16_t r = s->phy_regs[reg_addr]; |
134 | 07424544 | Michael Walle | |
135 | 57aa265d | Michael Walle | trace_milkymist_minimac2_mdio_read(phy_addr, reg_addr, r); |
136 | 07424544 | Michael Walle | |
137 | 07424544 | Michael Walle | return r;
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138 | 07424544 | Michael Walle | } |
139 | 07424544 | Michael Walle | |
140 | 57aa265d | Michael Walle | static void minimac2_update_mdio(MilkymistMinimac2State *s) |
141 | 07424544 | Michael Walle | { |
142 | 57aa265d | Michael Walle | MilkymistMinimac2MdioState *m = &s->mdio; |
143 | 07424544 | Michael Walle | |
144 | 07424544 | Michael Walle | /* detect rising clk edge */
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145 | 07424544 | Michael Walle | if (m->last_clk == 0 && (s->regs[R_MDIO] & MDIO_CLK)) { |
146 | 07424544 | Michael Walle | /* shift data in */
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147 | 07424544 | Michael Walle | int bit = ((s->regs[R_MDIO] & MDIO_DO)
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148 | 07424544 | Michael Walle | && (s->regs[R_MDIO] & MDIO_OE)) ? 1 : 0; |
149 | 07424544 | Michael Walle | m->data = (m->data << 1) | bit;
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150 | 07424544 | Michael Walle | |
151 | 07424544 | Michael Walle | /* check for sync */
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152 | 07424544 | Michael Walle | if (m->data == 0xffffffff) { |
153 | 07424544 | Michael Walle | m->count = 32;
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154 | 07424544 | Michael Walle | } |
155 | 07424544 | Michael Walle | |
156 | 07424544 | Michael Walle | if (m->count == 16) { |
157 | 07424544 | Michael Walle | uint8_t start = (m->data >> 14) & 0x3; |
158 | 07424544 | Michael Walle | uint8_t op = (m->data >> 12) & 0x3; |
159 | 07424544 | Michael Walle | uint8_t ta = (m->data) & 0x3;
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160 | 07424544 | Michael Walle | |
161 | 07424544 | Michael Walle | if (start == 1 && op == MDIO_OP_WRITE && ta == 2) { |
162 | 07424544 | Michael Walle | m->state = MDIO_STATE_WRITING; |
163 | 07424544 | Michael Walle | } else if (start == 1 && op == MDIO_OP_READ && (ta & 1) == 0) { |
164 | 07424544 | Michael Walle | m->state = MDIO_STATE_READING; |
165 | 07424544 | Michael Walle | } else {
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166 | 07424544 | Michael Walle | m->state = MDIO_STATE_IDLE; |
167 | 07424544 | Michael Walle | } |
168 | 07424544 | Michael Walle | |
169 | 07424544 | Michael Walle | if (m->state != MDIO_STATE_IDLE) {
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170 | 07424544 | Michael Walle | m->phy_addr = (m->data >> 7) & 0x1f; |
171 | 07424544 | Michael Walle | m->reg_addr = (m->data >> 2) & 0x1f; |
172 | 07424544 | Michael Walle | } |
173 | 07424544 | Michael Walle | |
174 | 07424544 | Michael Walle | if (m->state == MDIO_STATE_READING) {
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175 | 57aa265d | Michael Walle | m->data_out = minimac2_mdio_read_reg(s, m->phy_addr, |
176 | 07424544 | Michael Walle | m->reg_addr); |
177 | 07424544 | Michael Walle | } |
178 | 07424544 | Michael Walle | } |
179 | 07424544 | Michael Walle | |
180 | 07424544 | Michael Walle | if (m->count < 16 && m->state == MDIO_STATE_READING) { |
181 | 07424544 | Michael Walle | int bit = (m->data_out & 0x8000) ? 1 : 0; |
182 | 07424544 | Michael Walle | m->data_out <<= 1;
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183 | 07424544 | Michael Walle | |
184 | 07424544 | Michael Walle | if (bit) {
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185 | 07424544 | Michael Walle | s->regs[R_MDIO] |= MDIO_DI; |
186 | 07424544 | Michael Walle | } else {
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187 | 07424544 | Michael Walle | s->regs[R_MDIO] &= ~MDIO_DI; |
188 | 07424544 | Michael Walle | } |
189 | 07424544 | Michael Walle | } |
190 | 07424544 | Michael Walle | |
191 | 07424544 | Michael Walle | if (m->count == 0 && m->state) { |
192 | 07424544 | Michael Walle | if (m->state == MDIO_STATE_WRITING) {
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193 | 07424544 | Michael Walle | uint16_t data = m->data & 0xffff;
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194 | 57aa265d | Michael Walle | minimac2_mdio_write_reg(s, m->phy_addr, m->reg_addr, data); |
195 | 07424544 | Michael Walle | } |
196 | 07424544 | Michael Walle | m->state = MDIO_STATE_IDLE; |
197 | 07424544 | Michael Walle | } |
198 | 07424544 | Michael Walle | m->count--; |
199 | 07424544 | Michael Walle | } |
200 | 07424544 | Michael Walle | |
201 | 07424544 | Michael Walle | m->last_clk = (s->regs[R_MDIO] & MDIO_CLK) ? 1 : 0; |
202 | 07424544 | Michael Walle | } |
203 | 07424544 | Michael Walle | |
204 | 07424544 | Michael Walle | static size_t assemble_frame(uint8_t *buf, size_t size,
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205 | 07424544 | Michael Walle | const uint8_t *payload, size_t payload_size)
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206 | 07424544 | Michael Walle | { |
207 | 07424544 | Michael Walle | uint32_t crc; |
208 | 07424544 | Michael Walle | |
209 | 07424544 | Michael Walle | if (size < payload_size + 12) { |
210 | 57aa265d | Michael Walle | error_report("milkymist_minimac2: received too big ethernet frame");
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211 | 07424544 | Michael Walle | return 0; |
212 | 07424544 | Michael Walle | } |
213 | 07424544 | Michael Walle | |
214 | 07424544 | Michael Walle | /* prepend preamble and sfd */
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215 | 07424544 | Michael Walle | memcpy(buf, preamble_sfd, 8);
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216 | 07424544 | Michael Walle | |
217 | 07424544 | Michael Walle | /* now copy the payload */
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218 | 07424544 | Michael Walle | memcpy(buf + 8, payload, payload_size);
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219 | 07424544 | Michael Walle | |
220 | 07424544 | Michael Walle | /* pad frame if needed */
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221 | 07424544 | Michael Walle | if (payload_size < 60) { |
222 | 07424544 | Michael Walle | memset(buf + payload_size + 8, 0, 60 - payload_size); |
223 | 07424544 | Michael Walle | payload_size = 60;
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224 | 07424544 | Michael Walle | } |
225 | 07424544 | Michael Walle | |
226 | 07424544 | Michael Walle | /* append fcs */
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227 | 07424544 | Michael Walle | crc = cpu_to_le32(crc32(0, buf + 8, payload_size)); |
228 | 07424544 | Michael Walle | memcpy(buf + payload_size + 8, &crc, 4); |
229 | 07424544 | Michael Walle | |
230 | 07424544 | Michael Walle | return payload_size + 12; |
231 | 07424544 | Michael Walle | } |
232 | 07424544 | Michael Walle | |
233 | 57aa265d | Michael Walle | static void minimac2_tx(MilkymistMinimac2State *s) |
234 | 07424544 | Michael Walle | { |
235 | 07424544 | Michael Walle | uint32_t txcount = s->regs[R_TXCOUNT]; |
236 | 57aa265d | Michael Walle | uint8_t *buf = s->tx_buf; |
237 | 07424544 | Michael Walle | |
238 | 07424544 | Michael Walle | if (txcount < 64) { |
239 | 6daf194d | Markus Armbruster | error_report("milkymist_minimac2: ethernet frame too small (%u < %u)",
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240 | 07424544 | Michael Walle | txcount, 64);
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241 | 57aa265d | Michael Walle | goto err;
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242 | 07424544 | Michael Walle | } |
243 | 07424544 | Michael Walle | |
244 | 57aa265d | Michael Walle | if (txcount > MINIMAC2_MTU) {
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245 | 6daf194d | Markus Armbruster | error_report("milkymist_minimac2: MTU exceeded (%u > %u)",
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246 | 57aa265d | Michael Walle | txcount, MINIMAC2_MTU); |
247 | 57aa265d | Michael Walle | goto err;
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248 | 07424544 | Michael Walle | } |
249 | 07424544 | Michael Walle | |
250 | 07424544 | Michael Walle | if (memcmp(buf, preamble_sfd, 8) != 0) { |
251 | 57aa265d | Michael Walle | error_report("milkymist_minimac2: frame doesn't contain the preamble "
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252 | 6daf194d | Markus Armbruster | "and/or the SFD (%02x %02x %02x %02x %02x %02x %02x %02x)",
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253 | 07424544 | Michael Walle | buf[0], buf[1], buf[2], buf[3], buf[4], buf[5], buf[6], buf[7]); |
254 | 57aa265d | Michael Walle | goto err;
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255 | 07424544 | Michael Walle | } |
256 | 07424544 | Michael Walle | |
257 | 57aa265d | Michael Walle | trace_milkymist_minimac2_tx_frame(txcount - 12);
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258 | 07424544 | Michael Walle | |
259 | 07424544 | Michael Walle | /* send packet, skipping preamble and sfd */
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260 | 07424544 | Michael Walle | qemu_send_packet_raw(&s->nic->nc, buf + 8, txcount - 12); |
261 | 07424544 | Michael Walle | |
262 | 07424544 | Michael Walle | s->regs[R_TXCOUNT] = 0;
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263 | 07424544 | Michael Walle | |
264 | 57aa265d | Michael Walle | err:
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265 | 57aa265d | Michael Walle | trace_milkymist_minimac2_pulse_irq_tx(); |
266 | 07424544 | Michael Walle | qemu_irq_pulse(s->tx_irq); |
267 | 07424544 | Michael Walle | } |
268 | 07424544 | Michael Walle | |
269 | 57aa265d | Michael Walle | static void update_rx_interrupt(MilkymistMinimac2State *s) |
270 | 57aa265d | Michael Walle | { |
271 | 57aa265d | Michael Walle | if (s->regs[R_STATE0] == STATE_PENDING
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272 | 57aa265d | Michael Walle | || s->regs[R_STATE1] == STATE_PENDING) { |
273 | 57aa265d | Michael Walle | trace_milkymist_minimac2_raise_irq_rx(); |
274 | 57aa265d | Michael Walle | qemu_irq_raise(s->rx_irq); |
275 | 57aa265d | Michael Walle | } else {
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276 | 57aa265d | Michael Walle | trace_milkymist_minimac2_lower_irq_rx(); |
277 | 57aa265d | Michael Walle | qemu_irq_lower(s->rx_irq); |
278 | 57aa265d | Michael Walle | } |
279 | 57aa265d | Michael Walle | } |
280 | 57aa265d | Michael Walle | |
281 | 57aa265d | Michael Walle | static ssize_t minimac2_rx(VLANClientState *nc, const uint8_t *buf, size_t size) |
282 | 07424544 | Michael Walle | { |
283 | 57aa265d | Michael Walle | MilkymistMinimac2State *s = DO_UPCAST(NICState, nc, nc)->opaque; |
284 | 07424544 | Michael Walle | |
285 | 07424544 | Michael Walle | uint32_t r_count; |
286 | 07424544 | Michael Walle | uint32_t r_state; |
287 | 57aa265d | Michael Walle | uint8_t *rx_buf; |
288 | 07424544 | Michael Walle | |
289 | 07424544 | Michael Walle | size_t frame_size; |
290 | 07424544 | Michael Walle | |
291 | 57aa265d | Michael Walle | trace_milkymist_minimac2_rx_frame(buf, size); |
292 | 07424544 | Michael Walle | |
293 | 07424544 | Michael Walle | /* choose appropriate slot */
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294 | 07424544 | Michael Walle | if (s->regs[R_STATE0] == STATE_LOADED) {
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295 | 07424544 | Michael Walle | r_count = R_COUNT0; |
296 | 07424544 | Michael Walle | r_state = R_STATE0; |
297 | 57aa265d | Michael Walle | rx_buf = s->rx0_buf; |
298 | 07424544 | Michael Walle | } else if (s->regs[R_STATE1] == STATE_LOADED) { |
299 | 07424544 | Michael Walle | r_count = R_COUNT1; |
300 | 07424544 | Michael Walle | r_state = R_STATE1; |
301 | 57aa265d | Michael Walle | rx_buf = s->rx1_buf; |
302 | 07424544 | Michael Walle | } else {
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303 | 57aa265d | Michael Walle | trace_milkymist_minimac2_drop_rx_frame(buf); |
304 | 07424544 | Michael Walle | return size;
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305 | 07424544 | Michael Walle | } |
306 | 07424544 | Michael Walle | |
307 | 07424544 | Michael Walle | /* assemble frame */
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308 | 57aa265d | Michael Walle | frame_size = assemble_frame(rx_buf, MINIMAC2_BUFFER_SIZE, buf, size); |
309 | 07424544 | Michael Walle | |
310 | 07424544 | Michael Walle | if (frame_size == 0) { |
311 | 07424544 | Michael Walle | return size;
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312 | 07424544 | Michael Walle | } |
313 | 07424544 | Michael Walle | |
314 | 57aa265d | Michael Walle | trace_milkymist_minimac2_rx_transfer(rx_buf, frame_size); |
315 | 07424544 | Michael Walle | |
316 | 07424544 | Michael Walle | /* update slot */
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317 | 07424544 | Michael Walle | s->regs[r_count] = frame_size; |
318 | 07424544 | Michael Walle | s->regs[r_state] = STATE_PENDING; |
319 | 07424544 | Michael Walle | |
320 | 57aa265d | Michael Walle | update_rx_interrupt(s); |
321 | 07424544 | Michael Walle | |
322 | 07424544 | Michael Walle | return size;
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323 | 07424544 | Michael Walle | } |
324 | 07424544 | Michael Walle | |
325 | 8a53d56f | Avi Kivity | static uint64_t
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326 | 8a53d56f | Avi Kivity | minimac2_read(void *opaque, target_phys_addr_t addr, unsigned size) |
327 | 07424544 | Michael Walle | { |
328 | 57aa265d | Michael Walle | MilkymistMinimac2State *s = opaque; |
329 | 07424544 | Michael Walle | uint32_t r = 0;
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330 | 07424544 | Michael Walle | |
331 | 07424544 | Michael Walle | addr >>= 2;
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332 | 07424544 | Michael Walle | switch (addr) {
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333 | 07424544 | Michael Walle | case R_SETUP:
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334 | 07424544 | Michael Walle | case R_MDIO:
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335 | 07424544 | Michael Walle | case R_STATE0:
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336 | 07424544 | Michael Walle | case R_COUNT0:
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337 | 07424544 | Michael Walle | case R_STATE1:
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338 | 07424544 | Michael Walle | case R_COUNT1:
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339 | 07424544 | Michael Walle | case R_TXCOUNT:
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340 | 07424544 | Michael Walle | r = s->regs[addr]; |
341 | 07424544 | Michael Walle | break;
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342 | 07424544 | Michael Walle | |
343 | 07424544 | Michael Walle | default:
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344 | 57aa265d | Michael Walle | error_report("milkymist_minimac2: read access to unknown register 0x"
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345 | 07424544 | Michael Walle | TARGET_FMT_plx, addr << 2);
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346 | 07424544 | Michael Walle | break;
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347 | 07424544 | Michael Walle | } |
348 | 07424544 | Michael Walle | |
349 | 57aa265d | Michael Walle | trace_milkymist_minimac2_memory_read(addr << 2, r);
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350 | 07424544 | Michael Walle | |
351 | 07424544 | Michael Walle | return r;
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352 | 07424544 | Michael Walle | } |
353 | 07424544 | Michael Walle | |
354 | 07424544 | Michael Walle | static void |
355 | 8a53d56f | Avi Kivity | minimac2_write(void *opaque, target_phys_addr_t addr, uint64_t value,
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356 | 8a53d56f | Avi Kivity | unsigned size)
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357 | 07424544 | Michael Walle | { |
358 | 57aa265d | Michael Walle | MilkymistMinimac2State *s = opaque; |
359 | 07424544 | Michael Walle | |
360 | 57aa265d | Michael Walle | trace_milkymist_minimac2_memory_read(addr, value); |
361 | 07424544 | Michael Walle | |
362 | 07424544 | Michael Walle | addr >>= 2;
|
363 | 07424544 | Michael Walle | switch (addr) {
|
364 | 07424544 | Michael Walle | case R_MDIO:
|
365 | 07424544 | Michael Walle | { |
366 | 07424544 | Michael Walle | /* MDIO_DI is read only */
|
367 | 07424544 | Michael Walle | int mdio_di = (s->regs[R_MDIO] & MDIO_DI);
|
368 | 07424544 | Michael Walle | s->regs[R_MDIO] = value; |
369 | 07424544 | Michael Walle | if (mdio_di) {
|
370 | 07424544 | Michael Walle | s->regs[R_MDIO] |= mdio_di; |
371 | 07424544 | Michael Walle | } else {
|
372 | 07424544 | Michael Walle | s->regs[R_MDIO] &= ~mdio_di; |
373 | 07424544 | Michael Walle | } |
374 | 07424544 | Michael Walle | |
375 | 57aa265d | Michael Walle | minimac2_update_mdio(s); |
376 | 07424544 | Michael Walle | } break;
|
377 | 07424544 | Michael Walle | case R_TXCOUNT:
|
378 | 07424544 | Michael Walle | s->regs[addr] = value; |
379 | 07424544 | Michael Walle | if (value > 0) { |
380 | 57aa265d | Michael Walle | minimac2_tx(s); |
381 | 07424544 | Michael Walle | } |
382 | 07424544 | Michael Walle | break;
|
383 | 07424544 | Michael Walle | case R_STATE0:
|
384 | 07424544 | Michael Walle | case R_STATE1:
|
385 | 57aa265d | Michael Walle | s->regs[addr] = value; |
386 | 57aa265d | Michael Walle | update_rx_interrupt(s); |
387 | 57aa265d | Michael Walle | break;
|
388 | 57aa265d | Michael Walle | case R_SETUP:
|
389 | 57aa265d | Michael Walle | case R_COUNT0:
|
390 | 07424544 | Michael Walle | case R_COUNT1:
|
391 | 07424544 | Michael Walle | s->regs[addr] = value; |
392 | 07424544 | Michael Walle | break;
|
393 | 07424544 | Michael Walle | |
394 | 07424544 | Michael Walle | default:
|
395 | 57aa265d | Michael Walle | error_report("milkymist_minimac2: write access to unknown register 0x"
|
396 | 07424544 | Michael Walle | TARGET_FMT_plx, addr << 2);
|
397 | 07424544 | Michael Walle | break;
|
398 | 07424544 | Michael Walle | } |
399 | 07424544 | Michael Walle | } |
400 | 07424544 | Michael Walle | |
401 | 8a53d56f | Avi Kivity | static const MemoryRegionOps minimac2_ops = { |
402 | 8a53d56f | Avi Kivity | .read = minimac2_read, |
403 | 8a53d56f | Avi Kivity | .write = minimac2_write, |
404 | 8a53d56f | Avi Kivity | .valid = { |
405 | 8a53d56f | Avi Kivity | .min_access_size = 4,
|
406 | 8a53d56f | Avi Kivity | .max_access_size = 4,
|
407 | 8a53d56f | Avi Kivity | }, |
408 | 8a53d56f | Avi Kivity | .endianness = DEVICE_NATIVE_ENDIAN, |
409 | 07424544 | Michael Walle | }; |
410 | 07424544 | Michael Walle | |
411 | 57aa265d | Michael Walle | static int minimac2_can_rx(VLANClientState *nc) |
412 | 07424544 | Michael Walle | { |
413 | 57aa265d | Michael Walle | MilkymistMinimac2State *s = DO_UPCAST(NICState, nc, nc)->opaque; |
414 | 07424544 | Michael Walle | |
415 | 07424544 | Michael Walle | if (s->regs[R_STATE0] == STATE_LOADED) {
|
416 | 07424544 | Michael Walle | return 1; |
417 | 07424544 | Michael Walle | } |
418 | 07424544 | Michael Walle | if (s->regs[R_STATE1] == STATE_LOADED) {
|
419 | 07424544 | Michael Walle | return 1; |
420 | 07424544 | Michael Walle | } |
421 | 07424544 | Michael Walle | |
422 | 07424544 | Michael Walle | return 0; |
423 | 07424544 | Michael Walle | } |
424 | 07424544 | Michael Walle | |
425 | 57aa265d | Michael Walle | static void minimac2_cleanup(VLANClientState *nc) |
426 | 07424544 | Michael Walle | { |
427 | 57aa265d | Michael Walle | MilkymistMinimac2State *s = DO_UPCAST(NICState, nc, nc)->opaque; |
428 | 07424544 | Michael Walle | |
429 | 07424544 | Michael Walle | s->nic = NULL;
|
430 | 07424544 | Michael Walle | } |
431 | 07424544 | Michael Walle | |
432 | 57aa265d | Michael Walle | static void milkymist_minimac2_reset(DeviceState *d) |
433 | 07424544 | Michael Walle | { |
434 | 57aa265d | Michael Walle | MilkymistMinimac2State *s = |
435 | 57aa265d | Michael Walle | container_of(d, MilkymistMinimac2State, busdev.qdev); |
436 | 07424544 | Michael Walle | int i;
|
437 | 07424544 | Michael Walle | |
438 | 07424544 | Michael Walle | for (i = 0; i < R_MAX; i++) { |
439 | 07424544 | Michael Walle | s->regs[i] = 0;
|
440 | 07424544 | Michael Walle | } |
441 | 07424544 | Michael Walle | for (i = 0; i < R_PHY_MAX; i++) { |
442 | 07424544 | Michael Walle | s->phy_regs[i] = 0;
|
443 | 07424544 | Michael Walle | } |
444 | 07424544 | Michael Walle | |
445 | 07424544 | Michael Walle | /* defaults */
|
446 | 07424544 | Michael Walle | s->phy_regs[R_PHY_ID1] = 0x0022; /* Micrel KSZ8001L */ |
447 | 07424544 | Michael Walle | s->phy_regs[R_PHY_ID2] = 0x161a;
|
448 | 07424544 | Michael Walle | } |
449 | 07424544 | Michael Walle | |
450 | 57aa265d | Michael Walle | static NetClientInfo net_milkymist_minimac2_info = {
|
451 | 07424544 | Michael Walle | .type = NET_CLIENT_TYPE_NIC, |
452 | 07424544 | Michael Walle | .size = sizeof(NICState),
|
453 | 57aa265d | Michael Walle | .can_receive = minimac2_can_rx, |
454 | 57aa265d | Michael Walle | .receive = minimac2_rx, |
455 | 57aa265d | Michael Walle | .cleanup = minimac2_cleanup, |
456 | 07424544 | Michael Walle | }; |
457 | 07424544 | Michael Walle | |
458 | 57aa265d | Michael Walle | static int milkymist_minimac2_init(SysBusDevice *dev) |
459 | 07424544 | Michael Walle | { |
460 | 57aa265d | Michael Walle | MilkymistMinimac2State *s = FROM_SYSBUS(typeof(*s), dev); |
461 | 57aa265d | Michael Walle | size_t buffers_size = TARGET_PAGE_ALIGN(3 * MINIMAC2_BUFFER_SIZE);
|
462 | 07424544 | Michael Walle | |
463 | 07424544 | Michael Walle | sysbus_init_irq(dev, &s->rx_irq); |
464 | 07424544 | Michael Walle | sysbus_init_irq(dev, &s->tx_irq); |
465 | 07424544 | Michael Walle | |
466 | 8a53d56f | Avi Kivity | memory_region_init_io(&s->regs_region, &minimac2_ops, s, |
467 | 306f66b4 | Michael Walle | "milkymist-minimac2", R_MAX * 4); |
468 | 8a53d56f | Avi Kivity | sysbus_init_mmio_region(dev, &s->regs_region); |
469 | 07424544 | Michael Walle | |
470 | 57aa265d | Michael Walle | /* register buffers memory */
|
471 | 306f66b4 | Michael Walle | memory_region_init_ram(&s->buffers, NULL, "milkymist-minimac2.buffers", |
472 | 8a53d56f | Avi Kivity | buffers_size); |
473 | 8a53d56f | Avi Kivity | s->rx0_buf = memory_region_get_ram_ptr(&s->buffers); |
474 | 57aa265d | Michael Walle | s->rx1_buf = s->rx0_buf + MINIMAC2_BUFFER_SIZE; |
475 | 57aa265d | Michael Walle | s->tx_buf = s->rx1_buf + MINIMAC2_BUFFER_SIZE; |
476 | 57aa265d | Michael Walle | |
477 | 8a53d56f | Avi Kivity | sysbus_add_memory(dev, s->buffers_base, &s->buffers); |
478 | 57aa265d | Michael Walle | |
479 | 07424544 | Michael Walle | qemu_macaddr_default_if_unset(&s->conf.macaddr); |
480 | 57aa265d | Michael Walle | s->nic = qemu_new_nic(&net_milkymist_minimac2_info, &s->conf, |
481 | 07424544 | Michael Walle | dev->qdev.info->name, dev->qdev.id, s); |
482 | 07424544 | Michael Walle | qemu_format_nic_info_str(&s->nic->nc, s->conf.macaddr.a); |
483 | 07424544 | Michael Walle | |
484 | 07424544 | Michael Walle | return 0; |
485 | 07424544 | Michael Walle | } |
486 | 07424544 | Michael Walle | |
487 | 57aa265d | Michael Walle | static const VMStateDescription vmstate_milkymist_minimac2_mdio = { |
488 | 57aa265d | Michael Walle | .name = "milkymist-minimac2-mdio",
|
489 | 07424544 | Michael Walle | .version_id = 1,
|
490 | 07424544 | Michael Walle | .minimum_version_id = 1,
|
491 | 07424544 | Michael Walle | .minimum_version_id_old = 1,
|
492 | 07424544 | Michael Walle | .fields = (VMStateField[]) { |
493 | 57aa265d | Michael Walle | VMSTATE_INT32(last_clk, MilkymistMinimac2MdioState), |
494 | 57aa265d | Michael Walle | VMSTATE_INT32(count, MilkymistMinimac2MdioState), |
495 | 57aa265d | Michael Walle | VMSTATE_UINT32(data, MilkymistMinimac2MdioState), |
496 | 57aa265d | Michael Walle | VMSTATE_UINT16(data_out, MilkymistMinimac2MdioState), |
497 | 57aa265d | Michael Walle | VMSTATE_INT32(state, MilkymistMinimac2MdioState), |
498 | 57aa265d | Michael Walle | VMSTATE_UINT8(phy_addr, MilkymistMinimac2MdioState), |
499 | 57aa265d | Michael Walle | VMSTATE_UINT8(reg_addr, MilkymistMinimac2MdioState), |
500 | 07424544 | Michael Walle | VMSTATE_END_OF_LIST() |
501 | 07424544 | Michael Walle | } |
502 | 07424544 | Michael Walle | }; |
503 | 07424544 | Michael Walle | |
504 | 57aa265d | Michael Walle | static const VMStateDescription vmstate_milkymist_minimac2 = { |
505 | 57aa265d | Michael Walle | .name = "milkymist-minimac2",
|
506 | 07424544 | Michael Walle | .version_id = 1,
|
507 | 07424544 | Michael Walle | .minimum_version_id = 1,
|
508 | 07424544 | Michael Walle | .minimum_version_id_old = 1,
|
509 | 07424544 | Michael Walle | .fields = (VMStateField[]) { |
510 | 57aa265d | Michael Walle | VMSTATE_UINT32_ARRAY(regs, MilkymistMinimac2State, R_MAX), |
511 | 57aa265d | Michael Walle | VMSTATE_UINT16_ARRAY(phy_regs, MilkymistMinimac2State, R_PHY_MAX), |
512 | 57aa265d | Michael Walle | VMSTATE_STRUCT(mdio, MilkymistMinimac2State, 0,
|
513 | 57aa265d | Michael Walle | vmstate_milkymist_minimac2_mdio, MilkymistMinimac2MdioState), |
514 | 07424544 | Michael Walle | VMSTATE_END_OF_LIST() |
515 | 07424544 | Michael Walle | } |
516 | 07424544 | Michael Walle | }; |
517 | 07424544 | Michael Walle | |
518 | 57aa265d | Michael Walle | static SysBusDeviceInfo milkymist_minimac2_info = {
|
519 | 57aa265d | Michael Walle | .init = milkymist_minimac2_init, |
520 | 57aa265d | Michael Walle | .qdev.name = "milkymist-minimac2",
|
521 | 57aa265d | Michael Walle | .qdev.size = sizeof(MilkymistMinimac2State),
|
522 | 57aa265d | Michael Walle | .qdev.vmsd = &vmstate_milkymist_minimac2, |
523 | 57aa265d | Michael Walle | .qdev.reset = milkymist_minimac2_reset, |
524 | 07424544 | Michael Walle | .qdev.props = (Property[]) { |
525 | 57aa265d | Michael Walle | DEFINE_PROP_TADDR("buffers_base", MilkymistMinimac2State,
|
526 | 57aa265d | Michael Walle | buffers_base, 0),
|
527 | 57aa265d | Michael Walle | DEFINE_NIC_PROPERTIES(MilkymistMinimac2State, conf), |
528 | 57aa265d | Michael Walle | DEFINE_PROP_STRING("phy_model", MilkymistMinimac2State, phy_model),
|
529 | 07424544 | Michael Walle | DEFINE_PROP_END_OF_LIST(), |
530 | 07424544 | Michael Walle | } |
531 | 07424544 | Michael Walle | }; |
532 | 07424544 | Michael Walle | |
533 | 57aa265d | Michael Walle | static void milkymist_minimac2_register(void) |
534 | 07424544 | Michael Walle | { |
535 | 57aa265d | Michael Walle | sysbus_register_withprop(&milkymist_minimac2_info); |
536 | 07424544 | Michael Walle | } |
537 | 07424544 | Michael Walle | |
538 | 57aa265d | Michael Walle | device_init(milkymist_minimac2_register) |