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1 | 0d78f544 | ths | /*
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2 | 0d78f544 | ths | * Renesas SH7751R R2D-PLUS emulation
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3 | 0d78f544 | ths | *
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4 | 0d78f544 | ths | * Copyright (c) 2007 Magnus Damm
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5 | b319feb7 | aurel32 | * Copyright (c) 2008 Paul Mundt
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6 | 0d78f544 | ths | *
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7 | 0d78f544 | ths | * Permission is hereby granted, free of charge, to any person obtaining a copy
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8 | 0d78f544 | ths | * of this software and associated documentation files (the "Software"), to deal
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9 | 0d78f544 | ths | * in the Software without restriction, including without limitation the rights
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10 | 0d78f544 | ths | * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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11 | 0d78f544 | ths | * copies of the Software, and to permit persons to whom the Software is
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12 | 0d78f544 | ths | * furnished to do so, subject to the following conditions:
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13 | 0d78f544 | ths | *
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14 | 0d78f544 | ths | * The above copyright notice and this permission notice shall be included in
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15 | 0d78f544 | ths | * all copies or substantial portions of the Software.
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16 | 0d78f544 | ths | *
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17 | 0d78f544 | ths | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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18 | 0d78f544 | ths | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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19 | 0d78f544 | ths | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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20 | 0d78f544 | ths | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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21 | 0d78f544 | ths | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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22 | 0d78f544 | ths | * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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23 | 0d78f544 | ths | * THE SOFTWARE.
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24 | 0d78f544 | ths | */
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25 | 0d78f544 | ths | |
26 | cf154394 | Aurelien Jarno | #include "sysbus.h" |
27 | 87ecb68b | pbrook | #include "hw.h" |
28 | 87ecb68b | pbrook | #include "sh.h" |
29 | ffd39257 | blueswir1 | #include "devices.h" |
30 | 87ecb68b | pbrook | #include "sysemu.h" |
31 | 87ecb68b | pbrook | #include "boards.h" |
32 | c2f01775 | balrog | #include "pci.h" |
33 | c2f01775 | balrog | #include "net.h" |
34 | c2f01775 | balrog | #include "sh7750_regs.h" |
35 | 3d2bf4a1 | Gerd Hoffmann | #include "ide.h" |
36 | ca20cf32 | Blue Swirl | #include "loader.h" |
37 | 9caa3ec1 | Aurelien Jarno | #include "usb.h" |
38 | 56839a19 | Aurelien Jarno | #include "flash.h" |
39 | 2446333c | Blue Swirl | #include "blockdev.h" |
40 | 27a9d2ea | Richard Henderson | #include "exec-memory.h" |
41 | 56839a19 | Aurelien Jarno | |
42 | 56839a19 | Aurelien Jarno | #define FLASH_BASE 0x00000000 |
43 | 56839a19 | Aurelien Jarno | #define FLASH_SIZE 0x02000000 |
44 | 0d78f544 | ths | |
45 | 0d78f544 | ths | #define SDRAM_BASE 0x0c000000 /* Physical location of SDRAM: Area 3 */ |
46 | 0d78f544 | ths | #define SDRAM_SIZE 0x04000000 |
47 | 0d78f544 | ths | |
48 | ffd39257 | blueswir1 | #define SM501_VRAM_SIZE 0x800000 |
49 | ffd39257 | blueswir1 | |
50 | 73f19035 | Aurelien Jarno | #define BOOT_PARAMS_OFFSET 0x0010000 |
51 | e8afa065 | aurel32 | /* CONFIG_BOOT_LINK_OFFSET of Linux kernel */
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52 | 73f19035 | Aurelien Jarno | #define LINUX_LOAD_OFFSET 0x0800000 |
53 | 73f19035 | Aurelien Jarno | #define INITRD_LOAD_OFFSET 0x1800000 |
54 | e8afa065 | aurel32 | |
55 | d47ede60 | balrog | #define PA_IRLMSK 0x00 |
56 | b319feb7 | aurel32 | #define PA_POWOFF 0x30 |
57 | b319feb7 | aurel32 | #define PA_VERREG 0x32 |
58 | b319feb7 | aurel32 | #define PA_OUTPORT 0x36 |
59 | b319feb7 | aurel32 | |
60 | b319feb7 | aurel32 | typedef struct { |
61 | b319feb7 | aurel32 | uint16_t bcr; |
62 | d47ede60 | balrog | uint16_t irlmsk; |
63 | b319feb7 | aurel32 | uint16_t irlmon; |
64 | b319feb7 | aurel32 | uint16_t cfctl; |
65 | b319feb7 | aurel32 | uint16_t cfpow; |
66 | b319feb7 | aurel32 | uint16_t dispctl; |
67 | b319feb7 | aurel32 | uint16_t sdmpow; |
68 | b319feb7 | aurel32 | uint16_t rtcce; |
69 | b319feb7 | aurel32 | uint16_t pcicd; |
70 | b319feb7 | aurel32 | uint16_t voyagerrts; |
71 | b319feb7 | aurel32 | uint16_t cfrst; |
72 | b319feb7 | aurel32 | uint16_t admrts; |
73 | b319feb7 | aurel32 | uint16_t extrst; |
74 | b319feb7 | aurel32 | uint16_t cfcdintclr; |
75 | b319feb7 | aurel32 | uint16_t keyctlclr; |
76 | b319feb7 | aurel32 | uint16_t pad0; |
77 | b319feb7 | aurel32 | uint16_t pad1; |
78 | b319feb7 | aurel32 | uint16_t verreg; |
79 | b319feb7 | aurel32 | uint16_t inport; |
80 | b319feb7 | aurel32 | uint16_t outport; |
81 | b319feb7 | aurel32 | uint16_t bverreg; |
82 | d47ede60 | balrog | |
83 | d47ede60 | balrog | /* output pin */
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84 | d47ede60 | balrog | qemu_irq irl; |
85 | 5dea2efb | Avi Kivity | MemoryRegion iomem; |
86 | c227f099 | Anthony Liguori | } r2d_fpga_t; |
87 | b319feb7 | aurel32 | |
88 | d47ede60 | balrog | enum r2d_fpga_irq {
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89 | d47ede60 | balrog | PCI_INTD, CF_IDE, CF_CD, PCI_INTC, SM501, KEY, RTC_A, RTC_T, |
90 | d47ede60 | balrog | SDCARD, PCI_INTA, PCI_INTB, EXT, TP, |
91 | d47ede60 | balrog | NR_IRQS |
92 | d47ede60 | balrog | }; |
93 | d47ede60 | balrog | |
94 | d47ede60 | balrog | static const struct { short irl; uint16_t msk; } irqtab[NR_IRQS] = { |
95 | d47ede60 | balrog | [CF_IDE] = { 1, 1<<9 }, |
96 | d47ede60 | balrog | [CF_CD] = { 2, 1<<8 }, |
97 | d47ede60 | balrog | [PCI_INTA] = { 9, 1<<14 }, |
98 | d47ede60 | balrog | [PCI_INTB] = { 10, 1<<13 }, |
99 | d47ede60 | balrog | [PCI_INTC] = { 3, 1<<12 }, |
100 | d47ede60 | balrog | [PCI_INTD] = { 0, 1<<11 }, |
101 | d47ede60 | balrog | [SM501] = { 4, 1<<10 }, |
102 | d47ede60 | balrog | [KEY] = { 5, 1<<6 }, |
103 | d47ede60 | balrog | [RTC_A] = { 6, 1<<5 }, |
104 | d47ede60 | balrog | [RTC_T] = { 7, 1<<4 }, |
105 | d47ede60 | balrog | [SDCARD] = { 8, 1<<7 }, |
106 | d47ede60 | balrog | [EXT] = { 11, 1<<0 }, |
107 | d47ede60 | balrog | [TP] = { 12, 1<<15 }, |
108 | d47ede60 | balrog | }; |
109 | d47ede60 | balrog | |
110 | c227f099 | Anthony Liguori | static void update_irl(r2d_fpga_t *fpga) |
111 | d47ede60 | balrog | { |
112 | d47ede60 | balrog | int i, irl = 15; |
113 | d47ede60 | balrog | for (i = 0; i < NR_IRQS; i++) |
114 | d47ede60 | balrog | if (fpga->irlmon & fpga->irlmsk & irqtab[i].msk)
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115 | d47ede60 | balrog | if (irqtab[i].irl < irl)
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116 | d47ede60 | balrog | irl = irqtab[i].irl; |
117 | d47ede60 | balrog | qemu_set_irq(fpga->irl, irl ^ 15);
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118 | d47ede60 | balrog | } |
119 | d47ede60 | balrog | |
120 | d47ede60 | balrog | static void r2d_fpga_irq_set(void *opaque, int n, int level) |
121 | d47ede60 | balrog | { |
122 | c227f099 | Anthony Liguori | r2d_fpga_t *fpga = opaque; |
123 | d47ede60 | balrog | if (level)
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124 | d47ede60 | balrog | fpga->irlmon |= irqtab[n].msk; |
125 | d47ede60 | balrog | else
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126 | d47ede60 | balrog | fpga->irlmon &= ~irqtab[n].msk; |
127 | d47ede60 | balrog | update_irl(fpga); |
128 | d47ede60 | balrog | } |
129 | d47ede60 | balrog | |
130 | c227f099 | Anthony Liguori | static uint32_t r2d_fpga_read(void *opaque, target_phys_addr_t addr) |
131 | b319feb7 | aurel32 | { |
132 | c227f099 | Anthony Liguori | r2d_fpga_t *s = opaque; |
133 | b319feb7 | aurel32 | |
134 | b319feb7 | aurel32 | switch (addr) {
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135 | d47ede60 | balrog | case PA_IRLMSK:
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136 | d47ede60 | balrog | return s->irlmsk;
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137 | b319feb7 | aurel32 | case PA_OUTPORT:
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138 | b319feb7 | aurel32 | return s->outport;
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139 | b319feb7 | aurel32 | case PA_POWOFF:
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140 | 37cc0b44 | Aurelien Jarno | return 0x00; |
141 | b319feb7 | aurel32 | case PA_VERREG:
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142 | b319feb7 | aurel32 | return 0x10; |
143 | b319feb7 | aurel32 | } |
144 | b319feb7 | aurel32 | |
145 | b319feb7 | aurel32 | return 0; |
146 | b319feb7 | aurel32 | } |
147 | b319feb7 | aurel32 | |
148 | b319feb7 | aurel32 | static void |
149 | c227f099 | Anthony Liguori | r2d_fpga_write(void *opaque, target_phys_addr_t addr, uint32_t value)
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150 | b319feb7 | aurel32 | { |
151 | c227f099 | Anthony Liguori | r2d_fpga_t *s = opaque; |
152 | b319feb7 | aurel32 | |
153 | b319feb7 | aurel32 | switch (addr) {
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154 | d47ede60 | balrog | case PA_IRLMSK:
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155 | d47ede60 | balrog | s->irlmsk = value; |
156 | d47ede60 | balrog | update_irl(s); |
157 | d47ede60 | balrog | break;
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158 | b319feb7 | aurel32 | case PA_OUTPORT:
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159 | b319feb7 | aurel32 | s->outport = value; |
160 | b319feb7 | aurel32 | break;
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161 | b319feb7 | aurel32 | case PA_POWOFF:
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162 | 37cc0b44 | Aurelien Jarno | if (value & 1) { |
163 | 37cc0b44 | Aurelien Jarno | qemu_system_shutdown_request(); |
164 | 37cc0b44 | Aurelien Jarno | } |
165 | 37cc0b44 | Aurelien Jarno | break;
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166 | b319feb7 | aurel32 | case PA_VERREG:
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167 | b319feb7 | aurel32 | /* Discard writes */
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168 | b319feb7 | aurel32 | break;
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169 | b319feb7 | aurel32 | } |
170 | b319feb7 | aurel32 | } |
171 | b319feb7 | aurel32 | |
172 | 5dea2efb | Avi Kivity | static const MemoryRegionOps r2d_fpga_ops = { |
173 | 5dea2efb | Avi Kivity | .old_mmio = { |
174 | 5dea2efb | Avi Kivity | .read = { r2d_fpga_read, r2d_fpga_read, NULL, },
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175 | 5dea2efb | Avi Kivity | .write = { r2d_fpga_write, r2d_fpga_write, NULL, },
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176 | 5dea2efb | Avi Kivity | }, |
177 | 5dea2efb | Avi Kivity | .endianness = DEVICE_NATIVE_ENDIAN, |
178 | b319feb7 | aurel32 | }; |
179 | b319feb7 | aurel32 | |
180 | 5dea2efb | Avi Kivity | static qemu_irq *r2d_fpga_init(MemoryRegion *sysmem,
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181 | 5dea2efb | Avi Kivity | target_phys_addr_t base, qemu_irq irl) |
182 | b319feb7 | aurel32 | { |
183 | c227f099 | Anthony Liguori | r2d_fpga_t *s; |
184 | b319feb7 | aurel32 | |
185 | 7267c094 | Anthony Liguori | s = g_malloc0(sizeof(r2d_fpga_t));
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186 | d47ede60 | balrog | |
187 | d47ede60 | balrog | s->irl = irl; |
188 | b319feb7 | aurel32 | |
189 | 5dea2efb | Avi Kivity | memory_region_init_io(&s->iomem, &r2d_fpga_ops, s, "r2d-fpga", 0x40); |
190 | 5dea2efb | Avi Kivity | memory_region_add_subregion(sysmem, base, &s->iomem); |
191 | d47ede60 | balrog | return qemu_allocate_irqs(r2d_fpga_irq_set, s, NR_IRQS);
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192 | b319feb7 | aurel32 | } |
193 | b319feb7 | aurel32 | |
194 | 4f6493ff | Aurelien Jarno | typedef struct ResetData { |
195 | 4f6493ff | Aurelien Jarno | CPUState *env; |
196 | 4f6493ff | Aurelien Jarno | uint32_t vector; |
197 | 4f6493ff | Aurelien Jarno | } ResetData; |
198 | 4f6493ff | Aurelien Jarno | |
199 | 4f6493ff | Aurelien Jarno | static void main_cpu_reset(void *opaque) |
200 | 4f6493ff | Aurelien Jarno | { |
201 | 4f6493ff | Aurelien Jarno | ResetData *s = (ResetData *)opaque; |
202 | 4f6493ff | Aurelien Jarno | CPUState *env = s->env; |
203 | 4f6493ff | Aurelien Jarno | |
204 | 4f6493ff | Aurelien Jarno | cpu_reset(env); |
205 | 4f6493ff | Aurelien Jarno | env->pc = s->vector; |
206 | 4f6493ff | Aurelien Jarno | } |
207 | 4f6493ff | Aurelien Jarno | |
208 | 541dc0d4 | Stefan Weil | static struct QEMU_PACKED |
209 | 73f19035 | Aurelien Jarno | { |
210 | 73f19035 | Aurelien Jarno | int mount_root_rdonly;
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211 | 73f19035 | Aurelien Jarno | int ramdisk_flags;
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212 | 73f19035 | Aurelien Jarno | int orig_root_dev;
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213 | 73f19035 | Aurelien Jarno | int loader_type;
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214 | 73f19035 | Aurelien Jarno | int initrd_start;
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215 | 73f19035 | Aurelien Jarno | int initrd_size;
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216 | 73f19035 | Aurelien Jarno | |
217 | 73f19035 | Aurelien Jarno | char pad[232]; |
218 | 73f19035 | Aurelien Jarno | |
219 | 73f19035 | Aurelien Jarno | char kernel_cmdline[256]; |
220 | 73f19035 | Aurelien Jarno | } boot_params; |
221 | 73f19035 | Aurelien Jarno | |
222 | c227f099 | Anthony Liguori | static void r2d_init(ram_addr_t ram_size, |
223 | 3023f332 | aliguori | const char *boot_device, |
224 | 0d78f544 | ths | const char *kernel_filename, const char *kernel_cmdline, |
225 | 0d78f544 | ths | const char *initrd_filename, const char *cpu_model) |
226 | 0d78f544 | ths | { |
227 | 0d78f544 | ths | CPUState *env; |
228 | 4f6493ff | Aurelien Jarno | ResetData *reset_info; |
229 | 0d78f544 | ths | struct SH7750State *s;
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230 | 5dea2efb | Avi Kivity | MemoryRegion *sdram = g_new(MemoryRegion, 1);
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231 | d47ede60 | balrog | qemu_irq *irq; |
232 | 751c6a17 | Gerd Hoffmann | DriveInfo *dinfo; |
233 | c2f01775 | balrog | int i;
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234 | 27a9d2ea | Richard Henderson | MemoryRegion *address_space_mem = get_system_memory(); |
235 | 0d78f544 | ths | |
236 | aaed909a | bellard | if (!cpu_model)
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237 | 0fd3ca30 | aurel32 | cpu_model = "SH7751R";
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238 | aaed909a | bellard | |
239 | aaed909a | bellard | env = cpu_init(cpu_model); |
240 | aaed909a | bellard | if (!env) {
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241 | aaed909a | bellard | fprintf(stderr, "Unable to find CPU definition\n");
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242 | aaed909a | bellard | exit(1);
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243 | aaed909a | bellard | } |
244 | 7267c094 | Anthony Liguori | reset_info = g_malloc0(sizeof(ResetData));
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245 | 4f6493ff | Aurelien Jarno | reset_info->env = env; |
246 | 4f6493ff | Aurelien Jarno | reset_info->vector = env->pc; |
247 | 4f6493ff | Aurelien Jarno | qemu_register_reset(main_cpu_reset, reset_info); |
248 | 0d78f544 | ths | |
249 | 0d78f544 | ths | /* Allocate memory space */
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250 | 5dea2efb | Avi Kivity | memory_region_init_ram(sdram, NULL, "r2d.sdram", SDRAM_SIZE); |
251 | 5dea2efb | Avi Kivity | memory_region_add_subregion(address_space_mem, SDRAM_BASE, sdram); |
252 | 0d78f544 | ths | /* Register peripherals */
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253 | 0d78f544 | ths | s = sh7750_init(env); |
254 | 5dea2efb | Avi Kivity | irq = r2d_fpga_init(address_space_mem, 0x04000000, sh7750_irl(s));
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255 | cf154394 | Aurelien Jarno | sysbus_create_varargs("sh_pci", 0x1e200000, irq[PCI_INTA], irq[PCI_INTB], |
256 | cf154394 | Aurelien Jarno | irq[PCI_INTC], irq[PCI_INTD], NULL);
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257 | d47ede60 | balrog | |
258 | 27a9d2ea | Richard Henderson | sm501_init(address_space_mem, 0x10000000, SM501_VRAM_SIZE,
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259 | 27a9d2ea | Richard Henderson | irq[SM501], serial_hds[2]);
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260 | a4a771c0 | balrog | |
261 | a4a771c0 | balrog | /* onboard CF (True IDE mode, Master only). */
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262 | 612b2bd0 | Aurelien Jarno | dinfo = drive_get(IF_IDE, 0, 0); |
263 | 9d7f1b9a | Avi Kivity | mmio_ide_init(0x14001000, 0x1400080c, address_space_mem, irq[CF_IDE], 1, |
264 | 612b2bd0 | Aurelien Jarno | dinfo, NULL);
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265 | a4a771c0 | balrog | |
266 | 56839a19 | Aurelien Jarno | /* onboard flash memory */
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267 | 45e7e4bc | Aurelien Jarno | dinfo = drive_get(IF_PFLASH, 0, 0); |
268 | cfe5f011 | Avi Kivity | pflash_cfi02_register(0x0, NULL, "r2d.flash", FLASH_SIZE, |
269 | 612b2bd0 | Aurelien Jarno | dinfo ? dinfo->bdrv : NULL, (16 * 1024), |
270 | 612b2bd0 | Aurelien Jarno | FLASH_SIZE >> 16,
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271 | 612b2bd0 | Aurelien Jarno | 1, 4, 0x0000, 0x0000, 0x0000, 0x0000, |
272 | 01e0451a | Anthony Liguori | 0x555, 0x2aa, 0); |
273 | 56839a19 | Aurelien Jarno | |
274 | c2f01775 | balrog | /* NIC: rtl8139 on-board, and 2 slots. */
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275 | ab2da564 | aurel32 | for (i = 0; i < nb_nics; i++) |
276 | 07caea31 | Markus Armbruster | pci_nic_init_nofail(&nd_table[i], "rtl8139", i==0 ? "2" : NULL); |
277 | c2f01775 | balrog | |
278 | 9caa3ec1 | Aurelien Jarno | /* USB keyboard */
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279 | 9caa3ec1 | Aurelien Jarno | usbdevice_create("keyboard");
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280 | 9caa3ec1 | Aurelien Jarno | |
281 | 0d78f544 | ths | /* Todo: register on board registers */
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282 | 73f19035 | Aurelien Jarno | memset(&boot_params, 0, sizeof(boot_params)); |
283 | 73f19035 | Aurelien Jarno | |
284 | e8afa065 | aurel32 | if (kernel_filename) {
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285 | 73f19035 | Aurelien Jarno | int kernel_size;
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286 | 73f19035 | Aurelien Jarno | |
287 | 73f19035 | Aurelien Jarno | kernel_size = load_image_targphys(kernel_filename, |
288 | 73f19035 | Aurelien Jarno | SDRAM_BASE + LINUX_LOAD_OFFSET, |
289 | 73f19035 | Aurelien Jarno | INITRD_LOAD_OFFSET - LINUX_LOAD_OFFSET); |
290 | 73f19035 | Aurelien Jarno | if (kernel_size < 0) { |
291 | 73f19035 | Aurelien Jarno | fprintf(stderr, "qemu: could not load kernel '%s'\n", kernel_filename);
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292 | 73f19035 | Aurelien Jarno | exit(1);
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293 | 73f19035 | Aurelien Jarno | } |
294 | 73f19035 | Aurelien Jarno | |
295 | 73f19035 | Aurelien Jarno | /* initialization which should be done by firmware */
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296 | 73f19035 | Aurelien Jarno | stl_phys(SH7750_BCR1, 1<<3); /* cs3 SDRAM */ |
297 | 73f19035 | Aurelien Jarno | stw_phys(SH7750_BCR2, 3<<(3*2)); /* cs3 32bit */ |
298 | 4f6493ff | Aurelien Jarno | reset_info->vector = (SDRAM_BASE + LINUX_LOAD_OFFSET) | 0xa0000000; /* Start from P2 area */ |
299 | 0d78f544 | ths | } |
300 | 73f19035 | Aurelien Jarno | |
301 | 73f19035 | Aurelien Jarno | if (initrd_filename) {
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302 | 73f19035 | Aurelien Jarno | int initrd_size;
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303 | 73f19035 | Aurelien Jarno | |
304 | 73f19035 | Aurelien Jarno | initrd_size = load_image_targphys(initrd_filename, |
305 | 73f19035 | Aurelien Jarno | SDRAM_BASE + INITRD_LOAD_OFFSET, |
306 | 73f19035 | Aurelien Jarno | SDRAM_SIZE - INITRD_LOAD_OFFSET); |
307 | 73f19035 | Aurelien Jarno | |
308 | 73f19035 | Aurelien Jarno | if (initrd_size < 0) { |
309 | 73f19035 | Aurelien Jarno | fprintf(stderr, "qemu: could not load initrd '%s'\n", initrd_filename);
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310 | 73f19035 | Aurelien Jarno | exit(1);
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311 | 73f19035 | Aurelien Jarno | } |
312 | 73f19035 | Aurelien Jarno | |
313 | 73f19035 | Aurelien Jarno | /* initialization which should be done by firmware */
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314 | 73f19035 | Aurelien Jarno | boot_params.loader_type = 1;
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315 | 73f19035 | Aurelien Jarno | boot_params.initrd_start = INITRD_LOAD_OFFSET; |
316 | 73f19035 | Aurelien Jarno | boot_params.initrd_size = initrd_size; |
317 | 73f19035 | Aurelien Jarno | } |
318 | 73f19035 | Aurelien Jarno | |
319 | 73f19035 | Aurelien Jarno | if (kernel_cmdline) {
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320 | 73f19035 | Aurelien Jarno | strncpy(boot_params.kernel_cmdline, kernel_cmdline, |
321 | 73f19035 | Aurelien Jarno | sizeof(boot_params.kernel_cmdline));
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322 | 73f19035 | Aurelien Jarno | } |
323 | 73f19035 | Aurelien Jarno | |
324 | 73f19035 | Aurelien Jarno | rom_add_blob_fixed("boot_params", &boot_params, sizeof(boot_params), |
325 | 73f19035 | Aurelien Jarno | SDRAM_BASE + BOOT_PARAMS_OFFSET); |
326 | 0d78f544 | ths | } |
327 | 0d78f544 | ths | |
328 | f80f9ec9 | Anthony Liguori | static QEMUMachine r2d_machine = {
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329 | 4b32e168 | aliguori | .name = "r2d",
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330 | 4b32e168 | aliguori | .desc = "r2d-plus board",
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331 | 4b32e168 | aliguori | .init = r2d_init, |
332 | 0d78f544 | ths | }; |
333 | f80f9ec9 | Anthony Liguori | |
334 | f80f9ec9 | Anthony Liguori | static void r2d_machine_init(void) |
335 | f80f9ec9 | Anthony Liguori | { |
336 | f80f9ec9 | Anthony Liguori | qemu_register_machine(&r2d_machine); |
337 | f80f9ec9 | Anthony Liguori | } |
338 | f80f9ec9 | Anthony Liguori | |
339 | f80f9ec9 | Anthony Liguori | machine_init(r2d_machine_init); |