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1 | 6af0bf9c | bellard | /*
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2 | 6af0bf9c | bellard | * MIPS emulation helpers for qemu.
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3 | 6af0bf9c | bellard | *
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4 | 6af0bf9c | bellard | * Copyright (c) 2004-2005 Jocelyn Mayer
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5 | 6af0bf9c | bellard | *
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6 | 6af0bf9c | bellard | * This library is free software; you can redistribute it and/or
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7 | 6af0bf9c | bellard | * modify it under the terms of the GNU Lesser General Public
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8 | 6af0bf9c | bellard | * License as published by the Free Software Foundation; either
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9 | 6af0bf9c | bellard | * version 2 of the License, or (at your option) any later version.
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10 | 6af0bf9c | bellard | *
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11 | 6af0bf9c | bellard | * This library is distributed in the hope that it will be useful,
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12 | 6af0bf9c | bellard | * but WITHOUT ANY WARRANTY; without even the implied warranty of
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13 | 6af0bf9c | bellard | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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14 | 6af0bf9c | bellard | * Lesser General Public License for more details.
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15 | 6af0bf9c | bellard | *
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16 | 6af0bf9c | bellard | * You should have received a copy of the GNU Lesser General Public
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17 | 6af0bf9c | bellard | * License along with this library; if not, write to the Free Software
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18 | 6af0bf9c | bellard | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
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19 | 6af0bf9c | bellard | */
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20 | e37e863f | bellard | #include <stdarg.h> |
21 | e37e863f | bellard | #include <stdlib.h> |
22 | e37e863f | bellard | #include <stdio.h> |
23 | e37e863f | bellard | #include <string.h> |
24 | e37e863f | bellard | #include <inttypes.h> |
25 | e37e863f | bellard | #include <signal.h> |
26 | e37e863f | bellard | #include <assert.h> |
27 | e37e863f | bellard | |
28 | e37e863f | bellard | #include "cpu.h" |
29 | e37e863f | bellard | #include "exec-all.h" |
30 | 6af0bf9c | bellard | |
31 | 43057ab1 | bellard | enum {
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32 | 43057ab1 | bellard | TLBRET_DIRTY = -4,
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33 | 43057ab1 | bellard | TLBRET_INVALID = -3,
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34 | 43057ab1 | bellard | TLBRET_NOMATCH = -2,
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35 | 43057ab1 | bellard | TLBRET_BADADDR = -1,
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36 | 43057ab1 | bellard | TLBRET_MATCH = 0
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37 | 43057ab1 | bellard | }; |
38 | 43057ab1 | bellard | |
39 | 6af0bf9c | bellard | /* MIPS32 4K MMU emulation */
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40 | 9fb63ac2 | bellard | #ifdef MIPS_USES_R4K_TLB
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41 | 6af0bf9c | bellard | static int map_address (CPUState *env, target_ulong *physical, int *prot, |
42 | 6af0bf9c | bellard | target_ulong address, int rw, int access_type) |
43 | 6af0bf9c | bellard | { |
44 | 43057ab1 | bellard | target_ulong tag = address & (TARGET_PAGE_MASK << 1);
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45 | 43057ab1 | bellard | uint8_t ASID = env->CP0_EntryHi & 0xFF;
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46 | 6af0bf9c | bellard | tlb_t *tlb; |
47 | 6af0bf9c | bellard | int i, n;
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48 | 6af0bf9c | bellard | |
49 | 7a962d30 | bellard | for (i = 0; i < MIPS_TLB_NB; i++) { |
50 | 6af0bf9c | bellard | tlb = &env->tlb[i]; |
51 | 6af0bf9c | bellard | /* Check ASID, virtual page number & size */
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52 | 6af0bf9c | bellard | if ((tlb->G == 1 || tlb->ASID == ASID) && |
53 | 4ad40f36 | bellard | tlb->VPN == tag && address < tlb->end2) { |
54 | 6af0bf9c | bellard | /* TLB match */
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55 | 43057ab1 | bellard | n = (address >> TARGET_PAGE_BITS) & 1;
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56 | 6af0bf9c | bellard | /* Check access rights */
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57 | 43057ab1 | bellard | if (!(n ? tlb->V1 : tlb->V0))
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58 | 43057ab1 | bellard | return TLBRET_INVALID;
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59 | 43057ab1 | bellard | if (rw == 0 || (n ? tlb->D1 : tlb->D0)) { |
60 | 43057ab1 | bellard | *physical = tlb->PFN[n] | (address & ~TARGET_PAGE_MASK); |
61 | 9fb63ac2 | bellard | *prot = PAGE_READ; |
62 | 98c1b82b | pbrook | if (n ? tlb->D1 : tlb->D0)
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63 | 9fb63ac2 | bellard | *prot |= PAGE_WRITE; |
64 | 43057ab1 | bellard | return TLBRET_MATCH;
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65 | 6af0bf9c | bellard | } |
66 | 43057ab1 | bellard | return TLBRET_DIRTY;
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67 | 6af0bf9c | bellard | } |
68 | 6af0bf9c | bellard | } |
69 | 43057ab1 | bellard | return TLBRET_NOMATCH;
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70 | 6af0bf9c | bellard | } |
71 | 6af0bf9c | bellard | #endif
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72 | 6af0bf9c | bellard | |
73 | 43057ab1 | bellard | static int get_physical_address (CPUState *env, target_ulong *physical, |
74 | 43057ab1 | bellard | int *prot, target_ulong address,
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75 | 43057ab1 | bellard | int rw, int access_type) |
76 | 6af0bf9c | bellard | { |
77 | 6af0bf9c | bellard | /* User mode can only access useg */
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78 | 43057ab1 | bellard | int user_mode = (env->hflags & MIPS_HFLAG_MODE) == MIPS_HFLAG_UM;
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79 | 43057ab1 | bellard | int ret = TLBRET_MATCH;
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80 | 43057ab1 | bellard | |
81 | 6af0bf9c | bellard | #if 0
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82 | 6af0bf9c | bellard | if (logfile) {
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83 | 6af0bf9c | bellard | fprintf(logfile, "user mode %d h %08x\n",
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84 | 6af0bf9c | bellard | user_mode, env->hflags);
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85 | 6af0bf9c | bellard | }
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86 | 6af0bf9c | bellard | #endif
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87 | 6af0bf9c | bellard | if (user_mode && address > 0x7FFFFFFFUL) |
88 | 43057ab1 | bellard | return TLBRET_BADADDR;
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89 | 6af0bf9c | bellard | if (address < 0x80000000UL) { |
90 | 9fb63ac2 | bellard | if (!(env->hflags & MIPS_HFLAG_ERL)) {
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91 | 9fb63ac2 | bellard | #ifdef MIPS_USES_R4K_TLB
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92 | 9fb63ac2 | bellard | ret = map_address(env, physical, prot, address, rw, access_type); |
93 | 6af0bf9c | bellard | #else
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94 | 6af0bf9c | bellard | *physical = address + 0x40000000UL;
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95 | 6af0bf9c | bellard | *prot = PAGE_READ | PAGE_WRITE; |
96 | 6af0bf9c | bellard | #endif
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97 | 6af0bf9c | bellard | } else {
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98 | 6af0bf9c | bellard | *physical = address; |
99 | 6af0bf9c | bellard | *prot = PAGE_READ | PAGE_WRITE; |
100 | 6af0bf9c | bellard | } |
101 | 6af0bf9c | bellard | } else if (address < 0xA0000000UL) { |
102 | 6af0bf9c | bellard | /* kseg0 */
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103 | 6af0bf9c | bellard | /* XXX: check supervisor mode */
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104 | 6af0bf9c | bellard | *physical = address - 0x80000000UL;
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105 | 6af0bf9c | bellard | *prot = PAGE_READ | PAGE_WRITE; |
106 | 6af0bf9c | bellard | } else if (address < 0xC0000000UL) { |
107 | 6af0bf9c | bellard | /* kseg1 */
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108 | 6af0bf9c | bellard | /* XXX: check supervisor mode */
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109 | 6af0bf9c | bellard | *physical = address - 0xA0000000UL;
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110 | 6af0bf9c | bellard | *prot = PAGE_READ | PAGE_WRITE; |
111 | 6af0bf9c | bellard | } else if (address < 0xE0000000UL) { |
112 | 6af0bf9c | bellard | /* kseg2 */
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113 | 9fb63ac2 | bellard | #ifdef MIPS_USES_R4K_TLB
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114 | 9fb63ac2 | bellard | ret = map_address(env, physical, prot, address, rw, access_type); |
115 | 6af0bf9c | bellard | #else
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116 | 6af0bf9c | bellard | *physical = address; |
117 | 6af0bf9c | bellard | *prot = PAGE_READ | PAGE_WRITE; |
118 | 6af0bf9c | bellard | #endif
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119 | 6af0bf9c | bellard | } else {
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120 | 6af0bf9c | bellard | /* kseg3 */
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121 | 6af0bf9c | bellard | /* XXX: check supervisor mode */
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122 | 6af0bf9c | bellard | /* XXX: debug segment is not emulated */
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123 | 9fb63ac2 | bellard | #ifdef MIPS_USES_R4K_TLB
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124 | 9fb63ac2 | bellard | ret = map_address(env, physical, prot, address, rw, access_type); |
125 | 6af0bf9c | bellard | #else
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126 | 6af0bf9c | bellard | *physical = address; |
127 | 6af0bf9c | bellard | *prot = PAGE_READ | PAGE_WRITE; |
128 | 6af0bf9c | bellard | #endif
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129 | 6af0bf9c | bellard | } |
130 | 6af0bf9c | bellard | #if 0
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131 | 6af0bf9c | bellard | if (logfile) {
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132 | 6af0bf9c | bellard | fprintf(logfile, "%08x %d %d => %08x %d (%d)\n", address, rw,
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133 | 6af0bf9c | bellard | access_type, *physical, *prot, ret);
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134 | 6af0bf9c | bellard | }
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135 | 6af0bf9c | bellard | #endif
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136 | 6af0bf9c | bellard | |
137 | 6af0bf9c | bellard | return ret;
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138 | 6af0bf9c | bellard | } |
139 | 6af0bf9c | bellard | |
140 | 6af0bf9c | bellard | #if defined(CONFIG_USER_ONLY)
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141 | 6af0bf9c | bellard | target_ulong cpu_get_phys_page_debug(CPUState *env, target_ulong addr) |
142 | 6af0bf9c | bellard | { |
143 | 6af0bf9c | bellard | return addr;
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144 | 6af0bf9c | bellard | } |
145 | 6af0bf9c | bellard | #else
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146 | 6af0bf9c | bellard | target_ulong cpu_get_phys_page_debug(CPUState *env, target_ulong addr) |
147 | 6af0bf9c | bellard | { |
148 | 6af0bf9c | bellard | target_ulong phys_addr; |
149 | 6af0bf9c | bellard | int prot;
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150 | 6af0bf9c | bellard | |
151 | 6af0bf9c | bellard | if (get_physical_address(env, &phys_addr, &prot, addr, 0, ACCESS_INT) != 0) |
152 | 6af0bf9c | bellard | return -1; |
153 | 6af0bf9c | bellard | return phys_addr;
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154 | 6af0bf9c | bellard | } |
155 | 6af0bf9c | bellard | |
156 | 6af0bf9c | bellard | void cpu_mips_init_mmu (CPUState *env)
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157 | 6af0bf9c | bellard | { |
158 | 6af0bf9c | bellard | } |
159 | 6af0bf9c | bellard | #endif /* !defined(CONFIG_USER_ONLY) */ |
160 | 6af0bf9c | bellard | |
161 | 6af0bf9c | bellard | int cpu_mips_handle_mmu_fault (CPUState *env, target_ulong address, int rw, |
162 | 6af0bf9c | bellard | int is_user, int is_softmmu) |
163 | 6af0bf9c | bellard | { |
164 | 6af0bf9c | bellard | target_ulong physical; |
165 | 6af0bf9c | bellard | int prot;
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166 | 6af0bf9c | bellard | int exception = 0, error_code = 0; |
167 | 6af0bf9c | bellard | int access_type;
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168 | 6af0bf9c | bellard | int ret = 0; |
169 | 6af0bf9c | bellard | |
170 | 6af0bf9c | bellard | if (logfile) {
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171 | 4ad40f36 | bellard | #if 0
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172 | 6af0bf9c | bellard | cpu_dump_state(env, logfile, fprintf, 0);
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173 | 4ad40f36 | bellard | #endif
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174 | 6af0bf9c | bellard | fprintf(logfile, "%s pc %08x ad %08x rw %d is_user %d smmu %d\n",
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175 | 6af0bf9c | bellard | __func__, env->PC, address, rw, is_user, is_softmmu); |
176 | 6af0bf9c | bellard | } |
177 | 4ad40f36 | bellard | |
178 | 4ad40f36 | bellard | rw &= 1;
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179 | 4ad40f36 | bellard | |
180 | 6af0bf9c | bellard | /* data access */
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181 | 6af0bf9c | bellard | /* XXX: put correct access by using cpu_restore_state()
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182 | 6af0bf9c | bellard | correctly */
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183 | 6af0bf9c | bellard | access_type = ACCESS_INT; |
184 | 6af0bf9c | bellard | if (env->user_mode_only) {
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185 | 6af0bf9c | bellard | /* user mode only emulation */
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186 | 43057ab1 | bellard | ret = TLBRET_NOMATCH; |
187 | 6af0bf9c | bellard | goto do_fault;
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188 | 6af0bf9c | bellard | } |
189 | 6af0bf9c | bellard | ret = get_physical_address(env, &physical, &prot, |
190 | 6af0bf9c | bellard | address, rw, access_type); |
191 | 6af0bf9c | bellard | if (logfile) {
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192 | 6af0bf9c | bellard | fprintf(logfile, "%s address=%08x ret %d physical %08x prot %d\n",
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193 | 6af0bf9c | bellard | __func__, address, ret, physical, prot); |
194 | 6af0bf9c | bellard | } |
195 | 43057ab1 | bellard | if (ret == TLBRET_MATCH) {
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196 | 43057ab1 | bellard | ret = tlb_set_page(env, address & TARGET_PAGE_MASK, |
197 | 43057ab1 | bellard | physical & TARGET_PAGE_MASK, prot, |
198 | 43057ab1 | bellard | is_user, is_softmmu); |
199 | 6af0bf9c | bellard | } else if (ret < 0) { |
200 | 6af0bf9c | bellard | do_fault:
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201 | 6af0bf9c | bellard | switch (ret) {
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202 | 6af0bf9c | bellard | default:
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203 | 43057ab1 | bellard | case TLBRET_BADADDR:
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204 | 6af0bf9c | bellard | /* Reference to kernel address from user mode or supervisor mode */
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205 | 6af0bf9c | bellard | /* Reference to supervisor address from user mode */
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206 | 6af0bf9c | bellard | if (rw)
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207 | 6af0bf9c | bellard | exception = EXCP_AdES; |
208 | 6af0bf9c | bellard | else
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209 | 6af0bf9c | bellard | exception = EXCP_AdEL; |
210 | 6af0bf9c | bellard | break;
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211 | 43057ab1 | bellard | case TLBRET_NOMATCH:
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212 | 6af0bf9c | bellard | /* No TLB match for a mapped address */
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213 | 6af0bf9c | bellard | if (rw)
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214 | 6af0bf9c | bellard | exception = EXCP_TLBS; |
215 | 6af0bf9c | bellard | else
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216 | 6af0bf9c | bellard | exception = EXCP_TLBL; |
217 | 6af0bf9c | bellard | error_code = 1;
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218 | 6af0bf9c | bellard | break;
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219 | 43057ab1 | bellard | case TLBRET_INVALID:
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220 | 6af0bf9c | bellard | /* TLB match with no valid bit */
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221 | 6af0bf9c | bellard | if (rw)
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222 | 6af0bf9c | bellard | exception = EXCP_TLBS; |
223 | 6af0bf9c | bellard | else
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224 | 6af0bf9c | bellard | exception = EXCP_TLBL; |
225 | 6af0bf9c | bellard | break;
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226 | 43057ab1 | bellard | case TLBRET_DIRTY:
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227 | 6af0bf9c | bellard | /* TLB match but 'D' bit is cleared */
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228 | 6af0bf9c | bellard | exception = EXCP_LTLBL; |
229 | 6af0bf9c | bellard | break;
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230 | 6af0bf9c | bellard | |
231 | 6af0bf9c | bellard | } |
232 | 6af0bf9c | bellard | /* Raise exception */
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233 | 6af0bf9c | bellard | env->CP0_BadVAddr = address; |
234 | 85498508 | bellard | env->CP0_Context = (env->CP0_Context & 0xff800000) |
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235 | 4ad40f36 | bellard | ((address >> 9) & 0x007ffff0); |
236 | 6af0bf9c | bellard | env->CP0_EntryHi = |
237 | 43057ab1 | bellard | (env->CP0_EntryHi & 0xFF) | (address & (TARGET_PAGE_MASK << 1)); |
238 | 6af0bf9c | bellard | env->exception_index = exception; |
239 | 6af0bf9c | bellard | env->error_code = error_code; |
240 | 6af0bf9c | bellard | ret = 1;
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241 | 6af0bf9c | bellard | } |
242 | 6af0bf9c | bellard | |
243 | 6af0bf9c | bellard | return ret;
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244 | 6af0bf9c | bellard | } |
245 | 6af0bf9c | bellard | |
246 | 6af0bf9c | bellard | void do_interrupt (CPUState *env)
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247 | 6af0bf9c | bellard | { |
248 | 6af0bf9c | bellard | target_ulong pc, offset; |
249 | 6af0bf9c | bellard | int cause = -1; |
250 | 6af0bf9c | bellard | |
251 | 6af0bf9c | bellard | if (logfile && env->exception_index != EXCP_EXT_INTERRUPT) {
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252 | 6af0bf9c | bellard | fprintf(logfile, "%s enter: PC %08x EPC %08x cause %d excp %d\n",
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253 | 6af0bf9c | bellard | __func__, env->PC, env->CP0_EPC, cause, env->exception_index); |
254 | 6af0bf9c | bellard | } |
255 | 6af0bf9c | bellard | if (env->exception_index == EXCP_EXT_INTERRUPT &&
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256 | 6af0bf9c | bellard | (env->hflags & MIPS_HFLAG_DM)) |
257 | 6af0bf9c | bellard | env->exception_index = EXCP_DINT; |
258 | 6af0bf9c | bellard | offset = 0x180;
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259 | 6af0bf9c | bellard | switch (env->exception_index) {
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260 | 6af0bf9c | bellard | case EXCP_DSS:
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261 | 6af0bf9c | bellard | env->CP0_Debug |= 1 << CP0DB_DSS;
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262 | 6af0bf9c | bellard | /* Debug single step cannot be raised inside a delay slot and
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263 | 6af0bf9c | bellard | * resume will always occur on the next instruction
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264 | 6af0bf9c | bellard | * (but we assume the pc has always been updated during
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265 | 6af0bf9c | bellard | * code translation).
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266 | 6af0bf9c | bellard | */
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267 | 6af0bf9c | bellard | env->CP0_DEPC = env->PC; |
268 | 6af0bf9c | bellard | goto enter_debug_mode;
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269 | 6af0bf9c | bellard | case EXCP_DINT:
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270 | 6af0bf9c | bellard | env->CP0_Debug |= 1 << CP0DB_DINT;
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271 | 6af0bf9c | bellard | goto set_DEPC;
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272 | 6af0bf9c | bellard | case EXCP_DIB:
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273 | 6af0bf9c | bellard | env->CP0_Debug |= 1 << CP0DB_DIB;
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274 | 6af0bf9c | bellard | goto set_DEPC;
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275 | 6af0bf9c | bellard | case EXCP_DBp:
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276 | 6af0bf9c | bellard | env->CP0_Debug |= 1 << CP0DB_DBp;
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277 | 6af0bf9c | bellard | goto set_DEPC;
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278 | 6af0bf9c | bellard | case EXCP_DDBS:
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279 | 6af0bf9c | bellard | env->CP0_Debug |= 1 << CP0DB_DDBS;
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280 | 6af0bf9c | bellard | goto set_DEPC;
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281 | 6af0bf9c | bellard | case EXCP_DDBL:
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282 | 6af0bf9c | bellard | env->CP0_Debug |= 1 << CP0DB_DDBL;
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283 | 6af0bf9c | bellard | goto set_DEPC;
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284 | 6af0bf9c | bellard | set_DEPC:
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285 | 4ad40f36 | bellard | if (env->hflags & MIPS_HFLAG_BMASK) {
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286 | 6af0bf9c | bellard | /* If the exception was raised from a delay slot,
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287 | 6af0bf9c | bellard | * come back to the jump
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288 | 6af0bf9c | bellard | */
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289 | 6af0bf9c | bellard | env->CP0_DEPC = env->PC - 4;
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290 | 4ad40f36 | bellard | env->hflags &= ~MIPS_HFLAG_BMASK; |
291 | 6af0bf9c | bellard | } else {
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292 | 6af0bf9c | bellard | env->CP0_DEPC = env->PC; |
293 | 6af0bf9c | bellard | } |
294 | 6af0bf9c | bellard | enter_debug_mode:
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295 | 6af0bf9c | bellard | env->hflags |= MIPS_HFLAG_DM; |
296 | 6af0bf9c | bellard | /* EJTAG probe trap enable is not implemented... */
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297 | 6af0bf9c | bellard | pc = 0xBFC00480;
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298 | 6af0bf9c | bellard | break;
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299 | 6af0bf9c | bellard | case EXCP_RESET:
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300 | 9fb63ac2 | bellard | #ifdef MIPS_USES_R4K_TLB
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301 | 6af0bf9c | bellard | env->CP0_random = MIPS_TLB_NB - 1;
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302 | 6af0bf9c | bellard | #endif
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303 | 6af0bf9c | bellard | env->CP0_Wired = 0;
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304 | 6af0bf9c | bellard | env->CP0_Config0 = MIPS_CONFIG0; |
305 | 6af0bf9c | bellard | #if defined (MIPS_CONFIG1)
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306 | 6af0bf9c | bellard | env->CP0_Config1 = MIPS_CONFIG1; |
307 | 6af0bf9c | bellard | #endif
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308 | 6af0bf9c | bellard | #if defined (MIPS_CONFIG2)
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309 | 6af0bf9c | bellard | env->CP0_Config2 = MIPS_CONFIG2; |
310 | 6af0bf9c | bellard | #endif
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311 | 6af0bf9c | bellard | #if defined (MIPS_CONFIG3)
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312 | 6af0bf9c | bellard | env->CP0_Config3 = MIPS_CONFIG3; |
313 | 6af0bf9c | bellard | #endif
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314 | 6af0bf9c | bellard | env->CP0_WatchLo = 0;
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315 | 6af0bf9c | bellard | env->CP0_Status = (1 << CP0St_CU0) | (1 << CP0St_BEV); |
316 | 6af0bf9c | bellard | goto set_error_EPC;
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317 | 6af0bf9c | bellard | case EXCP_SRESET:
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318 | 6af0bf9c | bellard | env->CP0_Status = (1 << CP0St_CU0) | (1 << CP0St_BEV) | |
319 | 6af0bf9c | bellard | (1 << CP0St_SR);
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320 | 6af0bf9c | bellard | env->CP0_WatchLo = 0;
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321 | 6af0bf9c | bellard | goto set_error_EPC;
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322 | 6af0bf9c | bellard | case EXCP_NMI:
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323 | 6af0bf9c | bellard | env->CP0_Status = (1 << CP0St_CU0) | (1 << CP0St_BEV) | |
324 | 6af0bf9c | bellard | (1 << CP0St_NMI);
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325 | 6af0bf9c | bellard | set_error_EPC:
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326 | 4ad40f36 | bellard | if (env->hflags & MIPS_HFLAG_BMASK) {
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327 | 6af0bf9c | bellard | /* If the exception was raised from a delay slot,
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328 | 6af0bf9c | bellard | * come back to the jump
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329 | 6af0bf9c | bellard | */
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330 | 6af0bf9c | bellard | env->CP0_ErrorEPC = env->PC - 4;
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331 | ecd78a0a | pbrook | env->hflags &= ~MIPS_HFLAG_BMASK; |
332 | 6af0bf9c | bellard | } else {
|
333 | 6af0bf9c | bellard | env->CP0_ErrorEPC = env->PC; |
334 | 6af0bf9c | bellard | } |
335 | 4ad40f36 | bellard | env->hflags = MIPS_HFLAG_ERL; |
336 | 6af0bf9c | bellard | pc = 0xBFC00000;
|
337 | 6af0bf9c | bellard | break;
|
338 | 6af0bf9c | bellard | case EXCP_MCHECK:
|
339 | 6af0bf9c | bellard | cause = 24;
|
340 | 6af0bf9c | bellard | goto set_EPC;
|
341 | 6af0bf9c | bellard | case EXCP_EXT_INTERRUPT:
|
342 | 6af0bf9c | bellard | cause = 0;
|
343 | 6af0bf9c | bellard | if (env->CP0_Cause & (1 << CP0Ca_IV)) |
344 | 6af0bf9c | bellard | offset = 0x200;
|
345 | 6af0bf9c | bellard | goto set_EPC;
|
346 | 6af0bf9c | bellard | case EXCP_DWATCH:
|
347 | 6af0bf9c | bellard | cause = 23;
|
348 | 6af0bf9c | bellard | /* XXX: TODO: manage defered watch exceptions */
|
349 | 6af0bf9c | bellard | goto set_EPC;
|
350 | 6af0bf9c | bellard | case EXCP_AdEL:
|
351 | 6af0bf9c | bellard | case EXCP_AdES:
|
352 | 6af0bf9c | bellard | cause = 4;
|
353 | 6af0bf9c | bellard | goto set_EPC;
|
354 | 6af0bf9c | bellard | case EXCP_TLBL:
|
355 | 6af0bf9c | bellard | cause = 2;
|
356 | 6af0bf9c | bellard | if (env->error_code == 1 && !(env->hflags & MIPS_HFLAG_EXL)) |
357 | 6af0bf9c | bellard | offset = 0x000;
|
358 | 6af0bf9c | bellard | goto set_EPC;
|
359 | 6af0bf9c | bellard | case EXCP_IBE:
|
360 | 6af0bf9c | bellard | cause = 6;
|
361 | 6af0bf9c | bellard | goto set_EPC;
|
362 | 6af0bf9c | bellard | case EXCP_DBE:
|
363 | 6af0bf9c | bellard | cause = 7;
|
364 | 6af0bf9c | bellard | goto set_EPC;
|
365 | 6af0bf9c | bellard | case EXCP_SYSCALL:
|
366 | 6af0bf9c | bellard | cause = 8;
|
367 | 6af0bf9c | bellard | goto set_EPC;
|
368 | 6af0bf9c | bellard | case EXCP_BREAK:
|
369 | 6af0bf9c | bellard | cause = 9;
|
370 | 6af0bf9c | bellard | goto set_EPC;
|
371 | 6af0bf9c | bellard | case EXCP_RI:
|
372 | 6af0bf9c | bellard | cause = 10;
|
373 | 6af0bf9c | bellard | goto set_EPC;
|
374 | 6af0bf9c | bellard | case EXCP_CpU:
|
375 | 6af0bf9c | bellard | cause = 11;
|
376 | 4ad40f36 | bellard | env->CP0_Cause = (env->CP0_Cause & ~0x03000000) | (env->error_code << 28); |
377 | 6af0bf9c | bellard | goto set_EPC;
|
378 | 6af0bf9c | bellard | case EXCP_OVERFLOW:
|
379 | 6af0bf9c | bellard | cause = 12;
|
380 | 6af0bf9c | bellard | goto set_EPC;
|
381 | 6af0bf9c | bellard | case EXCP_TRAP:
|
382 | 6af0bf9c | bellard | cause = 13;
|
383 | 6af0bf9c | bellard | goto set_EPC;
|
384 | 6af0bf9c | bellard | case EXCP_LTLBL:
|
385 | 6af0bf9c | bellard | cause = 1;
|
386 | 6af0bf9c | bellard | goto set_EPC;
|
387 | 6af0bf9c | bellard | case EXCP_TLBS:
|
388 | 6af0bf9c | bellard | cause = 3;
|
389 | 0d8aca8c | bellard | if (env->error_code == 1 && !(env->hflags & MIPS_HFLAG_EXL)) |
390 | 0d8aca8c | bellard | offset = 0x000;
|
391 | 0d8aca8c | bellard | goto set_EPC;
|
392 | 6af0bf9c | bellard | set_EPC:
|
393 | 6af0bf9c | bellard | if (env->CP0_Status & (1 << CP0St_BEV)) { |
394 | 6af0bf9c | bellard | pc = 0xBFC00200;
|
395 | 6af0bf9c | bellard | } else {
|
396 | 6af0bf9c | bellard | pc = 0x80000000;
|
397 | 6af0bf9c | bellard | } |
398 | 6af0bf9c | bellard | env->hflags |= MIPS_HFLAG_EXL; |
399 | 6af0bf9c | bellard | pc += offset; |
400 | 6af0bf9c | bellard | env->CP0_Cause = (env->CP0_Cause & ~0x7C) | (cause << 2); |
401 | 4ad40f36 | bellard | if (env->hflags & MIPS_HFLAG_BMASK) {
|
402 | 6af0bf9c | bellard | /* If the exception was raised from a delay slot,
|
403 | 6af0bf9c | bellard | * come back to the jump
|
404 | 6af0bf9c | bellard | */
|
405 | 6af0bf9c | bellard | env->CP0_EPC = env->PC - 4;
|
406 | 6af0bf9c | bellard | env->CP0_Cause |= 0x80000000;
|
407 | 4ad40f36 | bellard | env->hflags &= ~MIPS_HFLAG_BMASK; |
408 | 6af0bf9c | bellard | } else {
|
409 | 6af0bf9c | bellard | env->CP0_EPC = env->PC; |
410 | 6af0bf9c | bellard | env->CP0_Cause &= ~0x80000000;
|
411 | 6af0bf9c | bellard | } |
412 | 6af0bf9c | bellard | break;
|
413 | 6af0bf9c | bellard | default:
|
414 | 6af0bf9c | bellard | if (logfile) {
|
415 | 6af0bf9c | bellard | fprintf(logfile, "Invalid MIPS exception %d. Exiting\n",
|
416 | 6af0bf9c | bellard | env->exception_index); |
417 | 6af0bf9c | bellard | } |
418 | 6af0bf9c | bellard | printf("Invalid MIPS exception %d. Exiting\n", env->exception_index);
|
419 | 6af0bf9c | bellard | exit(1);
|
420 | 6af0bf9c | bellard | } |
421 | 6af0bf9c | bellard | env->PC = pc; |
422 | 6af0bf9c | bellard | if (logfile && env->exception_index != EXCP_EXT_INTERRUPT) {
|
423 | 6af0bf9c | bellard | fprintf(logfile, "%s: PC %08x EPC %08x cause %d excp %d\n"
|
424 | 6af0bf9c | bellard | " S %08x C %08x A %08x D %08x\n",
|
425 | 6af0bf9c | bellard | __func__, env->PC, env->CP0_EPC, cause, env->exception_index, |
426 | 6af0bf9c | bellard | env->CP0_Status, env->CP0_Cause, env->CP0_BadVAddr, |
427 | 6af0bf9c | bellard | env->CP0_DEPC); |
428 | 6af0bf9c | bellard | } |
429 | 6af0bf9c | bellard | env->exception_index = EXCP_NONE; |
430 | 6af0bf9c | bellard | } |