root / target-sparc / translate.c @ ce8536e2
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1 | 7a3f1944 | bellard | /*
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2 | 7a3f1944 | bellard | SPARC translation
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3 | 7a3f1944 | bellard | |
4 | 7a3f1944 | bellard | Copyright (C) 2003 Thomas M. Ogrisegg <tom@fnord.at>
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5 | 3475187d | bellard | Copyright (C) 2003-2005 Fabrice Bellard
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6 | 7a3f1944 | bellard | |
7 | 7a3f1944 | bellard | This library is free software; you can redistribute it and/or
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8 | 7a3f1944 | bellard | modify it under the terms of the GNU Lesser General Public
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9 | 7a3f1944 | bellard | License as published by the Free Software Foundation; either
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10 | 7a3f1944 | bellard | version 2 of the License, or (at your option) any later version.
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11 | 7a3f1944 | bellard | |
12 | 7a3f1944 | bellard | This library is distributed in the hope that it will be useful,
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13 | 7a3f1944 | bellard | but WITHOUT ANY WARRANTY; without even the implied warranty of
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14 | 7a3f1944 | bellard | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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15 | 7a3f1944 | bellard | Lesser General Public License for more details.
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16 | 7a3f1944 | bellard | |
17 | 7a3f1944 | bellard | You should have received a copy of the GNU Lesser General Public
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18 | 7a3f1944 | bellard | License along with this library; if not, write to the Free Software
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19 | 7a3f1944 | bellard | Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
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20 | 7a3f1944 | bellard | */
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21 | 7a3f1944 | bellard | |
22 | 7a3f1944 | bellard | /*
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23 | 7a3f1944 | bellard | TODO-list:
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24 | 7a3f1944 | bellard | |
25 | 3475187d | bellard | Rest of V9 instructions, VIS instructions
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26 | bd497938 | bellard | NPC/PC static optimisations (use JUMP_TB when possible)
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27 | 7a3f1944 | bellard | Optimize synthetic instructions
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28 | bd497938 | bellard | */
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29 | 7a3f1944 | bellard | |
30 | 7a3f1944 | bellard | #include <stdarg.h> |
31 | 7a3f1944 | bellard | #include <stdlib.h> |
32 | 7a3f1944 | bellard | #include <stdio.h> |
33 | 7a3f1944 | bellard | #include <string.h> |
34 | 7a3f1944 | bellard | #include <inttypes.h> |
35 | 7a3f1944 | bellard | |
36 | 7a3f1944 | bellard | #include "cpu.h" |
37 | 7a3f1944 | bellard | #include "exec-all.h" |
38 | 7a3f1944 | bellard | #include "disas.h" |
39 | 1a2fb1c0 | blueswir1 | #include "helper.h" |
40 | 57fec1fe | bellard | #include "tcg-op.h" |
41 | 7a3f1944 | bellard | |
42 | 7a3f1944 | bellard | #define DEBUG_DISAS
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43 | 7a3f1944 | bellard | |
44 | 72cbca10 | bellard | #define DYNAMIC_PC 1 /* dynamic pc value */ |
45 | 72cbca10 | bellard | #define JUMP_PC 2 /* dynamic pc value which takes only two values |
46 | 72cbca10 | bellard | according to jump_pc[T2] */
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47 | 72cbca10 | bellard | |
48 | 1a2fb1c0 | blueswir1 | /* global register indexes */
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49 | d9bdab86 | blueswir1 | static TCGv cpu_env, cpu_T[3], cpu_regwptr, cpu_cc_src, cpu_cc_src2, cpu_cc_dst; |
50 | 48d5c82b | blueswir1 | static TCGv cpu_psr, cpu_fsr, cpu_pc, cpu_npc, cpu_gregs[8]; |
51 | dc99a3f2 | blueswir1 | #ifdef TARGET_SPARC64
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52 | dc99a3f2 | blueswir1 | static TCGv cpu_xcc;
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53 | dc99a3f2 | blueswir1 | #endif
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54 | 1a2fb1c0 | blueswir1 | /* local register indexes (only used inside old micro ops) */
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55 | 8911f501 | blueswir1 | static TCGv cpu_tmp0, cpu_tmp32, cpu_tmp64;
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56 | 1a2fb1c0 | blueswir1 | |
57 | 7a3f1944 | bellard | typedef struct DisasContext { |
58 | 0f8a249a | blueswir1 | target_ulong pc; /* current Program Counter: integer or DYNAMIC_PC */
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59 | 0f8a249a | blueswir1 | target_ulong npc; /* next PC: integer or DYNAMIC_PC or JUMP_PC */
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60 | 72cbca10 | bellard | target_ulong jump_pc[2]; /* used when JUMP_PC pc value is used */ |
61 | cf495bcf | bellard | int is_br;
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62 | e8af50a3 | bellard | int mem_idx;
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63 | a80dde08 | bellard | int fpu_enabled;
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64 | cf495bcf | bellard | struct TranslationBlock *tb;
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65 | 7a3f1944 | bellard | } DisasContext; |
66 | 7a3f1944 | bellard | |
67 | aaed909a | bellard | typedef struct sparc_def_t sparc_def_t; |
68 | aaed909a | bellard | |
69 | 62724a37 | blueswir1 | struct sparc_def_t {
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70 | 62724a37 | blueswir1 | const unsigned char *name; |
71 | 62724a37 | blueswir1 | target_ulong iu_version; |
72 | 62724a37 | blueswir1 | uint32_t fpu_version; |
73 | 62724a37 | blueswir1 | uint32_t mmu_version; |
74 | 6d5f237a | blueswir1 | uint32_t mmu_bm; |
75 | 3deaeab7 | blueswir1 | uint32_t mmu_ctpr_mask; |
76 | 3deaeab7 | blueswir1 | uint32_t mmu_cxr_mask; |
77 | 3deaeab7 | blueswir1 | uint32_t mmu_sfsr_mask; |
78 | 3deaeab7 | blueswir1 | uint32_t mmu_trcr_mask; |
79 | 62724a37 | blueswir1 | }; |
80 | 62724a37 | blueswir1 | |
81 | aaed909a | bellard | static const sparc_def_t *cpu_sparc_find_by_name(const unsigned char *name); |
82 | aaed909a | bellard | |
83 | 7a3f1944 | bellard | extern FILE *logfile;
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84 | 7a3f1944 | bellard | extern int loglevel; |
85 | 7a3f1944 | bellard | |
86 | 3475187d | bellard | // This function uses non-native bit order
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87 | 7a3f1944 | bellard | #define GET_FIELD(X, FROM, TO) \
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88 | 7a3f1944 | bellard | ((X) >> (31 - (TO)) & ((1 << ((TO) - (FROM) + 1)) - 1)) |
89 | 7a3f1944 | bellard | |
90 | 3475187d | bellard | // This function uses the order in the manuals, i.e. bit 0 is 2^0
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91 | 3475187d | bellard | #define GET_FIELD_SP(X, FROM, TO) \
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92 | 3475187d | bellard | GET_FIELD(X, 31 - (TO), 31 - (FROM)) |
93 | 3475187d | bellard | |
94 | 3475187d | bellard | #define GET_FIELDs(x,a,b) sign_extend (GET_FIELD(x,a,b), (b) - (a) + 1) |
95 | 46d38ba8 | blueswir1 | #define GET_FIELD_SPs(x,a,b) sign_extend (GET_FIELD_SP(x,a,b), ((b) - (a) + 1)) |
96 | 3475187d | bellard | |
97 | 3475187d | bellard | #ifdef TARGET_SPARC64
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98 | 19f329ad | blueswir1 | #define FFPREG(r) (r)
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99 | 0387d928 | blueswir1 | #define DFPREG(r) (((r & 1) << 5) | (r & 0x1e)) |
100 | 1f587329 | blueswir1 | #define QFPREG(r) (((r & 1) << 5) | (r & 0x1c)) |
101 | 3475187d | bellard | #else
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102 | 19f329ad | blueswir1 | #define FFPREG(r) (r)
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103 | c185970a | blueswir1 | #define DFPREG(r) (r & 0x1e) |
104 | 1f587329 | blueswir1 | #define QFPREG(r) (r & 0x1c) |
105 | 3475187d | bellard | #endif
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106 | 3475187d | bellard | |
107 | 3475187d | bellard | static int sign_extend(int x, int len) |
108 | 3475187d | bellard | { |
109 | 3475187d | bellard | len = 32 - len;
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110 | 3475187d | bellard | return (x << len) >> len;
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111 | 3475187d | bellard | } |
112 | 3475187d | bellard | |
113 | 7a3f1944 | bellard | #define IS_IMM (insn & (1<<13)) |
114 | 7a3f1944 | bellard | |
115 | cf495bcf | bellard | static void disas_sparc_insn(DisasContext * dc); |
116 | 7a3f1944 | bellard | |
117 | ff07ec83 | blueswir1 | /* floating point registers moves */
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118 | ff07ec83 | blueswir1 | static void gen_op_load_fpr_FT0(unsigned int src) |
119 | ff07ec83 | blueswir1 | { |
120 | 8911f501 | blueswir1 | tcg_gen_ld_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, fpr[src])); |
121 | 8911f501 | blueswir1 | tcg_gen_st_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, ft0)); |
122 | 3475187d | bellard | } |
123 | ff07ec83 | blueswir1 | |
124 | ff07ec83 | blueswir1 | static void gen_op_load_fpr_FT1(unsigned int src) |
125 | ff07ec83 | blueswir1 | { |
126 | 8911f501 | blueswir1 | tcg_gen_ld_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, fpr[src])); |
127 | 8911f501 | blueswir1 | tcg_gen_st_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, ft1)); |
128 | e8af50a3 | bellard | } |
129 | e8af50a3 | bellard | |
130 | ff07ec83 | blueswir1 | static void gen_op_store_FT0_fpr(unsigned int dst) |
131 | ff07ec83 | blueswir1 | { |
132 | 8911f501 | blueswir1 | tcg_gen_ld_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, ft0)); |
133 | 8911f501 | blueswir1 | tcg_gen_st_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, fpr[dst])); |
134 | ff07ec83 | blueswir1 | } |
135 | ff07ec83 | blueswir1 | |
136 | ff07ec83 | blueswir1 | static void gen_op_load_fpr_DT0(unsigned int src) |
137 | ff07ec83 | blueswir1 | { |
138 | 8911f501 | blueswir1 | tcg_gen_ld_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, fpr[src])); |
139 | 8911f501 | blueswir1 | tcg_gen_st_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, dt0) + offsetof(CPU_DoubleU, l.upper)); |
140 | 8911f501 | blueswir1 | tcg_gen_ld_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, fpr[src + 1]));
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141 | 8911f501 | blueswir1 | tcg_gen_st_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, dt0) + offsetof(CPU_DoubleU, l.lower)); |
142 | ff07ec83 | blueswir1 | } |
143 | ff07ec83 | blueswir1 | |
144 | ff07ec83 | blueswir1 | static void gen_op_load_fpr_DT1(unsigned int src) |
145 | ff07ec83 | blueswir1 | { |
146 | 8911f501 | blueswir1 | tcg_gen_ld_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, fpr[src])); |
147 | 8911f501 | blueswir1 | tcg_gen_st_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, dt1) + offsetof(CPU_DoubleU, l.upper)); |
148 | 8911f501 | blueswir1 | tcg_gen_ld_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, fpr[src + 1]));
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149 | 8911f501 | blueswir1 | tcg_gen_st_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, dt1) + offsetof(CPU_DoubleU, l.lower)); |
150 | ff07ec83 | blueswir1 | } |
151 | ff07ec83 | blueswir1 | |
152 | ff07ec83 | blueswir1 | static void gen_op_store_DT0_fpr(unsigned int dst) |
153 | ff07ec83 | blueswir1 | { |
154 | 8911f501 | blueswir1 | tcg_gen_ld_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, dt0) + offsetof(CPU_DoubleU, l.upper)); |
155 | 8911f501 | blueswir1 | tcg_gen_st_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, fpr[dst])); |
156 | 8911f501 | blueswir1 | tcg_gen_ld_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, dt0) + offsetof(CPU_DoubleU, l.lower)); |
157 | 8911f501 | blueswir1 | tcg_gen_st_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, fpr[dst + 1]));
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158 | ff07ec83 | blueswir1 | } |
159 | ff07ec83 | blueswir1 | |
160 | ff07ec83 | blueswir1 | #ifdef CONFIG_USER_ONLY
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161 | ff07ec83 | blueswir1 | static void gen_op_load_fpr_QT0(unsigned int src) |
162 | ff07ec83 | blueswir1 | { |
163 | 8911f501 | blueswir1 | tcg_gen_ld_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, fpr[src])); |
164 | 8911f501 | blueswir1 | tcg_gen_st_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, qt0) + offsetof(CPU_QuadU, l.upmost)); |
165 | 8911f501 | blueswir1 | tcg_gen_ld_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, fpr[src + 1]));
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166 | 8911f501 | blueswir1 | tcg_gen_st_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, qt0) + offsetof(CPU_QuadU, l.upper)); |
167 | 8911f501 | blueswir1 | tcg_gen_ld_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, fpr[src + 2]));
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168 | 8911f501 | blueswir1 | tcg_gen_st_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, qt0) + offsetof(CPU_QuadU, l.lower)); |
169 | 8911f501 | blueswir1 | tcg_gen_ld_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, fpr[src + 3]));
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170 | 8911f501 | blueswir1 | tcg_gen_st_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, qt0) + offsetof(CPU_QuadU, l.lowest)); |
171 | ff07ec83 | blueswir1 | } |
172 | ff07ec83 | blueswir1 | |
173 | ff07ec83 | blueswir1 | static void gen_op_load_fpr_QT1(unsigned int src) |
174 | ff07ec83 | blueswir1 | { |
175 | 8911f501 | blueswir1 | tcg_gen_ld_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, fpr[src])); |
176 | 8911f501 | blueswir1 | tcg_gen_st_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, qt1) + offsetof(CPU_QuadU, l.upmost)); |
177 | 8911f501 | blueswir1 | tcg_gen_ld_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, fpr[src + 1]));
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178 | 8911f501 | blueswir1 | tcg_gen_st_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, qt1) + offsetof(CPU_QuadU, l.upper)); |
179 | 8911f501 | blueswir1 | tcg_gen_ld_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, fpr[src + 2]));
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180 | 8911f501 | blueswir1 | tcg_gen_st_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, qt1) + offsetof(CPU_QuadU, l.lower)); |
181 | 8911f501 | blueswir1 | tcg_gen_ld_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, fpr[src + 3]));
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182 | 8911f501 | blueswir1 | tcg_gen_st_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, qt1) + offsetof(CPU_QuadU, l.lowest)); |
183 | ff07ec83 | blueswir1 | } |
184 | ff07ec83 | blueswir1 | |
185 | ff07ec83 | blueswir1 | static void gen_op_store_QT0_fpr(unsigned int dst) |
186 | ff07ec83 | blueswir1 | { |
187 | 8911f501 | blueswir1 | tcg_gen_ld_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, qt0) + offsetof(CPU_QuadU, l.upmost)); |
188 | 8911f501 | blueswir1 | tcg_gen_st_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, fpr[dst])); |
189 | 8911f501 | blueswir1 | tcg_gen_ld_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, qt0) + offsetof(CPU_QuadU, l.upper)); |
190 | 8911f501 | blueswir1 | tcg_gen_st_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, fpr[dst + 1]));
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191 | 8911f501 | blueswir1 | tcg_gen_ld_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, qt0) + offsetof(CPU_QuadU, l.lower)); |
192 | 8911f501 | blueswir1 | tcg_gen_st_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, fpr[dst + 2]));
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193 | 8911f501 | blueswir1 | tcg_gen_ld_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, qt0) + offsetof(CPU_QuadU, l.lowest)); |
194 | 8911f501 | blueswir1 | tcg_gen_st_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, fpr[dst + 3]));
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195 | ff07ec83 | blueswir1 | } |
196 | 1f587329 | blueswir1 | #endif
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197 | 1f587329 | blueswir1 | |
198 | 81ad8ba2 | blueswir1 | /* moves */
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199 | 81ad8ba2 | blueswir1 | #ifdef CONFIG_USER_ONLY
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200 | 3475187d | bellard | #define supervisor(dc) 0 |
201 | 81ad8ba2 | blueswir1 | #ifdef TARGET_SPARC64
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202 | e9ebed4d | blueswir1 | #define hypervisor(dc) 0 |
203 | 81ad8ba2 | blueswir1 | #endif
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204 | 3475187d | bellard | #define gen_op_ldst(name) gen_op_##name##_raw() |
205 | 3475187d | bellard | #else
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206 | 6f27aba6 | blueswir1 | #define supervisor(dc) (dc->mem_idx >= 1) |
207 | 81ad8ba2 | blueswir1 | #ifdef TARGET_SPARC64
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208 | 81ad8ba2 | blueswir1 | #define hypervisor(dc) (dc->mem_idx == 2) |
209 | 6f27aba6 | blueswir1 | #define OP_LD_TABLE(width) \
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210 | 6f27aba6 | blueswir1 | static GenOpFunc * const gen_op_##width[] = { \ |
211 | 6f27aba6 | blueswir1 | &gen_op_##width##_user, \ |
212 | 6f27aba6 | blueswir1 | &gen_op_##width##_kernel, \ |
213 | 6f27aba6 | blueswir1 | &gen_op_##width##_hypv, \ |
214 | 6f27aba6 | blueswir1 | }; |
215 | 6f27aba6 | blueswir1 | #else
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216 | 0f8a249a | blueswir1 | #define OP_LD_TABLE(width) \
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217 | a68156d0 | blueswir1 | static GenOpFunc * const gen_op_##width[] = { \ |
218 | 0f8a249a | blueswir1 | &gen_op_##width##_user, \ |
219 | 0f8a249a | blueswir1 | &gen_op_##width##_kernel, \ |
220 | 81ad8ba2 | blueswir1 | }; |
221 | 3475187d | bellard | #endif
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222 | 6f27aba6 | blueswir1 | #define gen_op_ldst(name) (*gen_op_##name[dc->mem_idx])() |
223 | 6f27aba6 | blueswir1 | #endif
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224 | e8af50a3 | bellard | |
225 | 81ad8ba2 | blueswir1 | #ifndef CONFIG_USER_ONLY
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226 | b25deda7 | blueswir1 | #ifdef __i386__
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227 | b25deda7 | blueswir1 | OP_LD_TABLE(std); |
228 | b25deda7 | blueswir1 | #endif /* __i386__ */ |
229 | e8af50a3 | bellard | OP_LD_TABLE(stdf); |
230 | e8af50a3 | bellard | OP_LD_TABLE(lddf); |
231 | 81ad8ba2 | blueswir1 | #endif
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232 | 81ad8ba2 | blueswir1 | |
233 | 1a2fb1c0 | blueswir1 | #ifdef TARGET_ABI32
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234 | 8911f501 | blueswir1 | #define ABI32_MASK(addr) tcg_gen_andi_tl(addr, addr, 0xffffffffULL); |
235 | 1a2fb1c0 | blueswir1 | #else
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236 | 1a2fb1c0 | blueswir1 | #define ABI32_MASK(addr)
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237 | 1a2fb1c0 | blueswir1 | #endif
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238 | 3391c818 | blueswir1 | |
239 | 1a2fb1c0 | blueswir1 | static inline void gen_movl_simm_T1(int32_t val) |
240 | 81ad8ba2 | blueswir1 | { |
241 | 1a2fb1c0 | blueswir1 | tcg_gen_movi_tl(cpu_T[1], val);
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242 | 81ad8ba2 | blueswir1 | } |
243 | 81ad8ba2 | blueswir1 | |
244 | 1a2fb1c0 | blueswir1 | static inline void gen_movl_reg_TN(int reg, TCGv tn) |
245 | 81ad8ba2 | blueswir1 | { |
246 | 1a2fb1c0 | blueswir1 | if (reg == 0) |
247 | 1a2fb1c0 | blueswir1 | tcg_gen_movi_tl(tn, 0);
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248 | 1a2fb1c0 | blueswir1 | else if (reg < 8) |
249 | f5069b26 | blueswir1 | tcg_gen_mov_tl(tn, cpu_gregs[reg]); |
250 | 1a2fb1c0 | blueswir1 | else {
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251 | 1a2fb1c0 | blueswir1 | tcg_gen_ld_tl(tn, cpu_regwptr, (reg - 8) * sizeof(target_ulong)); |
252 | 81ad8ba2 | blueswir1 | } |
253 | 81ad8ba2 | blueswir1 | } |
254 | 81ad8ba2 | blueswir1 | |
255 | 1a2fb1c0 | blueswir1 | static inline void gen_movl_reg_T0(int reg) |
256 | 81ad8ba2 | blueswir1 | { |
257 | 1a2fb1c0 | blueswir1 | gen_movl_reg_TN(reg, cpu_T[0]);
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258 | 81ad8ba2 | blueswir1 | } |
259 | 81ad8ba2 | blueswir1 | |
260 | 1a2fb1c0 | blueswir1 | static inline void gen_movl_reg_T1(int reg) |
261 | 81ad8ba2 | blueswir1 | { |
262 | 1a2fb1c0 | blueswir1 | gen_movl_reg_TN(reg, cpu_T[1]);
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263 | 81ad8ba2 | blueswir1 | } |
264 | 81ad8ba2 | blueswir1 | |
265 | b25deda7 | blueswir1 | #ifdef __i386__
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266 | b25deda7 | blueswir1 | static inline void gen_movl_reg_T2(int reg) |
267 | b25deda7 | blueswir1 | { |
268 | b25deda7 | blueswir1 | gen_movl_reg_TN(reg, cpu_T[2]);
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269 | b25deda7 | blueswir1 | } |
270 | b25deda7 | blueswir1 | |
271 | b25deda7 | blueswir1 | #endif /* __i386__ */ |
272 | 1a2fb1c0 | blueswir1 | static inline void gen_movl_TN_reg(int reg, TCGv tn) |
273 | 81ad8ba2 | blueswir1 | { |
274 | 1a2fb1c0 | blueswir1 | if (reg == 0) |
275 | 1a2fb1c0 | blueswir1 | return;
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276 | 1a2fb1c0 | blueswir1 | else if (reg < 8) |
277 | f5069b26 | blueswir1 | tcg_gen_mov_tl(cpu_gregs[reg], tn); |
278 | 1a2fb1c0 | blueswir1 | else {
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279 | 1a2fb1c0 | blueswir1 | tcg_gen_st_tl(tn, cpu_regwptr, (reg - 8) * sizeof(target_ulong)); |
280 | 81ad8ba2 | blueswir1 | } |
281 | 81ad8ba2 | blueswir1 | } |
282 | 81ad8ba2 | blueswir1 | |
283 | 1a2fb1c0 | blueswir1 | static inline void gen_movl_T0_reg(int reg) |
284 | 3475187d | bellard | { |
285 | 1a2fb1c0 | blueswir1 | gen_movl_TN_reg(reg, cpu_T[0]);
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286 | 3475187d | bellard | } |
287 | 3475187d | bellard | |
288 | 1a2fb1c0 | blueswir1 | static inline void gen_movl_T1_reg(int reg) |
289 | 3475187d | bellard | { |
290 | 1a2fb1c0 | blueswir1 | gen_movl_TN_reg(reg, cpu_T[1]);
|
291 | 3475187d | bellard | } |
292 | 3475187d | bellard | |
293 | 1a2fb1c0 | blueswir1 | static inline void gen_op_movl_T0_env(size_t offset) |
294 | 7a3f1944 | bellard | { |
295 | 8911f501 | blueswir1 | tcg_gen_ld_i32(cpu_tmp32, cpu_env, offset); |
296 | 8911f501 | blueswir1 | tcg_gen_ext_i32_tl(cpu_T[0], cpu_tmp32);
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297 | 7a3f1944 | bellard | } |
298 | 7a3f1944 | bellard | |
299 | 1a2fb1c0 | blueswir1 | static inline void gen_op_movl_env_T0(size_t offset) |
300 | 7a3f1944 | bellard | { |
301 | 8911f501 | blueswir1 | tcg_gen_trunc_tl_i32(cpu_tmp32, cpu_T[0]);
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302 | 8911f501 | blueswir1 | tcg_gen_st_i32(cpu_tmp32, cpu_env, offset); |
303 | 7a3f1944 | bellard | } |
304 | 7a3f1944 | bellard | |
305 | 1a2fb1c0 | blueswir1 | static inline void gen_op_movtl_T0_env(size_t offset) |
306 | 7a3f1944 | bellard | { |
307 | 1a2fb1c0 | blueswir1 | tcg_gen_ld_tl(cpu_T[0], cpu_env, offset);
|
308 | 7a3f1944 | bellard | } |
309 | 7a3f1944 | bellard | |
310 | 1a2fb1c0 | blueswir1 | static inline void gen_op_movtl_env_T0(size_t offset) |
311 | 7a3f1944 | bellard | { |
312 | 1a2fb1c0 | blueswir1 | tcg_gen_st_tl(cpu_T[0], cpu_env, offset);
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313 | 7a3f1944 | bellard | } |
314 | 7a3f1944 | bellard | |
315 | 1a2fb1c0 | blueswir1 | static inline void gen_op_add_T1_T0(void) |
316 | 7a3f1944 | bellard | { |
317 | 1a2fb1c0 | blueswir1 | tcg_gen_add_tl(cpu_T[0], cpu_T[0], cpu_T[1]); |
318 | 7a3f1944 | bellard | } |
319 | 7a3f1944 | bellard | |
320 | 1a2fb1c0 | blueswir1 | static inline void gen_op_or_T1_T0(void) |
321 | 7a3f1944 | bellard | { |
322 | 1a2fb1c0 | blueswir1 | tcg_gen_or_tl(cpu_T[0], cpu_T[0], cpu_T[1]); |
323 | 7a3f1944 | bellard | } |
324 | 7a3f1944 | bellard | |
325 | 1a2fb1c0 | blueswir1 | static inline void gen_op_xor_T1_T0(void) |
326 | 7a3f1944 | bellard | { |
327 | 1a2fb1c0 | blueswir1 | tcg_gen_xor_tl(cpu_T[0], cpu_T[0], cpu_T[1]); |
328 | 7a3f1944 | bellard | } |
329 | 7a3f1944 | bellard | |
330 | 3475187d | bellard | static inline void gen_jmp_im(target_ulong pc) |
331 | 3475187d | bellard | { |
332 | 48d5c82b | blueswir1 | tcg_gen_movi_tl(cpu_pc, pc); |
333 | 3475187d | bellard | } |
334 | 3475187d | bellard | |
335 | 3475187d | bellard | static inline void gen_movl_npc_im(target_ulong npc) |
336 | 3475187d | bellard | { |
337 | 48d5c82b | blueswir1 | tcg_gen_movi_tl(cpu_npc, npc); |
338 | 3475187d | bellard | } |
339 | 3475187d | bellard | |
340 | 5fafdf24 | ths | static inline void gen_goto_tb(DisasContext *s, int tb_num, |
341 | 6e256c93 | bellard | target_ulong pc, target_ulong npc) |
342 | 6e256c93 | bellard | { |
343 | 6e256c93 | bellard | TranslationBlock *tb; |
344 | 6e256c93 | bellard | |
345 | 6e256c93 | bellard | tb = s->tb; |
346 | 6e256c93 | bellard | if ((pc & TARGET_PAGE_MASK) == (tb->pc & TARGET_PAGE_MASK) &&
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347 | 6e256c93 | bellard | (npc & TARGET_PAGE_MASK) == (tb->pc & TARGET_PAGE_MASK)) { |
348 | 6e256c93 | bellard | /* jump to same page: we can use a direct jump */
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349 | 57fec1fe | bellard | tcg_gen_goto_tb(tb_num); |
350 | 6e256c93 | bellard | gen_jmp_im(pc); |
351 | 6e256c93 | bellard | gen_movl_npc_im(npc); |
352 | 57fec1fe | bellard | tcg_gen_exit_tb((long)tb + tb_num);
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353 | 6e256c93 | bellard | } else {
|
354 | 6e256c93 | bellard | /* jump to another page: currently not optimized */
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355 | 6e256c93 | bellard | gen_jmp_im(pc); |
356 | 6e256c93 | bellard | gen_movl_npc_im(npc); |
357 | 57fec1fe | bellard | tcg_gen_exit_tb(0);
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358 | 6e256c93 | bellard | } |
359 | 6e256c93 | bellard | } |
360 | 6e256c93 | bellard | |
361 | 19f329ad | blueswir1 | // XXX suboptimal
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362 | 19f329ad | blueswir1 | static inline void gen_mov_reg_N(TCGv reg, TCGv src) |
363 | 19f329ad | blueswir1 | { |
364 | 8911f501 | blueswir1 | tcg_gen_extu_i32_tl(reg, src); |
365 | 8911f501 | blueswir1 | tcg_gen_shri_tl(reg, reg, 23);
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366 | 19f329ad | blueswir1 | tcg_gen_andi_tl(reg, reg, 0x1);
|
367 | 19f329ad | blueswir1 | } |
368 | 19f329ad | blueswir1 | |
369 | 19f329ad | blueswir1 | static inline void gen_mov_reg_Z(TCGv reg, TCGv src) |
370 | 19f329ad | blueswir1 | { |
371 | 8911f501 | blueswir1 | tcg_gen_extu_i32_tl(reg, src); |
372 | 8911f501 | blueswir1 | tcg_gen_shri_tl(reg, reg, 22);
|
373 | 19f329ad | blueswir1 | tcg_gen_andi_tl(reg, reg, 0x1);
|
374 | 19f329ad | blueswir1 | } |
375 | 19f329ad | blueswir1 | |
376 | 19f329ad | blueswir1 | static inline void gen_mov_reg_V(TCGv reg, TCGv src) |
377 | 19f329ad | blueswir1 | { |
378 | 8911f501 | blueswir1 | tcg_gen_extu_i32_tl(reg, src); |
379 | 8911f501 | blueswir1 | tcg_gen_shri_tl(reg, reg, 21);
|
380 | 19f329ad | blueswir1 | tcg_gen_andi_tl(reg, reg, 0x1);
|
381 | 19f329ad | blueswir1 | } |
382 | 19f329ad | blueswir1 | |
383 | 19f329ad | blueswir1 | static inline void gen_mov_reg_C(TCGv reg, TCGv src) |
384 | 19f329ad | blueswir1 | { |
385 | 8911f501 | blueswir1 | tcg_gen_extu_i32_tl(reg, src); |
386 | 8911f501 | blueswir1 | tcg_gen_shri_tl(reg, reg, 20);
|
387 | 19f329ad | blueswir1 | tcg_gen_andi_tl(reg, reg, 0x1);
|
388 | 19f329ad | blueswir1 | } |
389 | 19f329ad | blueswir1 | |
390 | dc99a3f2 | blueswir1 | static inline void gen_op_exception(int exception) |
391 | dc99a3f2 | blueswir1 | { |
392 | 8911f501 | blueswir1 | tcg_gen_movi_i32(cpu_tmp32, exception); |
393 | 8911f501 | blueswir1 | tcg_gen_helper_0_1(raise_exception, cpu_tmp32); |
394 | dc99a3f2 | blueswir1 | } |
395 | dc99a3f2 | blueswir1 | |
396 | dc99a3f2 | blueswir1 | static inline void gen_cc_clear(void) |
397 | dc99a3f2 | blueswir1 | { |
398 | dc99a3f2 | blueswir1 | tcg_gen_movi_i32(cpu_psr, 0);
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399 | dc99a3f2 | blueswir1 | #ifdef TARGET_SPARC64
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400 | dc99a3f2 | blueswir1 | tcg_gen_movi_i32(cpu_xcc, 0);
|
401 | dc99a3f2 | blueswir1 | #endif
|
402 | dc99a3f2 | blueswir1 | } |
403 | dc99a3f2 | blueswir1 | |
404 | dc99a3f2 | blueswir1 | /* old op:
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405 | dc99a3f2 | blueswir1 | if (!T0)
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406 | dc99a3f2 | blueswir1 | env->psr |= PSR_ZERO;
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407 | dc99a3f2 | blueswir1 | if ((int32_t) T0 < 0)
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408 | dc99a3f2 | blueswir1 | env->psr |= PSR_NEG;
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409 | dc99a3f2 | blueswir1 | */
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410 | dc99a3f2 | blueswir1 | static inline void gen_cc_NZ(TCGv dst) |
411 | dc99a3f2 | blueswir1 | { |
412 | 8911f501 | blueswir1 | TCGv r_temp; |
413 | dc99a3f2 | blueswir1 | int l1, l2;
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414 | dc99a3f2 | blueswir1 | |
415 | dc99a3f2 | blueswir1 | l1 = gen_new_label(); |
416 | dc99a3f2 | blueswir1 | l2 = gen_new_label(); |
417 | 8911f501 | blueswir1 | r_temp = tcg_temp_new(TCG_TYPE_TL); |
418 | 8911f501 | blueswir1 | tcg_gen_andi_tl(r_temp, dst, 0xffffffffULL);
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419 | 8911f501 | blueswir1 | tcg_gen_brcond_tl(TCG_COND_NE, r_temp, tcg_const_tl(0), l1);
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420 | dc99a3f2 | blueswir1 | tcg_gen_ori_i32(cpu_psr, cpu_psr, PSR_ZERO); |
421 | dc99a3f2 | blueswir1 | gen_set_label(l1); |
422 | 8911f501 | blueswir1 | tcg_gen_andi_tl(r_temp, dst, 0xffffffffULL);
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423 | 8911f501 | blueswir1 | tcg_gen_brcond_tl(TCG_COND_GE, r_temp, tcg_const_tl(0), l2);
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424 | dc99a3f2 | blueswir1 | tcg_gen_ori_i32(cpu_psr, cpu_psr, PSR_NEG); |
425 | dc99a3f2 | blueswir1 | gen_set_label(l2); |
426 | dc99a3f2 | blueswir1 | #ifdef TARGET_SPARC64
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427 | dc99a3f2 | blueswir1 | { |
428 | dc99a3f2 | blueswir1 | int l3, l4;
|
429 | dc99a3f2 | blueswir1 | |
430 | dc99a3f2 | blueswir1 | l3 = gen_new_label(); |
431 | dc99a3f2 | blueswir1 | l4 = gen_new_label(); |
432 | 0425bee5 | blueswir1 | tcg_gen_brcond_tl(TCG_COND_NE, dst, tcg_const_tl(0), l3);
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433 | dc99a3f2 | blueswir1 | tcg_gen_ori_i32(cpu_xcc, cpu_xcc, PSR_ZERO); |
434 | dc99a3f2 | blueswir1 | gen_set_label(l3); |
435 | 0425bee5 | blueswir1 | tcg_gen_brcond_tl(TCG_COND_GE, dst, tcg_const_tl(0), l4);
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436 | dc99a3f2 | blueswir1 | tcg_gen_ori_i32(cpu_xcc, cpu_xcc, PSR_NEG); |
437 | dc99a3f2 | blueswir1 | gen_set_label(l4); |
438 | dc99a3f2 | blueswir1 | } |
439 | dc99a3f2 | blueswir1 | #endif
|
440 | dc99a3f2 | blueswir1 | } |
441 | dc99a3f2 | blueswir1 | |
442 | dc99a3f2 | blueswir1 | /* old op:
|
443 | dc99a3f2 | blueswir1 | if (T0 < src1)
|
444 | dc99a3f2 | blueswir1 | env->psr |= PSR_CARRY;
|
445 | dc99a3f2 | blueswir1 | */
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446 | dc99a3f2 | blueswir1 | static inline void gen_cc_C_add(TCGv dst, TCGv src1) |
447 | dc99a3f2 | blueswir1 | { |
448 | 8911f501 | blueswir1 | TCGv r_temp; |
449 | dc99a3f2 | blueswir1 | int l1;
|
450 | dc99a3f2 | blueswir1 | |
451 | dc99a3f2 | blueswir1 | l1 = gen_new_label(); |
452 | 8911f501 | blueswir1 | r_temp = tcg_temp_new(TCG_TYPE_TL); |
453 | 8911f501 | blueswir1 | tcg_gen_andi_tl(r_temp, dst, 0xffffffffULL);
|
454 | 8911f501 | blueswir1 | tcg_gen_brcond_tl(TCG_COND_GEU, dst, src1, l1); |
455 | dc99a3f2 | blueswir1 | tcg_gen_ori_i32(cpu_psr, cpu_psr, PSR_CARRY); |
456 | dc99a3f2 | blueswir1 | gen_set_label(l1); |
457 | dc99a3f2 | blueswir1 | #ifdef TARGET_SPARC64
|
458 | dc99a3f2 | blueswir1 | { |
459 | dc99a3f2 | blueswir1 | int l2;
|
460 | dc99a3f2 | blueswir1 | |
461 | dc99a3f2 | blueswir1 | l2 = gen_new_label(); |
462 | dc99a3f2 | blueswir1 | tcg_gen_brcond_tl(TCG_COND_GEU, dst, src1, l2); |
463 | dc99a3f2 | blueswir1 | tcg_gen_ori_i32(cpu_xcc, cpu_xcc, PSR_CARRY); |
464 | dc99a3f2 | blueswir1 | gen_set_label(l2); |
465 | dc99a3f2 | blueswir1 | } |
466 | dc99a3f2 | blueswir1 | #endif
|
467 | dc99a3f2 | blueswir1 | } |
468 | dc99a3f2 | blueswir1 | |
469 | dc99a3f2 | blueswir1 | /* old op:
|
470 | dc99a3f2 | blueswir1 | if (((src1 ^ T1 ^ -1) & (src1 ^ T0)) & (1 << 31))
|
471 | dc99a3f2 | blueswir1 | env->psr |= PSR_OVF;
|
472 | dc99a3f2 | blueswir1 | */
|
473 | dc99a3f2 | blueswir1 | static inline void gen_cc_V_add(TCGv dst, TCGv src1, TCGv src2) |
474 | dc99a3f2 | blueswir1 | { |
475 | 0425bee5 | blueswir1 | TCGv r_temp; |
476 | dc99a3f2 | blueswir1 | int l1;
|
477 | dc99a3f2 | blueswir1 | |
478 | dc99a3f2 | blueswir1 | l1 = gen_new_label(); |
479 | dc99a3f2 | blueswir1 | |
480 | dc99a3f2 | blueswir1 | r_temp = tcg_temp_new(TCG_TYPE_TL); |
481 | dc99a3f2 | blueswir1 | tcg_gen_xor_tl(r_temp, src1, src2); |
482 | dc99a3f2 | blueswir1 | tcg_gen_xori_tl(r_temp, r_temp, -1);
|
483 | 0425bee5 | blueswir1 | tcg_gen_xor_tl(cpu_tmp0, src1, dst); |
484 | 0425bee5 | blueswir1 | tcg_gen_and_tl(r_temp, r_temp, cpu_tmp0); |
485 | 0425bee5 | blueswir1 | tcg_gen_andi_tl(r_temp, r_temp, (1 << 31)); |
486 | 8911f501 | blueswir1 | tcg_gen_brcond_tl(TCG_COND_EQ, r_temp, tcg_const_tl(0), l1);
|
487 | dc99a3f2 | blueswir1 | tcg_gen_ori_i32(cpu_psr, cpu_psr, PSR_OVF); |
488 | dc99a3f2 | blueswir1 | gen_set_label(l1); |
489 | dc99a3f2 | blueswir1 | #ifdef TARGET_SPARC64
|
490 | dc99a3f2 | blueswir1 | { |
491 | dc99a3f2 | blueswir1 | int l2;
|
492 | dc99a3f2 | blueswir1 | |
493 | dc99a3f2 | blueswir1 | l2 = gen_new_label(); |
494 | dc99a3f2 | blueswir1 | tcg_gen_xor_tl(r_temp, src1, src2); |
495 | dc99a3f2 | blueswir1 | tcg_gen_xori_tl(r_temp, r_temp, -1);
|
496 | 0425bee5 | blueswir1 | tcg_gen_xor_tl(cpu_tmp0, src1, dst); |
497 | 0425bee5 | blueswir1 | tcg_gen_and_tl(r_temp, r_temp, cpu_tmp0); |
498 | 0425bee5 | blueswir1 | tcg_gen_andi_tl(r_temp, r_temp, (1ULL << 63)); |
499 | 0425bee5 | blueswir1 | tcg_gen_brcond_tl(TCG_COND_EQ, r_temp, tcg_const_tl(0), l2);
|
500 | dc99a3f2 | blueswir1 | tcg_gen_ori_i32(cpu_xcc, cpu_xcc, PSR_OVF); |
501 | dc99a3f2 | blueswir1 | gen_set_label(l2); |
502 | dc99a3f2 | blueswir1 | } |
503 | dc99a3f2 | blueswir1 | #endif
|
504 | 0425bee5 | blueswir1 | tcg_gen_discard_tl(r_temp); |
505 | dc99a3f2 | blueswir1 | } |
506 | dc99a3f2 | blueswir1 | |
507 | dc99a3f2 | blueswir1 | static inline void gen_add_tv(TCGv dst, TCGv src1, TCGv src2) |
508 | dc99a3f2 | blueswir1 | { |
509 | 0425bee5 | blueswir1 | TCGv r_temp; |
510 | dc99a3f2 | blueswir1 | int l1;
|
511 | dc99a3f2 | blueswir1 | |
512 | dc99a3f2 | blueswir1 | l1 = gen_new_label(); |
513 | dc99a3f2 | blueswir1 | |
514 | dc99a3f2 | blueswir1 | r_temp = tcg_temp_new(TCG_TYPE_TL); |
515 | dc99a3f2 | blueswir1 | tcg_gen_xor_tl(r_temp, src1, src2); |
516 | dc99a3f2 | blueswir1 | tcg_gen_xori_tl(r_temp, r_temp, -1);
|
517 | 0425bee5 | blueswir1 | tcg_gen_xor_tl(cpu_tmp0, src1, dst); |
518 | 0425bee5 | blueswir1 | tcg_gen_and_tl(r_temp, r_temp, cpu_tmp0); |
519 | 0425bee5 | blueswir1 | tcg_gen_andi_tl(r_temp, r_temp, (1 << 31)); |
520 | 8911f501 | blueswir1 | tcg_gen_brcond_tl(TCG_COND_EQ, r_temp, tcg_const_tl(0), l1);
|
521 | dc99a3f2 | blueswir1 | gen_op_exception(TT_TOVF); |
522 | dc99a3f2 | blueswir1 | gen_set_label(l1); |
523 | dc99a3f2 | blueswir1 | #ifdef TARGET_SPARC64
|
524 | dc99a3f2 | blueswir1 | { |
525 | dc99a3f2 | blueswir1 | int l2;
|
526 | dc99a3f2 | blueswir1 | |
527 | dc99a3f2 | blueswir1 | l2 = gen_new_label(); |
528 | dc99a3f2 | blueswir1 | tcg_gen_xor_tl(r_temp, src1, src2); |
529 | dc99a3f2 | blueswir1 | tcg_gen_xori_tl(r_temp, r_temp, -1);
|
530 | 0425bee5 | blueswir1 | tcg_gen_xor_tl(cpu_tmp0, src1, dst); |
531 | 0425bee5 | blueswir1 | tcg_gen_and_tl(r_temp, r_temp, cpu_tmp0); |
532 | 0425bee5 | blueswir1 | tcg_gen_andi_tl(r_temp, r_temp, (1ULL << 63)); |
533 | 0425bee5 | blueswir1 | tcg_gen_brcond_tl(TCG_COND_EQ, r_temp, tcg_const_tl(0), l2);
|
534 | dc99a3f2 | blueswir1 | gen_op_exception(TT_TOVF); |
535 | dc99a3f2 | blueswir1 | gen_set_label(l2); |
536 | dc99a3f2 | blueswir1 | } |
537 | dc99a3f2 | blueswir1 | #endif
|
538 | 0425bee5 | blueswir1 | tcg_gen_discard_tl(r_temp); |
539 | dc99a3f2 | blueswir1 | } |
540 | dc99a3f2 | blueswir1 | |
541 | dc99a3f2 | blueswir1 | static inline void gen_cc_V_tag(TCGv src1, TCGv src2) |
542 | dc99a3f2 | blueswir1 | { |
543 | dc99a3f2 | blueswir1 | int l1;
|
544 | dc99a3f2 | blueswir1 | |
545 | dc99a3f2 | blueswir1 | l1 = gen_new_label(); |
546 | 0425bee5 | blueswir1 | tcg_gen_or_tl(cpu_tmp0, src1, src2); |
547 | 0425bee5 | blueswir1 | tcg_gen_andi_tl(cpu_tmp0, cpu_tmp0, 0x3);
|
548 | 0425bee5 | blueswir1 | tcg_gen_brcond_tl(TCG_COND_EQ, cpu_tmp0, tcg_const_tl(0), l1);
|
549 | dc99a3f2 | blueswir1 | tcg_gen_ori_i32(cpu_psr, cpu_psr, PSR_OVF); |
550 | dc99a3f2 | blueswir1 | gen_set_label(l1); |
551 | dc99a3f2 | blueswir1 | } |
552 | dc99a3f2 | blueswir1 | |
553 | dc99a3f2 | blueswir1 | static inline void gen_tag_tv(TCGv src1, TCGv src2) |
554 | dc99a3f2 | blueswir1 | { |
555 | dc99a3f2 | blueswir1 | int l1;
|
556 | dc99a3f2 | blueswir1 | |
557 | dc99a3f2 | blueswir1 | l1 = gen_new_label(); |
558 | 0425bee5 | blueswir1 | tcg_gen_or_tl(cpu_tmp0, src1, src2); |
559 | 0425bee5 | blueswir1 | tcg_gen_andi_tl(cpu_tmp0, cpu_tmp0, 0x3);
|
560 | 0425bee5 | blueswir1 | tcg_gen_brcond_tl(TCG_COND_EQ, cpu_tmp0, tcg_const_tl(0), l1);
|
561 | dc99a3f2 | blueswir1 | gen_op_exception(TT_TOVF); |
562 | dc99a3f2 | blueswir1 | gen_set_label(l1); |
563 | dc99a3f2 | blueswir1 | } |
564 | dc99a3f2 | blueswir1 | |
565 | dc99a3f2 | blueswir1 | static inline void gen_op_add_T1_T0_cc(void) |
566 | dc99a3f2 | blueswir1 | { |
567 | dc99a3f2 | blueswir1 | tcg_gen_mov_tl(cpu_cc_src, cpu_T[0]);
|
568 | dc99a3f2 | blueswir1 | tcg_gen_add_tl(cpu_T[0], cpu_T[0], cpu_T[1]); |
569 | dc99a3f2 | blueswir1 | gen_cc_clear(); |
570 | dc99a3f2 | blueswir1 | gen_cc_NZ(cpu_T[0]);
|
571 | dc99a3f2 | blueswir1 | gen_cc_C_add(cpu_T[0], cpu_cc_src);
|
572 | dc99a3f2 | blueswir1 | gen_cc_V_add(cpu_T[0], cpu_cc_src, cpu_T[1]); |
573 | dc99a3f2 | blueswir1 | } |
574 | dc99a3f2 | blueswir1 | |
575 | dc99a3f2 | blueswir1 | static inline void gen_op_addx_T1_T0_cc(void) |
576 | dc99a3f2 | blueswir1 | { |
577 | dc99a3f2 | blueswir1 | tcg_gen_mov_tl(cpu_cc_src, cpu_T[0]);
|
578 | dc99a3f2 | blueswir1 | gen_mov_reg_C(cpu_tmp0, cpu_psr); |
579 | dc99a3f2 | blueswir1 | tcg_gen_add_tl(cpu_T[0], cpu_T[0], cpu_tmp0); |
580 | dc99a3f2 | blueswir1 | gen_cc_clear(); |
581 | dc99a3f2 | blueswir1 | gen_cc_C_add(cpu_T[0], cpu_cc_src);
|
582 | dc99a3f2 | blueswir1 | tcg_gen_add_tl(cpu_T[0], cpu_T[0], cpu_T[1]); |
583 | dc99a3f2 | blueswir1 | gen_cc_C_add(cpu_T[0], cpu_cc_src);
|
584 | dc99a3f2 | blueswir1 | gen_cc_NZ(cpu_T[0]);
|
585 | dc99a3f2 | blueswir1 | gen_cc_V_add(cpu_T[0], cpu_cc_src, cpu_T[1]); |
586 | dc99a3f2 | blueswir1 | } |
587 | dc99a3f2 | blueswir1 | |
588 | dc99a3f2 | blueswir1 | static inline void gen_op_tadd_T1_T0_cc(void) |
589 | dc99a3f2 | blueswir1 | { |
590 | dc99a3f2 | blueswir1 | tcg_gen_mov_tl(cpu_cc_src, cpu_T[0]);
|
591 | dc99a3f2 | blueswir1 | tcg_gen_add_tl(cpu_T[0], cpu_T[0], cpu_T[1]); |
592 | dc99a3f2 | blueswir1 | gen_cc_clear(); |
593 | dc99a3f2 | blueswir1 | gen_cc_NZ(cpu_T[0]);
|
594 | dc99a3f2 | blueswir1 | gen_cc_C_add(cpu_T[0], cpu_cc_src);
|
595 | dc99a3f2 | blueswir1 | gen_cc_V_add(cpu_T[0], cpu_cc_src, cpu_T[1]); |
596 | dc99a3f2 | blueswir1 | gen_cc_V_tag(cpu_cc_src, cpu_T[1]);
|
597 | dc99a3f2 | blueswir1 | } |
598 | dc99a3f2 | blueswir1 | |
599 | dc99a3f2 | blueswir1 | static inline void gen_op_tadd_T1_T0_ccTV(void) |
600 | dc99a3f2 | blueswir1 | { |
601 | dc99a3f2 | blueswir1 | gen_tag_tv(cpu_T[0], cpu_T[1]); |
602 | dc99a3f2 | blueswir1 | tcg_gen_mov_tl(cpu_cc_src, cpu_T[0]);
|
603 | dc99a3f2 | blueswir1 | tcg_gen_add_tl(cpu_T[0], cpu_T[0], cpu_T[1]); |
604 | dc99a3f2 | blueswir1 | gen_add_tv(cpu_T[0], cpu_cc_src, cpu_T[1]); |
605 | dc99a3f2 | blueswir1 | gen_cc_clear(); |
606 | dc99a3f2 | blueswir1 | gen_cc_NZ(cpu_T[0]);
|
607 | dc99a3f2 | blueswir1 | gen_cc_C_add(cpu_T[0], cpu_cc_src);
|
608 | dc99a3f2 | blueswir1 | } |
609 | dc99a3f2 | blueswir1 | |
610 | dc99a3f2 | blueswir1 | /* old op:
|
611 | dc99a3f2 | blueswir1 | if (src1 < T1)
|
612 | dc99a3f2 | blueswir1 | env->psr |= PSR_CARRY;
|
613 | dc99a3f2 | blueswir1 | */
|
614 | dc99a3f2 | blueswir1 | static inline void gen_cc_C_sub(TCGv src1, TCGv src2) |
615 | dc99a3f2 | blueswir1 | { |
616 | 8911f501 | blueswir1 | TCGv r_temp1, r_temp2; |
617 | dc99a3f2 | blueswir1 | int l1;
|
618 | dc99a3f2 | blueswir1 | |
619 | dc99a3f2 | blueswir1 | l1 = gen_new_label(); |
620 | 8911f501 | blueswir1 | r_temp1 = tcg_temp_new(TCG_TYPE_TL); |
621 | 8911f501 | blueswir1 | r_temp2 = tcg_temp_new(TCG_TYPE_TL); |
622 | 8911f501 | blueswir1 | tcg_gen_andi_tl(r_temp1, src1, 0xffffffffULL);
|
623 | 8911f501 | blueswir1 | tcg_gen_andi_tl(r_temp2, src2, 0xffffffffULL);
|
624 | 8911f501 | blueswir1 | tcg_gen_brcond_tl(TCG_COND_GEU, r_temp1, r_temp2, l1); |
625 | dc99a3f2 | blueswir1 | tcg_gen_ori_i32(cpu_psr, cpu_psr, PSR_CARRY); |
626 | dc99a3f2 | blueswir1 | gen_set_label(l1); |
627 | dc99a3f2 | blueswir1 | #ifdef TARGET_SPARC64
|
628 | dc99a3f2 | blueswir1 | { |
629 | dc99a3f2 | blueswir1 | int l2;
|
630 | dc99a3f2 | blueswir1 | |
631 | dc99a3f2 | blueswir1 | l2 = gen_new_label(); |
632 | dc99a3f2 | blueswir1 | tcg_gen_brcond_tl(TCG_COND_GEU, src1, src2, l2); |
633 | dc99a3f2 | blueswir1 | tcg_gen_ori_i32(cpu_xcc, cpu_xcc, PSR_CARRY); |
634 | dc99a3f2 | blueswir1 | gen_set_label(l2); |
635 | dc99a3f2 | blueswir1 | } |
636 | dc99a3f2 | blueswir1 | #endif
|
637 | dc99a3f2 | blueswir1 | } |
638 | dc99a3f2 | blueswir1 | |
639 | dc99a3f2 | blueswir1 | /* old op:
|
640 | dc99a3f2 | blueswir1 | if (((src1 ^ T1) & (src1 ^ T0)) & (1 << 31))
|
641 | dc99a3f2 | blueswir1 | env->psr |= PSR_OVF;
|
642 | dc99a3f2 | blueswir1 | */
|
643 | dc99a3f2 | blueswir1 | static inline void gen_cc_V_sub(TCGv dst, TCGv src1, TCGv src2) |
644 | dc99a3f2 | blueswir1 | { |
645 | 0425bee5 | blueswir1 | TCGv r_temp; |
646 | dc99a3f2 | blueswir1 | int l1;
|
647 | dc99a3f2 | blueswir1 | |
648 | dc99a3f2 | blueswir1 | l1 = gen_new_label(); |
649 | dc99a3f2 | blueswir1 | |
650 | dc99a3f2 | blueswir1 | r_temp = tcg_temp_new(TCG_TYPE_TL); |
651 | dc99a3f2 | blueswir1 | tcg_gen_xor_tl(r_temp, src1, src2); |
652 | 0425bee5 | blueswir1 | tcg_gen_xor_tl(cpu_tmp0, src1, dst); |
653 | 0425bee5 | blueswir1 | tcg_gen_and_tl(r_temp, r_temp, cpu_tmp0); |
654 | 0425bee5 | blueswir1 | tcg_gen_andi_tl(r_temp, r_temp, (1 << 31)); |
655 | 8911f501 | blueswir1 | tcg_gen_brcond_tl(TCG_COND_EQ, r_temp, tcg_const_tl(0), l1);
|
656 | dc99a3f2 | blueswir1 | tcg_gen_ori_i32(cpu_psr, cpu_psr, PSR_OVF); |
657 | dc99a3f2 | blueswir1 | gen_set_label(l1); |
658 | dc99a3f2 | blueswir1 | #ifdef TARGET_SPARC64
|
659 | dc99a3f2 | blueswir1 | { |
660 | dc99a3f2 | blueswir1 | int l2;
|
661 | dc99a3f2 | blueswir1 | |
662 | dc99a3f2 | blueswir1 | l2 = gen_new_label(); |
663 | dc99a3f2 | blueswir1 | tcg_gen_xor_tl(r_temp, src1, src2); |
664 | 0425bee5 | blueswir1 | tcg_gen_xor_tl(cpu_tmp0, src1, dst); |
665 | 0425bee5 | blueswir1 | tcg_gen_and_tl(r_temp, r_temp, cpu_tmp0); |
666 | 0425bee5 | blueswir1 | tcg_gen_andi_tl(r_temp, r_temp, (1ULL << 63)); |
667 | 0425bee5 | blueswir1 | tcg_gen_brcond_tl(TCG_COND_EQ, r_temp, tcg_const_tl(0), l2);
|
668 | dc99a3f2 | blueswir1 | tcg_gen_ori_i32(cpu_xcc, cpu_xcc, PSR_OVF); |
669 | dc99a3f2 | blueswir1 | gen_set_label(l2); |
670 | dc99a3f2 | blueswir1 | } |
671 | dc99a3f2 | blueswir1 | #endif
|
672 | 0425bee5 | blueswir1 | tcg_gen_discard_tl(r_temp); |
673 | dc99a3f2 | blueswir1 | } |
674 | dc99a3f2 | blueswir1 | |
675 | dc99a3f2 | blueswir1 | static inline void gen_sub_tv(TCGv dst, TCGv src1, TCGv src2) |
676 | dc99a3f2 | blueswir1 | { |
677 | 0425bee5 | blueswir1 | TCGv r_temp; |
678 | dc99a3f2 | blueswir1 | int l1;
|
679 | dc99a3f2 | blueswir1 | |
680 | dc99a3f2 | blueswir1 | l1 = gen_new_label(); |
681 | dc99a3f2 | blueswir1 | |
682 | dc99a3f2 | blueswir1 | r_temp = tcg_temp_new(TCG_TYPE_TL); |
683 | dc99a3f2 | blueswir1 | tcg_gen_xor_tl(r_temp, src1, src2); |
684 | 0425bee5 | blueswir1 | tcg_gen_xor_tl(cpu_tmp0, src1, dst); |
685 | 0425bee5 | blueswir1 | tcg_gen_and_tl(r_temp, r_temp, cpu_tmp0); |
686 | 0425bee5 | blueswir1 | tcg_gen_andi_tl(r_temp, r_temp, (1 << 31)); |
687 | 8911f501 | blueswir1 | tcg_gen_brcond_tl(TCG_COND_EQ, r_temp, tcg_const_tl(0), l1);
|
688 | dc99a3f2 | blueswir1 | gen_op_exception(TT_TOVF); |
689 | dc99a3f2 | blueswir1 | gen_set_label(l1); |
690 | dc99a3f2 | blueswir1 | #ifdef TARGET_SPARC64
|
691 | dc99a3f2 | blueswir1 | { |
692 | dc99a3f2 | blueswir1 | int l2;
|
693 | dc99a3f2 | blueswir1 | |
694 | dc99a3f2 | blueswir1 | l2 = gen_new_label(); |
695 | dc99a3f2 | blueswir1 | tcg_gen_xor_tl(r_temp, src1, src2); |
696 | 0425bee5 | blueswir1 | tcg_gen_xor_tl(cpu_tmp0, src1, dst); |
697 | 0425bee5 | blueswir1 | tcg_gen_and_tl(r_temp, r_temp, cpu_tmp0); |
698 | 0425bee5 | blueswir1 | tcg_gen_andi_tl(r_temp, r_temp, (1ULL << 63)); |
699 | 0425bee5 | blueswir1 | tcg_gen_brcond_tl(TCG_COND_EQ, r_temp, tcg_const_tl(0), l2);
|
700 | dc99a3f2 | blueswir1 | gen_op_exception(TT_TOVF); |
701 | dc99a3f2 | blueswir1 | gen_set_label(l2); |
702 | dc99a3f2 | blueswir1 | } |
703 | dc99a3f2 | blueswir1 | #endif
|
704 | 0425bee5 | blueswir1 | tcg_gen_discard_tl(r_temp); |
705 | dc99a3f2 | blueswir1 | } |
706 | dc99a3f2 | blueswir1 | |
707 | dc99a3f2 | blueswir1 | static inline void gen_op_sub_T1_T0_cc(void) |
708 | dc99a3f2 | blueswir1 | { |
709 | dc99a3f2 | blueswir1 | tcg_gen_mov_tl(cpu_cc_src, cpu_T[0]);
|
710 | dc99a3f2 | blueswir1 | tcg_gen_sub_tl(cpu_T[0], cpu_T[0], cpu_T[1]); |
711 | dc99a3f2 | blueswir1 | gen_cc_clear(); |
712 | dc99a3f2 | blueswir1 | gen_cc_NZ(cpu_T[0]);
|
713 | dc99a3f2 | blueswir1 | gen_cc_C_sub(cpu_cc_src, cpu_T[1]);
|
714 | dc99a3f2 | blueswir1 | gen_cc_V_sub(cpu_T[0], cpu_cc_src, cpu_T[1]); |
715 | dc99a3f2 | blueswir1 | } |
716 | dc99a3f2 | blueswir1 | |
717 | dc99a3f2 | blueswir1 | static inline void gen_op_subx_T1_T0_cc(void) |
718 | dc99a3f2 | blueswir1 | { |
719 | dc99a3f2 | blueswir1 | tcg_gen_mov_tl(cpu_cc_src, cpu_T[0]);
|
720 | dc99a3f2 | blueswir1 | gen_mov_reg_C(cpu_tmp0, cpu_psr); |
721 | dc99a3f2 | blueswir1 | tcg_gen_sub_tl(cpu_T[0], cpu_T[0], cpu_tmp0); |
722 | dc99a3f2 | blueswir1 | gen_cc_clear(); |
723 | dc99a3f2 | blueswir1 | gen_cc_C_sub(cpu_T[0], cpu_cc_src);
|
724 | dc99a3f2 | blueswir1 | tcg_gen_sub_tl(cpu_T[0], cpu_T[0], cpu_T[1]); |
725 | dc99a3f2 | blueswir1 | gen_cc_C_sub(cpu_T[0], cpu_cc_src);
|
726 | dc99a3f2 | blueswir1 | gen_cc_NZ(cpu_T[0]);
|
727 | dc99a3f2 | blueswir1 | gen_cc_V_sub(cpu_T[0], cpu_cc_src, cpu_T[1]); |
728 | dc99a3f2 | blueswir1 | } |
729 | dc99a3f2 | blueswir1 | |
730 | dc99a3f2 | blueswir1 | static inline void gen_op_tsub_T1_T0_cc(void) |
731 | dc99a3f2 | blueswir1 | { |
732 | dc99a3f2 | blueswir1 | tcg_gen_mov_tl(cpu_cc_src, cpu_T[0]);
|
733 | dc99a3f2 | blueswir1 | tcg_gen_sub_tl(cpu_T[0], cpu_T[0], cpu_T[1]); |
734 | dc99a3f2 | blueswir1 | gen_cc_clear(); |
735 | dc99a3f2 | blueswir1 | gen_cc_NZ(cpu_T[0]);
|
736 | dc99a3f2 | blueswir1 | gen_cc_C_sub(cpu_cc_src, cpu_T[1]);
|
737 | dc99a3f2 | blueswir1 | gen_cc_V_sub(cpu_T[0], cpu_cc_src, cpu_T[1]); |
738 | dc99a3f2 | blueswir1 | gen_cc_V_tag(cpu_cc_src, cpu_T[1]);
|
739 | dc99a3f2 | blueswir1 | } |
740 | dc99a3f2 | blueswir1 | |
741 | dc99a3f2 | blueswir1 | static inline void gen_op_tsub_T1_T0_ccTV(void) |
742 | dc99a3f2 | blueswir1 | { |
743 | dc99a3f2 | blueswir1 | gen_tag_tv(cpu_T[0], cpu_T[1]); |
744 | dc99a3f2 | blueswir1 | tcg_gen_mov_tl(cpu_cc_src, cpu_T[0]);
|
745 | dc99a3f2 | blueswir1 | tcg_gen_sub_tl(cpu_T[0], cpu_T[0], cpu_T[1]); |
746 | dc99a3f2 | blueswir1 | gen_sub_tv(cpu_T[0], cpu_cc_src, cpu_T[1]); |
747 | dc99a3f2 | blueswir1 | gen_cc_clear(); |
748 | dc99a3f2 | blueswir1 | gen_cc_NZ(cpu_T[0]);
|
749 | dc99a3f2 | blueswir1 | gen_cc_C_sub(cpu_cc_src, cpu_T[1]);
|
750 | dc99a3f2 | blueswir1 | } |
751 | dc99a3f2 | blueswir1 | |
752 | d9bdab86 | blueswir1 | static inline void gen_op_mulscc_T1_T0(void) |
753 | d9bdab86 | blueswir1 | { |
754 | d9bdab86 | blueswir1 | TCGv r_temp; |
755 | d9bdab86 | blueswir1 | int l1, l2;
|
756 | d9bdab86 | blueswir1 | |
757 | d9bdab86 | blueswir1 | l1 = gen_new_label(); |
758 | d9bdab86 | blueswir1 | l2 = gen_new_label(); |
759 | d9bdab86 | blueswir1 | r_temp = tcg_temp_new(TCG_TYPE_TL); |
760 | d9bdab86 | blueswir1 | |
761 | d9bdab86 | blueswir1 | /* old op:
|
762 | d9bdab86 | blueswir1 | if (!(env->y & 1))
|
763 | d9bdab86 | blueswir1 | T1 = 0;
|
764 | d9bdab86 | blueswir1 | */
|
765 | 8911f501 | blueswir1 | tcg_gen_ld_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, y)); |
766 | 8911f501 | blueswir1 | tcg_gen_extu_i32_tl(r_temp, cpu_tmp32); |
767 | 8911f501 | blueswir1 | tcg_gen_andi_tl(r_temp, r_temp, 0x1);
|
768 | 8911f501 | blueswir1 | tcg_gen_brcond_tl(TCG_COND_EQ, r_temp, tcg_const_tl(0), l1);
|
769 | d9bdab86 | blueswir1 | tcg_gen_mov_tl(cpu_cc_src2, cpu_T[1]);
|
770 | 06b3e1b3 | blueswir1 | tcg_gen_br(l2); |
771 | d9bdab86 | blueswir1 | gen_set_label(l1); |
772 | d9bdab86 | blueswir1 | tcg_gen_movi_tl(cpu_cc_src2, 0);
|
773 | d9bdab86 | blueswir1 | gen_set_label(l2); |
774 | d9bdab86 | blueswir1 | |
775 | d9bdab86 | blueswir1 | // b2 = T0 & 1;
|
776 | d9bdab86 | blueswir1 | // env->y = (b2 << 31) | (env->y >> 1);
|
777 | 8911f501 | blueswir1 | tcg_gen_shli_tl(r_temp, cpu_T[0], 31); |
778 | 8911f501 | blueswir1 | tcg_gen_ld_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, y)); |
779 | 8911f501 | blueswir1 | tcg_gen_shri_i32(cpu_tmp32, cpu_tmp32, 1);
|
780 | 8911f501 | blueswir1 | tcg_gen_or_i32(cpu_tmp32, cpu_tmp32, r_temp); |
781 | 8911f501 | blueswir1 | tcg_gen_st_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, y)); |
782 | d9bdab86 | blueswir1 | |
783 | d9bdab86 | blueswir1 | // b1 = N ^ V;
|
784 | d9bdab86 | blueswir1 | gen_mov_reg_N(cpu_tmp0, cpu_psr); |
785 | d9bdab86 | blueswir1 | gen_mov_reg_V(r_temp, cpu_psr); |
786 | d9bdab86 | blueswir1 | tcg_gen_xor_tl(cpu_tmp0, cpu_tmp0, r_temp); |
787 | d9bdab86 | blueswir1 | |
788 | d9bdab86 | blueswir1 | // T0 = (b1 << 31) | (T0 >> 1);
|
789 | d9bdab86 | blueswir1 | // src1 = T0;
|
790 | d9bdab86 | blueswir1 | tcg_gen_shli_tl(cpu_tmp0, cpu_tmp0, 31);
|
791 | d9bdab86 | blueswir1 | tcg_gen_shri_tl(cpu_cc_src, cpu_T[0], 1); |
792 | d9bdab86 | blueswir1 | tcg_gen_or_tl(cpu_cc_src, cpu_cc_src, cpu_tmp0); |
793 | d9bdab86 | blueswir1 | |
794 | d9bdab86 | blueswir1 | /* do addition and update flags */
|
795 | d9bdab86 | blueswir1 | tcg_gen_add_tl(cpu_T[0], cpu_cc_src, cpu_cc_src2);
|
796 | d9bdab86 | blueswir1 | tcg_gen_discard_tl(r_temp); |
797 | d9bdab86 | blueswir1 | |
798 | d9bdab86 | blueswir1 | gen_cc_clear(); |
799 | d9bdab86 | blueswir1 | gen_cc_NZ(cpu_T[0]);
|
800 | d9bdab86 | blueswir1 | gen_cc_V_add(cpu_T[0], cpu_cc_src, cpu_cc_src2);
|
801 | d9bdab86 | blueswir1 | gen_cc_C_add(cpu_T[0], cpu_cc_src);
|
802 | d9bdab86 | blueswir1 | } |
803 | d9bdab86 | blueswir1 | |
804 | 8879d139 | blueswir1 | static inline void gen_op_umul_T1_T0(void) |
805 | 8879d139 | blueswir1 | { |
806 | 8879d139 | blueswir1 | TCGv r_temp, r_temp2; |
807 | 8879d139 | blueswir1 | |
808 | 8879d139 | blueswir1 | r_temp = tcg_temp_new(TCG_TYPE_I64); |
809 | 8879d139 | blueswir1 | r_temp2 = tcg_temp_new(TCG_TYPE_I64); |
810 | 8879d139 | blueswir1 | |
811 | 8911f501 | blueswir1 | tcg_gen_extu_tl_i64(r_temp, cpu_T[1]);
|
812 | 8911f501 | blueswir1 | tcg_gen_extu_tl_i64(r_temp2, cpu_T[0]);
|
813 | 8879d139 | blueswir1 | tcg_gen_mul_i64(r_temp2, r_temp, r_temp2); |
814 | 8879d139 | blueswir1 | |
815 | 8879d139 | blueswir1 | tcg_gen_shri_i64(r_temp, r_temp2, 32);
|
816 | 8879d139 | blueswir1 | tcg_gen_trunc_i64_i32(r_temp, r_temp); |
817 | 8879d139 | blueswir1 | tcg_gen_st_i32(r_temp, cpu_env, offsetof(CPUSPARCState, y)); |
818 | 8879d139 | blueswir1 | #ifdef TARGET_SPARC64
|
819 | 8879d139 | blueswir1 | tcg_gen_mov_i64(cpu_T[0], r_temp2);
|
820 | 8879d139 | blueswir1 | #else
|
821 | 8911f501 | blueswir1 | tcg_gen_trunc_i64_tl(cpu_T[0], r_temp2);
|
822 | 8879d139 | blueswir1 | #endif
|
823 | 8879d139 | blueswir1 | |
824 | 8879d139 | blueswir1 | tcg_gen_discard_i64(r_temp); |
825 | 8879d139 | blueswir1 | tcg_gen_discard_i64(r_temp2); |
826 | 8879d139 | blueswir1 | } |
827 | 8879d139 | blueswir1 | |
828 | 8879d139 | blueswir1 | static inline void gen_op_smul_T1_T0(void) |
829 | 8879d139 | blueswir1 | { |
830 | 8879d139 | blueswir1 | TCGv r_temp, r_temp2; |
831 | 8879d139 | blueswir1 | |
832 | 8879d139 | blueswir1 | r_temp = tcg_temp_new(TCG_TYPE_I64); |
833 | 8879d139 | blueswir1 | r_temp2 = tcg_temp_new(TCG_TYPE_I64); |
834 | 8879d139 | blueswir1 | |
835 | 8911f501 | blueswir1 | tcg_gen_ext_tl_i64(r_temp, cpu_T[1]);
|
836 | 8911f501 | blueswir1 | tcg_gen_ext_tl_i64(r_temp2, cpu_T[0]);
|
837 | 8879d139 | blueswir1 | tcg_gen_mul_i64(r_temp2, r_temp, r_temp2); |
838 | 8879d139 | blueswir1 | |
839 | 8879d139 | blueswir1 | tcg_gen_shri_i64(r_temp, r_temp2, 32);
|
840 | 8879d139 | blueswir1 | tcg_gen_trunc_i64_i32(r_temp, r_temp); |
841 | 8879d139 | blueswir1 | tcg_gen_st_i32(r_temp, cpu_env, offsetof(CPUSPARCState, y)); |
842 | 8879d139 | blueswir1 | #ifdef TARGET_SPARC64
|
843 | 8879d139 | blueswir1 | tcg_gen_mov_i64(cpu_T[0], r_temp2);
|
844 | 8879d139 | blueswir1 | #else
|
845 | 8911f501 | blueswir1 | tcg_gen_trunc_i64_tl(cpu_T[0], r_temp2);
|
846 | 8879d139 | blueswir1 | #endif
|
847 | 8879d139 | blueswir1 | |
848 | 8879d139 | blueswir1 | tcg_gen_discard_i64(r_temp); |
849 | 8879d139 | blueswir1 | tcg_gen_discard_i64(r_temp2); |
850 | 8879d139 | blueswir1 | } |
851 | 8879d139 | blueswir1 | |
852 | 3b89f26c | blueswir1 | static inline void gen_op_udiv_T1_T0(void) |
853 | 3b89f26c | blueswir1 | { |
854 | 3b89f26c | blueswir1 | tcg_gen_helper_1_2(helper_udiv, cpu_T[0], cpu_T[0], cpu_T[1]); |
855 | 3b89f26c | blueswir1 | } |
856 | 3b89f26c | blueswir1 | |
857 | 3b89f26c | blueswir1 | static inline void gen_op_sdiv_T1_T0(void) |
858 | 3b89f26c | blueswir1 | { |
859 | 3b89f26c | blueswir1 | tcg_gen_helper_1_2(helper_sdiv, cpu_T[0], cpu_T[0], cpu_T[1]); |
860 | 3b89f26c | blueswir1 | } |
861 | 3b89f26c | blueswir1 | |
862 | 1a7b60e7 | blueswir1 | #ifdef TARGET_SPARC64
|
863 | 8911f501 | blueswir1 | static inline void gen_trap_ifdivzero_tl(TCGv divisor) |
864 | 1a7b60e7 | blueswir1 | { |
865 | 1a7b60e7 | blueswir1 | int l1;
|
866 | 1a7b60e7 | blueswir1 | |
867 | 1a7b60e7 | blueswir1 | l1 = gen_new_label(); |
868 | 8911f501 | blueswir1 | tcg_gen_brcond_tl(TCG_COND_NE, divisor, tcg_const_tl(0), l1);
|
869 | 1a7b60e7 | blueswir1 | gen_op_exception(TT_DIV_ZERO); |
870 | 1a7b60e7 | blueswir1 | gen_set_label(l1); |
871 | 1a7b60e7 | blueswir1 | } |
872 | 1a7b60e7 | blueswir1 | |
873 | 1a7b60e7 | blueswir1 | static inline void gen_op_sdivx_T1_T0(void) |
874 | 1a7b60e7 | blueswir1 | { |
875 | 1a7b60e7 | blueswir1 | int l1, l2;
|
876 | 1a7b60e7 | blueswir1 | |
877 | 1a7b60e7 | blueswir1 | l1 = gen_new_label(); |
878 | 1a7b60e7 | blueswir1 | l2 = gen_new_label(); |
879 | 8911f501 | blueswir1 | gen_trap_ifdivzero_tl(cpu_T[1]);
|
880 | 8911f501 | blueswir1 | tcg_gen_brcond_tl(TCG_COND_NE, cpu_T[0], tcg_const_tl(INT64_MIN), l1);
|
881 | 8911f501 | blueswir1 | tcg_gen_brcond_tl(TCG_COND_NE, cpu_T[1], tcg_const_tl(-1), l1); |
882 | 1a7b60e7 | blueswir1 | tcg_gen_movi_i64(cpu_T[0], INT64_MIN);
|
883 | 06b3e1b3 | blueswir1 | tcg_gen_br(l2); |
884 | 1a7b60e7 | blueswir1 | gen_set_label(l1); |
885 | 1a7b60e7 | blueswir1 | tcg_gen_div_i64(cpu_T[0], cpu_T[0], cpu_T[1]); |
886 | 1a7b60e7 | blueswir1 | gen_set_label(l2); |
887 | 1a7b60e7 | blueswir1 | } |
888 | 1a7b60e7 | blueswir1 | #endif
|
889 | 1a7b60e7 | blueswir1 | |
890 | dc99a3f2 | blueswir1 | static inline void gen_op_div_cc(void) |
891 | dc99a3f2 | blueswir1 | { |
892 | dc99a3f2 | blueswir1 | int l1;
|
893 | dc99a3f2 | blueswir1 | |
894 | dc99a3f2 | blueswir1 | gen_cc_clear(); |
895 | dc99a3f2 | blueswir1 | gen_cc_NZ(cpu_T[0]);
|
896 | dc99a3f2 | blueswir1 | l1 = gen_new_label(); |
897 | 3b89f26c | blueswir1 | tcg_gen_ld_tl(cpu_tmp0, cpu_env, offsetof(CPUSPARCState, cc_src2)); |
898 | 3b89f26c | blueswir1 | tcg_gen_brcond_tl(TCG_COND_EQ, cpu_tmp0, tcg_const_tl(0), l1);
|
899 | dc99a3f2 | blueswir1 | tcg_gen_ori_i32(cpu_psr, cpu_psr, PSR_OVF); |
900 | dc99a3f2 | blueswir1 | gen_set_label(l1); |
901 | dc99a3f2 | blueswir1 | } |
902 | dc99a3f2 | blueswir1 | |
903 | dc99a3f2 | blueswir1 | static inline void gen_op_logic_T0_cc(void) |
904 | dc99a3f2 | blueswir1 | { |
905 | dc99a3f2 | blueswir1 | gen_cc_clear(); |
906 | dc99a3f2 | blueswir1 | gen_cc_NZ(cpu_T[0]);
|
907 | dc99a3f2 | blueswir1 | } |
908 | dc99a3f2 | blueswir1 | |
909 | 19f329ad | blueswir1 | // 1
|
910 | 19f329ad | blueswir1 | static inline void gen_op_eval_ba(TCGv dst) |
911 | 19f329ad | blueswir1 | { |
912 | 19f329ad | blueswir1 | tcg_gen_movi_tl(dst, 1);
|
913 | 19f329ad | blueswir1 | } |
914 | 19f329ad | blueswir1 | |
915 | 19f329ad | blueswir1 | // Z
|
916 | 19f329ad | blueswir1 | static inline void gen_op_eval_be(TCGv dst, TCGv src) |
917 | 19f329ad | blueswir1 | { |
918 | 19f329ad | blueswir1 | gen_mov_reg_Z(dst, src); |
919 | 19f329ad | blueswir1 | } |
920 | 19f329ad | blueswir1 | |
921 | 19f329ad | blueswir1 | // Z | (N ^ V)
|
922 | 19f329ad | blueswir1 | static inline void gen_op_eval_ble(TCGv dst, TCGv src) |
923 | 19f329ad | blueswir1 | { |
924 | 0425bee5 | blueswir1 | gen_mov_reg_N(cpu_tmp0, src); |
925 | 19f329ad | blueswir1 | gen_mov_reg_V(dst, src); |
926 | 0425bee5 | blueswir1 | tcg_gen_xor_tl(dst, dst, cpu_tmp0); |
927 | 0425bee5 | blueswir1 | gen_mov_reg_Z(cpu_tmp0, src); |
928 | 0425bee5 | blueswir1 | tcg_gen_or_tl(dst, dst, cpu_tmp0); |
929 | 19f329ad | blueswir1 | } |
930 | 19f329ad | blueswir1 | |
931 | 19f329ad | blueswir1 | // N ^ V
|
932 | 19f329ad | blueswir1 | static inline void gen_op_eval_bl(TCGv dst, TCGv src) |
933 | 19f329ad | blueswir1 | { |
934 | 0425bee5 | blueswir1 | gen_mov_reg_V(cpu_tmp0, src); |
935 | 19f329ad | blueswir1 | gen_mov_reg_N(dst, src); |
936 | 0425bee5 | blueswir1 | tcg_gen_xor_tl(dst, dst, cpu_tmp0); |
937 | 19f329ad | blueswir1 | } |
938 | 19f329ad | blueswir1 | |
939 | 19f329ad | blueswir1 | // C | Z
|
940 | 19f329ad | blueswir1 | static inline void gen_op_eval_bleu(TCGv dst, TCGv src) |
941 | 19f329ad | blueswir1 | { |
942 | 0425bee5 | blueswir1 | gen_mov_reg_Z(cpu_tmp0, src); |
943 | 19f329ad | blueswir1 | gen_mov_reg_C(dst, src); |
944 | 0425bee5 | blueswir1 | tcg_gen_or_tl(dst, dst, cpu_tmp0); |
945 | 19f329ad | blueswir1 | } |
946 | 19f329ad | blueswir1 | |
947 | 19f329ad | blueswir1 | // C
|
948 | 19f329ad | blueswir1 | static inline void gen_op_eval_bcs(TCGv dst, TCGv src) |
949 | 19f329ad | blueswir1 | { |
950 | 19f329ad | blueswir1 | gen_mov_reg_C(dst, src); |
951 | 19f329ad | blueswir1 | } |
952 | 19f329ad | blueswir1 | |
953 | 19f329ad | blueswir1 | // V
|
954 | 19f329ad | blueswir1 | static inline void gen_op_eval_bvs(TCGv dst, TCGv src) |
955 | 19f329ad | blueswir1 | { |
956 | 19f329ad | blueswir1 | gen_mov_reg_V(dst, src); |
957 | 19f329ad | blueswir1 | } |
958 | 19f329ad | blueswir1 | |
959 | 19f329ad | blueswir1 | // 0
|
960 | 19f329ad | blueswir1 | static inline void gen_op_eval_bn(TCGv dst) |
961 | 19f329ad | blueswir1 | { |
962 | 19f329ad | blueswir1 | tcg_gen_movi_tl(dst, 0);
|
963 | 19f329ad | blueswir1 | } |
964 | 19f329ad | blueswir1 | |
965 | 19f329ad | blueswir1 | // N
|
966 | 19f329ad | blueswir1 | static inline void gen_op_eval_bneg(TCGv dst, TCGv src) |
967 | 19f329ad | blueswir1 | { |
968 | 19f329ad | blueswir1 | gen_mov_reg_N(dst, src); |
969 | 19f329ad | blueswir1 | } |
970 | 19f329ad | blueswir1 | |
971 | 19f329ad | blueswir1 | // !Z
|
972 | 19f329ad | blueswir1 | static inline void gen_op_eval_bne(TCGv dst, TCGv src) |
973 | 19f329ad | blueswir1 | { |
974 | 19f329ad | blueswir1 | gen_mov_reg_Z(dst, src); |
975 | 19f329ad | blueswir1 | tcg_gen_xori_tl(dst, dst, 0x1);
|
976 | 19f329ad | blueswir1 | } |
977 | 19f329ad | blueswir1 | |
978 | 19f329ad | blueswir1 | // !(Z | (N ^ V))
|
979 | 19f329ad | blueswir1 | static inline void gen_op_eval_bg(TCGv dst, TCGv src) |
980 | 19f329ad | blueswir1 | { |
981 | 0425bee5 | blueswir1 | gen_mov_reg_N(cpu_tmp0, src); |
982 | 19f329ad | blueswir1 | gen_mov_reg_V(dst, src); |
983 | 0425bee5 | blueswir1 | tcg_gen_xor_tl(dst, dst, cpu_tmp0); |
984 | 0425bee5 | blueswir1 | gen_mov_reg_Z(cpu_tmp0, src); |
985 | 0425bee5 | blueswir1 | tcg_gen_or_tl(dst, dst, cpu_tmp0); |
986 | 19f329ad | blueswir1 | tcg_gen_xori_tl(dst, dst, 0x1);
|
987 | 19f329ad | blueswir1 | } |
988 | 19f329ad | blueswir1 | |
989 | 19f329ad | blueswir1 | // !(N ^ V)
|
990 | 19f329ad | blueswir1 | static inline void gen_op_eval_bge(TCGv dst, TCGv src) |
991 | 19f329ad | blueswir1 | { |
992 | 0425bee5 | blueswir1 | gen_mov_reg_V(cpu_tmp0, src); |
993 | 19f329ad | blueswir1 | gen_mov_reg_N(dst, src); |
994 | 0425bee5 | blueswir1 | tcg_gen_xor_tl(dst, dst, cpu_tmp0); |
995 | 19f329ad | blueswir1 | tcg_gen_xori_tl(dst, dst, 0x1);
|
996 | 19f329ad | blueswir1 | } |
997 | 19f329ad | blueswir1 | |
998 | 19f329ad | blueswir1 | // !(C | Z)
|
999 | 19f329ad | blueswir1 | static inline void gen_op_eval_bgu(TCGv dst, TCGv src) |
1000 | 19f329ad | blueswir1 | { |
1001 | 0425bee5 | blueswir1 | gen_mov_reg_Z(cpu_tmp0, src); |
1002 | 19f329ad | blueswir1 | gen_mov_reg_C(dst, src); |
1003 | 0425bee5 | blueswir1 | tcg_gen_or_tl(dst, dst, cpu_tmp0); |
1004 | 19f329ad | blueswir1 | tcg_gen_xori_tl(dst, dst, 0x1);
|
1005 | 19f329ad | blueswir1 | } |
1006 | 19f329ad | blueswir1 | |
1007 | 19f329ad | blueswir1 | // !C
|
1008 | 19f329ad | blueswir1 | static inline void gen_op_eval_bcc(TCGv dst, TCGv src) |
1009 | 19f329ad | blueswir1 | { |
1010 | 19f329ad | blueswir1 | gen_mov_reg_C(dst, src); |
1011 | 19f329ad | blueswir1 | tcg_gen_xori_tl(dst, dst, 0x1);
|
1012 | 19f329ad | blueswir1 | } |
1013 | 19f329ad | blueswir1 | |
1014 | 19f329ad | blueswir1 | // !N
|
1015 | 19f329ad | blueswir1 | static inline void gen_op_eval_bpos(TCGv dst, TCGv src) |
1016 | 19f329ad | blueswir1 | { |
1017 | 19f329ad | blueswir1 | gen_mov_reg_N(dst, src); |
1018 | 19f329ad | blueswir1 | tcg_gen_xori_tl(dst, dst, 0x1);
|
1019 | 19f329ad | blueswir1 | } |
1020 | 19f329ad | blueswir1 | |
1021 | 19f329ad | blueswir1 | // !V
|
1022 | 19f329ad | blueswir1 | static inline void gen_op_eval_bvc(TCGv dst, TCGv src) |
1023 | 19f329ad | blueswir1 | { |
1024 | 19f329ad | blueswir1 | gen_mov_reg_V(dst, src); |
1025 | 19f329ad | blueswir1 | tcg_gen_xori_tl(dst, dst, 0x1);
|
1026 | 19f329ad | blueswir1 | } |
1027 | 19f329ad | blueswir1 | |
1028 | 19f329ad | blueswir1 | /*
|
1029 | 19f329ad | blueswir1 | FPSR bit field FCC1 | FCC0:
|
1030 | 19f329ad | blueswir1 | 0 =
|
1031 | 19f329ad | blueswir1 | 1 <
|
1032 | 19f329ad | blueswir1 | 2 >
|
1033 | 19f329ad | blueswir1 | 3 unordered
|
1034 | 19f329ad | blueswir1 | */
|
1035 | 19f329ad | blueswir1 | static inline void gen_mov_reg_FCC0(TCGv reg, TCGv src, |
1036 | 19f329ad | blueswir1 | unsigned int fcc_offset) |
1037 | 19f329ad | blueswir1 | { |
1038 | 8911f501 | blueswir1 | tcg_gen_extu_i32_tl(reg, src); |
1039 | 8911f501 | blueswir1 | tcg_gen_shri_tl(reg, reg, 10 + fcc_offset);
|
1040 | 19f329ad | blueswir1 | tcg_gen_andi_tl(reg, reg, 0x1);
|
1041 | 19f329ad | blueswir1 | } |
1042 | 19f329ad | blueswir1 | |
1043 | 19f329ad | blueswir1 | static inline void gen_mov_reg_FCC1(TCGv reg, TCGv src, |
1044 | 19f329ad | blueswir1 | unsigned int fcc_offset) |
1045 | 19f329ad | blueswir1 | { |
1046 | 8911f501 | blueswir1 | tcg_gen_extu_i32_tl(reg, src); |
1047 | 8911f501 | blueswir1 | tcg_gen_shri_tl(reg, reg, 11 + fcc_offset);
|
1048 | 19f329ad | blueswir1 | tcg_gen_andi_tl(reg, reg, 0x1);
|
1049 | 19f329ad | blueswir1 | } |
1050 | 19f329ad | blueswir1 | |
1051 | 19f329ad | blueswir1 | // !0: FCC0 | FCC1
|
1052 | 19f329ad | blueswir1 | static inline void gen_op_eval_fbne(TCGv dst, TCGv src, |
1053 | 19f329ad | blueswir1 | unsigned int fcc_offset) |
1054 | 19f329ad | blueswir1 | { |
1055 | 19f329ad | blueswir1 | gen_mov_reg_FCC0(dst, src, fcc_offset); |
1056 | 0425bee5 | blueswir1 | gen_mov_reg_FCC1(cpu_tmp0, src, fcc_offset); |
1057 | 0425bee5 | blueswir1 | tcg_gen_or_tl(dst, dst, cpu_tmp0); |
1058 | 19f329ad | blueswir1 | } |
1059 | 19f329ad | blueswir1 | |
1060 | 19f329ad | blueswir1 | // 1 or 2: FCC0 ^ FCC1
|
1061 | 19f329ad | blueswir1 | static inline void gen_op_eval_fblg(TCGv dst, TCGv src, |
1062 | 19f329ad | blueswir1 | unsigned int fcc_offset) |
1063 | 19f329ad | blueswir1 | { |
1064 | 19f329ad | blueswir1 | gen_mov_reg_FCC0(dst, src, fcc_offset); |
1065 | 0425bee5 | blueswir1 | gen_mov_reg_FCC1(cpu_tmp0, src, fcc_offset); |
1066 | 0425bee5 | blueswir1 | tcg_gen_xor_tl(dst, dst, cpu_tmp0); |
1067 | 19f329ad | blueswir1 | } |
1068 | 19f329ad | blueswir1 | |
1069 | 19f329ad | blueswir1 | // 1 or 3: FCC0
|
1070 | 19f329ad | blueswir1 | static inline void gen_op_eval_fbul(TCGv dst, TCGv src, |
1071 | 19f329ad | blueswir1 | unsigned int fcc_offset) |
1072 | 19f329ad | blueswir1 | { |
1073 | 19f329ad | blueswir1 | gen_mov_reg_FCC0(dst, src, fcc_offset); |
1074 | 19f329ad | blueswir1 | } |
1075 | 19f329ad | blueswir1 | |
1076 | 19f329ad | blueswir1 | // 1: FCC0 & !FCC1
|
1077 | 19f329ad | blueswir1 | static inline void gen_op_eval_fbl(TCGv dst, TCGv src, |
1078 | 19f329ad | blueswir1 | unsigned int fcc_offset) |
1079 | 19f329ad | blueswir1 | { |
1080 | 19f329ad | blueswir1 | gen_mov_reg_FCC0(dst, src, fcc_offset); |
1081 | 0425bee5 | blueswir1 | gen_mov_reg_FCC1(cpu_tmp0, src, fcc_offset); |
1082 | 0425bee5 | blueswir1 | tcg_gen_xori_tl(cpu_tmp0, cpu_tmp0, 0x1);
|
1083 | 0425bee5 | blueswir1 | tcg_gen_and_tl(dst, dst, cpu_tmp0); |
1084 | 19f329ad | blueswir1 | } |
1085 | 19f329ad | blueswir1 | |
1086 | 19f329ad | blueswir1 | // 2 or 3: FCC1
|
1087 | 19f329ad | blueswir1 | static inline void gen_op_eval_fbug(TCGv dst, TCGv src, |
1088 | 19f329ad | blueswir1 | unsigned int fcc_offset) |
1089 | 19f329ad | blueswir1 | { |
1090 | 19f329ad | blueswir1 | gen_mov_reg_FCC1(dst, src, fcc_offset); |
1091 | 19f329ad | blueswir1 | } |
1092 | 19f329ad | blueswir1 | |
1093 | 19f329ad | blueswir1 | // 2: !FCC0 & FCC1
|
1094 | 19f329ad | blueswir1 | static inline void gen_op_eval_fbg(TCGv dst, TCGv src, |
1095 | 19f329ad | blueswir1 | unsigned int fcc_offset) |
1096 | 19f329ad | blueswir1 | { |
1097 | 19f329ad | blueswir1 | gen_mov_reg_FCC0(dst, src, fcc_offset); |
1098 | 19f329ad | blueswir1 | tcg_gen_xori_tl(dst, dst, 0x1);
|
1099 | 0425bee5 | blueswir1 | gen_mov_reg_FCC1(cpu_tmp0, src, fcc_offset); |
1100 | 0425bee5 | blueswir1 | tcg_gen_and_tl(dst, dst, cpu_tmp0); |
1101 | 19f329ad | blueswir1 | } |
1102 | 19f329ad | blueswir1 | |
1103 | 19f329ad | blueswir1 | // 3: FCC0 & FCC1
|
1104 | 19f329ad | blueswir1 | static inline void gen_op_eval_fbu(TCGv dst, TCGv src, |
1105 | 19f329ad | blueswir1 | unsigned int fcc_offset) |
1106 | 19f329ad | blueswir1 | { |
1107 | 19f329ad | blueswir1 | gen_mov_reg_FCC0(dst, src, fcc_offset); |
1108 | 0425bee5 | blueswir1 | gen_mov_reg_FCC1(cpu_tmp0, src, fcc_offset); |
1109 | 0425bee5 | blueswir1 | tcg_gen_and_tl(dst, dst, cpu_tmp0); |
1110 | 19f329ad | blueswir1 | } |
1111 | 19f329ad | blueswir1 | |
1112 | 19f329ad | blueswir1 | // 0: !(FCC0 | FCC1)
|
1113 | 19f329ad | blueswir1 | static inline void gen_op_eval_fbe(TCGv dst, TCGv src, |
1114 | 19f329ad | blueswir1 | unsigned int fcc_offset) |
1115 | 19f329ad | blueswir1 | { |
1116 | 19f329ad | blueswir1 | gen_mov_reg_FCC0(dst, src, fcc_offset); |
1117 | 0425bee5 | blueswir1 | gen_mov_reg_FCC1(cpu_tmp0, src, fcc_offset); |
1118 | 0425bee5 | blueswir1 | tcg_gen_or_tl(dst, dst, cpu_tmp0); |
1119 | 19f329ad | blueswir1 | tcg_gen_xori_tl(dst, dst, 0x1);
|
1120 | 19f329ad | blueswir1 | } |
1121 | 19f329ad | blueswir1 | |
1122 | 19f329ad | blueswir1 | // 0 or 3: !(FCC0 ^ FCC1)
|
1123 | 19f329ad | blueswir1 | static inline void gen_op_eval_fbue(TCGv dst, TCGv src, |
1124 | 19f329ad | blueswir1 | unsigned int fcc_offset) |
1125 | 19f329ad | blueswir1 | { |
1126 | 19f329ad | blueswir1 | gen_mov_reg_FCC0(dst, src, fcc_offset); |
1127 | 0425bee5 | blueswir1 | gen_mov_reg_FCC1(cpu_tmp0, src, fcc_offset); |
1128 | 0425bee5 | blueswir1 | tcg_gen_xor_tl(dst, dst, cpu_tmp0); |
1129 | 19f329ad | blueswir1 | tcg_gen_xori_tl(dst, dst, 0x1);
|
1130 | 19f329ad | blueswir1 | } |
1131 | 19f329ad | blueswir1 | |
1132 | 19f329ad | blueswir1 | // 0 or 2: !FCC0
|
1133 | 19f329ad | blueswir1 | static inline void gen_op_eval_fbge(TCGv dst, TCGv src, |
1134 | 19f329ad | blueswir1 | unsigned int fcc_offset) |
1135 | 19f329ad | blueswir1 | { |
1136 | 19f329ad | blueswir1 | gen_mov_reg_FCC0(dst, src, fcc_offset); |
1137 | 19f329ad | blueswir1 | tcg_gen_xori_tl(dst, dst, 0x1);
|
1138 | 19f329ad | blueswir1 | } |
1139 | 19f329ad | blueswir1 | |
1140 | 19f329ad | blueswir1 | // !1: !(FCC0 & !FCC1)
|
1141 | 19f329ad | blueswir1 | static inline void gen_op_eval_fbuge(TCGv dst, TCGv src, |
1142 | 19f329ad | blueswir1 | unsigned int fcc_offset) |
1143 | 19f329ad | blueswir1 | { |
1144 | 19f329ad | blueswir1 | gen_mov_reg_FCC0(dst, src, fcc_offset); |
1145 | 0425bee5 | blueswir1 | gen_mov_reg_FCC1(cpu_tmp0, src, fcc_offset); |
1146 | 0425bee5 | blueswir1 | tcg_gen_xori_tl(cpu_tmp0, cpu_tmp0, 0x1);
|
1147 | 0425bee5 | blueswir1 | tcg_gen_and_tl(dst, dst, cpu_tmp0); |
1148 | 19f329ad | blueswir1 | tcg_gen_xori_tl(dst, dst, 0x1);
|
1149 | 19f329ad | blueswir1 | } |
1150 | 19f329ad | blueswir1 | |
1151 | 19f329ad | blueswir1 | // 0 or 1: !FCC1
|
1152 | 19f329ad | blueswir1 | static inline void gen_op_eval_fble(TCGv dst, TCGv src, |
1153 | 19f329ad | blueswir1 | unsigned int fcc_offset) |
1154 | 19f329ad | blueswir1 | { |
1155 | 19f329ad | blueswir1 | gen_mov_reg_FCC1(dst, src, fcc_offset); |
1156 | 19f329ad | blueswir1 | tcg_gen_xori_tl(dst, dst, 0x1);
|
1157 | 19f329ad | blueswir1 | } |
1158 | 19f329ad | blueswir1 | |
1159 | 19f329ad | blueswir1 | // !2: !(!FCC0 & FCC1)
|
1160 | 19f329ad | blueswir1 | static inline void gen_op_eval_fbule(TCGv dst, TCGv src, |
1161 | 19f329ad | blueswir1 | unsigned int fcc_offset) |
1162 | 19f329ad | blueswir1 | { |
1163 | 19f329ad | blueswir1 | gen_mov_reg_FCC0(dst, src, fcc_offset); |
1164 | 19f329ad | blueswir1 | tcg_gen_xori_tl(dst, dst, 0x1);
|
1165 | 0425bee5 | blueswir1 | gen_mov_reg_FCC1(cpu_tmp0, src, fcc_offset); |
1166 | 0425bee5 | blueswir1 | tcg_gen_and_tl(dst, dst, cpu_tmp0); |
1167 | 19f329ad | blueswir1 | tcg_gen_xori_tl(dst, dst, 0x1);
|
1168 | 19f329ad | blueswir1 | } |
1169 | 19f329ad | blueswir1 | |
1170 | 19f329ad | blueswir1 | // !3: !(FCC0 & FCC1)
|
1171 | 19f329ad | blueswir1 | static inline void gen_op_eval_fbo(TCGv dst, TCGv src, |
1172 | 19f329ad | blueswir1 | unsigned int fcc_offset) |
1173 | 19f329ad | blueswir1 | { |
1174 | 19f329ad | blueswir1 | gen_mov_reg_FCC0(dst, src, fcc_offset); |
1175 | 0425bee5 | blueswir1 | gen_mov_reg_FCC1(cpu_tmp0, src, fcc_offset); |
1176 | 0425bee5 | blueswir1 | tcg_gen_and_tl(dst, dst, cpu_tmp0); |
1177 | 19f329ad | blueswir1 | tcg_gen_xori_tl(dst, dst, 0x1);
|
1178 | 19f329ad | blueswir1 | } |
1179 | 19f329ad | blueswir1 | |
1180 | 46525e1f | blueswir1 | static inline void gen_branch2(DisasContext *dc, target_ulong pc1, |
1181 | 19f329ad | blueswir1 | target_ulong pc2, TCGv r_cond) |
1182 | 83469015 | bellard | { |
1183 | 83469015 | bellard | int l1;
|
1184 | 83469015 | bellard | |
1185 | 83469015 | bellard | l1 = gen_new_label(); |
1186 | 83469015 | bellard | |
1187 | 0425bee5 | blueswir1 | tcg_gen_brcond_tl(TCG_COND_EQ, r_cond, tcg_const_tl(0), l1);
|
1188 | 83469015 | bellard | |
1189 | 6e256c93 | bellard | gen_goto_tb(dc, 0, pc1, pc1 + 4); |
1190 | 83469015 | bellard | |
1191 | 83469015 | bellard | gen_set_label(l1); |
1192 | 6e256c93 | bellard | gen_goto_tb(dc, 1, pc2, pc2 + 4); |
1193 | 83469015 | bellard | } |
1194 | 83469015 | bellard | |
1195 | 46525e1f | blueswir1 | static inline void gen_branch_a(DisasContext *dc, target_ulong pc1, |
1196 | 19f329ad | blueswir1 | target_ulong pc2, TCGv r_cond) |
1197 | 83469015 | bellard | { |
1198 | 83469015 | bellard | int l1;
|
1199 | 83469015 | bellard | |
1200 | 83469015 | bellard | l1 = gen_new_label(); |
1201 | 83469015 | bellard | |
1202 | 0425bee5 | blueswir1 | tcg_gen_brcond_tl(TCG_COND_EQ, r_cond, tcg_const_tl(0), l1);
|
1203 | 83469015 | bellard | |
1204 | 6e256c93 | bellard | gen_goto_tb(dc, 0, pc2, pc1);
|
1205 | 83469015 | bellard | |
1206 | 83469015 | bellard | gen_set_label(l1); |
1207 | 6e256c93 | bellard | gen_goto_tb(dc, 1, pc2 + 4, pc2 + 8); |
1208 | 83469015 | bellard | } |
1209 | 83469015 | bellard | |
1210 | 46525e1f | blueswir1 | static inline void gen_branch(DisasContext *dc, target_ulong pc, |
1211 | 46525e1f | blueswir1 | target_ulong npc) |
1212 | 83469015 | bellard | { |
1213 | 6e256c93 | bellard | gen_goto_tb(dc, 0, pc, npc);
|
1214 | 83469015 | bellard | } |
1215 | 83469015 | bellard | |
1216 | 19f329ad | blueswir1 | static inline void gen_generic_branch(target_ulong npc1, target_ulong npc2, |
1217 | 19f329ad | blueswir1 | TCGv r_cond) |
1218 | 83469015 | bellard | { |
1219 | 83469015 | bellard | int l1, l2;
|
1220 | 83469015 | bellard | |
1221 | 83469015 | bellard | l1 = gen_new_label(); |
1222 | 83469015 | bellard | l2 = gen_new_label(); |
1223 | 19f329ad | blueswir1 | |
1224 | 0425bee5 | blueswir1 | tcg_gen_brcond_tl(TCG_COND_EQ, r_cond, tcg_const_tl(0), l1);
|
1225 | 83469015 | bellard | |
1226 | 83469015 | bellard | gen_movl_npc_im(npc1); |
1227 | 06b3e1b3 | blueswir1 | tcg_gen_br(l2); |
1228 | 83469015 | bellard | |
1229 | 83469015 | bellard | gen_set_label(l1); |
1230 | 83469015 | bellard | gen_movl_npc_im(npc2); |
1231 | 83469015 | bellard | gen_set_label(l2); |
1232 | 83469015 | bellard | } |
1233 | 83469015 | bellard | |
1234 | 83469015 | bellard | /* call this function before using T2 as it may have been set for a jump */
|
1235 | 83469015 | bellard | static inline void flush_T2(DisasContext * dc) |
1236 | 83469015 | bellard | { |
1237 | 83469015 | bellard | if (dc->npc == JUMP_PC) {
|
1238 | 19f329ad | blueswir1 | gen_generic_branch(dc->jump_pc[0], dc->jump_pc[1], cpu_T[2]); |
1239 | 83469015 | bellard | dc->npc = DYNAMIC_PC; |
1240 | 83469015 | bellard | } |
1241 | 83469015 | bellard | } |
1242 | 83469015 | bellard | |
1243 | 72cbca10 | bellard | static inline void save_npc(DisasContext * dc) |
1244 | 72cbca10 | bellard | { |
1245 | 72cbca10 | bellard | if (dc->npc == JUMP_PC) {
|
1246 | 19f329ad | blueswir1 | gen_generic_branch(dc->jump_pc[0], dc->jump_pc[1], cpu_T[2]); |
1247 | 72cbca10 | bellard | dc->npc = DYNAMIC_PC; |
1248 | 72cbca10 | bellard | } else if (dc->npc != DYNAMIC_PC) { |
1249 | 3475187d | bellard | gen_movl_npc_im(dc->npc); |
1250 | 72cbca10 | bellard | } |
1251 | 72cbca10 | bellard | } |
1252 | 72cbca10 | bellard | |
1253 | 72cbca10 | bellard | static inline void save_state(DisasContext * dc) |
1254 | 72cbca10 | bellard | { |
1255 | 3475187d | bellard | gen_jmp_im(dc->pc); |
1256 | 72cbca10 | bellard | save_npc(dc); |
1257 | 72cbca10 | bellard | } |
1258 | 72cbca10 | bellard | |
1259 | 0bee699e | bellard | static inline void gen_mov_pc_npc(DisasContext * dc) |
1260 | 0bee699e | bellard | { |
1261 | 0bee699e | bellard | if (dc->npc == JUMP_PC) {
|
1262 | 19f329ad | blueswir1 | gen_generic_branch(dc->jump_pc[0], dc->jump_pc[1], cpu_T[2]); |
1263 | 48d5c82b | blueswir1 | tcg_gen_mov_tl(cpu_pc, cpu_npc); |
1264 | 0bee699e | bellard | dc->pc = DYNAMIC_PC; |
1265 | 0bee699e | bellard | } else if (dc->npc == DYNAMIC_PC) { |
1266 | 48d5c82b | blueswir1 | tcg_gen_mov_tl(cpu_pc, cpu_npc); |
1267 | 0bee699e | bellard | dc->pc = DYNAMIC_PC; |
1268 | 0bee699e | bellard | } else {
|
1269 | 0bee699e | bellard | dc->pc = dc->npc; |
1270 | 0bee699e | bellard | } |
1271 | 0bee699e | bellard | } |
1272 | 0bee699e | bellard | |
1273 | 38bc628b | blueswir1 | static inline void gen_op_next_insn(void) |
1274 | 38bc628b | blueswir1 | { |
1275 | 48d5c82b | blueswir1 | tcg_gen_mov_tl(cpu_pc, cpu_npc); |
1276 | 48d5c82b | blueswir1 | tcg_gen_addi_tl(cpu_npc, cpu_npc, 4);
|
1277 | 38bc628b | blueswir1 | } |
1278 | 38bc628b | blueswir1 | |
1279 | 19f329ad | blueswir1 | static inline void gen_cond(TCGv r_dst, unsigned int cc, unsigned int cond) |
1280 | 19f329ad | blueswir1 | { |
1281 | 19f329ad | blueswir1 | TCGv r_src; |
1282 | 3475187d | bellard | |
1283 | 3475187d | bellard | #ifdef TARGET_SPARC64
|
1284 | 19f329ad | blueswir1 | if (cc)
|
1285 | dc99a3f2 | blueswir1 | r_src = cpu_xcc; |
1286 | 19f329ad | blueswir1 | else
|
1287 | dc99a3f2 | blueswir1 | r_src = cpu_psr; |
1288 | 3475187d | bellard | #else
|
1289 | dc99a3f2 | blueswir1 | r_src = cpu_psr; |
1290 | 3475187d | bellard | #endif
|
1291 | 19f329ad | blueswir1 | switch (cond) {
|
1292 | 19f329ad | blueswir1 | case 0x0: |
1293 | 19f329ad | blueswir1 | gen_op_eval_bn(r_dst); |
1294 | 19f329ad | blueswir1 | break;
|
1295 | 19f329ad | blueswir1 | case 0x1: |
1296 | 19f329ad | blueswir1 | gen_op_eval_be(r_dst, r_src); |
1297 | 19f329ad | blueswir1 | break;
|
1298 | 19f329ad | blueswir1 | case 0x2: |
1299 | 19f329ad | blueswir1 | gen_op_eval_ble(r_dst, r_src); |
1300 | 19f329ad | blueswir1 | break;
|
1301 | 19f329ad | blueswir1 | case 0x3: |
1302 | 19f329ad | blueswir1 | gen_op_eval_bl(r_dst, r_src); |
1303 | 19f329ad | blueswir1 | break;
|
1304 | 19f329ad | blueswir1 | case 0x4: |
1305 | 19f329ad | blueswir1 | gen_op_eval_bleu(r_dst, r_src); |
1306 | 19f329ad | blueswir1 | break;
|
1307 | 19f329ad | blueswir1 | case 0x5: |
1308 | 19f329ad | blueswir1 | gen_op_eval_bcs(r_dst, r_src); |
1309 | 19f329ad | blueswir1 | break;
|
1310 | 19f329ad | blueswir1 | case 0x6: |
1311 | 19f329ad | blueswir1 | gen_op_eval_bneg(r_dst, r_src); |
1312 | 19f329ad | blueswir1 | break;
|
1313 | 19f329ad | blueswir1 | case 0x7: |
1314 | 19f329ad | blueswir1 | gen_op_eval_bvs(r_dst, r_src); |
1315 | 19f329ad | blueswir1 | break;
|
1316 | 19f329ad | blueswir1 | case 0x8: |
1317 | 19f329ad | blueswir1 | gen_op_eval_ba(r_dst); |
1318 | 19f329ad | blueswir1 | break;
|
1319 | 19f329ad | blueswir1 | case 0x9: |
1320 | 19f329ad | blueswir1 | gen_op_eval_bne(r_dst, r_src); |
1321 | 19f329ad | blueswir1 | break;
|
1322 | 19f329ad | blueswir1 | case 0xa: |
1323 | 19f329ad | blueswir1 | gen_op_eval_bg(r_dst, r_src); |
1324 | 19f329ad | blueswir1 | break;
|
1325 | 19f329ad | blueswir1 | case 0xb: |
1326 | 19f329ad | blueswir1 | gen_op_eval_bge(r_dst, r_src); |
1327 | 19f329ad | blueswir1 | break;
|
1328 | 19f329ad | blueswir1 | case 0xc: |
1329 | 19f329ad | blueswir1 | gen_op_eval_bgu(r_dst, r_src); |
1330 | 19f329ad | blueswir1 | break;
|
1331 | 19f329ad | blueswir1 | case 0xd: |
1332 | 19f329ad | blueswir1 | gen_op_eval_bcc(r_dst, r_src); |
1333 | 19f329ad | blueswir1 | break;
|
1334 | 19f329ad | blueswir1 | case 0xe: |
1335 | 19f329ad | blueswir1 | gen_op_eval_bpos(r_dst, r_src); |
1336 | 19f329ad | blueswir1 | break;
|
1337 | 19f329ad | blueswir1 | case 0xf: |
1338 | 19f329ad | blueswir1 | gen_op_eval_bvc(r_dst, r_src); |
1339 | 19f329ad | blueswir1 | break;
|
1340 | 19f329ad | blueswir1 | } |
1341 | 19f329ad | blueswir1 | } |
1342 | 7a3f1944 | bellard | |
1343 | 19f329ad | blueswir1 | static inline void gen_fcond(TCGv r_dst, unsigned int cc, unsigned int cond) |
1344 | e8af50a3 | bellard | { |
1345 | 19f329ad | blueswir1 | unsigned int offset; |
1346 | 19f329ad | blueswir1 | |
1347 | 19f329ad | blueswir1 | switch (cc) {
|
1348 | 19f329ad | blueswir1 | default:
|
1349 | 19f329ad | blueswir1 | case 0x0: |
1350 | 19f329ad | blueswir1 | offset = 0;
|
1351 | 19f329ad | blueswir1 | break;
|
1352 | 19f329ad | blueswir1 | case 0x1: |
1353 | 19f329ad | blueswir1 | offset = 32 - 10; |
1354 | 19f329ad | blueswir1 | break;
|
1355 | 19f329ad | blueswir1 | case 0x2: |
1356 | 19f329ad | blueswir1 | offset = 34 - 10; |
1357 | 19f329ad | blueswir1 | break;
|
1358 | 19f329ad | blueswir1 | case 0x3: |
1359 | 19f329ad | blueswir1 | offset = 36 - 10; |
1360 | 19f329ad | blueswir1 | break;
|
1361 | 19f329ad | blueswir1 | } |
1362 | 19f329ad | blueswir1 | |
1363 | 19f329ad | blueswir1 | switch (cond) {
|
1364 | 19f329ad | blueswir1 | case 0x0: |
1365 | 19f329ad | blueswir1 | gen_op_eval_bn(r_dst); |
1366 | 19f329ad | blueswir1 | break;
|
1367 | 19f329ad | blueswir1 | case 0x1: |
1368 | 87e92502 | blueswir1 | gen_op_eval_fbne(r_dst, cpu_fsr, offset); |
1369 | 19f329ad | blueswir1 | break;
|
1370 | 19f329ad | blueswir1 | case 0x2: |
1371 | 87e92502 | blueswir1 | gen_op_eval_fblg(r_dst, cpu_fsr, offset); |
1372 | 19f329ad | blueswir1 | break;
|
1373 | 19f329ad | blueswir1 | case 0x3: |
1374 | 87e92502 | blueswir1 | gen_op_eval_fbul(r_dst, cpu_fsr, offset); |
1375 | 19f329ad | blueswir1 | break;
|
1376 | 19f329ad | blueswir1 | case 0x4: |
1377 | 87e92502 | blueswir1 | gen_op_eval_fbl(r_dst, cpu_fsr, offset); |
1378 | 19f329ad | blueswir1 | break;
|
1379 | 19f329ad | blueswir1 | case 0x5: |
1380 | 87e92502 | blueswir1 | gen_op_eval_fbug(r_dst, cpu_fsr, offset); |
1381 | 19f329ad | blueswir1 | break;
|
1382 | 19f329ad | blueswir1 | case 0x6: |
1383 | 87e92502 | blueswir1 | gen_op_eval_fbg(r_dst, cpu_fsr, offset); |
1384 | 19f329ad | blueswir1 | break;
|
1385 | 19f329ad | blueswir1 | case 0x7: |
1386 | 87e92502 | blueswir1 | gen_op_eval_fbu(r_dst, cpu_fsr, offset); |
1387 | 19f329ad | blueswir1 | break;
|
1388 | 19f329ad | blueswir1 | case 0x8: |
1389 | 19f329ad | blueswir1 | gen_op_eval_ba(r_dst); |
1390 | 19f329ad | blueswir1 | break;
|
1391 | 19f329ad | blueswir1 | case 0x9: |
1392 | 87e92502 | blueswir1 | gen_op_eval_fbe(r_dst, cpu_fsr, offset); |
1393 | 19f329ad | blueswir1 | break;
|
1394 | 19f329ad | blueswir1 | case 0xa: |
1395 | 87e92502 | blueswir1 | gen_op_eval_fbue(r_dst, cpu_fsr, offset); |
1396 | 19f329ad | blueswir1 | break;
|
1397 | 19f329ad | blueswir1 | case 0xb: |
1398 | 87e92502 | blueswir1 | gen_op_eval_fbge(r_dst, cpu_fsr, offset); |
1399 | 19f329ad | blueswir1 | break;
|
1400 | 19f329ad | blueswir1 | case 0xc: |
1401 | 87e92502 | blueswir1 | gen_op_eval_fbuge(r_dst, cpu_fsr, offset); |
1402 | 19f329ad | blueswir1 | break;
|
1403 | 19f329ad | blueswir1 | case 0xd: |
1404 | 87e92502 | blueswir1 | gen_op_eval_fble(r_dst, cpu_fsr, offset); |
1405 | 19f329ad | blueswir1 | break;
|
1406 | 19f329ad | blueswir1 | case 0xe: |
1407 | 87e92502 | blueswir1 | gen_op_eval_fbule(r_dst, cpu_fsr, offset); |
1408 | 19f329ad | blueswir1 | break;
|
1409 | 19f329ad | blueswir1 | case 0xf: |
1410 | 87e92502 | blueswir1 | gen_op_eval_fbo(r_dst, cpu_fsr, offset); |
1411 | 19f329ad | blueswir1 | break;
|
1412 | 19f329ad | blueswir1 | } |
1413 | e8af50a3 | bellard | } |
1414 | 00f219bf | blueswir1 | |
1415 | 19f329ad | blueswir1 | #ifdef TARGET_SPARC64
|
1416 | 00f219bf | blueswir1 | // Inverted logic
|
1417 | 00f219bf | blueswir1 | static const int gen_tcg_cond_reg[8] = { |
1418 | 00f219bf | blueswir1 | -1,
|
1419 | 00f219bf | blueswir1 | TCG_COND_NE, |
1420 | 00f219bf | blueswir1 | TCG_COND_GT, |
1421 | 00f219bf | blueswir1 | TCG_COND_GE, |
1422 | 00f219bf | blueswir1 | -1,
|
1423 | 00f219bf | blueswir1 | TCG_COND_EQ, |
1424 | 00f219bf | blueswir1 | TCG_COND_LE, |
1425 | 00f219bf | blueswir1 | TCG_COND_LT, |
1426 | 00f219bf | blueswir1 | }; |
1427 | 19f329ad | blueswir1 | |
1428 | 19f329ad | blueswir1 | static inline void gen_cond_reg(TCGv r_dst, int cond) |
1429 | 19f329ad | blueswir1 | { |
1430 | 19f329ad | blueswir1 | int l1;
|
1431 | 19f329ad | blueswir1 | |
1432 | 19f329ad | blueswir1 | l1 = gen_new_label(); |
1433 | 0425bee5 | blueswir1 | tcg_gen_movi_tl(r_dst, 0);
|
1434 | 0425bee5 | blueswir1 | tcg_gen_brcond_tl(gen_tcg_cond_reg[cond], cpu_T[0], tcg_const_tl(0), l1); |
1435 | 19f329ad | blueswir1 | tcg_gen_movi_tl(r_dst, 1);
|
1436 | 19f329ad | blueswir1 | gen_set_label(l1); |
1437 | 19f329ad | blueswir1 | } |
1438 | 3475187d | bellard | #endif
|
1439 | cf495bcf | bellard | |
1440 | 0bee699e | bellard | /* XXX: potentially incorrect if dynamic npc */
|
1441 | 3475187d | bellard | static void do_branch(DisasContext * dc, int32_t offset, uint32_t insn, int cc) |
1442 | 7a3f1944 | bellard | { |
1443 | cf495bcf | bellard | unsigned int cond = GET_FIELD(insn, 3, 6), a = (insn & (1 << 29)); |
1444 | af7bf89b | bellard | target_ulong target = dc->pc + offset; |
1445 | 5fafdf24 | ths | |
1446 | cf495bcf | bellard | if (cond == 0x0) { |
1447 | 0f8a249a | blueswir1 | /* unconditional not taken */
|
1448 | 0f8a249a | blueswir1 | if (a) {
|
1449 | 0f8a249a | blueswir1 | dc->pc = dc->npc + 4;
|
1450 | 0f8a249a | blueswir1 | dc->npc = dc->pc + 4;
|
1451 | 0f8a249a | blueswir1 | } else {
|
1452 | 0f8a249a | blueswir1 | dc->pc = dc->npc; |
1453 | 0f8a249a | blueswir1 | dc->npc = dc->pc + 4;
|
1454 | 0f8a249a | blueswir1 | } |
1455 | cf495bcf | bellard | } else if (cond == 0x8) { |
1456 | 0f8a249a | blueswir1 | /* unconditional taken */
|
1457 | 0f8a249a | blueswir1 | if (a) {
|
1458 | 0f8a249a | blueswir1 | dc->pc = target; |
1459 | 0f8a249a | blueswir1 | dc->npc = dc->pc + 4;
|
1460 | 0f8a249a | blueswir1 | } else {
|
1461 | 0f8a249a | blueswir1 | dc->pc = dc->npc; |
1462 | 0f8a249a | blueswir1 | dc->npc = target; |
1463 | 0f8a249a | blueswir1 | } |
1464 | cf495bcf | bellard | } else {
|
1465 | 72cbca10 | bellard | flush_T2(dc); |
1466 | 19f329ad | blueswir1 | gen_cond(cpu_T[2], cc, cond);
|
1467 | 0f8a249a | blueswir1 | if (a) {
|
1468 | 19f329ad | blueswir1 | gen_branch_a(dc, target, dc->npc, cpu_T[2]);
|
1469 | cf495bcf | bellard | dc->is_br = 1;
|
1470 | 0f8a249a | blueswir1 | } else {
|
1471 | cf495bcf | bellard | dc->pc = dc->npc; |
1472 | 72cbca10 | bellard | dc->jump_pc[0] = target;
|
1473 | 72cbca10 | bellard | dc->jump_pc[1] = dc->npc + 4; |
1474 | 72cbca10 | bellard | dc->npc = JUMP_PC; |
1475 | 0f8a249a | blueswir1 | } |
1476 | cf495bcf | bellard | } |
1477 | 7a3f1944 | bellard | } |
1478 | 7a3f1944 | bellard | |
1479 | 0bee699e | bellard | /* XXX: potentially incorrect if dynamic npc */
|
1480 | 3475187d | bellard | static void do_fbranch(DisasContext * dc, int32_t offset, uint32_t insn, int cc) |
1481 | e8af50a3 | bellard | { |
1482 | e8af50a3 | bellard | unsigned int cond = GET_FIELD(insn, 3, 6), a = (insn & (1 << 29)); |
1483 | af7bf89b | bellard | target_ulong target = dc->pc + offset; |
1484 | af7bf89b | bellard | |
1485 | e8af50a3 | bellard | if (cond == 0x0) { |
1486 | 0f8a249a | blueswir1 | /* unconditional not taken */
|
1487 | 0f8a249a | blueswir1 | if (a) {
|
1488 | 0f8a249a | blueswir1 | dc->pc = dc->npc + 4;
|
1489 | 0f8a249a | blueswir1 | dc->npc = dc->pc + 4;
|
1490 | 0f8a249a | blueswir1 | } else {
|
1491 | 0f8a249a | blueswir1 | dc->pc = dc->npc; |
1492 | 0f8a249a | blueswir1 | dc->npc = dc->pc + 4;
|
1493 | 0f8a249a | blueswir1 | } |
1494 | e8af50a3 | bellard | } else if (cond == 0x8) { |
1495 | 0f8a249a | blueswir1 | /* unconditional taken */
|
1496 | 0f8a249a | blueswir1 | if (a) {
|
1497 | 0f8a249a | blueswir1 | dc->pc = target; |
1498 | 0f8a249a | blueswir1 | dc->npc = dc->pc + 4;
|
1499 | 0f8a249a | blueswir1 | } else {
|
1500 | 0f8a249a | blueswir1 | dc->pc = dc->npc; |
1501 | 0f8a249a | blueswir1 | dc->npc = target; |
1502 | 0f8a249a | blueswir1 | } |
1503 | e8af50a3 | bellard | } else {
|
1504 | e8af50a3 | bellard | flush_T2(dc); |
1505 | 19f329ad | blueswir1 | gen_fcond(cpu_T[2], cc, cond);
|
1506 | 0f8a249a | blueswir1 | if (a) {
|
1507 | 19f329ad | blueswir1 | gen_branch_a(dc, target, dc->npc, cpu_T[2]);
|
1508 | e8af50a3 | bellard | dc->is_br = 1;
|
1509 | 0f8a249a | blueswir1 | } else {
|
1510 | e8af50a3 | bellard | dc->pc = dc->npc; |
1511 | e8af50a3 | bellard | dc->jump_pc[0] = target;
|
1512 | e8af50a3 | bellard | dc->jump_pc[1] = dc->npc + 4; |
1513 | e8af50a3 | bellard | dc->npc = JUMP_PC; |
1514 | 0f8a249a | blueswir1 | } |
1515 | e8af50a3 | bellard | } |
1516 | e8af50a3 | bellard | } |
1517 | e8af50a3 | bellard | |
1518 | 3475187d | bellard | #ifdef TARGET_SPARC64
|
1519 | 3475187d | bellard | /* XXX: potentially incorrect if dynamic npc */
|
1520 | 3475187d | bellard | static void do_branch_reg(DisasContext * dc, int32_t offset, uint32_t insn) |
1521 | 7a3f1944 | bellard | { |
1522 | 3475187d | bellard | unsigned int cond = GET_FIELD_SP(insn, 25, 27), a = (insn & (1 << 29)); |
1523 | 3475187d | bellard | target_ulong target = dc->pc + offset; |
1524 | 3475187d | bellard | |
1525 | 3475187d | bellard | flush_T2(dc); |
1526 | 19f329ad | blueswir1 | gen_cond_reg(cpu_T[2], cond);
|
1527 | 3475187d | bellard | if (a) {
|
1528 | 19f329ad | blueswir1 | gen_branch_a(dc, target, dc->npc, cpu_T[2]);
|
1529 | 0f8a249a | blueswir1 | dc->is_br = 1;
|
1530 | 3475187d | bellard | } else {
|
1531 | 0f8a249a | blueswir1 | dc->pc = dc->npc; |
1532 | 0f8a249a | blueswir1 | dc->jump_pc[0] = target;
|
1533 | 0f8a249a | blueswir1 | dc->jump_pc[1] = dc->npc + 4; |
1534 | 0f8a249a | blueswir1 | dc->npc = JUMP_PC; |
1535 | 3475187d | bellard | } |
1536 | 7a3f1944 | bellard | } |
1537 | 7a3f1944 | bellard | |
1538 | 3475187d | bellard | static GenOpFunc * const gen_fcmps[4] = { |
1539 | 7e8c2b6c | blueswir1 | helper_fcmps, |
1540 | 7e8c2b6c | blueswir1 | helper_fcmps_fcc1, |
1541 | 7e8c2b6c | blueswir1 | helper_fcmps_fcc2, |
1542 | 7e8c2b6c | blueswir1 | helper_fcmps_fcc3, |
1543 | 3475187d | bellard | }; |
1544 | 3475187d | bellard | |
1545 | 3475187d | bellard | static GenOpFunc * const gen_fcmpd[4] = { |
1546 | 7e8c2b6c | blueswir1 | helper_fcmpd, |
1547 | 7e8c2b6c | blueswir1 | helper_fcmpd_fcc1, |
1548 | 7e8c2b6c | blueswir1 | helper_fcmpd_fcc2, |
1549 | 7e8c2b6c | blueswir1 | helper_fcmpd_fcc3, |
1550 | 3475187d | bellard | }; |
1551 | 417454b0 | blueswir1 | |
1552 | 1f587329 | blueswir1 | #if defined(CONFIG_USER_ONLY)
|
1553 | 1f587329 | blueswir1 | static GenOpFunc * const gen_fcmpq[4] = { |
1554 | 7e8c2b6c | blueswir1 | helper_fcmpq, |
1555 | 7e8c2b6c | blueswir1 | helper_fcmpq_fcc1, |
1556 | 7e8c2b6c | blueswir1 | helper_fcmpq_fcc2, |
1557 | 7e8c2b6c | blueswir1 | helper_fcmpq_fcc3, |
1558 | 1f587329 | blueswir1 | }; |
1559 | 1f587329 | blueswir1 | #endif
|
1560 | 1f587329 | blueswir1 | |
1561 | 417454b0 | blueswir1 | static GenOpFunc * const gen_fcmpes[4] = { |
1562 | 7e8c2b6c | blueswir1 | helper_fcmpes, |
1563 | 7e8c2b6c | blueswir1 | helper_fcmpes_fcc1, |
1564 | 7e8c2b6c | blueswir1 | helper_fcmpes_fcc2, |
1565 | 7e8c2b6c | blueswir1 | helper_fcmpes_fcc3, |
1566 | 417454b0 | blueswir1 | }; |
1567 | 417454b0 | blueswir1 | |
1568 | 417454b0 | blueswir1 | static GenOpFunc * const gen_fcmped[4] = { |
1569 | 7e8c2b6c | blueswir1 | helper_fcmped, |
1570 | 7e8c2b6c | blueswir1 | helper_fcmped_fcc1, |
1571 | 7e8c2b6c | blueswir1 | helper_fcmped_fcc2, |
1572 | 7e8c2b6c | blueswir1 | helper_fcmped_fcc3, |
1573 | 417454b0 | blueswir1 | }; |
1574 | 417454b0 | blueswir1 | |
1575 | 1f587329 | blueswir1 | #if defined(CONFIG_USER_ONLY)
|
1576 | 1f587329 | blueswir1 | static GenOpFunc * const gen_fcmpeq[4] = { |
1577 | 7e8c2b6c | blueswir1 | helper_fcmpeq, |
1578 | 7e8c2b6c | blueswir1 | helper_fcmpeq_fcc1, |
1579 | 7e8c2b6c | blueswir1 | helper_fcmpeq_fcc2, |
1580 | 7e8c2b6c | blueswir1 | helper_fcmpeq_fcc3, |
1581 | 1f587329 | blueswir1 | }; |
1582 | 1f587329 | blueswir1 | #endif
|
1583 | 7e8c2b6c | blueswir1 | |
1584 | 7e8c2b6c | blueswir1 | static inline void gen_op_fcmps(int fccno) |
1585 | 7e8c2b6c | blueswir1 | { |
1586 | 7e8c2b6c | blueswir1 | tcg_gen_helper_0_0(gen_fcmps[fccno]); |
1587 | 7e8c2b6c | blueswir1 | } |
1588 | 7e8c2b6c | blueswir1 | |
1589 | 7e8c2b6c | blueswir1 | static inline void gen_op_fcmpd(int fccno) |
1590 | 7e8c2b6c | blueswir1 | { |
1591 | 7e8c2b6c | blueswir1 | tcg_gen_helper_0_0(gen_fcmpd[fccno]); |
1592 | 7e8c2b6c | blueswir1 | } |
1593 | 7e8c2b6c | blueswir1 | |
1594 | 7e8c2b6c | blueswir1 | #if defined(CONFIG_USER_ONLY)
|
1595 | 7e8c2b6c | blueswir1 | static inline void gen_op_fcmpq(int fccno) |
1596 | 7e8c2b6c | blueswir1 | { |
1597 | 7e8c2b6c | blueswir1 | tcg_gen_helper_0_0(gen_fcmpq[fccno]); |
1598 | 7e8c2b6c | blueswir1 | } |
1599 | 7e8c2b6c | blueswir1 | #endif
|
1600 | 7e8c2b6c | blueswir1 | |
1601 | 7e8c2b6c | blueswir1 | static inline void gen_op_fcmpes(int fccno) |
1602 | 7e8c2b6c | blueswir1 | { |
1603 | 7e8c2b6c | blueswir1 | tcg_gen_helper_0_0(gen_fcmpes[fccno]); |
1604 | 7e8c2b6c | blueswir1 | } |
1605 | 7e8c2b6c | blueswir1 | |
1606 | 7e8c2b6c | blueswir1 | static inline void gen_op_fcmped(int fccno) |
1607 | 7e8c2b6c | blueswir1 | { |
1608 | 7e8c2b6c | blueswir1 | tcg_gen_helper_0_0(gen_fcmped[fccno]); |
1609 | 7e8c2b6c | blueswir1 | } |
1610 | 7e8c2b6c | blueswir1 | |
1611 | 7e8c2b6c | blueswir1 | #if defined(CONFIG_USER_ONLY)
|
1612 | 7e8c2b6c | blueswir1 | static inline void gen_op_fcmpeq(int fccno) |
1613 | 7e8c2b6c | blueswir1 | { |
1614 | 7e8c2b6c | blueswir1 | tcg_gen_helper_0_0(gen_fcmpeq[fccno]); |
1615 | 7e8c2b6c | blueswir1 | } |
1616 | 7e8c2b6c | blueswir1 | #endif
|
1617 | 7e8c2b6c | blueswir1 | |
1618 | 7e8c2b6c | blueswir1 | #else
|
1619 | 7e8c2b6c | blueswir1 | |
1620 | 7e8c2b6c | blueswir1 | static inline void gen_op_fcmps(int fccno) |
1621 | 7e8c2b6c | blueswir1 | { |
1622 | 7e8c2b6c | blueswir1 | tcg_gen_helper_0_0(helper_fcmps); |
1623 | 7e8c2b6c | blueswir1 | } |
1624 | 7e8c2b6c | blueswir1 | |
1625 | 7e8c2b6c | blueswir1 | static inline void gen_op_fcmpd(int fccno) |
1626 | 7e8c2b6c | blueswir1 | { |
1627 | 7e8c2b6c | blueswir1 | tcg_gen_helper_0_0(helper_fcmpd); |
1628 | 7e8c2b6c | blueswir1 | } |
1629 | 7e8c2b6c | blueswir1 | |
1630 | 7e8c2b6c | blueswir1 | #if defined(CONFIG_USER_ONLY)
|
1631 | 7e8c2b6c | blueswir1 | static inline void gen_op_fcmpq(int fccno) |
1632 | 7e8c2b6c | blueswir1 | { |
1633 | 7e8c2b6c | blueswir1 | tcg_gen_helper_0_0(helper_fcmpq); |
1634 | 7e8c2b6c | blueswir1 | } |
1635 | 7e8c2b6c | blueswir1 | #endif
|
1636 | 7e8c2b6c | blueswir1 | |
1637 | 7e8c2b6c | blueswir1 | static inline void gen_op_fcmpes(int fccno) |
1638 | 7e8c2b6c | blueswir1 | { |
1639 | 7e8c2b6c | blueswir1 | tcg_gen_helper_0_0(helper_fcmpes); |
1640 | 7e8c2b6c | blueswir1 | } |
1641 | 7e8c2b6c | blueswir1 | |
1642 | 7e8c2b6c | blueswir1 | static inline void gen_op_fcmped(int fccno) |
1643 | 7e8c2b6c | blueswir1 | { |
1644 | 7e8c2b6c | blueswir1 | tcg_gen_helper_0_0(helper_fcmped); |
1645 | 7e8c2b6c | blueswir1 | } |
1646 | 7e8c2b6c | blueswir1 | |
1647 | 7e8c2b6c | blueswir1 | #if defined(CONFIG_USER_ONLY)
|
1648 | 7e8c2b6c | blueswir1 | static inline void gen_op_fcmpeq(int fccno) |
1649 | 7e8c2b6c | blueswir1 | { |
1650 | 7e8c2b6c | blueswir1 | tcg_gen_helper_0_0(helper_fcmpeq); |
1651 | 7e8c2b6c | blueswir1 | } |
1652 | 7e8c2b6c | blueswir1 | #endif
|
1653 | 7e8c2b6c | blueswir1 | |
1654 | 3475187d | bellard | #endif
|
1655 | 3475187d | bellard | |
1656 | 134d77a1 | blueswir1 | static inline void gen_op_fpexception_im(int fsr_flags) |
1657 | 134d77a1 | blueswir1 | { |
1658 | 87e92502 | blueswir1 | tcg_gen_andi_tl(cpu_fsr, cpu_fsr, ~FSR_FTT_MASK); |
1659 | 87e92502 | blueswir1 | tcg_gen_ori_tl(cpu_fsr, cpu_fsr, fsr_flags); |
1660 | 134d77a1 | blueswir1 | gen_op_exception(TT_FP_EXCP); |
1661 | 134d77a1 | blueswir1 | } |
1662 | 134d77a1 | blueswir1 | |
1663 | a80dde08 | bellard | static int gen_trap_ifnofpu(DisasContext * dc) |
1664 | a80dde08 | bellard | { |
1665 | a80dde08 | bellard | #if !defined(CONFIG_USER_ONLY)
|
1666 | a80dde08 | bellard | if (!dc->fpu_enabled) {
|
1667 | a80dde08 | bellard | save_state(dc); |
1668 | a80dde08 | bellard | gen_op_exception(TT_NFPU_INSN); |
1669 | a80dde08 | bellard | dc->is_br = 1;
|
1670 | a80dde08 | bellard | return 1; |
1671 | a80dde08 | bellard | } |
1672 | a80dde08 | bellard | #endif
|
1673 | a80dde08 | bellard | return 0; |
1674 | a80dde08 | bellard | } |
1675 | a80dde08 | bellard | |
1676 | 7e8c2b6c | blueswir1 | static inline void gen_op_clear_ieee_excp_and_FTT(void) |
1677 | 7e8c2b6c | blueswir1 | { |
1678 | 87e92502 | blueswir1 | tcg_gen_andi_tl(cpu_fsr, cpu_fsr, ~(FSR_FTT_MASK | FSR_CEXC_MASK)); |
1679 | 7e8c2b6c | blueswir1 | } |
1680 | 7e8c2b6c | blueswir1 | |
1681 | 7e8c2b6c | blueswir1 | static inline void gen_clear_float_exceptions(void) |
1682 | 7e8c2b6c | blueswir1 | { |
1683 | 7e8c2b6c | blueswir1 | tcg_gen_helper_0_0(helper_clear_float_exceptions); |
1684 | 7e8c2b6c | blueswir1 | } |
1685 | 7e8c2b6c | blueswir1 | |
1686 | 2b29924f | blueswir1 | static inline void gen_check_align(TCGv r_addr, int align) |
1687 | 2b29924f | blueswir1 | { |
1688 | 2b29924f | blueswir1 | tcg_gen_helper_0_2(helper_check_align, r_addr, tcg_const_i32(align)); |
1689 | 2b29924f | blueswir1 | } |
1690 | 2b29924f | blueswir1 | |
1691 | 2b29924f | blueswir1 | static inline void gen_op_check_align_T0_1(void) |
1692 | 2b29924f | blueswir1 | { |
1693 | 2b29924f | blueswir1 | gen_check_align(cpu_T[0], 1); |
1694 | 2b29924f | blueswir1 | } |
1695 | 2b29924f | blueswir1 | |
1696 | 2b29924f | blueswir1 | static inline void gen_op_check_align_T0_3(void) |
1697 | 2b29924f | blueswir1 | { |
1698 | 2b29924f | blueswir1 | gen_check_align(cpu_T[0], 3); |
1699 | 2b29924f | blueswir1 | } |
1700 | 2b29924f | blueswir1 | |
1701 | 2b29924f | blueswir1 | static inline void gen_op_check_align_T0_7(void) |
1702 | 2b29924f | blueswir1 | { |
1703 | 2b29924f | blueswir1 | gen_check_align(cpu_T[0], 7); |
1704 | 2b29924f | blueswir1 | } |
1705 | 2b29924f | blueswir1 | |
1706 | 1a2fb1c0 | blueswir1 | /* asi moves */
|
1707 | 1a2fb1c0 | blueswir1 | #ifdef TARGET_SPARC64
|
1708 | 0425bee5 | blueswir1 | static inline TCGv gen_get_asi(int insn, TCGv r_addr) |
1709 | 1a2fb1c0 | blueswir1 | { |
1710 | 1a2fb1c0 | blueswir1 | int asi, offset;
|
1711 | 0425bee5 | blueswir1 | TCGv r_asi; |
1712 | 1a2fb1c0 | blueswir1 | |
1713 | 1a2fb1c0 | blueswir1 | if (IS_IMM) {
|
1714 | 0425bee5 | blueswir1 | r_asi = tcg_temp_new(TCG_TYPE_I32); |
1715 | 1a2fb1c0 | blueswir1 | offset = GET_FIELD(insn, 25, 31); |
1716 | 0425bee5 | blueswir1 | tcg_gen_addi_tl(r_addr, r_addr, offset); |
1717 | 0425bee5 | blueswir1 | tcg_gen_ld_i32(r_asi, cpu_env, offsetof(CPUSPARCState, asi)); |
1718 | 1a2fb1c0 | blueswir1 | } else {
|
1719 | 1a2fb1c0 | blueswir1 | asi = GET_FIELD(insn, 19, 26); |
1720 | 0425bee5 | blueswir1 | r_asi = tcg_const_i32(asi); |
1721 | 1a2fb1c0 | blueswir1 | } |
1722 | 0425bee5 | blueswir1 | return r_asi;
|
1723 | 0425bee5 | blueswir1 | } |
1724 | 0425bee5 | blueswir1 | |
1725 | 0425bee5 | blueswir1 | static inline void gen_ld_asi(int insn, int size, int sign) |
1726 | 0425bee5 | blueswir1 | { |
1727 | 0425bee5 | blueswir1 | TCGv r_asi; |
1728 | 0425bee5 | blueswir1 | |
1729 | 0425bee5 | blueswir1 | r_asi = gen_get_asi(insn, cpu_T[0]);
|
1730 | 0425bee5 | blueswir1 | tcg_gen_helper_1_4(helper_ld_asi, cpu_T[1], cpu_T[0], r_asi, |
1731 | 0425bee5 | blueswir1 | tcg_const_i32(size), tcg_const_i32(sign)); |
1732 | 0425bee5 | blueswir1 | tcg_gen_discard_i32(r_asi); |
1733 | 1a2fb1c0 | blueswir1 | } |
1734 | 1a2fb1c0 | blueswir1 | |
1735 | 1a2fb1c0 | blueswir1 | static inline void gen_st_asi(int insn, int size) |
1736 | 1a2fb1c0 | blueswir1 | { |
1737 | 0425bee5 | blueswir1 | TCGv r_asi; |
1738 | 1a2fb1c0 | blueswir1 | |
1739 | 0425bee5 | blueswir1 | r_asi = gen_get_asi(insn, cpu_T[0]);
|
1740 | 0425bee5 | blueswir1 | tcg_gen_helper_0_4(helper_st_asi, cpu_T[0], cpu_T[1], r_asi, |
1741 | 0425bee5 | blueswir1 | tcg_const_i32(size)); |
1742 | 0425bee5 | blueswir1 | tcg_gen_discard_i32(r_asi); |
1743 | 1a2fb1c0 | blueswir1 | } |
1744 | 1a2fb1c0 | blueswir1 | |
1745 | 1a2fb1c0 | blueswir1 | static inline void gen_ldf_asi(int insn, int size, int rd) |
1746 | 1a2fb1c0 | blueswir1 | { |
1747 | 0425bee5 | blueswir1 | TCGv r_asi; |
1748 | 1a2fb1c0 | blueswir1 | |
1749 | 0425bee5 | blueswir1 | r_asi = gen_get_asi(insn, cpu_T[0]);
|
1750 | 0425bee5 | blueswir1 | tcg_gen_helper_0_4(helper_ldf_asi, cpu_T[0], r_asi, tcg_const_i32(size),
|
1751 | 0425bee5 | blueswir1 | tcg_const_i32(rd)); |
1752 | 0425bee5 | blueswir1 | tcg_gen_discard_i32(r_asi); |
1753 | 1a2fb1c0 | blueswir1 | } |
1754 | 1a2fb1c0 | blueswir1 | |
1755 | 1a2fb1c0 | blueswir1 | static inline void gen_stf_asi(int insn, int size, int rd) |
1756 | 1a2fb1c0 | blueswir1 | { |
1757 | 0425bee5 | blueswir1 | TCGv r_asi; |
1758 | 1a2fb1c0 | blueswir1 | |
1759 | 0425bee5 | blueswir1 | r_asi = gen_get_asi(insn, cpu_T[0]);
|
1760 | 0425bee5 | blueswir1 | tcg_gen_helper_0_4(helper_stf_asi, cpu_T[0], r_asi, tcg_const_i32(size),
|
1761 | 0425bee5 | blueswir1 | tcg_const_i32(rd)); |
1762 | 0425bee5 | blueswir1 | tcg_gen_discard_i32(r_asi); |
1763 | 1a2fb1c0 | blueswir1 | } |
1764 | 1a2fb1c0 | blueswir1 | |
1765 | 1a2fb1c0 | blueswir1 | static inline void gen_swap_asi(int insn) |
1766 | 1a2fb1c0 | blueswir1 | { |
1767 | 0425bee5 | blueswir1 | TCGv r_temp, r_asi; |
1768 | 1a2fb1c0 | blueswir1 | |
1769 | 1a2fb1c0 | blueswir1 | r_temp = tcg_temp_new(TCG_TYPE_I32); |
1770 | 0425bee5 | blueswir1 | r_asi = gen_get_asi(insn, cpu_T[0]);
|
1771 | 0425bee5 | blueswir1 | tcg_gen_helper_1_4(helper_ld_asi, r_temp, cpu_T[0], r_asi,
|
1772 | 0425bee5 | blueswir1 | tcg_const_i32(4), tcg_const_i32(0)); |
1773 | 0425bee5 | blueswir1 | tcg_gen_helper_0_4(helper_st_asi, cpu_T[0], r_temp, r_asi,
|
1774 | 0425bee5 | blueswir1 | tcg_const_i32(4));
|
1775 | 8911f501 | blueswir1 | tcg_gen_extu_i32_tl(cpu_T[1], r_temp);
|
1776 | 0425bee5 | blueswir1 | tcg_gen_discard_i32(r_asi); |
1777 | 0425bee5 | blueswir1 | tcg_gen_discard_i32(r_temp); |
1778 | 1a2fb1c0 | blueswir1 | } |
1779 | 1a2fb1c0 | blueswir1 | |
1780 | 1a2fb1c0 | blueswir1 | static inline void gen_ldda_asi(int insn) |
1781 | 1a2fb1c0 | blueswir1 | { |
1782 | 8911f501 | blueswir1 | TCGv r_asi; |
1783 | 1a2fb1c0 | blueswir1 | |
1784 | 0425bee5 | blueswir1 | r_asi = gen_get_asi(insn, cpu_T[0]);
|
1785 | 8911f501 | blueswir1 | tcg_gen_helper_1_4(helper_ld_asi, cpu_tmp64, cpu_T[0], r_asi,
|
1786 | 0425bee5 | blueswir1 | tcg_const_i32(8), tcg_const_i32(0)); |
1787 | 8911f501 | blueswir1 | tcg_gen_andi_i64(cpu_T[0], cpu_tmp64, 0xffffffffULL); |
1788 | 8911f501 | blueswir1 | tcg_gen_shri_i64(cpu_tmp64, cpu_tmp64, 32);
|
1789 | 8911f501 | blueswir1 | tcg_gen_andi_i64(cpu_T[1], cpu_tmp64, 0xffffffffULL); |
1790 | 0425bee5 | blueswir1 | tcg_gen_discard_i32(r_asi); |
1791 | 0425bee5 | blueswir1 | } |
1792 | 0425bee5 | blueswir1 | |
1793 | 0425bee5 | blueswir1 | static inline void gen_stda_asi(int insn, int rd) |
1794 | 0425bee5 | blueswir1 | { |
1795 | 8911f501 | blueswir1 | TCGv r_temp, r_asi; |
1796 | 0425bee5 | blueswir1 | |
1797 | 0425bee5 | blueswir1 | r_temp = tcg_temp_new(TCG_TYPE_I32); |
1798 | 0425bee5 | blueswir1 | gen_movl_reg_TN(rd + 1, r_temp);
|
1799 | 8911f501 | blueswir1 | tcg_gen_helper_1_2(helper_pack64, cpu_tmp64, cpu_T[1],
|
1800 | 0425bee5 | blueswir1 | r_temp); |
1801 | 0425bee5 | blueswir1 | r_asi = gen_get_asi(insn, cpu_T[0]);
|
1802 | 8911f501 | blueswir1 | tcg_gen_helper_0_4(helper_st_asi, cpu_T[0], cpu_tmp64, r_asi,
|
1803 | 0425bee5 | blueswir1 | tcg_const_i32(8));
|
1804 | 0425bee5 | blueswir1 | tcg_gen_discard_i32(r_asi); |
1805 | 0425bee5 | blueswir1 | tcg_gen_discard_i32(r_temp); |
1806 | 1a2fb1c0 | blueswir1 | } |
1807 | 1a2fb1c0 | blueswir1 | |
1808 | 1a2fb1c0 | blueswir1 | static inline void gen_cas_asi(int insn, int rd) |
1809 | 1a2fb1c0 | blueswir1 | { |
1810 | 1a2fb1c0 | blueswir1 | TCGv r_val1, r_asi; |
1811 | 1a2fb1c0 | blueswir1 | |
1812 | 1a2fb1c0 | blueswir1 | r_val1 = tcg_temp_new(TCG_TYPE_I32); |
1813 | 1a2fb1c0 | blueswir1 | gen_movl_reg_TN(rd, r_val1); |
1814 | 0425bee5 | blueswir1 | r_asi = gen_get_asi(insn, cpu_T[0]);
|
1815 | 1a2fb1c0 | blueswir1 | tcg_gen_helper_1_4(helper_cas_asi, cpu_T[1], cpu_T[0], r_val1, cpu_T[1], |
1816 | 1a2fb1c0 | blueswir1 | r_asi); |
1817 | 0425bee5 | blueswir1 | tcg_gen_discard_i32(r_asi); |
1818 | 0425bee5 | blueswir1 | tcg_gen_discard_i32(r_val1); |
1819 | 1a2fb1c0 | blueswir1 | } |
1820 | 1a2fb1c0 | blueswir1 | |
1821 | 1a2fb1c0 | blueswir1 | static inline void gen_casx_asi(int insn, int rd) |
1822 | 1a2fb1c0 | blueswir1 | { |
1823 | 8911f501 | blueswir1 | TCGv r_asi; |
1824 | 1a2fb1c0 | blueswir1 | |
1825 | 8911f501 | blueswir1 | gen_movl_reg_TN(rd, cpu_tmp64); |
1826 | 0425bee5 | blueswir1 | r_asi = gen_get_asi(insn, cpu_T[0]);
|
1827 | 8911f501 | blueswir1 | tcg_gen_helper_1_4(helper_casx_asi, cpu_T[1], cpu_T[0], cpu_tmp64, cpu_T[1], |
1828 | 1a2fb1c0 | blueswir1 | r_asi); |
1829 | 0425bee5 | blueswir1 | tcg_gen_discard_i32(r_asi); |
1830 | 1a2fb1c0 | blueswir1 | } |
1831 | 1a2fb1c0 | blueswir1 | |
1832 | 1a2fb1c0 | blueswir1 | #elif !defined(CONFIG_USER_ONLY)
|
1833 | 1a2fb1c0 | blueswir1 | |
1834 | 1a2fb1c0 | blueswir1 | static inline void gen_ld_asi(int insn, int size, int sign) |
1835 | 1a2fb1c0 | blueswir1 | { |
1836 | 1a2fb1c0 | blueswir1 | int asi;
|
1837 | 1a2fb1c0 | blueswir1 | |
1838 | 1a2fb1c0 | blueswir1 | asi = GET_FIELD(insn, 19, 26); |
1839 | 8911f501 | blueswir1 | tcg_gen_helper_1_4(helper_ld_asi, cpu_tmp64, cpu_T[0], tcg_const_i32(asi),
|
1840 | 0425bee5 | blueswir1 | tcg_const_i32(size), tcg_const_i32(sign)); |
1841 | 8911f501 | blueswir1 | tcg_gen_trunc_i64_tl(cpu_T[1], cpu_tmp64);
|
1842 | 1a2fb1c0 | blueswir1 | } |
1843 | 1a2fb1c0 | blueswir1 | |
1844 | 1a2fb1c0 | blueswir1 | static inline void gen_st_asi(int insn, int size) |
1845 | 1a2fb1c0 | blueswir1 | { |
1846 | 1a2fb1c0 | blueswir1 | int asi;
|
1847 | 1a2fb1c0 | blueswir1 | |
1848 | 8911f501 | blueswir1 | tcg_gen_extu_tl_i64(cpu_tmp64, cpu_T[1]);
|
1849 | 1a2fb1c0 | blueswir1 | asi = GET_FIELD(insn, 19, 26); |
1850 | 8911f501 | blueswir1 | tcg_gen_helper_0_4(helper_st_asi, cpu_T[0], cpu_tmp64, tcg_const_i32(asi),
|
1851 | 0425bee5 | blueswir1 | tcg_const_i32(size)); |
1852 | 1a2fb1c0 | blueswir1 | } |
1853 | 1a2fb1c0 | blueswir1 | |
1854 | 1a2fb1c0 | blueswir1 | static inline void gen_swap_asi(int insn) |
1855 | 1a2fb1c0 | blueswir1 | { |
1856 | 1a2fb1c0 | blueswir1 | int asi;
|
1857 | 0425bee5 | blueswir1 | TCGv r_temp; |
1858 | 1a2fb1c0 | blueswir1 | |
1859 | 1a2fb1c0 | blueswir1 | r_temp = tcg_temp_new(TCG_TYPE_I32); |
1860 | 1a2fb1c0 | blueswir1 | asi = GET_FIELD(insn, 19, 26); |
1861 | 0425bee5 | blueswir1 | tcg_gen_helper_1_4(helper_ld_asi, r_temp, cpu_T[0], tcg_const_i32(asi),
|
1862 | 0425bee5 | blueswir1 | tcg_const_i32(4), tcg_const_i32(0)); |
1863 | 0425bee5 | blueswir1 | tcg_gen_helper_0_4(helper_st_asi, cpu_T[0], cpu_T[1], tcg_const_i32(asi), |
1864 | 0425bee5 | blueswir1 | tcg_const_i32(4));
|
1865 | 8911f501 | blueswir1 | tcg_gen_extu_i32_tl(cpu_T[1], r_temp);
|
1866 | 0425bee5 | blueswir1 | tcg_gen_discard_i32(r_temp); |
1867 | 1a2fb1c0 | blueswir1 | } |
1868 | 1a2fb1c0 | blueswir1 | |
1869 | 1a2fb1c0 | blueswir1 | static inline void gen_ldda_asi(int insn) |
1870 | 1a2fb1c0 | blueswir1 | { |
1871 | 1a2fb1c0 | blueswir1 | int asi;
|
1872 | 1a2fb1c0 | blueswir1 | |
1873 | 1a2fb1c0 | blueswir1 | asi = GET_FIELD(insn, 19, 26); |
1874 | 8911f501 | blueswir1 | tcg_gen_helper_1_4(helper_ld_asi, cpu_tmp64, cpu_T[0], tcg_const_i32(asi),
|
1875 | 0425bee5 | blueswir1 | tcg_const_i32(8), tcg_const_i32(0)); |
1876 | 8911f501 | blueswir1 | tcg_gen_trunc_i64_tl(cpu_T[0], cpu_tmp64);
|
1877 | 8911f501 | blueswir1 | tcg_gen_shri_i64(cpu_tmp64, cpu_tmp64, 32);
|
1878 | 8911f501 | blueswir1 | tcg_gen_trunc_i64_tl(cpu_T[1], cpu_tmp64);
|
1879 | 0425bee5 | blueswir1 | } |
1880 | 0425bee5 | blueswir1 | |
1881 | 0425bee5 | blueswir1 | static inline void gen_stda_asi(int insn, int rd) |
1882 | 0425bee5 | blueswir1 | { |
1883 | 0425bee5 | blueswir1 | int asi;
|
1884 | 8911f501 | blueswir1 | TCGv r_temp; |
1885 | 0425bee5 | blueswir1 | |
1886 | 0425bee5 | blueswir1 | r_temp = tcg_temp_new(TCG_TYPE_I32); |
1887 | 0425bee5 | blueswir1 | gen_movl_reg_TN(rd + 1, r_temp);
|
1888 | 8911f501 | blueswir1 | tcg_gen_helper_1_2(helper_pack64, cpu_tmp64, cpu_T[1], r_temp);
|
1889 | 0425bee5 | blueswir1 | asi = GET_FIELD(insn, 19, 26); |
1890 | 8911f501 | blueswir1 | tcg_gen_helper_0_4(helper_st_asi, cpu_T[0], cpu_tmp64, tcg_const_i32(asi),
|
1891 | 0425bee5 | blueswir1 | tcg_const_i32(8));
|
1892 | 1a2fb1c0 | blueswir1 | } |
1893 | 1a2fb1c0 | blueswir1 | #endif
|
1894 | 1a2fb1c0 | blueswir1 | |
1895 | 1a2fb1c0 | blueswir1 | #if !defined(CONFIG_USER_ONLY) || defined(TARGET_SPARC64)
|
1896 | 1a2fb1c0 | blueswir1 | static inline void gen_ldstub_asi(int insn) |
1897 | 1a2fb1c0 | blueswir1 | { |
1898 | 1a2fb1c0 | blueswir1 | int asi;
|
1899 | 1a2fb1c0 | blueswir1 | |
1900 | 1a2fb1c0 | blueswir1 | gen_ld_asi(insn, 1, 0); |
1901 | 1a2fb1c0 | blueswir1 | |
1902 | 1a2fb1c0 | blueswir1 | asi = GET_FIELD(insn, 19, 26); |
1903 | 8911f501 | blueswir1 | tcg_gen_helper_0_4(helper_st_asi, cpu_T[0], tcg_const_i64(0xffULL), |
1904 | 0425bee5 | blueswir1 | tcg_const_i32(asi), tcg_const_i32(1));
|
1905 | 1a2fb1c0 | blueswir1 | } |
1906 | 1a2fb1c0 | blueswir1 | #endif
|
1907 | 1a2fb1c0 | blueswir1 | |
1908 | 0bee699e | bellard | /* before an instruction, dc->pc must be static */
|
1909 | cf495bcf | bellard | static void disas_sparc_insn(DisasContext * dc) |
1910 | cf495bcf | bellard | { |
1911 | cf495bcf | bellard | unsigned int insn, opc, rs1, rs2, rd; |
1912 | 7a3f1944 | bellard | |
1913 | 0fa85d43 | bellard | insn = ldl_code(dc->pc); |
1914 | cf495bcf | bellard | opc = GET_FIELD(insn, 0, 1); |
1915 | 7a3f1944 | bellard | |
1916 | cf495bcf | bellard | rd = GET_FIELD(insn, 2, 6); |
1917 | cf495bcf | bellard | switch (opc) {
|
1918 | 0f8a249a | blueswir1 | case 0: /* branches/sethi */ |
1919 | 0f8a249a | blueswir1 | { |
1920 | 0f8a249a | blueswir1 | unsigned int xop = GET_FIELD(insn, 7, 9); |
1921 | 0f8a249a | blueswir1 | int32_t target; |
1922 | 0f8a249a | blueswir1 | switch (xop) {
|
1923 | 3475187d | bellard | #ifdef TARGET_SPARC64
|
1924 | 0f8a249a | blueswir1 | case 0x1: /* V9 BPcc */ |
1925 | 0f8a249a | blueswir1 | { |
1926 | 0f8a249a | blueswir1 | int cc;
|
1927 | 0f8a249a | blueswir1 | |
1928 | 0f8a249a | blueswir1 | target = GET_FIELD_SP(insn, 0, 18); |
1929 | 0f8a249a | blueswir1 | target = sign_extend(target, 18);
|
1930 | 0f8a249a | blueswir1 | target <<= 2;
|
1931 | 0f8a249a | blueswir1 | cc = GET_FIELD_SP(insn, 20, 21); |
1932 | 0f8a249a | blueswir1 | if (cc == 0) |
1933 | 0f8a249a | blueswir1 | do_branch(dc, target, insn, 0);
|
1934 | 0f8a249a | blueswir1 | else if (cc == 2) |
1935 | 0f8a249a | blueswir1 | do_branch(dc, target, insn, 1);
|
1936 | 0f8a249a | blueswir1 | else
|
1937 | 0f8a249a | blueswir1 | goto illegal_insn;
|
1938 | 0f8a249a | blueswir1 | goto jmp_insn;
|
1939 | 0f8a249a | blueswir1 | } |
1940 | 0f8a249a | blueswir1 | case 0x3: /* V9 BPr */ |
1941 | 0f8a249a | blueswir1 | { |
1942 | 0f8a249a | blueswir1 | target = GET_FIELD_SP(insn, 0, 13) | |
1943 | 13846e70 | bellard | (GET_FIELD_SP(insn, 20, 21) << 14); |
1944 | 0f8a249a | blueswir1 | target = sign_extend(target, 16);
|
1945 | 0f8a249a | blueswir1 | target <<= 2;
|
1946 | 0f8a249a | blueswir1 | rs1 = GET_FIELD(insn, 13, 17); |
1947 | 0f8a249a | blueswir1 | gen_movl_reg_T0(rs1); |
1948 | 0f8a249a | blueswir1 | do_branch_reg(dc, target, insn); |
1949 | 0f8a249a | blueswir1 | goto jmp_insn;
|
1950 | 0f8a249a | blueswir1 | } |
1951 | 0f8a249a | blueswir1 | case 0x5: /* V9 FBPcc */ |
1952 | 0f8a249a | blueswir1 | { |
1953 | 0f8a249a | blueswir1 | int cc = GET_FIELD_SP(insn, 20, 21); |
1954 | a80dde08 | bellard | if (gen_trap_ifnofpu(dc))
|
1955 | a80dde08 | bellard | goto jmp_insn;
|
1956 | 0f8a249a | blueswir1 | target = GET_FIELD_SP(insn, 0, 18); |
1957 | 0f8a249a | blueswir1 | target = sign_extend(target, 19);
|
1958 | 0f8a249a | blueswir1 | target <<= 2;
|
1959 | 0f8a249a | blueswir1 | do_fbranch(dc, target, insn, cc); |
1960 | 0f8a249a | blueswir1 | goto jmp_insn;
|
1961 | 0f8a249a | blueswir1 | } |
1962 | a4d17f19 | blueswir1 | #else
|
1963 | 0f8a249a | blueswir1 | case 0x7: /* CBN+x */ |
1964 | 0f8a249a | blueswir1 | { |
1965 | 0f8a249a | blueswir1 | goto ncp_insn;
|
1966 | 0f8a249a | blueswir1 | } |
1967 | 0f8a249a | blueswir1 | #endif
|
1968 | 0f8a249a | blueswir1 | case 0x2: /* BN+x */ |
1969 | 0f8a249a | blueswir1 | { |
1970 | 0f8a249a | blueswir1 | target = GET_FIELD(insn, 10, 31); |
1971 | 0f8a249a | blueswir1 | target = sign_extend(target, 22);
|
1972 | 0f8a249a | blueswir1 | target <<= 2;
|
1973 | 0f8a249a | blueswir1 | do_branch(dc, target, insn, 0);
|
1974 | 0f8a249a | blueswir1 | goto jmp_insn;
|
1975 | 0f8a249a | blueswir1 | } |
1976 | 0f8a249a | blueswir1 | case 0x6: /* FBN+x */ |
1977 | 0f8a249a | blueswir1 | { |
1978 | a80dde08 | bellard | if (gen_trap_ifnofpu(dc))
|
1979 | a80dde08 | bellard | goto jmp_insn;
|
1980 | 0f8a249a | blueswir1 | target = GET_FIELD(insn, 10, 31); |
1981 | 0f8a249a | blueswir1 | target = sign_extend(target, 22);
|
1982 | 0f8a249a | blueswir1 | target <<= 2;
|
1983 | 0f8a249a | blueswir1 | do_fbranch(dc, target, insn, 0);
|
1984 | 0f8a249a | blueswir1 | goto jmp_insn;
|
1985 | 0f8a249a | blueswir1 | } |
1986 | 0f8a249a | blueswir1 | case 0x4: /* SETHI */ |
1987 | e80cfcfc | bellard | #define OPTIM
|
1988 | e80cfcfc | bellard | #if defined(OPTIM)
|
1989 | 0f8a249a | blueswir1 | if (rd) { // nop |
1990 | e80cfcfc | bellard | #endif
|
1991 | 0f8a249a | blueswir1 | uint32_t value = GET_FIELD(insn, 10, 31); |
1992 | 1a2fb1c0 | blueswir1 | tcg_gen_movi_tl(cpu_T[0], value << 10); |
1993 | 0f8a249a | blueswir1 | gen_movl_T0_reg(rd); |
1994 | e80cfcfc | bellard | #if defined(OPTIM)
|
1995 | 0f8a249a | blueswir1 | } |
1996 | e80cfcfc | bellard | #endif
|
1997 | 0f8a249a | blueswir1 | break;
|
1998 | 0f8a249a | blueswir1 | case 0x0: /* UNIMPL */ |
1999 | 0f8a249a | blueswir1 | default:
|
2000 | 3475187d | bellard | goto illegal_insn;
|
2001 | 0f8a249a | blueswir1 | } |
2002 | 0f8a249a | blueswir1 | break;
|
2003 | 0f8a249a | blueswir1 | } |
2004 | 0f8a249a | blueswir1 | break;
|
2005 | cf495bcf | bellard | case 1: |
2006 | 0f8a249a | blueswir1 | /*CALL*/ {
|
2007 | 0f8a249a | blueswir1 | target_long target = GET_FIELDs(insn, 2, 31) << 2; |
2008 | cf495bcf | bellard | |
2009 | 48d5c82b | blueswir1 | gen_movl_TN_reg(15, tcg_const_tl(dc->pc));
|
2010 | 0f8a249a | blueswir1 | target += dc->pc; |
2011 | 0bee699e | bellard | gen_mov_pc_npc(dc); |
2012 | 0f8a249a | blueswir1 | dc->npc = target; |
2013 | 0f8a249a | blueswir1 | } |
2014 | 0f8a249a | blueswir1 | goto jmp_insn;
|
2015 | 0f8a249a | blueswir1 | case 2: /* FPU & Logical Operations */ |
2016 | 0f8a249a | blueswir1 | { |
2017 | 0f8a249a | blueswir1 | unsigned int xop = GET_FIELD(insn, 7, 12); |
2018 | 0f8a249a | blueswir1 | if (xop == 0x3a) { /* generate trap */ |
2019 | cf495bcf | bellard | int cond;
|
2020 | 3475187d | bellard | |
2021 | cf495bcf | bellard | rs1 = GET_FIELD(insn, 13, 17); |
2022 | cf495bcf | bellard | gen_movl_reg_T0(rs1); |
2023 | 0f8a249a | blueswir1 | if (IS_IMM) {
|
2024 | 0f8a249a | blueswir1 | rs2 = GET_FIELD(insn, 25, 31); |
2025 | 1a2fb1c0 | blueswir1 | tcg_gen_addi_tl(cpu_T[0], cpu_T[0], rs2); |
2026 | cf495bcf | bellard | } else {
|
2027 | cf495bcf | bellard | rs2 = GET_FIELD(insn, 27, 31); |
2028 | e80cfcfc | bellard | #if defined(OPTIM)
|
2029 | 0f8a249a | blueswir1 | if (rs2 != 0) { |
2030 | e80cfcfc | bellard | #endif
|
2031 | 0f8a249a | blueswir1 | gen_movl_reg_T1(rs2); |
2032 | 0f8a249a | blueswir1 | gen_op_add_T1_T0(); |
2033 | e80cfcfc | bellard | #if defined(OPTIM)
|
2034 | 0f8a249a | blueswir1 | } |
2035 | e80cfcfc | bellard | #endif
|
2036 | cf495bcf | bellard | } |
2037 | cf495bcf | bellard | cond = GET_FIELD(insn, 3, 6); |
2038 | cf495bcf | bellard | if (cond == 0x8) { |
2039 | a80dde08 | bellard | save_state(dc); |
2040 | 1a2fb1c0 | blueswir1 | tcg_gen_helper_0_1(helper_trap, cpu_T[0]);
|
2041 | af7bf89b | bellard | } else if (cond != 0) { |
2042 | 748b9d8e | blueswir1 | TCGv r_cond = tcg_temp_new(TCG_TYPE_TL); |
2043 | 3475187d | bellard | #ifdef TARGET_SPARC64
|
2044 | 0f8a249a | blueswir1 | /* V9 icc/xcc */
|
2045 | 0f8a249a | blueswir1 | int cc = GET_FIELD_SP(insn, 11, 12); |
2046 | 748b9d8e | blueswir1 | |
2047 | a80dde08 | bellard | save_state(dc); |
2048 | 0f8a249a | blueswir1 | if (cc == 0) |
2049 | 748b9d8e | blueswir1 | gen_cond(r_cond, 0, cond);
|
2050 | 0f8a249a | blueswir1 | else if (cc == 2) |
2051 | 748b9d8e | blueswir1 | gen_cond(r_cond, 1, cond);
|
2052 | 0f8a249a | blueswir1 | else
|
2053 | 0f8a249a | blueswir1 | goto illegal_insn;
|
2054 | 3475187d | bellard | #else
|
2055 | a80dde08 | bellard | save_state(dc); |
2056 | 748b9d8e | blueswir1 | gen_cond(r_cond, 0, cond);
|
2057 | 3475187d | bellard | #endif
|
2058 | 748b9d8e | blueswir1 | tcg_gen_helper_0_2(helper_trapcc, cpu_T[0], r_cond);
|
2059 | 0425bee5 | blueswir1 | tcg_gen_discard_tl(r_cond); |
2060 | cf495bcf | bellard | } |
2061 | a80dde08 | bellard | gen_op_next_insn(); |
2062 | 57fec1fe | bellard | tcg_gen_exit_tb(0);
|
2063 | a80dde08 | bellard | dc->is_br = 1;
|
2064 | a80dde08 | bellard | goto jmp_insn;
|
2065 | cf495bcf | bellard | } else if (xop == 0x28) { |
2066 | cf495bcf | bellard | rs1 = GET_FIELD(insn, 13, 17); |
2067 | cf495bcf | bellard | switch(rs1) {
|
2068 | cf495bcf | bellard | case 0: /* rdy */ |
2069 | 65fe7b09 | blueswir1 | #ifndef TARGET_SPARC64
|
2070 | 65fe7b09 | blueswir1 | case 0x01 ... 0x0e: /* undefined in the SPARCv8 |
2071 | 65fe7b09 | blueswir1 | manual, rdy on the microSPARC
|
2072 | 65fe7b09 | blueswir1 | II */
|
2073 | 65fe7b09 | blueswir1 | case 0x0f: /* stbar in the SPARCv8 manual, |
2074 | 65fe7b09 | blueswir1 | rdy on the microSPARC II */
|
2075 | 65fe7b09 | blueswir1 | case 0x10 ... 0x1f: /* implementation-dependent in the |
2076 | 65fe7b09 | blueswir1 | SPARCv8 manual, rdy on the
|
2077 | 65fe7b09 | blueswir1 | microSPARC II */
|
2078 | 65fe7b09 | blueswir1 | #endif
|
2079 | 65fe7b09 | blueswir1 | gen_op_movtl_T0_env(offsetof(CPUSPARCState, y)); |
2080 | cf495bcf | bellard | gen_movl_T0_reg(rd); |
2081 | cf495bcf | bellard | break;
|
2082 | 3475187d | bellard | #ifdef TARGET_SPARC64
|
2083 | 0f8a249a | blueswir1 | case 0x2: /* V9 rdccr */ |
2084 | d35527d9 | blueswir1 | tcg_gen_helper_1_0(helper_rdccr, cpu_T[0]);
|
2085 | 3475187d | bellard | gen_movl_T0_reg(rd); |
2086 | 3475187d | bellard | break;
|
2087 | 0f8a249a | blueswir1 | case 0x3: /* V9 rdasi */ |
2088 | 0f8a249a | blueswir1 | gen_op_movl_T0_env(offsetof(CPUSPARCState, asi)); |
2089 | 3475187d | bellard | gen_movl_T0_reg(rd); |
2090 | 3475187d | bellard | break;
|
2091 | 0f8a249a | blueswir1 | case 0x4: /* V9 rdtick */ |
2092 | ccd4a219 | blueswir1 | { |
2093 | ccd4a219 | blueswir1 | TCGv r_tickptr; |
2094 | ccd4a219 | blueswir1 | |
2095 | ccd4a219 | blueswir1 | r_tickptr = tcg_temp_new(TCG_TYPE_PTR); |
2096 | ccd4a219 | blueswir1 | tcg_gen_ld_ptr(r_tickptr, cpu_env, |
2097 | ccd4a219 | blueswir1 | offsetof(CPUState, tick)); |
2098 | ccd4a219 | blueswir1 | tcg_gen_helper_1_1(helper_tick_get_count, cpu_T[0],
|
2099 | ccd4a219 | blueswir1 | r_tickptr); |
2100 | ccd4a219 | blueswir1 | gen_movl_T0_reg(rd); |
2101 | 0425bee5 | blueswir1 | tcg_gen_discard_ptr(r_tickptr); |
2102 | ccd4a219 | blueswir1 | } |
2103 | 3475187d | bellard | break;
|
2104 | 0f8a249a | blueswir1 | case 0x5: /* V9 rdpc */ |
2105 | 1a2fb1c0 | blueswir1 | tcg_gen_movi_tl(cpu_T[0], dc->pc);
|
2106 | 0f8a249a | blueswir1 | gen_movl_T0_reg(rd); |
2107 | 0f8a249a | blueswir1 | break;
|
2108 | 0f8a249a | blueswir1 | case 0x6: /* V9 rdfprs */ |
2109 | 0f8a249a | blueswir1 | gen_op_movl_T0_env(offsetof(CPUSPARCState, fprs)); |
2110 | 3475187d | bellard | gen_movl_T0_reg(rd); |
2111 | 3475187d | bellard | break;
|
2112 | 65fe7b09 | blueswir1 | case 0xf: /* V9 membar */ |
2113 | 65fe7b09 | blueswir1 | break; /* no effect */ |
2114 | 0f8a249a | blueswir1 | case 0x13: /* Graphics Status */ |
2115 | 725cb90b | bellard | if (gen_trap_ifnofpu(dc))
|
2116 | 725cb90b | bellard | goto jmp_insn;
|
2117 | 0f8a249a | blueswir1 | gen_op_movtl_T0_env(offsetof(CPUSPARCState, gsr)); |
2118 | 725cb90b | bellard | gen_movl_T0_reg(rd); |
2119 | 725cb90b | bellard | break;
|
2120 | 0f8a249a | blueswir1 | case 0x17: /* Tick compare */ |
2121 | 0f8a249a | blueswir1 | gen_op_movtl_T0_env(offsetof(CPUSPARCState, tick_cmpr)); |
2122 | 83469015 | bellard | gen_movl_T0_reg(rd); |
2123 | 83469015 | bellard | break;
|
2124 | 0f8a249a | blueswir1 | case 0x18: /* System tick */ |
2125 | ccd4a219 | blueswir1 | { |
2126 | ccd4a219 | blueswir1 | TCGv r_tickptr; |
2127 | ccd4a219 | blueswir1 | |
2128 | ccd4a219 | blueswir1 | r_tickptr = tcg_temp_new(TCG_TYPE_PTR); |
2129 | ccd4a219 | blueswir1 | tcg_gen_ld_ptr(r_tickptr, cpu_env, |
2130 | ccd4a219 | blueswir1 | offsetof(CPUState, stick)); |
2131 | ccd4a219 | blueswir1 | tcg_gen_helper_1_1(helper_tick_get_count, cpu_T[0],
|
2132 | ccd4a219 | blueswir1 | r_tickptr); |
2133 | ccd4a219 | blueswir1 | gen_movl_T0_reg(rd); |
2134 | 0425bee5 | blueswir1 | tcg_gen_discard_ptr(r_tickptr); |
2135 | ccd4a219 | blueswir1 | } |
2136 | 83469015 | bellard | break;
|
2137 | 0f8a249a | blueswir1 | case 0x19: /* System tick compare */ |
2138 | 0f8a249a | blueswir1 | gen_op_movtl_T0_env(offsetof(CPUSPARCState, stick_cmpr)); |
2139 | 83469015 | bellard | gen_movl_T0_reg(rd); |
2140 | 83469015 | bellard | break;
|
2141 | 0f8a249a | blueswir1 | case 0x10: /* Performance Control */ |
2142 | 0f8a249a | blueswir1 | case 0x11: /* Performance Instrumentation Counter */ |
2143 | 0f8a249a | blueswir1 | case 0x12: /* Dispatch Control */ |
2144 | 0f8a249a | blueswir1 | case 0x14: /* Softint set, WO */ |
2145 | 0f8a249a | blueswir1 | case 0x15: /* Softint clear, WO */ |
2146 | 0f8a249a | blueswir1 | case 0x16: /* Softint write */ |
2147 | 3475187d | bellard | #endif
|
2148 | 3475187d | bellard | default:
|
2149 | cf495bcf | bellard | goto illegal_insn;
|
2150 | cf495bcf | bellard | } |
2151 | e8af50a3 | bellard | #if !defined(CONFIG_USER_ONLY)
|
2152 | e9ebed4d | blueswir1 | } else if (xop == 0x29) { /* rdpsr / UA2005 rdhpr */ |
2153 | 3475187d | bellard | #ifndef TARGET_SPARC64
|
2154 | 0f8a249a | blueswir1 | if (!supervisor(dc))
|
2155 | 0f8a249a | blueswir1 | goto priv_insn;
|
2156 | 1a2fb1c0 | blueswir1 | tcg_gen_helper_1_0(helper_rdpsr, cpu_T[0]);
|
2157 | e9ebed4d | blueswir1 | #else
|
2158 | e9ebed4d | blueswir1 | if (!hypervisor(dc))
|
2159 | e9ebed4d | blueswir1 | goto priv_insn;
|
2160 | e9ebed4d | blueswir1 | rs1 = GET_FIELD(insn, 13, 17); |
2161 | e9ebed4d | blueswir1 | switch (rs1) {
|
2162 | e9ebed4d | blueswir1 | case 0: // hpstate |
2163 | e9ebed4d | blueswir1 | // gen_op_rdhpstate();
|
2164 | e9ebed4d | blueswir1 | break;
|
2165 | e9ebed4d | blueswir1 | case 1: // htstate |
2166 | e9ebed4d | blueswir1 | // gen_op_rdhtstate();
|
2167 | e9ebed4d | blueswir1 | break;
|
2168 | e9ebed4d | blueswir1 | case 3: // hintp |
2169 | e9ebed4d | blueswir1 | gen_op_movl_T0_env(offsetof(CPUSPARCState, hintp)); |
2170 | e9ebed4d | blueswir1 | break;
|
2171 | e9ebed4d | blueswir1 | case 5: // htba |
2172 | e9ebed4d | blueswir1 | gen_op_movl_T0_env(offsetof(CPUSPARCState, htba)); |
2173 | e9ebed4d | blueswir1 | break;
|
2174 | e9ebed4d | blueswir1 | case 6: // hver |
2175 | e9ebed4d | blueswir1 | gen_op_movl_T0_env(offsetof(CPUSPARCState, hver)); |
2176 | e9ebed4d | blueswir1 | break;
|
2177 | e9ebed4d | blueswir1 | case 31: // hstick_cmpr |
2178 | e9ebed4d | blueswir1 | gen_op_movl_env_T0(offsetof(CPUSPARCState, hstick_cmpr)); |
2179 | e9ebed4d | blueswir1 | break;
|
2180 | e9ebed4d | blueswir1 | default:
|
2181 | e9ebed4d | blueswir1 | goto illegal_insn;
|
2182 | e9ebed4d | blueswir1 | } |
2183 | e9ebed4d | blueswir1 | #endif
|
2184 | e8af50a3 | bellard | gen_movl_T0_reg(rd); |
2185 | e8af50a3 | bellard | break;
|
2186 | 3475187d | bellard | } else if (xop == 0x2a) { /* rdwim / V9 rdpr */ |
2187 | 0f8a249a | blueswir1 | if (!supervisor(dc))
|
2188 | 0f8a249a | blueswir1 | goto priv_insn;
|
2189 | 3475187d | bellard | #ifdef TARGET_SPARC64
|
2190 | 3475187d | bellard | rs1 = GET_FIELD(insn, 13, 17); |
2191 | 0f8a249a | blueswir1 | switch (rs1) {
|
2192 | 0f8a249a | blueswir1 | case 0: // tpc |
2193 | 375ee38b | blueswir1 | { |
2194 | 375ee38b | blueswir1 | TCGv r_tsptr; |
2195 | 375ee38b | blueswir1 | |
2196 | 375ee38b | blueswir1 | r_tsptr = tcg_temp_new(TCG_TYPE_PTR); |
2197 | 375ee38b | blueswir1 | tcg_gen_ld_ptr(r_tsptr, cpu_env, |
2198 | 375ee38b | blueswir1 | offsetof(CPUState, tsptr)); |
2199 | 375ee38b | blueswir1 | tcg_gen_ld_tl(cpu_T[0], r_tsptr,
|
2200 | 375ee38b | blueswir1 | offsetof(trap_state, tpc)); |
2201 | 0425bee5 | blueswir1 | tcg_gen_discard_ptr(r_tsptr); |
2202 | 375ee38b | blueswir1 | } |
2203 | 0f8a249a | blueswir1 | break;
|
2204 | 0f8a249a | blueswir1 | case 1: // tnpc |
2205 | 375ee38b | blueswir1 | { |
2206 | 375ee38b | blueswir1 | TCGv r_tsptr; |
2207 | 375ee38b | blueswir1 | |
2208 | 375ee38b | blueswir1 | r_tsptr = tcg_temp_new(TCG_TYPE_PTR); |
2209 | 375ee38b | blueswir1 | tcg_gen_ld_ptr(r_tsptr, cpu_env, |
2210 | 375ee38b | blueswir1 | offsetof(CPUState, tsptr)); |
2211 | 375ee38b | blueswir1 | tcg_gen_ld_tl(cpu_T[0], r_tsptr,
|
2212 | 375ee38b | blueswir1 | offsetof(trap_state, tnpc)); |
2213 | 0425bee5 | blueswir1 | tcg_gen_discard_ptr(r_tsptr); |
2214 | 375ee38b | blueswir1 | } |
2215 | 0f8a249a | blueswir1 | break;
|
2216 | 0f8a249a | blueswir1 | case 2: // tstate |
2217 | 375ee38b | blueswir1 | { |
2218 | 375ee38b | blueswir1 | TCGv r_tsptr; |
2219 | 375ee38b | blueswir1 | |
2220 | 375ee38b | blueswir1 | r_tsptr = tcg_temp_new(TCG_TYPE_PTR); |
2221 | 375ee38b | blueswir1 | tcg_gen_ld_ptr(r_tsptr, cpu_env, |
2222 | 375ee38b | blueswir1 | offsetof(CPUState, tsptr)); |
2223 | 375ee38b | blueswir1 | tcg_gen_ld_tl(cpu_T[0], r_tsptr,
|
2224 | 375ee38b | blueswir1 | offsetof(trap_state, tstate)); |
2225 | 0425bee5 | blueswir1 | tcg_gen_discard_ptr(r_tsptr); |
2226 | 375ee38b | blueswir1 | } |
2227 | 0f8a249a | blueswir1 | break;
|
2228 | 0f8a249a | blueswir1 | case 3: // tt |
2229 | 375ee38b | blueswir1 | { |
2230 | 375ee38b | blueswir1 | TCGv r_tsptr; |
2231 | 375ee38b | blueswir1 | |
2232 | 375ee38b | blueswir1 | r_tsptr = tcg_temp_new(TCG_TYPE_PTR); |
2233 | 375ee38b | blueswir1 | tcg_gen_ld_ptr(r_tsptr, cpu_env, |
2234 | 375ee38b | blueswir1 | offsetof(CPUState, tsptr)); |
2235 | 375ee38b | blueswir1 | tcg_gen_ld_i32(cpu_T[0], r_tsptr,
|
2236 | 375ee38b | blueswir1 | offsetof(trap_state, tt)); |
2237 | 0425bee5 | blueswir1 | tcg_gen_discard_ptr(r_tsptr); |
2238 | 375ee38b | blueswir1 | } |
2239 | 0f8a249a | blueswir1 | break;
|
2240 | 0f8a249a | blueswir1 | case 4: // tick |
2241 | ccd4a219 | blueswir1 | { |
2242 | ccd4a219 | blueswir1 | TCGv r_tickptr; |
2243 | ccd4a219 | blueswir1 | |
2244 | ccd4a219 | blueswir1 | r_tickptr = tcg_temp_new(TCG_TYPE_PTR); |
2245 | ccd4a219 | blueswir1 | tcg_gen_ld_ptr(r_tickptr, cpu_env, |
2246 | ccd4a219 | blueswir1 | offsetof(CPUState, tick)); |
2247 | ccd4a219 | blueswir1 | tcg_gen_helper_1_1(helper_tick_get_count, cpu_T[0],
|
2248 | ccd4a219 | blueswir1 | r_tickptr); |
2249 | ccd4a219 | blueswir1 | gen_movl_T0_reg(rd); |
2250 | 0425bee5 | blueswir1 | tcg_gen_discard_ptr(r_tickptr); |
2251 | ccd4a219 | blueswir1 | } |
2252 | 0f8a249a | blueswir1 | break;
|
2253 | 0f8a249a | blueswir1 | case 5: // tba |
2254 | 0f8a249a | blueswir1 | gen_op_movtl_T0_env(offsetof(CPUSPARCState, tbr)); |
2255 | 0f8a249a | blueswir1 | break;
|
2256 | 0f8a249a | blueswir1 | case 6: // pstate |
2257 | 1a2fb1c0 | blueswir1 | gen_op_movl_T0_env(offsetof(CPUSPARCState, pstate)); |
2258 | 0f8a249a | blueswir1 | break;
|
2259 | 0f8a249a | blueswir1 | case 7: // tl |
2260 | 0f8a249a | blueswir1 | gen_op_movl_T0_env(offsetof(CPUSPARCState, tl)); |
2261 | 0f8a249a | blueswir1 | break;
|
2262 | 0f8a249a | blueswir1 | case 8: // pil |
2263 | 0f8a249a | blueswir1 | gen_op_movl_T0_env(offsetof(CPUSPARCState, psrpil)); |
2264 | 0f8a249a | blueswir1 | break;
|
2265 | 0f8a249a | blueswir1 | case 9: // cwp |
2266 | d35527d9 | blueswir1 | tcg_gen_helper_1_0(helper_rdcwp, cpu_T[0]);
|
2267 | 0f8a249a | blueswir1 | break;
|
2268 | 0f8a249a | blueswir1 | case 10: // cansave |
2269 | 0f8a249a | blueswir1 | gen_op_movl_T0_env(offsetof(CPUSPARCState, cansave)); |
2270 | 0f8a249a | blueswir1 | break;
|
2271 | 0f8a249a | blueswir1 | case 11: // canrestore |
2272 | 0f8a249a | blueswir1 | gen_op_movl_T0_env(offsetof(CPUSPARCState, canrestore)); |
2273 | 0f8a249a | blueswir1 | break;
|
2274 | 0f8a249a | blueswir1 | case 12: // cleanwin |
2275 | 0f8a249a | blueswir1 | gen_op_movl_T0_env(offsetof(CPUSPARCState, cleanwin)); |
2276 | 0f8a249a | blueswir1 | break;
|
2277 | 0f8a249a | blueswir1 | case 13: // otherwin |
2278 | 0f8a249a | blueswir1 | gen_op_movl_T0_env(offsetof(CPUSPARCState, otherwin)); |
2279 | 0f8a249a | blueswir1 | break;
|
2280 | 0f8a249a | blueswir1 | case 14: // wstate |
2281 | 0f8a249a | blueswir1 | gen_op_movl_T0_env(offsetof(CPUSPARCState, wstate)); |
2282 | 0f8a249a | blueswir1 | break;
|
2283 | e9ebed4d | blueswir1 | case 16: // UA2005 gl |
2284 | e9ebed4d | blueswir1 | gen_op_movl_T0_env(offsetof(CPUSPARCState, gl)); |
2285 | e9ebed4d | blueswir1 | break;
|
2286 | e9ebed4d | blueswir1 | case 26: // UA2005 strand status |
2287 | e9ebed4d | blueswir1 | if (!hypervisor(dc))
|
2288 | e9ebed4d | blueswir1 | goto priv_insn;
|
2289 | e9ebed4d | blueswir1 | gen_op_movl_T0_env(offsetof(CPUSPARCState, ssr)); |
2290 | e9ebed4d | blueswir1 | break;
|
2291 | 0f8a249a | blueswir1 | case 31: // ver |
2292 | 0f8a249a | blueswir1 | gen_op_movtl_T0_env(offsetof(CPUSPARCState, version)); |
2293 | 0f8a249a | blueswir1 | break;
|
2294 | 0f8a249a | blueswir1 | case 15: // fq |
2295 | 0f8a249a | blueswir1 | default:
|
2296 | 0f8a249a | blueswir1 | goto illegal_insn;
|
2297 | 0f8a249a | blueswir1 | } |
2298 | 3475187d | bellard | #else
|
2299 | 0f8a249a | blueswir1 | gen_op_movl_T0_env(offsetof(CPUSPARCState, wim)); |
2300 | 3475187d | bellard | #endif
|
2301 | e8af50a3 | bellard | gen_movl_T0_reg(rd); |
2302 | e8af50a3 | bellard | break;
|
2303 | 3475187d | bellard | } else if (xop == 0x2b) { /* rdtbr / V9 flushw */ |
2304 | 3475187d | bellard | #ifdef TARGET_SPARC64
|
2305 | 72a9747b | blueswir1 | tcg_gen_helper_0_0(helper_flushw); |
2306 | 3475187d | bellard | #else
|
2307 | 0f8a249a | blueswir1 | if (!supervisor(dc))
|
2308 | 0f8a249a | blueswir1 | goto priv_insn;
|
2309 | 0f8a249a | blueswir1 | gen_op_movtl_T0_env(offsetof(CPUSPARCState, tbr)); |
2310 | e8af50a3 | bellard | gen_movl_T0_reg(rd); |
2311 | 3475187d | bellard | #endif
|
2312 | e8af50a3 | bellard | break;
|
2313 | e8af50a3 | bellard | #endif
|
2314 | 0f8a249a | blueswir1 | } else if (xop == 0x34) { /* FPU Operations */ |
2315 | a80dde08 | bellard | if (gen_trap_ifnofpu(dc))
|
2316 | a80dde08 | bellard | goto jmp_insn;
|
2317 | 0f8a249a | blueswir1 | gen_op_clear_ieee_excp_and_FTT(); |
2318 | e8af50a3 | bellard | rs1 = GET_FIELD(insn, 13, 17); |
2319 | 0f8a249a | blueswir1 | rs2 = GET_FIELD(insn, 27, 31); |
2320 | 0f8a249a | blueswir1 | xop = GET_FIELD(insn, 18, 26); |
2321 | 0f8a249a | blueswir1 | switch (xop) {
|
2322 | 0f8a249a | blueswir1 | case 0x1: /* fmovs */ |
2323 | 0f8a249a | blueswir1 | gen_op_load_fpr_FT0(rs2); |
2324 | 0f8a249a | blueswir1 | gen_op_store_FT0_fpr(rd); |
2325 | 0f8a249a | blueswir1 | break;
|
2326 | 0f8a249a | blueswir1 | case 0x5: /* fnegs */ |
2327 | 0f8a249a | blueswir1 | gen_op_load_fpr_FT1(rs2); |
2328 | 44e7757c | blueswir1 | tcg_gen_helper_0_0(helper_fnegs); |
2329 | 0f8a249a | blueswir1 | gen_op_store_FT0_fpr(rd); |
2330 | 0f8a249a | blueswir1 | break;
|
2331 | 0f8a249a | blueswir1 | case 0x9: /* fabss */ |
2332 | 0f8a249a | blueswir1 | gen_op_load_fpr_FT1(rs2); |
2333 | 7e8c2b6c | blueswir1 | tcg_gen_helper_0_0(helper_fabss); |
2334 | 0f8a249a | blueswir1 | gen_op_store_FT0_fpr(rd); |
2335 | 0f8a249a | blueswir1 | break;
|
2336 | 0f8a249a | blueswir1 | case 0x29: /* fsqrts */ |
2337 | 0f8a249a | blueswir1 | gen_op_load_fpr_FT1(rs2); |
2338 | 7e8c2b6c | blueswir1 | gen_clear_float_exceptions(); |
2339 | 7e8c2b6c | blueswir1 | tcg_gen_helper_0_0(helper_fsqrts); |
2340 | 7e8c2b6c | blueswir1 | tcg_gen_helper_0_0(helper_check_ieee_exceptions); |
2341 | 0f8a249a | blueswir1 | gen_op_store_FT0_fpr(rd); |
2342 | 0f8a249a | blueswir1 | break;
|
2343 | 0f8a249a | blueswir1 | case 0x2a: /* fsqrtd */ |
2344 | 0f8a249a | blueswir1 | gen_op_load_fpr_DT1(DFPREG(rs2)); |
2345 | 7e8c2b6c | blueswir1 | gen_clear_float_exceptions(); |
2346 | 7e8c2b6c | blueswir1 | tcg_gen_helper_0_0(helper_fsqrtd); |
2347 | 7e8c2b6c | blueswir1 | tcg_gen_helper_0_0(helper_check_ieee_exceptions); |
2348 | 0f8a249a | blueswir1 | gen_op_store_DT0_fpr(DFPREG(rd)); |
2349 | 0f8a249a | blueswir1 | break;
|
2350 | 0f8a249a | blueswir1 | case 0x2b: /* fsqrtq */ |
2351 | 1f587329 | blueswir1 | #if defined(CONFIG_USER_ONLY)
|
2352 | 1f587329 | blueswir1 | gen_op_load_fpr_QT1(QFPREG(rs2)); |
2353 | 7e8c2b6c | blueswir1 | gen_clear_float_exceptions(); |
2354 | 7e8c2b6c | blueswir1 | tcg_gen_helper_0_0(helper_fsqrtq); |
2355 | 7e8c2b6c | blueswir1 | tcg_gen_helper_0_0(helper_check_ieee_exceptions); |
2356 | 1f587329 | blueswir1 | gen_op_store_QT0_fpr(QFPREG(rd)); |
2357 | 1f587329 | blueswir1 | break;
|
2358 | 1f587329 | blueswir1 | #else
|
2359 | 0f8a249a | blueswir1 | goto nfpu_insn;
|
2360 | 1f587329 | blueswir1 | #endif
|
2361 | 0f8a249a | blueswir1 | case 0x41: |
2362 | 0f8a249a | blueswir1 | gen_op_load_fpr_FT0(rs1); |
2363 | 0f8a249a | blueswir1 | gen_op_load_fpr_FT1(rs2); |
2364 | 7e8c2b6c | blueswir1 | gen_clear_float_exceptions(); |
2365 | 44e7757c | blueswir1 | tcg_gen_helper_0_0(helper_fadds); |
2366 | 7e8c2b6c | blueswir1 | tcg_gen_helper_0_0(helper_check_ieee_exceptions); |
2367 | 0f8a249a | blueswir1 | gen_op_store_FT0_fpr(rd); |
2368 | 0f8a249a | blueswir1 | break;
|
2369 | 0f8a249a | blueswir1 | case 0x42: |
2370 | 0f8a249a | blueswir1 | gen_op_load_fpr_DT0(DFPREG(rs1)); |
2371 | 0f8a249a | blueswir1 | gen_op_load_fpr_DT1(DFPREG(rs2)); |
2372 | 7e8c2b6c | blueswir1 | gen_clear_float_exceptions(); |
2373 | 44e7757c | blueswir1 | tcg_gen_helper_0_0(helper_faddd); |
2374 | 7e8c2b6c | blueswir1 | tcg_gen_helper_0_0(helper_check_ieee_exceptions); |
2375 | 0f8a249a | blueswir1 | gen_op_store_DT0_fpr(DFPREG(rd)); |
2376 | 0f8a249a | blueswir1 | break;
|
2377 | 0f8a249a | blueswir1 | case 0x43: /* faddq */ |
2378 | 1f587329 | blueswir1 | #if defined(CONFIG_USER_ONLY)
|
2379 | 1f587329 | blueswir1 | gen_op_load_fpr_QT0(QFPREG(rs1)); |
2380 | 1f587329 | blueswir1 | gen_op_load_fpr_QT1(QFPREG(rs2)); |
2381 | 7e8c2b6c | blueswir1 | gen_clear_float_exceptions(); |
2382 | 44e7757c | blueswir1 | tcg_gen_helper_0_0(helper_faddq); |
2383 | 7e8c2b6c | blueswir1 | tcg_gen_helper_0_0(helper_check_ieee_exceptions); |
2384 | 1f587329 | blueswir1 | gen_op_store_QT0_fpr(QFPREG(rd)); |
2385 | 1f587329 | blueswir1 | break;
|
2386 | 1f587329 | blueswir1 | #else
|
2387 | 0f8a249a | blueswir1 | goto nfpu_insn;
|
2388 | 1f587329 | blueswir1 | #endif
|
2389 | 0f8a249a | blueswir1 | case 0x45: |
2390 | 0f8a249a | blueswir1 | gen_op_load_fpr_FT0(rs1); |
2391 | 0f8a249a | blueswir1 | gen_op_load_fpr_FT1(rs2); |
2392 | 7e8c2b6c | blueswir1 | gen_clear_float_exceptions(); |
2393 | 44e7757c | blueswir1 | tcg_gen_helper_0_0(helper_fsubs); |
2394 | 7e8c2b6c | blueswir1 | tcg_gen_helper_0_0(helper_check_ieee_exceptions); |
2395 | 0f8a249a | blueswir1 | gen_op_store_FT0_fpr(rd); |
2396 | 0f8a249a | blueswir1 | break;
|
2397 | 0f8a249a | blueswir1 | case 0x46: |
2398 | 0f8a249a | blueswir1 | gen_op_load_fpr_DT0(DFPREG(rs1)); |
2399 | 0f8a249a | blueswir1 | gen_op_load_fpr_DT1(DFPREG(rs2)); |
2400 | 7e8c2b6c | blueswir1 | gen_clear_float_exceptions(); |
2401 | 44e7757c | blueswir1 | tcg_gen_helper_0_0(helper_fsubd); |
2402 | 7e8c2b6c | blueswir1 | tcg_gen_helper_0_0(helper_check_ieee_exceptions); |
2403 | 0f8a249a | blueswir1 | gen_op_store_DT0_fpr(DFPREG(rd)); |
2404 | 0f8a249a | blueswir1 | break;
|
2405 | 0f8a249a | blueswir1 | case 0x47: /* fsubq */ |
2406 | 1f587329 | blueswir1 | #if defined(CONFIG_USER_ONLY)
|
2407 | 1f587329 | blueswir1 | gen_op_load_fpr_QT0(QFPREG(rs1)); |
2408 | 1f587329 | blueswir1 | gen_op_load_fpr_QT1(QFPREG(rs2)); |
2409 | 7e8c2b6c | blueswir1 | gen_clear_float_exceptions(); |
2410 | 44e7757c | blueswir1 | tcg_gen_helper_0_0(helper_fsubq); |
2411 | 7e8c2b6c | blueswir1 | tcg_gen_helper_0_0(helper_check_ieee_exceptions); |
2412 | 1f587329 | blueswir1 | gen_op_store_QT0_fpr(QFPREG(rd)); |
2413 | 1f587329 | blueswir1 | break;
|
2414 | 1f587329 | blueswir1 | #else
|
2415 | 0f8a249a | blueswir1 | goto nfpu_insn;
|
2416 | 1f587329 | blueswir1 | #endif
|
2417 | 0f8a249a | blueswir1 | case 0x49: |
2418 | 0f8a249a | blueswir1 | gen_op_load_fpr_FT0(rs1); |
2419 | 0f8a249a | blueswir1 | gen_op_load_fpr_FT1(rs2); |
2420 | 7e8c2b6c | blueswir1 | gen_clear_float_exceptions(); |
2421 | 44e7757c | blueswir1 | tcg_gen_helper_0_0(helper_fmuls); |
2422 | 7e8c2b6c | blueswir1 | tcg_gen_helper_0_0(helper_check_ieee_exceptions); |
2423 | 0f8a249a | blueswir1 | gen_op_store_FT0_fpr(rd); |
2424 | 0f8a249a | blueswir1 | break;
|
2425 | 0f8a249a | blueswir1 | case 0x4a: |
2426 | 0f8a249a | blueswir1 | gen_op_load_fpr_DT0(DFPREG(rs1)); |
2427 | 0f8a249a | blueswir1 | gen_op_load_fpr_DT1(DFPREG(rs2)); |
2428 | 7e8c2b6c | blueswir1 | gen_clear_float_exceptions(); |
2429 | 44e7757c | blueswir1 | tcg_gen_helper_0_0(helper_fmuld); |
2430 | 7e8c2b6c | blueswir1 | tcg_gen_helper_0_0(helper_check_ieee_exceptions); |
2431 | 2382dc6b | blueswir1 | gen_op_store_DT0_fpr(DFPREG(rd)); |
2432 | 0f8a249a | blueswir1 | break;
|
2433 | 0f8a249a | blueswir1 | case 0x4b: /* fmulq */ |
2434 | 1f587329 | blueswir1 | #if defined(CONFIG_USER_ONLY)
|
2435 | 1f587329 | blueswir1 | gen_op_load_fpr_QT0(QFPREG(rs1)); |
2436 | 1f587329 | blueswir1 | gen_op_load_fpr_QT1(QFPREG(rs2)); |
2437 | 7e8c2b6c | blueswir1 | gen_clear_float_exceptions(); |
2438 | 44e7757c | blueswir1 | tcg_gen_helper_0_0(helper_fmulq); |
2439 | 7e8c2b6c | blueswir1 | tcg_gen_helper_0_0(helper_check_ieee_exceptions); |
2440 | 1f587329 | blueswir1 | gen_op_store_QT0_fpr(QFPREG(rd)); |
2441 | 1f587329 | blueswir1 | break;
|
2442 | 1f587329 | blueswir1 | #else
|
2443 | 0f8a249a | blueswir1 | goto nfpu_insn;
|
2444 | 1f587329 | blueswir1 | #endif
|
2445 | 0f8a249a | blueswir1 | case 0x4d: |
2446 | 0f8a249a | blueswir1 | gen_op_load_fpr_FT0(rs1); |
2447 | 0f8a249a | blueswir1 | gen_op_load_fpr_FT1(rs2); |
2448 | 7e8c2b6c | blueswir1 | gen_clear_float_exceptions(); |
2449 | 44e7757c | blueswir1 | tcg_gen_helper_0_0(helper_fdivs); |
2450 | 7e8c2b6c | blueswir1 | tcg_gen_helper_0_0(helper_check_ieee_exceptions); |
2451 | 0f8a249a | blueswir1 | gen_op_store_FT0_fpr(rd); |
2452 | 0f8a249a | blueswir1 | break;
|
2453 | 0f8a249a | blueswir1 | case 0x4e: |
2454 | 0f8a249a | blueswir1 | gen_op_load_fpr_DT0(DFPREG(rs1)); |
2455 | 0f8a249a | blueswir1 | gen_op_load_fpr_DT1(DFPREG(rs2)); |
2456 | 7e8c2b6c | blueswir1 | gen_clear_float_exceptions(); |
2457 | 44e7757c | blueswir1 | tcg_gen_helper_0_0(helper_fdivd); |
2458 | 7e8c2b6c | blueswir1 | tcg_gen_helper_0_0(helper_check_ieee_exceptions); |
2459 | 0f8a249a | blueswir1 | gen_op_store_DT0_fpr(DFPREG(rd)); |
2460 | 0f8a249a | blueswir1 | break;
|
2461 | 0f8a249a | blueswir1 | case 0x4f: /* fdivq */ |
2462 | 1f587329 | blueswir1 | #if defined(CONFIG_USER_ONLY)
|
2463 | 1f587329 | blueswir1 | gen_op_load_fpr_QT0(QFPREG(rs1)); |
2464 | 1f587329 | blueswir1 | gen_op_load_fpr_QT1(QFPREG(rs2)); |
2465 | 7e8c2b6c | blueswir1 | gen_clear_float_exceptions(); |
2466 | 44e7757c | blueswir1 | tcg_gen_helper_0_0(helper_fdivq); |
2467 | 7e8c2b6c | blueswir1 | tcg_gen_helper_0_0(helper_check_ieee_exceptions); |
2468 | 1f587329 | blueswir1 | gen_op_store_QT0_fpr(QFPREG(rd)); |
2469 | 1f587329 | blueswir1 | break;
|
2470 | 1f587329 | blueswir1 | #else
|
2471 | 0f8a249a | blueswir1 | goto nfpu_insn;
|
2472 | 1f587329 | blueswir1 | #endif
|
2473 | 0f8a249a | blueswir1 | case 0x69: |
2474 | 0f8a249a | blueswir1 | gen_op_load_fpr_FT0(rs1); |
2475 | 0f8a249a | blueswir1 | gen_op_load_fpr_FT1(rs2); |
2476 | 7e8c2b6c | blueswir1 | gen_clear_float_exceptions(); |
2477 | 44e7757c | blueswir1 | tcg_gen_helper_0_0(helper_fsmuld); |
2478 | 7e8c2b6c | blueswir1 | tcg_gen_helper_0_0(helper_check_ieee_exceptions); |
2479 | 0f8a249a | blueswir1 | gen_op_store_DT0_fpr(DFPREG(rd)); |
2480 | 0f8a249a | blueswir1 | break;
|
2481 | 0f8a249a | blueswir1 | case 0x6e: /* fdmulq */ |
2482 | 1f587329 | blueswir1 | #if defined(CONFIG_USER_ONLY)
|
2483 | 1f587329 | blueswir1 | gen_op_load_fpr_DT0(DFPREG(rs1)); |
2484 | 1f587329 | blueswir1 | gen_op_load_fpr_DT1(DFPREG(rs2)); |
2485 | 7e8c2b6c | blueswir1 | gen_clear_float_exceptions(); |
2486 | 44e7757c | blueswir1 | tcg_gen_helper_0_0(helper_fdmulq); |
2487 | 7e8c2b6c | blueswir1 | tcg_gen_helper_0_0(helper_check_ieee_exceptions); |
2488 | 1f587329 | blueswir1 | gen_op_store_QT0_fpr(QFPREG(rd)); |
2489 | 1f587329 | blueswir1 | break;
|
2490 | 1f587329 | blueswir1 | #else
|
2491 | 0f8a249a | blueswir1 | goto nfpu_insn;
|
2492 | 1f587329 | blueswir1 | #endif
|
2493 | 0f8a249a | blueswir1 | case 0xc4: |
2494 | 0f8a249a | blueswir1 | gen_op_load_fpr_FT1(rs2); |
2495 | 7e8c2b6c | blueswir1 | gen_clear_float_exceptions(); |
2496 | 44e7757c | blueswir1 | tcg_gen_helper_0_0(helper_fitos); |
2497 | 7e8c2b6c | blueswir1 | tcg_gen_helper_0_0(helper_check_ieee_exceptions); |
2498 | 0f8a249a | blueswir1 | gen_op_store_FT0_fpr(rd); |
2499 | 0f8a249a | blueswir1 | break;
|
2500 | 0f8a249a | blueswir1 | case 0xc6: |
2501 | 0f8a249a | blueswir1 | gen_op_load_fpr_DT1(DFPREG(rs2)); |
2502 | 7e8c2b6c | blueswir1 | gen_clear_float_exceptions(); |
2503 | 44e7757c | blueswir1 | tcg_gen_helper_0_0(helper_fdtos); |
2504 | 7e8c2b6c | blueswir1 | tcg_gen_helper_0_0(helper_check_ieee_exceptions); |
2505 | 0f8a249a | blueswir1 | gen_op_store_FT0_fpr(rd); |
2506 | 0f8a249a | blueswir1 | break;
|
2507 | 0f8a249a | blueswir1 | case 0xc7: /* fqtos */ |
2508 | 1f587329 | blueswir1 | #if defined(CONFIG_USER_ONLY)
|
2509 | 1f587329 | blueswir1 | gen_op_load_fpr_QT1(QFPREG(rs2)); |
2510 | 7e8c2b6c | blueswir1 | gen_clear_float_exceptions(); |
2511 | 44e7757c | blueswir1 | tcg_gen_helper_0_0(helper_fqtos); |
2512 | 7e8c2b6c | blueswir1 | tcg_gen_helper_0_0(helper_check_ieee_exceptions); |
2513 | 1f587329 | blueswir1 | gen_op_store_FT0_fpr(rd); |
2514 | 1f587329 | blueswir1 | break;
|
2515 | 1f587329 | blueswir1 | #else
|
2516 | 0f8a249a | blueswir1 | goto nfpu_insn;
|
2517 | 1f587329 | blueswir1 | #endif
|
2518 | 0f8a249a | blueswir1 | case 0xc8: |
2519 | 0f8a249a | blueswir1 | gen_op_load_fpr_FT1(rs2); |
2520 | 44e7757c | blueswir1 | tcg_gen_helper_0_0(helper_fitod); |
2521 | 0f8a249a | blueswir1 | gen_op_store_DT0_fpr(DFPREG(rd)); |
2522 | 0f8a249a | blueswir1 | break;
|
2523 | 0f8a249a | blueswir1 | case 0xc9: |
2524 | 0f8a249a | blueswir1 | gen_op_load_fpr_FT1(rs2); |
2525 | 44e7757c | blueswir1 | tcg_gen_helper_0_0(helper_fstod); |
2526 | 0f8a249a | blueswir1 | gen_op_store_DT0_fpr(DFPREG(rd)); |
2527 | 0f8a249a | blueswir1 | break;
|
2528 | 0f8a249a | blueswir1 | case 0xcb: /* fqtod */ |
2529 | 1f587329 | blueswir1 | #if defined(CONFIG_USER_ONLY)
|
2530 | 1f587329 | blueswir1 | gen_op_load_fpr_QT1(QFPREG(rs2)); |
2531 | 7e8c2b6c | blueswir1 | gen_clear_float_exceptions(); |
2532 | 44e7757c | blueswir1 | tcg_gen_helper_0_0(helper_fqtod); |
2533 | 7e8c2b6c | blueswir1 | tcg_gen_helper_0_0(helper_check_ieee_exceptions); |
2534 | 1f587329 | blueswir1 | gen_op_store_DT0_fpr(DFPREG(rd)); |
2535 | 1f587329 | blueswir1 | break;
|
2536 | 1f587329 | blueswir1 | #else
|
2537 | 0f8a249a | blueswir1 | goto nfpu_insn;
|
2538 | 1f587329 | blueswir1 | #endif
|
2539 | 0f8a249a | blueswir1 | case 0xcc: /* fitoq */ |
2540 | 1f587329 | blueswir1 | #if defined(CONFIG_USER_ONLY)
|
2541 | 1f587329 | blueswir1 | gen_op_load_fpr_FT1(rs2); |
2542 | 44e7757c | blueswir1 | tcg_gen_helper_0_0(helper_fitoq); |
2543 | 1f587329 | blueswir1 | gen_op_store_QT0_fpr(QFPREG(rd)); |
2544 | 1f587329 | blueswir1 | break;
|
2545 | 1f587329 | blueswir1 | #else
|
2546 | 0f8a249a | blueswir1 | goto nfpu_insn;
|
2547 | 1f587329 | blueswir1 | #endif
|
2548 | 0f8a249a | blueswir1 | case 0xcd: /* fstoq */ |
2549 | 1f587329 | blueswir1 | #if defined(CONFIG_USER_ONLY)
|
2550 | 1f587329 | blueswir1 | gen_op_load_fpr_FT1(rs2); |
2551 | 44e7757c | blueswir1 | tcg_gen_helper_0_0(helper_fstoq); |
2552 | 1f587329 | blueswir1 | gen_op_store_QT0_fpr(QFPREG(rd)); |
2553 | 1f587329 | blueswir1 | break;
|
2554 | 1f587329 | blueswir1 | #else
|
2555 | 0f8a249a | blueswir1 | goto nfpu_insn;
|
2556 | 1f587329 | blueswir1 | #endif
|
2557 | 0f8a249a | blueswir1 | case 0xce: /* fdtoq */ |
2558 | 1f587329 | blueswir1 | #if defined(CONFIG_USER_ONLY)
|
2559 | 1f587329 | blueswir1 | gen_op_load_fpr_DT1(DFPREG(rs2)); |
2560 | 44e7757c | blueswir1 | tcg_gen_helper_0_0(helper_fdtoq); |
2561 | 1f587329 | blueswir1 | gen_op_store_QT0_fpr(QFPREG(rd)); |
2562 | 1f587329 | blueswir1 | break;
|
2563 | 1f587329 | blueswir1 | #else
|
2564 | 0f8a249a | blueswir1 | goto nfpu_insn;
|
2565 | 1f587329 | blueswir1 | #endif
|
2566 | 0f8a249a | blueswir1 | case 0xd1: |
2567 | 0f8a249a | blueswir1 | gen_op_load_fpr_FT1(rs2); |
2568 | 7e8c2b6c | blueswir1 | gen_clear_float_exceptions(); |
2569 | 44e7757c | blueswir1 | tcg_gen_helper_0_0(helper_fstoi); |
2570 | 7e8c2b6c | blueswir1 | tcg_gen_helper_0_0(helper_check_ieee_exceptions); |
2571 | 0f8a249a | blueswir1 | gen_op_store_FT0_fpr(rd); |
2572 | 0f8a249a | blueswir1 | break;
|
2573 | 0f8a249a | blueswir1 | case 0xd2: |
2574 | 2382dc6b | blueswir1 | gen_op_load_fpr_DT1(DFPREG(rs2)); |
2575 | 7e8c2b6c | blueswir1 | gen_clear_float_exceptions(); |
2576 | 44e7757c | blueswir1 | tcg_gen_helper_0_0(helper_fdtoi); |
2577 | 7e8c2b6c | blueswir1 | tcg_gen_helper_0_0(helper_check_ieee_exceptions); |
2578 | 0f8a249a | blueswir1 | gen_op_store_FT0_fpr(rd); |
2579 | 0f8a249a | blueswir1 | break;
|
2580 | 0f8a249a | blueswir1 | case 0xd3: /* fqtoi */ |
2581 | 1f587329 | blueswir1 | #if defined(CONFIG_USER_ONLY)
|
2582 | 1f587329 | blueswir1 | gen_op_load_fpr_QT1(QFPREG(rs2)); |
2583 | 7e8c2b6c | blueswir1 | gen_clear_float_exceptions(); |
2584 | 44e7757c | blueswir1 | tcg_gen_helper_0_0(helper_fqtoi); |
2585 | 7e8c2b6c | blueswir1 | tcg_gen_helper_0_0(helper_check_ieee_exceptions); |
2586 | 1f587329 | blueswir1 | gen_op_store_FT0_fpr(rd); |
2587 | 1f587329 | blueswir1 | break;
|
2588 | 1f587329 | blueswir1 | #else
|
2589 | 0f8a249a | blueswir1 | goto nfpu_insn;
|
2590 | 1f587329 | blueswir1 | #endif
|
2591 | 3475187d | bellard | #ifdef TARGET_SPARC64
|
2592 | 0f8a249a | blueswir1 | case 0x2: /* V9 fmovd */ |
2593 | 0f8a249a | blueswir1 | gen_op_load_fpr_DT0(DFPREG(rs2)); |
2594 | 0f8a249a | blueswir1 | gen_op_store_DT0_fpr(DFPREG(rd)); |
2595 | 0f8a249a | blueswir1 | break;
|
2596 | 1f587329 | blueswir1 | case 0x3: /* V9 fmovq */ |
2597 | 1f587329 | blueswir1 | #if defined(CONFIG_USER_ONLY)
|
2598 | 1f587329 | blueswir1 | gen_op_load_fpr_QT0(QFPREG(rs2)); |
2599 | 1f587329 | blueswir1 | gen_op_store_QT0_fpr(QFPREG(rd)); |
2600 | 1f587329 | blueswir1 | break;
|
2601 | 1f587329 | blueswir1 | #else
|
2602 | 1f587329 | blueswir1 | goto nfpu_insn;
|
2603 | 1f587329 | blueswir1 | #endif
|
2604 | 0f8a249a | blueswir1 | case 0x6: /* V9 fnegd */ |
2605 | 0f8a249a | blueswir1 | gen_op_load_fpr_DT1(DFPREG(rs2)); |
2606 | 44e7757c | blueswir1 | tcg_gen_helper_0_0(helper_fnegd); |
2607 | 0f8a249a | blueswir1 | gen_op_store_DT0_fpr(DFPREG(rd)); |
2608 | 0f8a249a | blueswir1 | break;
|
2609 | 1f587329 | blueswir1 | case 0x7: /* V9 fnegq */ |
2610 | 1f587329 | blueswir1 | #if defined(CONFIG_USER_ONLY)
|
2611 | 1f587329 | blueswir1 | gen_op_load_fpr_QT1(QFPREG(rs2)); |
2612 | 44e7757c | blueswir1 | tcg_gen_helper_0_0(helper_fnegq); |
2613 | 1f587329 | blueswir1 | gen_op_store_QT0_fpr(QFPREG(rd)); |
2614 | 1f587329 | blueswir1 | break;
|
2615 | 1f587329 | blueswir1 | #else
|
2616 | 1f587329 | blueswir1 | goto nfpu_insn;
|
2617 | 1f587329 | blueswir1 | #endif
|
2618 | 0f8a249a | blueswir1 | case 0xa: /* V9 fabsd */ |
2619 | 0f8a249a | blueswir1 | gen_op_load_fpr_DT1(DFPREG(rs2)); |
2620 | 7e8c2b6c | blueswir1 | tcg_gen_helper_0_0(helper_fabsd); |
2621 | 0f8a249a | blueswir1 | gen_op_store_DT0_fpr(DFPREG(rd)); |
2622 | 0f8a249a | blueswir1 | break;
|
2623 | 1f587329 | blueswir1 | case 0xb: /* V9 fabsq */ |
2624 | 1f587329 | blueswir1 | #if defined(CONFIG_USER_ONLY)
|
2625 | 1f587329 | blueswir1 | gen_op_load_fpr_QT1(QFPREG(rs2)); |
2626 | 7e8c2b6c | blueswir1 | tcg_gen_helper_0_0(helper_fabsq); |
2627 | 1f587329 | blueswir1 | gen_op_store_QT0_fpr(QFPREG(rd)); |
2628 | 1f587329 | blueswir1 | break;
|
2629 | 1f587329 | blueswir1 | #else
|
2630 | 1f587329 | blueswir1 | goto nfpu_insn;
|
2631 | 1f587329 | blueswir1 | #endif
|
2632 | 0f8a249a | blueswir1 | case 0x81: /* V9 fstox */ |
2633 | 0f8a249a | blueswir1 | gen_op_load_fpr_FT1(rs2); |
2634 | 7e8c2b6c | blueswir1 | gen_clear_float_exceptions(); |
2635 | 44e7757c | blueswir1 | tcg_gen_helper_0_0(helper_fstox); |
2636 | 7e8c2b6c | blueswir1 | tcg_gen_helper_0_0(helper_check_ieee_exceptions); |
2637 | 0f8a249a | blueswir1 | gen_op_store_DT0_fpr(DFPREG(rd)); |
2638 | 0f8a249a | blueswir1 | break;
|
2639 | 0f8a249a | blueswir1 | case 0x82: /* V9 fdtox */ |
2640 | 0f8a249a | blueswir1 | gen_op_load_fpr_DT1(DFPREG(rs2)); |
2641 | 7e8c2b6c | blueswir1 | gen_clear_float_exceptions(); |
2642 | 44e7757c | blueswir1 | tcg_gen_helper_0_0(helper_fdtox); |
2643 | 7e8c2b6c | blueswir1 | tcg_gen_helper_0_0(helper_check_ieee_exceptions); |
2644 | 0f8a249a | blueswir1 | gen_op_store_DT0_fpr(DFPREG(rd)); |
2645 | 0f8a249a | blueswir1 | break;
|
2646 | 1f587329 | blueswir1 | case 0x83: /* V9 fqtox */ |
2647 | 1f587329 | blueswir1 | #if defined(CONFIG_USER_ONLY)
|
2648 | 1f587329 | blueswir1 | gen_op_load_fpr_QT1(QFPREG(rs2)); |
2649 | 7e8c2b6c | blueswir1 | gen_clear_float_exceptions(); |
2650 | 44e7757c | blueswir1 | tcg_gen_helper_0_0(helper_fqtox); |
2651 | 7e8c2b6c | blueswir1 | tcg_gen_helper_0_0(helper_check_ieee_exceptions); |
2652 | 1f587329 | blueswir1 | gen_op_store_DT0_fpr(DFPREG(rd)); |
2653 | 1f587329 | blueswir1 | break;
|
2654 | 1f587329 | blueswir1 | #else
|
2655 | 1f587329 | blueswir1 | goto nfpu_insn;
|
2656 | 1f587329 | blueswir1 | #endif
|
2657 | 0f8a249a | blueswir1 | case 0x84: /* V9 fxtos */ |
2658 | 0f8a249a | blueswir1 | gen_op_load_fpr_DT1(DFPREG(rs2)); |
2659 | 7e8c2b6c | blueswir1 | gen_clear_float_exceptions(); |
2660 | 44e7757c | blueswir1 | tcg_gen_helper_0_0(helper_fxtos); |
2661 | 7e8c2b6c | blueswir1 | tcg_gen_helper_0_0(helper_check_ieee_exceptions); |
2662 | 0f8a249a | blueswir1 | gen_op_store_FT0_fpr(rd); |
2663 | 0f8a249a | blueswir1 | break;
|
2664 | 0f8a249a | blueswir1 | case 0x88: /* V9 fxtod */ |
2665 | 0f8a249a | blueswir1 | gen_op_load_fpr_DT1(DFPREG(rs2)); |
2666 | 7e8c2b6c | blueswir1 | gen_clear_float_exceptions(); |
2667 | 44e7757c | blueswir1 | tcg_gen_helper_0_0(helper_fxtod); |
2668 | 7e8c2b6c | blueswir1 | tcg_gen_helper_0_0(helper_check_ieee_exceptions); |
2669 | 0f8a249a | blueswir1 | gen_op_store_DT0_fpr(DFPREG(rd)); |
2670 | 0f8a249a | blueswir1 | break;
|
2671 | 0f8a249a | blueswir1 | case 0x8c: /* V9 fxtoq */ |
2672 | 1f587329 | blueswir1 | #if defined(CONFIG_USER_ONLY)
|
2673 | 1f587329 | blueswir1 | gen_op_load_fpr_DT1(DFPREG(rs2)); |
2674 | 7e8c2b6c | blueswir1 | gen_clear_float_exceptions(); |
2675 | 44e7757c | blueswir1 | tcg_gen_helper_0_0(helper_fxtoq); |
2676 | 7e8c2b6c | blueswir1 | tcg_gen_helper_0_0(helper_check_ieee_exceptions); |
2677 | 1f587329 | blueswir1 | gen_op_store_QT0_fpr(QFPREG(rd)); |
2678 | 1f587329 | blueswir1 | break;
|
2679 | 1f587329 | blueswir1 | #else
|
2680 | 0f8a249a | blueswir1 | goto nfpu_insn;
|
2681 | 0f8a249a | blueswir1 | #endif
|
2682 | 1f587329 | blueswir1 | #endif
|
2683 | 0f8a249a | blueswir1 | default:
|
2684 | 0f8a249a | blueswir1 | goto illegal_insn;
|
2685 | 0f8a249a | blueswir1 | } |
2686 | 0f8a249a | blueswir1 | } else if (xop == 0x35) { /* FPU Operations */ |
2687 | 3475187d | bellard | #ifdef TARGET_SPARC64
|
2688 | 0f8a249a | blueswir1 | int cond;
|
2689 | 3475187d | bellard | #endif
|
2690 | a80dde08 | bellard | if (gen_trap_ifnofpu(dc))
|
2691 | a80dde08 | bellard | goto jmp_insn;
|
2692 | 0f8a249a | blueswir1 | gen_op_clear_ieee_excp_and_FTT(); |
2693 | cf495bcf | bellard | rs1 = GET_FIELD(insn, 13, 17); |
2694 | 0f8a249a | blueswir1 | rs2 = GET_FIELD(insn, 27, 31); |
2695 | 0f8a249a | blueswir1 | xop = GET_FIELD(insn, 18, 26); |
2696 | 3475187d | bellard | #ifdef TARGET_SPARC64
|
2697 | 0f8a249a | blueswir1 | if ((xop & 0x11f) == 0x005) { // V9 fmovsr |
2698 | dcf24905 | blueswir1 | int l1;
|
2699 | dcf24905 | blueswir1 | |
2700 | dcf24905 | blueswir1 | l1 = gen_new_label(); |
2701 | 0f8a249a | blueswir1 | cond = GET_FIELD_SP(insn, 14, 17); |
2702 | 0f8a249a | blueswir1 | rs1 = GET_FIELD(insn, 13, 17); |
2703 | 0f8a249a | blueswir1 | gen_movl_reg_T0(rs1); |
2704 | 0425bee5 | blueswir1 | tcg_gen_brcond_tl(gen_tcg_cond_reg[cond], cpu_T[0],
|
2705 | 0425bee5 | blueswir1 | tcg_const_tl(0), l1);
|
2706 | 19f329ad | blueswir1 | gen_op_load_fpr_FT0(rs2); |
2707 | 0f8a249a | blueswir1 | gen_op_store_FT0_fpr(rd); |
2708 | dcf24905 | blueswir1 | gen_set_label(l1); |
2709 | 0f8a249a | blueswir1 | break;
|
2710 | 0f8a249a | blueswir1 | } else if ((xop & 0x11f) == 0x006) { // V9 fmovdr |
2711 | dcf24905 | blueswir1 | int l1;
|
2712 | dcf24905 | blueswir1 | |
2713 | dcf24905 | blueswir1 | l1 = gen_new_label(); |
2714 | 0f8a249a | blueswir1 | cond = GET_FIELD_SP(insn, 14, 17); |
2715 | 0f8a249a | blueswir1 | rs1 = GET_FIELD(insn, 13, 17); |
2716 | 0f8a249a | blueswir1 | gen_movl_reg_T0(rs1); |
2717 | 0425bee5 | blueswir1 | tcg_gen_brcond_tl(gen_tcg_cond_reg[cond], cpu_T[0],
|
2718 | 0425bee5 | blueswir1 | tcg_const_tl(0), l1);
|
2719 | 19f329ad | blueswir1 | gen_op_load_fpr_DT0(DFPREG(rs2)); |
2720 | 2382dc6b | blueswir1 | gen_op_store_DT0_fpr(DFPREG(rd)); |
2721 | dcf24905 | blueswir1 | gen_set_label(l1); |
2722 | 0f8a249a | blueswir1 | break;
|
2723 | 0f8a249a | blueswir1 | } else if ((xop & 0x11f) == 0x007) { // V9 fmovqr |
2724 | 1f587329 | blueswir1 | #if defined(CONFIG_USER_ONLY)
|
2725 | dcf24905 | blueswir1 | int l1;
|
2726 | dcf24905 | blueswir1 | |
2727 | dcf24905 | blueswir1 | l1 = gen_new_label(); |
2728 | 1f587329 | blueswir1 | cond = GET_FIELD_SP(insn, 14, 17); |
2729 | 1f587329 | blueswir1 | rs1 = GET_FIELD(insn, 13, 17); |
2730 | 1f587329 | blueswir1 | gen_movl_reg_T0(rs1); |
2731 | 0425bee5 | blueswir1 | tcg_gen_brcond_tl(gen_tcg_cond_reg[cond], cpu_T[0],
|
2732 | 0425bee5 | blueswir1 | tcg_const_tl(0), l1);
|
2733 | 19f329ad | blueswir1 | gen_op_load_fpr_QT0(QFPREG(rs2)); |
2734 | 1f587329 | blueswir1 | gen_op_store_QT0_fpr(QFPREG(rd)); |
2735 | dcf24905 | blueswir1 | gen_set_label(l1); |
2736 | 1f587329 | blueswir1 | break;
|
2737 | 1f587329 | blueswir1 | #else
|
2738 | 0f8a249a | blueswir1 | goto nfpu_insn;
|
2739 | 1f587329 | blueswir1 | #endif
|
2740 | 0f8a249a | blueswir1 | } |
2741 | 0f8a249a | blueswir1 | #endif
|
2742 | 0f8a249a | blueswir1 | switch (xop) {
|
2743 | 3475187d | bellard | #ifdef TARGET_SPARC64
|
2744 | 19f329ad | blueswir1 | #define FMOVCC(size_FDQ, fcc) \
|
2745 | 19f329ad | blueswir1 | { \ |
2746 | 0425bee5 | blueswir1 | TCGv r_cond; \ |
2747 | 19f329ad | blueswir1 | int l1; \
|
2748 | 19f329ad | blueswir1 | \ |
2749 | 19f329ad | blueswir1 | l1 = gen_new_label(); \ |
2750 | 19f329ad | blueswir1 | r_cond = tcg_temp_new(TCG_TYPE_TL); \ |
2751 | 19f329ad | blueswir1 | cond = GET_FIELD_SP(insn, 14, 17); \ |
2752 | 19f329ad | blueswir1 | gen_fcond(r_cond, fcc, cond); \ |
2753 | 0425bee5 | blueswir1 | tcg_gen_brcond_tl(TCG_COND_EQ, r_cond, \ |
2754 | 0425bee5 | blueswir1 | tcg_const_tl(0), l1); \
|
2755 | 19f329ad | blueswir1 | glue(glue(gen_op_load_fpr_, size_FDQ), T0)(glue(size_FDQ, FPREG(rs2))); \ |
2756 | 19f329ad | blueswir1 | glue(glue(gen_op_store_, size_FDQ), T0_fpr)(glue(size_FDQ, FPREG(rd))); \ |
2757 | 19f329ad | blueswir1 | gen_set_label(l1); \ |
2758 | 0425bee5 | blueswir1 | tcg_gen_discard_tl(r_cond); \ |
2759 | 19f329ad | blueswir1 | } |
2760 | 0f8a249a | blueswir1 | case 0x001: /* V9 fmovscc %fcc0 */ |
2761 | 19f329ad | blueswir1 | FMOVCC(F, 0);
|
2762 | 0f8a249a | blueswir1 | break;
|
2763 | 0f8a249a | blueswir1 | case 0x002: /* V9 fmovdcc %fcc0 */ |
2764 | 19f329ad | blueswir1 | FMOVCC(D, 0);
|
2765 | 0f8a249a | blueswir1 | break;
|
2766 | 0f8a249a | blueswir1 | case 0x003: /* V9 fmovqcc %fcc0 */ |
2767 | 1f587329 | blueswir1 | #if defined(CONFIG_USER_ONLY)
|
2768 | 19f329ad | blueswir1 | FMOVCC(Q, 0);
|
2769 | 1f587329 | blueswir1 | break;
|
2770 | 1f587329 | blueswir1 | #else
|
2771 | 0f8a249a | blueswir1 | goto nfpu_insn;
|
2772 | 1f587329 | blueswir1 | #endif
|
2773 | 0f8a249a | blueswir1 | case 0x041: /* V9 fmovscc %fcc1 */ |
2774 | 19f329ad | blueswir1 | FMOVCC(F, 1);
|
2775 | 0f8a249a | blueswir1 | break;
|
2776 | 0f8a249a | blueswir1 | case 0x042: /* V9 fmovdcc %fcc1 */ |
2777 | 19f329ad | blueswir1 | FMOVCC(D, 1);
|
2778 | 0f8a249a | blueswir1 | break;
|
2779 | 0f8a249a | blueswir1 | case 0x043: /* V9 fmovqcc %fcc1 */ |
2780 | 1f587329 | blueswir1 | #if defined(CONFIG_USER_ONLY)
|
2781 | 19f329ad | blueswir1 | FMOVCC(Q, 1);
|
2782 | 1f587329 | blueswir1 | break;
|
2783 | 1f587329 | blueswir1 | #else
|
2784 | 0f8a249a | blueswir1 | goto nfpu_insn;
|
2785 | 1f587329 | blueswir1 | #endif
|
2786 | 0f8a249a | blueswir1 | case 0x081: /* V9 fmovscc %fcc2 */ |
2787 | 19f329ad | blueswir1 | FMOVCC(F, 2);
|
2788 | 0f8a249a | blueswir1 | break;
|
2789 | 0f8a249a | blueswir1 | case 0x082: /* V9 fmovdcc %fcc2 */ |
2790 | 19f329ad | blueswir1 | FMOVCC(D, 2);
|
2791 | 0f8a249a | blueswir1 | break;
|
2792 | 0f8a249a | blueswir1 | case 0x083: /* V9 fmovqcc %fcc2 */ |
2793 | 1f587329 | blueswir1 | #if defined(CONFIG_USER_ONLY)
|
2794 | 19f329ad | blueswir1 | FMOVCC(Q, 2);
|
2795 | 1f587329 | blueswir1 | break;
|
2796 | 1f587329 | blueswir1 | #else
|
2797 | 0f8a249a | blueswir1 | goto nfpu_insn;
|
2798 | 1f587329 | blueswir1 | #endif
|
2799 | 0f8a249a | blueswir1 | case 0x0c1: /* V9 fmovscc %fcc3 */ |
2800 | 19f329ad | blueswir1 | FMOVCC(F, 3);
|
2801 | 0f8a249a | blueswir1 | break;
|
2802 | 0f8a249a | blueswir1 | case 0x0c2: /* V9 fmovdcc %fcc3 */ |
2803 | 19f329ad | blueswir1 | FMOVCC(D, 3);
|
2804 | 0f8a249a | blueswir1 | break;
|
2805 | 0f8a249a | blueswir1 | case 0x0c3: /* V9 fmovqcc %fcc3 */ |
2806 | 1f587329 | blueswir1 | #if defined(CONFIG_USER_ONLY)
|
2807 | 19f329ad | blueswir1 | FMOVCC(Q, 3);
|
2808 | 1f587329 | blueswir1 | break;
|
2809 | 1f587329 | blueswir1 | #else
|
2810 | 0f8a249a | blueswir1 | goto nfpu_insn;
|
2811 | 1f587329 | blueswir1 | #endif
|
2812 | 19f329ad | blueswir1 | #undef FMOVCC
|
2813 | 19f329ad | blueswir1 | #define FMOVCC(size_FDQ, icc) \
|
2814 | 19f329ad | blueswir1 | { \ |
2815 | 0425bee5 | blueswir1 | TCGv r_cond; \ |
2816 | 19f329ad | blueswir1 | int l1; \
|
2817 | 19f329ad | blueswir1 | \ |
2818 | 19f329ad | blueswir1 | l1 = gen_new_label(); \ |
2819 | 19f329ad | blueswir1 | r_cond = tcg_temp_new(TCG_TYPE_TL); \ |
2820 | 19f329ad | blueswir1 | cond = GET_FIELD_SP(insn, 14, 17); \ |
2821 | 19f329ad | blueswir1 | gen_cond(r_cond, icc, cond); \ |
2822 | 0425bee5 | blueswir1 | tcg_gen_brcond_tl(TCG_COND_EQ, r_cond, \ |
2823 | 0425bee5 | blueswir1 | tcg_const_tl(0), l1); \
|
2824 | 19f329ad | blueswir1 | glue(glue(gen_op_load_fpr_, size_FDQ), T0)(glue(size_FDQ, FPREG(rs2))); \ |
2825 | 19f329ad | blueswir1 | glue(glue(gen_op_store_, size_FDQ), T0_fpr)(glue(size_FDQ, FPREG(rd))); \ |
2826 | 19f329ad | blueswir1 | gen_set_label(l1); \ |
2827 | 0425bee5 | blueswir1 | tcg_gen_discard_tl(r_cond); \ |
2828 | 19f329ad | blueswir1 | } |
2829 | 19f329ad | blueswir1 | |
2830 | 0f8a249a | blueswir1 | case 0x101: /* V9 fmovscc %icc */ |
2831 | 19f329ad | blueswir1 | FMOVCC(F, 0);
|
2832 | 0f8a249a | blueswir1 | break;
|
2833 | 0f8a249a | blueswir1 | case 0x102: /* V9 fmovdcc %icc */ |
2834 | 19f329ad | blueswir1 | FMOVCC(D, 0);
|
2835 | 0f8a249a | blueswir1 | case 0x103: /* V9 fmovqcc %icc */ |
2836 | 1f587329 | blueswir1 | #if defined(CONFIG_USER_ONLY)
|
2837 | 19f329ad | blueswir1 | FMOVCC(D, 0);
|
2838 | 1f587329 | blueswir1 | break;
|
2839 | 1f587329 | blueswir1 | #else
|
2840 | 0f8a249a | blueswir1 | goto nfpu_insn;
|
2841 | 1f587329 | blueswir1 | #endif
|
2842 | 0f8a249a | blueswir1 | case 0x181: /* V9 fmovscc %xcc */ |
2843 | 19f329ad | blueswir1 | FMOVCC(F, 1);
|
2844 | 0f8a249a | blueswir1 | break;
|
2845 | 0f8a249a | blueswir1 | case 0x182: /* V9 fmovdcc %xcc */ |
2846 | 19f329ad | blueswir1 | FMOVCC(D, 1);
|
2847 | 0f8a249a | blueswir1 | break;
|
2848 | 0f8a249a | blueswir1 | case 0x183: /* V9 fmovqcc %xcc */ |
2849 | 1f587329 | blueswir1 | #if defined(CONFIG_USER_ONLY)
|
2850 | 19f329ad | blueswir1 | FMOVCC(Q, 1);
|
2851 | 1f587329 | blueswir1 | break;
|
2852 | 1f587329 | blueswir1 | #else
|
2853 | 0f8a249a | blueswir1 | goto nfpu_insn;
|
2854 | 0f8a249a | blueswir1 | #endif
|
2855 | 19f329ad | blueswir1 | #undef FMOVCC
|
2856 | 1f587329 | blueswir1 | #endif
|
2857 | 1f587329 | blueswir1 | case 0x51: /* fcmps, V9 %fcc */ |
2858 | 0f8a249a | blueswir1 | gen_op_load_fpr_FT0(rs1); |
2859 | 0f8a249a | blueswir1 | gen_op_load_fpr_FT1(rs2); |
2860 | 7e8c2b6c | blueswir1 | gen_op_fcmps(rd & 3);
|
2861 | 0f8a249a | blueswir1 | break;
|
2862 | 1f587329 | blueswir1 | case 0x52: /* fcmpd, V9 %fcc */ |
2863 | 0f8a249a | blueswir1 | gen_op_load_fpr_DT0(DFPREG(rs1)); |
2864 | 0f8a249a | blueswir1 | gen_op_load_fpr_DT1(DFPREG(rs2)); |
2865 | 7e8c2b6c | blueswir1 | gen_op_fcmpd(rd & 3);
|
2866 | 0f8a249a | blueswir1 | break;
|
2867 | 1f587329 | blueswir1 | case 0x53: /* fcmpq, V9 %fcc */ |
2868 | 1f587329 | blueswir1 | #if defined(CONFIG_USER_ONLY)
|
2869 | 1f587329 | blueswir1 | gen_op_load_fpr_QT0(QFPREG(rs1)); |
2870 | 1f587329 | blueswir1 | gen_op_load_fpr_QT1(QFPREG(rs2)); |
2871 | 7e8c2b6c | blueswir1 | gen_op_fcmpq(rd & 3);
|
2872 | 1f587329 | blueswir1 | break;
|
2873 | 1f587329 | blueswir1 | #else /* !defined(CONFIG_USER_ONLY) */ |
2874 | 0f8a249a | blueswir1 | goto nfpu_insn;
|
2875 | 1f587329 | blueswir1 | #endif
|
2876 | 0f8a249a | blueswir1 | case 0x55: /* fcmpes, V9 %fcc */ |
2877 | 0f8a249a | blueswir1 | gen_op_load_fpr_FT0(rs1); |
2878 | 0f8a249a | blueswir1 | gen_op_load_fpr_FT1(rs2); |
2879 | 7e8c2b6c | blueswir1 | gen_op_fcmpes(rd & 3);
|
2880 | 0f8a249a | blueswir1 | break;
|
2881 | 0f8a249a | blueswir1 | case 0x56: /* fcmped, V9 %fcc */ |
2882 | 0f8a249a | blueswir1 | gen_op_load_fpr_DT0(DFPREG(rs1)); |
2883 | 0f8a249a | blueswir1 | gen_op_load_fpr_DT1(DFPREG(rs2)); |
2884 | 7e8c2b6c | blueswir1 | gen_op_fcmped(rd & 3);
|
2885 | 0f8a249a | blueswir1 | break;
|
2886 | 1f587329 | blueswir1 | case 0x57: /* fcmpeq, V9 %fcc */ |
2887 | 1f587329 | blueswir1 | #if defined(CONFIG_USER_ONLY)
|
2888 | 1f587329 | blueswir1 | gen_op_load_fpr_QT0(QFPREG(rs1)); |
2889 | 1f587329 | blueswir1 | gen_op_load_fpr_QT1(QFPREG(rs2)); |
2890 | 7e8c2b6c | blueswir1 | gen_op_fcmpeq(rd & 3);
|
2891 | 1f587329 | blueswir1 | break;
|
2892 | 1f587329 | blueswir1 | #else/* !defined(CONFIG_USER_ONLY) */ |
2893 | 0f8a249a | blueswir1 | goto nfpu_insn;
|
2894 | 1f587329 | blueswir1 | #endif
|
2895 | 0f8a249a | blueswir1 | default:
|
2896 | 0f8a249a | blueswir1 | goto illegal_insn;
|
2897 | 0f8a249a | blueswir1 | } |
2898 | e80cfcfc | bellard | #if defined(OPTIM)
|
2899 | 0f8a249a | blueswir1 | } else if (xop == 0x2) { |
2900 | 0f8a249a | blueswir1 | // clr/mov shortcut
|
2901 | e80cfcfc | bellard | |
2902 | e80cfcfc | bellard | rs1 = GET_FIELD(insn, 13, 17); |
2903 | 0f8a249a | blueswir1 | if (rs1 == 0) { |
2904 | 1a2fb1c0 | blueswir1 | // or %g0, x, y -> mov T0, x; mov y, T0
|
2905 | 0f8a249a | blueswir1 | if (IS_IMM) { /* immediate */ |
2906 | 0f8a249a | blueswir1 | rs2 = GET_FIELDs(insn, 19, 31); |
2907 | 1a2fb1c0 | blueswir1 | tcg_gen_movi_tl(cpu_T[0], (int)rs2); |
2908 | 0f8a249a | blueswir1 | } else { /* register */ |
2909 | 0f8a249a | blueswir1 | rs2 = GET_FIELD(insn, 27, 31); |
2910 | 1a2fb1c0 | blueswir1 | gen_movl_reg_T0(rs2); |
2911 | 0f8a249a | blueswir1 | } |
2912 | 0f8a249a | blueswir1 | } else {
|
2913 | 0f8a249a | blueswir1 | gen_movl_reg_T0(rs1); |
2914 | 0f8a249a | blueswir1 | if (IS_IMM) { /* immediate */ |
2915 | 0f8a249a | blueswir1 | rs2 = GET_FIELDs(insn, 19, 31); |
2916 | 1a2fb1c0 | blueswir1 | tcg_gen_ori_tl(cpu_T[0], cpu_T[0], (int)rs2); |
2917 | 0f8a249a | blueswir1 | } else { /* register */ |
2918 | 0f8a249a | blueswir1 | // or x, %g0, y -> mov T1, x; mov y, T1
|
2919 | 0f8a249a | blueswir1 | rs2 = GET_FIELD(insn, 27, 31); |
2920 | 0f8a249a | blueswir1 | if (rs2 != 0) { |
2921 | 0f8a249a | blueswir1 | gen_movl_reg_T1(rs2); |
2922 | 0f8a249a | blueswir1 | gen_op_or_T1_T0(); |
2923 | 0f8a249a | blueswir1 | } |
2924 | 0f8a249a | blueswir1 | } |
2925 | 0f8a249a | blueswir1 | } |
2926 | 1a2fb1c0 | blueswir1 | gen_movl_T0_reg(rd); |
2927 | e80cfcfc | bellard | #endif
|
2928 | 83469015 | bellard | #ifdef TARGET_SPARC64
|
2929 | 0f8a249a | blueswir1 | } else if (xop == 0x25) { /* sll, V9 sllx */ |
2930 | 83469015 | bellard | rs1 = GET_FIELD(insn, 13, 17); |
2931 | 0f8a249a | blueswir1 | gen_movl_reg_T0(rs1); |
2932 | 0f8a249a | blueswir1 | if (IS_IMM) { /* immediate */ |
2933 | 83469015 | bellard | rs2 = GET_FIELDs(insn, 20, 31); |
2934 | 1a2fb1c0 | blueswir1 | if (insn & (1 << 12)) { |
2935 | 1a2fb1c0 | blueswir1 | tcg_gen_shli_i64(cpu_T[0], cpu_T[0], rs2 & 0x3f); |
2936 | 1a2fb1c0 | blueswir1 | } else {
|
2937 | 1a2fb1c0 | blueswir1 | tcg_gen_andi_i64(cpu_T[0], cpu_T[0], 0xffffffffULL); |
2938 | 1a2fb1c0 | blueswir1 | tcg_gen_shli_i64(cpu_T[0], cpu_T[0], rs2 & 0x1f); |
2939 | 1a2fb1c0 | blueswir1 | } |
2940 | 0f8a249a | blueswir1 | } else { /* register */ |
2941 | 83469015 | bellard | rs2 = GET_FIELD(insn, 27, 31); |
2942 | 83469015 | bellard | gen_movl_reg_T1(rs2); |
2943 | 1a2fb1c0 | blueswir1 | if (insn & (1 << 12)) { |
2944 | 1a2fb1c0 | blueswir1 | tcg_gen_andi_i64(cpu_T[1], cpu_T[1], 0x3f); |
2945 | 1a2fb1c0 | blueswir1 | tcg_gen_shl_i64(cpu_T[0], cpu_T[0], cpu_T[1]); |
2946 | 1a2fb1c0 | blueswir1 | } else {
|
2947 | 1a2fb1c0 | blueswir1 | tcg_gen_andi_i64(cpu_T[1], cpu_T[1], 0x1f); |
2948 | 1a2fb1c0 | blueswir1 | tcg_gen_andi_i64(cpu_T[0], cpu_T[0], 0xffffffffULL); |
2949 | 1a2fb1c0 | blueswir1 | tcg_gen_shl_i64(cpu_T[0], cpu_T[0], cpu_T[1]); |
2950 | 1a2fb1c0 | blueswir1 | } |
2951 | 83469015 | bellard | } |
2952 | 0f8a249a | blueswir1 | gen_movl_T0_reg(rd); |
2953 | 0f8a249a | blueswir1 | } else if (xop == 0x26) { /* srl, V9 srlx */ |
2954 | 83469015 | bellard | rs1 = GET_FIELD(insn, 13, 17); |
2955 | 0f8a249a | blueswir1 | gen_movl_reg_T0(rs1); |
2956 | 0f8a249a | blueswir1 | if (IS_IMM) { /* immediate */ |
2957 | 83469015 | bellard | rs2 = GET_FIELDs(insn, 20, 31); |
2958 | 1a2fb1c0 | blueswir1 | if (insn & (1 << 12)) { |
2959 | 1a2fb1c0 | blueswir1 | tcg_gen_shri_i64(cpu_T[0], cpu_T[0], rs2 & 0x3f); |
2960 | 1a2fb1c0 | blueswir1 | } else {
|
2961 | 1a2fb1c0 | blueswir1 | tcg_gen_andi_i64(cpu_T[0], cpu_T[0], 0xffffffffULL); |
2962 | 1a2fb1c0 | blueswir1 | tcg_gen_shri_i64(cpu_T[0], cpu_T[0], rs2 & 0x1f); |
2963 | 1a2fb1c0 | blueswir1 | } |
2964 | 0f8a249a | blueswir1 | } else { /* register */ |
2965 | 83469015 | bellard | rs2 = GET_FIELD(insn, 27, 31); |
2966 | 83469015 | bellard | gen_movl_reg_T1(rs2); |
2967 | 1a2fb1c0 | blueswir1 | if (insn & (1 << 12)) { |
2968 | 1a2fb1c0 | blueswir1 | tcg_gen_andi_i64(cpu_T[1], cpu_T[1], 0x3f); |
2969 | 1a2fb1c0 | blueswir1 | tcg_gen_shr_i64(cpu_T[0], cpu_T[0], cpu_T[1]); |
2970 | 1a2fb1c0 | blueswir1 | } else {
|
2971 | 1a2fb1c0 | blueswir1 | tcg_gen_andi_i64(cpu_T[1], cpu_T[1], 0x1f); |
2972 | 1a2fb1c0 | blueswir1 | tcg_gen_andi_i64(cpu_T[0], cpu_T[0], 0xffffffffULL); |
2973 | 1a2fb1c0 | blueswir1 | tcg_gen_shr_i64(cpu_T[0], cpu_T[0], cpu_T[1]); |
2974 | 1a2fb1c0 | blueswir1 | } |
2975 | 83469015 | bellard | } |
2976 | 0f8a249a | blueswir1 | gen_movl_T0_reg(rd); |
2977 | 0f8a249a | blueswir1 | } else if (xop == 0x27) { /* sra, V9 srax */ |
2978 | 83469015 | bellard | rs1 = GET_FIELD(insn, 13, 17); |
2979 | 0f8a249a | blueswir1 | gen_movl_reg_T0(rs1); |
2980 | 0f8a249a | blueswir1 | if (IS_IMM) { /* immediate */ |
2981 | 83469015 | bellard | rs2 = GET_FIELDs(insn, 20, 31); |
2982 | 1a2fb1c0 | blueswir1 | if (insn & (1 << 12)) { |
2983 | 1a2fb1c0 | blueswir1 | tcg_gen_sari_i64(cpu_T[0], cpu_T[0], rs2 & 0x3f); |
2984 | 1a2fb1c0 | blueswir1 | } else {
|
2985 | 1a2fb1c0 | blueswir1 | tcg_gen_andi_i64(cpu_T[0], cpu_T[0], 0xffffffffULL); |
2986 | 1a2fb1c0 | blueswir1 | tcg_gen_ext_i32_i64(cpu_T[0], cpu_T[0]); |
2987 | 1a2fb1c0 | blueswir1 | tcg_gen_sari_i64(cpu_T[0], cpu_T[0], rs2 & 0x1f); |
2988 | 1a2fb1c0 | blueswir1 | } |
2989 | 0f8a249a | blueswir1 | } else { /* register */ |
2990 | 83469015 | bellard | rs2 = GET_FIELD(insn, 27, 31); |
2991 | 83469015 | bellard | gen_movl_reg_T1(rs2); |
2992 | 1a2fb1c0 | blueswir1 | if (insn & (1 << 12)) { |
2993 | 1a2fb1c0 | blueswir1 | tcg_gen_andi_i64(cpu_T[1], cpu_T[1], 0x3f); |
2994 | 1a2fb1c0 | blueswir1 | tcg_gen_sar_i64(cpu_T[0], cpu_T[0], cpu_T[1]); |
2995 | 1a2fb1c0 | blueswir1 | } else {
|
2996 | 1a2fb1c0 | blueswir1 | tcg_gen_andi_i64(cpu_T[1], cpu_T[1], 0x1f); |
2997 | 1a2fb1c0 | blueswir1 | tcg_gen_andi_i64(cpu_T[0], cpu_T[0], 0xffffffffULL); |
2998 | 1a2fb1c0 | blueswir1 | tcg_gen_sar_i64(cpu_T[0], cpu_T[0], cpu_T[1]); |
2999 | 1a2fb1c0 | blueswir1 | } |
3000 | 83469015 | bellard | } |
3001 | 0f8a249a | blueswir1 | gen_movl_T0_reg(rd); |
3002 | 83469015 | bellard | #endif
|
3003 | fcc72045 | blueswir1 | } else if (xop < 0x36) { |
3004 | e80cfcfc | bellard | rs1 = GET_FIELD(insn, 13, 17); |
3005 | 0f8a249a | blueswir1 | gen_movl_reg_T0(rs1); |
3006 | 0f8a249a | blueswir1 | if (IS_IMM) { /* immediate */ |
3007 | cf495bcf | bellard | rs2 = GET_FIELDs(insn, 19, 31); |
3008 | 3475187d | bellard | gen_movl_simm_T1(rs2); |
3009 | 0f8a249a | blueswir1 | } else { /* register */ |
3010 | cf495bcf | bellard | rs2 = GET_FIELD(insn, 27, 31); |
3011 | cf495bcf | bellard | gen_movl_reg_T1(rs2); |
3012 | cf495bcf | bellard | } |
3013 | cf495bcf | bellard | if (xop < 0x20) { |
3014 | cf495bcf | bellard | switch (xop & ~0x10) { |
3015 | cf495bcf | bellard | case 0x0: |
3016 | cf495bcf | bellard | if (xop & 0x10) |
3017 | cf495bcf | bellard | gen_op_add_T1_T0_cc(); |
3018 | cf495bcf | bellard | else
|
3019 | cf495bcf | bellard | gen_op_add_T1_T0(); |
3020 | cf495bcf | bellard | break;
|
3021 | cf495bcf | bellard | case 0x1: |
3022 | 1a2fb1c0 | blueswir1 | tcg_gen_and_tl(cpu_T[0], cpu_T[0], cpu_T[1]); |
3023 | cf495bcf | bellard | if (xop & 0x10) |
3024 | cf495bcf | bellard | gen_op_logic_T0_cc(); |
3025 | cf495bcf | bellard | break;
|
3026 | cf495bcf | bellard | case 0x2: |
3027 | 1a2fb1c0 | blueswir1 | tcg_gen_or_tl(cpu_T[0], cpu_T[0], cpu_T[1]); |
3028 | 0f8a249a | blueswir1 | if (xop & 0x10) |
3029 | 0f8a249a | blueswir1 | gen_op_logic_T0_cc(); |
3030 | 0f8a249a | blueswir1 | break;
|
3031 | cf495bcf | bellard | case 0x3: |
3032 | 1a2fb1c0 | blueswir1 | tcg_gen_xor_tl(cpu_T[0], cpu_T[0], cpu_T[1]); |
3033 | cf495bcf | bellard | if (xop & 0x10) |
3034 | cf495bcf | bellard | gen_op_logic_T0_cc(); |
3035 | cf495bcf | bellard | break;
|
3036 | cf495bcf | bellard | case 0x4: |
3037 | cf495bcf | bellard | if (xop & 0x10) |
3038 | cf495bcf | bellard | gen_op_sub_T1_T0_cc(); |
3039 | cf495bcf | bellard | else
|
3040 | 1a2fb1c0 | blueswir1 | tcg_gen_sub_tl(cpu_T[0], cpu_T[0], cpu_T[1]); |
3041 | cf495bcf | bellard | break;
|
3042 | cf495bcf | bellard | case 0x5: |
3043 | 56ec06bb | blueswir1 | tcg_gen_xori_tl(cpu_T[1], cpu_T[1], -1); |
3044 | 56ec06bb | blueswir1 | tcg_gen_and_tl(cpu_T[0], cpu_T[0], cpu_T[1]); |
3045 | cf495bcf | bellard | if (xop & 0x10) |
3046 | cf495bcf | bellard | gen_op_logic_T0_cc(); |
3047 | cf495bcf | bellard | break;
|
3048 | cf495bcf | bellard | case 0x6: |
3049 | 56ec06bb | blueswir1 | tcg_gen_xori_tl(cpu_T[1], cpu_T[1], -1); |
3050 | 56ec06bb | blueswir1 | tcg_gen_or_tl(cpu_T[0], cpu_T[0], cpu_T[1]); |
3051 | cf495bcf | bellard | if (xop & 0x10) |
3052 | cf495bcf | bellard | gen_op_logic_T0_cc(); |
3053 | cf495bcf | bellard | break;
|
3054 | cf495bcf | bellard | case 0x7: |
3055 | 56ec06bb | blueswir1 | tcg_gen_xori_tl(cpu_T[1], cpu_T[1], -1); |
3056 | 56ec06bb | blueswir1 | tcg_gen_xor_tl(cpu_T[0], cpu_T[0], cpu_T[1]); |
3057 | cf495bcf | bellard | if (xop & 0x10) |
3058 | cf495bcf | bellard | gen_op_logic_T0_cc(); |
3059 | cf495bcf | bellard | break;
|
3060 | cf495bcf | bellard | case 0x8: |
3061 | cf495bcf | bellard | if (xop & 0x10) |
3062 | af7bf89b | bellard | gen_op_addx_T1_T0_cc(); |
3063 | 38bc628b | blueswir1 | else {
|
3064 | dc99a3f2 | blueswir1 | gen_mov_reg_C(cpu_tmp0, cpu_psr); |
3065 | 38bc628b | blueswir1 | tcg_gen_add_tl(cpu_T[1], cpu_T[1], cpu_tmp0); |
3066 | 38bc628b | blueswir1 | tcg_gen_add_tl(cpu_T[0], cpu_T[0], cpu_T[1]); |
3067 | 38bc628b | blueswir1 | } |
3068 | cf495bcf | bellard | break;
|
3069 | ded3ab80 | pbrook | #ifdef TARGET_SPARC64
|
3070 | 0f8a249a | blueswir1 | case 0x9: /* V9 mulx */ |
3071 | 1a2fb1c0 | blueswir1 | tcg_gen_mul_i64(cpu_T[0], cpu_T[0], cpu_T[1]); |
3072 | ded3ab80 | pbrook | break;
|
3073 | ded3ab80 | pbrook | #endif
|
3074 | cf495bcf | bellard | case 0xa: |
3075 | cf495bcf | bellard | gen_op_umul_T1_T0(); |
3076 | cf495bcf | bellard | if (xop & 0x10) |
3077 | cf495bcf | bellard | gen_op_logic_T0_cc(); |
3078 | cf495bcf | bellard | break;
|
3079 | cf495bcf | bellard | case 0xb: |
3080 | cf495bcf | bellard | gen_op_smul_T1_T0(); |
3081 | cf495bcf | bellard | if (xop & 0x10) |
3082 | cf495bcf | bellard | gen_op_logic_T0_cc(); |
3083 | cf495bcf | bellard | break;
|
3084 | cf495bcf | bellard | case 0xc: |
3085 | cf495bcf | bellard | if (xop & 0x10) |
3086 | af7bf89b | bellard | gen_op_subx_T1_T0_cc(); |
3087 | 38bc628b | blueswir1 | else {
|
3088 | dc99a3f2 | blueswir1 | gen_mov_reg_C(cpu_tmp0, cpu_psr); |
3089 | 38bc628b | blueswir1 | tcg_gen_add_tl(cpu_T[1], cpu_T[1], cpu_tmp0); |
3090 | 38bc628b | blueswir1 | tcg_gen_sub_tl(cpu_T[0], cpu_T[0], cpu_T[1]); |
3091 | 38bc628b | blueswir1 | } |
3092 | cf495bcf | bellard | break;
|
3093 | ded3ab80 | pbrook | #ifdef TARGET_SPARC64
|
3094 | 0f8a249a | blueswir1 | case 0xd: /* V9 udivx */ |
3095 | 8911f501 | blueswir1 | gen_trap_ifdivzero_tl(cpu_T[1]);
|
3096 | 1a7b60e7 | blueswir1 | tcg_gen_divu_i64(cpu_T[0], cpu_T[0], cpu_T[1]); |
3097 | ded3ab80 | pbrook | break;
|
3098 | ded3ab80 | pbrook | #endif
|
3099 | cf495bcf | bellard | case 0xe: |
3100 | cf495bcf | bellard | gen_op_udiv_T1_T0(); |
3101 | cf495bcf | bellard | if (xop & 0x10) |
3102 | cf495bcf | bellard | gen_op_div_cc(); |
3103 | cf495bcf | bellard | break;
|
3104 | cf495bcf | bellard | case 0xf: |
3105 | cf495bcf | bellard | gen_op_sdiv_T1_T0(); |
3106 | cf495bcf | bellard | if (xop & 0x10) |
3107 | cf495bcf | bellard | gen_op_div_cc(); |
3108 | cf495bcf | bellard | break;
|
3109 | cf495bcf | bellard | default:
|
3110 | cf495bcf | bellard | goto illegal_insn;
|
3111 | cf495bcf | bellard | } |
3112 | 0f8a249a | blueswir1 | gen_movl_T0_reg(rd); |
3113 | cf495bcf | bellard | } else {
|
3114 | cf495bcf | bellard | switch (xop) {
|
3115 | 0f8a249a | blueswir1 | case 0x20: /* taddcc */ |
3116 | 0f8a249a | blueswir1 | gen_op_tadd_T1_T0_cc(); |
3117 | 0f8a249a | blueswir1 | gen_movl_T0_reg(rd); |
3118 | 0f8a249a | blueswir1 | break;
|
3119 | 0f8a249a | blueswir1 | case 0x21: /* tsubcc */ |
3120 | 0f8a249a | blueswir1 | gen_op_tsub_T1_T0_cc(); |
3121 | 0f8a249a | blueswir1 | gen_movl_T0_reg(rd); |
3122 | 0f8a249a | blueswir1 | break;
|
3123 | 0f8a249a | blueswir1 | case 0x22: /* taddcctv */ |
3124 | 90251fb9 | blueswir1 | save_state(dc); |
3125 | 0f8a249a | blueswir1 | gen_op_tadd_T1_T0_ccTV(); |
3126 | 0f8a249a | blueswir1 | gen_movl_T0_reg(rd); |
3127 | 0f8a249a | blueswir1 | break;
|
3128 | 0f8a249a | blueswir1 | case 0x23: /* tsubcctv */ |
3129 | 90251fb9 | blueswir1 | save_state(dc); |
3130 | 0f8a249a | blueswir1 | gen_op_tsub_T1_T0_ccTV(); |
3131 | 0f8a249a | blueswir1 | gen_movl_T0_reg(rd); |
3132 | 0f8a249a | blueswir1 | break;
|
3133 | cf495bcf | bellard | case 0x24: /* mulscc */ |
3134 | cf495bcf | bellard | gen_op_mulscc_T1_T0(); |
3135 | cf495bcf | bellard | gen_movl_T0_reg(rd); |
3136 | cf495bcf | bellard | break;
|
3137 | 83469015 | bellard | #ifndef TARGET_SPARC64
|
3138 | 0f8a249a | blueswir1 | case 0x25: /* sll */ |
3139 | 8911f501 | blueswir1 | tcg_gen_andi_tl(cpu_T[1], cpu_T[1], 0x1f); |
3140 | 8911f501 | blueswir1 | tcg_gen_shl_tl(cpu_T[0], cpu_T[0], cpu_T[1]); |
3141 | cf495bcf | bellard | gen_movl_T0_reg(rd); |
3142 | cf495bcf | bellard | break;
|
3143 | 83469015 | bellard | case 0x26: /* srl */ |
3144 | 8911f501 | blueswir1 | tcg_gen_andi_tl(cpu_T[1], cpu_T[1], 0x1f); |
3145 | 8911f501 | blueswir1 | tcg_gen_shr_tl(cpu_T[0], cpu_T[0], cpu_T[1]); |
3146 | cf495bcf | bellard | gen_movl_T0_reg(rd); |
3147 | cf495bcf | bellard | break;
|
3148 | 83469015 | bellard | case 0x27: /* sra */ |
3149 | 8911f501 | blueswir1 | tcg_gen_andi_tl(cpu_T[1], cpu_T[1], 0x1f); |
3150 | 8911f501 | blueswir1 | tcg_gen_sar_tl(cpu_T[0], cpu_T[0], cpu_T[1]); |
3151 | cf495bcf | bellard | gen_movl_T0_reg(rd); |
3152 | cf495bcf | bellard | break;
|
3153 | 83469015 | bellard | #endif
|
3154 | cf495bcf | bellard | case 0x30: |
3155 | cf495bcf | bellard | { |
3156 | cf495bcf | bellard | switch(rd) {
|
3157 | 3475187d | bellard | case 0: /* wry */ |
3158 | 0f8a249a | blueswir1 | gen_op_xor_T1_T0(); |
3159 | 0f8a249a | blueswir1 | gen_op_movtl_env_T0(offsetof(CPUSPARCState, y)); |
3160 | cf495bcf | bellard | break;
|
3161 | 65fe7b09 | blueswir1 | #ifndef TARGET_SPARC64
|
3162 | 65fe7b09 | blueswir1 | case 0x01 ... 0x0f: /* undefined in the |
3163 | 65fe7b09 | blueswir1 | SPARCv8 manual, nop
|
3164 | 65fe7b09 | blueswir1 | on the microSPARC
|
3165 | 65fe7b09 | blueswir1 | II */
|
3166 | 65fe7b09 | blueswir1 | case 0x10 ... 0x1f: /* implementation-dependent |
3167 | 65fe7b09 | blueswir1 | in the SPARCv8
|
3168 | 65fe7b09 | blueswir1 | manual, nop on the
|
3169 | 65fe7b09 | blueswir1 | microSPARC II */
|
3170 | 65fe7b09 | blueswir1 | break;
|
3171 | 65fe7b09 | blueswir1 | #else
|
3172 | 0f8a249a | blueswir1 | case 0x2: /* V9 wrccr */ |
3173 | ee0b03fd | blueswir1 | gen_op_xor_T1_T0(); |
3174 | d35527d9 | blueswir1 | tcg_gen_helper_0_1(helper_wrccr, cpu_T[0]);
|
3175 | 0f8a249a | blueswir1 | break;
|
3176 | 0f8a249a | blueswir1 | case 0x3: /* V9 wrasi */ |
3177 | ee0b03fd | blueswir1 | gen_op_xor_T1_T0(); |
3178 | 0f8a249a | blueswir1 | gen_op_movl_env_T0(offsetof(CPUSPARCState, asi)); |
3179 | 0f8a249a | blueswir1 | break;
|
3180 | 0f8a249a | blueswir1 | case 0x6: /* V9 wrfprs */ |
3181 | 0f8a249a | blueswir1 | gen_op_xor_T1_T0(); |
3182 | 0f8a249a | blueswir1 | gen_op_movl_env_T0(offsetof(CPUSPARCState, fprs)); |
3183 | 3299908c | blueswir1 | save_state(dc); |
3184 | 3299908c | blueswir1 | gen_op_next_insn(); |
3185 | 57fec1fe | bellard | tcg_gen_exit_tb(0);
|
3186 | 3299908c | blueswir1 | dc->is_br = 1;
|
3187 | 0f8a249a | blueswir1 | break;
|
3188 | 0f8a249a | blueswir1 | case 0xf: /* V9 sir, nop if user */ |
3189 | 3475187d | bellard | #if !defined(CONFIG_USER_ONLY)
|
3190 | 0f8a249a | blueswir1 | if (supervisor(dc))
|
3191 | 1a2fb1c0 | blueswir1 | ; // XXX
|
3192 | 3475187d | bellard | #endif
|
3193 | 0f8a249a | blueswir1 | break;
|
3194 | 0f8a249a | blueswir1 | case 0x13: /* Graphics Status */ |
3195 | 725cb90b | bellard | if (gen_trap_ifnofpu(dc))
|
3196 | 725cb90b | bellard | goto jmp_insn;
|
3197 | ee0b03fd | blueswir1 | gen_op_xor_T1_T0(); |
3198 | 0f8a249a | blueswir1 | gen_op_movtl_env_T0(offsetof(CPUSPARCState, gsr)); |
3199 | 0f8a249a | blueswir1 | break;
|
3200 | 0f8a249a | blueswir1 | case 0x17: /* Tick compare */ |
3201 | 83469015 | bellard | #if !defined(CONFIG_USER_ONLY)
|
3202 | 0f8a249a | blueswir1 | if (!supervisor(dc))
|
3203 | 0f8a249a | blueswir1 | goto illegal_insn;
|
3204 | 83469015 | bellard | #endif
|
3205 | ccd4a219 | blueswir1 | { |
3206 | ccd4a219 | blueswir1 | TCGv r_tickptr; |
3207 | ccd4a219 | blueswir1 | |
3208 | ccd4a219 | blueswir1 | gen_op_xor_T1_T0(); |
3209 | ccd4a219 | blueswir1 | gen_op_movtl_env_T0(offsetof(CPUSPARCState, |
3210 | ccd4a219 | blueswir1 | tick_cmpr)); |
3211 | ccd4a219 | blueswir1 | r_tickptr = tcg_temp_new(TCG_TYPE_PTR); |
3212 | ccd4a219 | blueswir1 | tcg_gen_ld_ptr(r_tickptr, cpu_env, |
3213 | ccd4a219 | blueswir1 | offsetof(CPUState, tick)); |
3214 | ccd4a219 | blueswir1 | tcg_gen_helper_0_2(helper_tick_set_limit, |
3215 | ccd4a219 | blueswir1 | r_tickptr, cpu_T[0]);
|
3216 | 0425bee5 | blueswir1 | tcg_gen_discard_ptr(r_tickptr); |
3217 | ccd4a219 | blueswir1 | } |
3218 | 0f8a249a | blueswir1 | break;
|
3219 | 0f8a249a | blueswir1 | case 0x18: /* System tick */ |
3220 | 83469015 | bellard | #if !defined(CONFIG_USER_ONLY)
|
3221 | 0f8a249a | blueswir1 | if (!supervisor(dc))
|
3222 | 0f8a249a | blueswir1 | goto illegal_insn;
|
3223 | 83469015 | bellard | #endif
|
3224 | ccd4a219 | blueswir1 | { |
3225 | ccd4a219 | blueswir1 | TCGv r_tickptr; |
3226 | ccd4a219 | blueswir1 | |
3227 | ccd4a219 | blueswir1 | gen_op_xor_T1_T0(); |
3228 | ccd4a219 | blueswir1 | r_tickptr = tcg_temp_new(TCG_TYPE_PTR); |
3229 | ccd4a219 | blueswir1 | tcg_gen_ld_ptr(r_tickptr, cpu_env, |
3230 | ccd4a219 | blueswir1 | offsetof(CPUState, stick)); |
3231 | ccd4a219 | blueswir1 | tcg_gen_helper_0_2(helper_tick_set_count, |
3232 | ccd4a219 | blueswir1 | r_tickptr, cpu_T[0]);
|
3233 | 0425bee5 | blueswir1 | tcg_gen_discard_ptr(r_tickptr); |
3234 | ccd4a219 | blueswir1 | } |
3235 | 0f8a249a | blueswir1 | break;
|
3236 | 0f8a249a | blueswir1 | case 0x19: /* System tick compare */ |
3237 | 83469015 | bellard | #if !defined(CONFIG_USER_ONLY)
|
3238 | 0f8a249a | blueswir1 | if (!supervisor(dc))
|
3239 | 0f8a249a | blueswir1 | goto illegal_insn;
|
3240 | 3475187d | bellard | #endif
|
3241 | ccd4a219 | blueswir1 | { |
3242 | ccd4a219 | blueswir1 | TCGv r_tickptr; |
3243 | ccd4a219 | blueswir1 | |
3244 | ccd4a219 | blueswir1 | gen_op_xor_T1_T0(); |
3245 | ccd4a219 | blueswir1 | gen_op_movtl_env_T0(offsetof(CPUSPARCState, |
3246 | ccd4a219 | blueswir1 | stick_cmpr)); |
3247 | ccd4a219 | blueswir1 | r_tickptr = tcg_temp_new(TCG_TYPE_PTR); |
3248 | ccd4a219 | blueswir1 | tcg_gen_ld_ptr(r_tickptr, cpu_env, |
3249 | ccd4a219 | blueswir1 | offsetof(CPUState, stick)); |
3250 | ccd4a219 | blueswir1 | tcg_gen_helper_0_2(helper_tick_set_limit, |
3251 | ccd4a219 | blueswir1 | r_tickptr, cpu_T[0]);
|
3252 | 0425bee5 | blueswir1 | tcg_gen_discard_ptr(r_tickptr); |
3253 | ccd4a219 | blueswir1 | } |
3254 | 0f8a249a | blueswir1 | break;
|
3255 | 83469015 | bellard | |
3256 | 0f8a249a | blueswir1 | case 0x10: /* Performance Control */ |
3257 | 0f8a249a | blueswir1 | case 0x11: /* Performance Instrumentation Counter */ |
3258 | 0f8a249a | blueswir1 | case 0x12: /* Dispatch Control */ |
3259 | 0f8a249a | blueswir1 | case 0x14: /* Softint set */ |
3260 | 0f8a249a | blueswir1 | case 0x15: /* Softint clear */ |
3261 | 0f8a249a | blueswir1 | case 0x16: /* Softint write */ |
3262 | 83469015 | bellard | #endif
|
3263 | 3475187d | bellard | default:
|
3264 | cf495bcf | bellard | goto illegal_insn;
|
3265 | cf495bcf | bellard | } |
3266 | cf495bcf | bellard | } |
3267 | cf495bcf | bellard | break;
|
3268 | e8af50a3 | bellard | #if !defined(CONFIG_USER_ONLY)
|
3269 | af7bf89b | bellard | case 0x31: /* wrpsr, V9 saved, restored */ |
3270 | e8af50a3 | bellard | { |
3271 | 0f8a249a | blueswir1 | if (!supervisor(dc))
|
3272 | 0f8a249a | blueswir1 | goto priv_insn;
|
3273 | 3475187d | bellard | #ifdef TARGET_SPARC64
|
3274 | 0f8a249a | blueswir1 | switch (rd) {
|
3275 | 0f8a249a | blueswir1 | case 0: |
3276 | 72a9747b | blueswir1 | tcg_gen_helper_0_0(helper_saved); |
3277 | 0f8a249a | blueswir1 | break;
|
3278 | 0f8a249a | blueswir1 | case 1: |
3279 | 72a9747b | blueswir1 | tcg_gen_helper_0_0(helper_restored); |
3280 | 0f8a249a | blueswir1 | break;
|
3281 | e9ebed4d | blueswir1 | case 2: /* UA2005 allclean */ |
3282 | e9ebed4d | blueswir1 | case 3: /* UA2005 otherw */ |
3283 | e9ebed4d | blueswir1 | case 4: /* UA2005 normalw */ |
3284 | e9ebed4d | blueswir1 | case 5: /* UA2005 invalw */ |
3285 | e9ebed4d | blueswir1 | // XXX
|
3286 | 0f8a249a | blueswir1 | default:
|
3287 | 3475187d | bellard | goto illegal_insn;
|
3288 | 3475187d | bellard | } |
3289 | 3475187d | bellard | #else
|
3290 | e8af50a3 | bellard | gen_op_xor_T1_T0(); |
3291 | 1a2fb1c0 | blueswir1 | tcg_gen_helper_0_1(helper_wrpsr, cpu_T[0]);
|
3292 | 9e61bde5 | bellard | save_state(dc); |
3293 | 9e61bde5 | bellard | gen_op_next_insn(); |
3294 | 57fec1fe | bellard | tcg_gen_exit_tb(0);
|
3295 | 0f8a249a | blueswir1 | dc->is_br = 1;
|
3296 | 3475187d | bellard | #endif
|
3297 | e8af50a3 | bellard | } |
3298 | e8af50a3 | bellard | break;
|
3299 | af7bf89b | bellard | case 0x32: /* wrwim, V9 wrpr */ |
3300 | e8af50a3 | bellard | { |
3301 | 0f8a249a | blueswir1 | if (!supervisor(dc))
|
3302 | 0f8a249a | blueswir1 | goto priv_insn;
|
3303 | e8af50a3 | bellard | gen_op_xor_T1_T0(); |
3304 | 3475187d | bellard | #ifdef TARGET_SPARC64
|
3305 | 0f8a249a | blueswir1 | switch (rd) {
|
3306 | 0f8a249a | blueswir1 | case 0: // tpc |
3307 | 375ee38b | blueswir1 | { |
3308 | 375ee38b | blueswir1 | TCGv r_tsptr; |
3309 | 375ee38b | blueswir1 | |
3310 | 375ee38b | blueswir1 | r_tsptr = tcg_temp_new(TCG_TYPE_PTR); |
3311 | 375ee38b | blueswir1 | tcg_gen_ld_ptr(r_tsptr, cpu_env, |
3312 | 375ee38b | blueswir1 | offsetof(CPUState, tsptr)); |
3313 | 375ee38b | blueswir1 | tcg_gen_st_tl(cpu_T[0], r_tsptr,
|
3314 | 375ee38b | blueswir1 | offsetof(trap_state, tpc)); |
3315 | 0425bee5 | blueswir1 | tcg_gen_discard_ptr(r_tsptr); |
3316 | 375ee38b | blueswir1 | } |
3317 | 0f8a249a | blueswir1 | break;
|
3318 | 0f8a249a | blueswir1 | case 1: // tnpc |
3319 | 375ee38b | blueswir1 | { |
3320 | 375ee38b | blueswir1 | TCGv r_tsptr; |
3321 | 375ee38b | blueswir1 | |
3322 | 375ee38b | blueswir1 | r_tsptr = tcg_temp_new(TCG_TYPE_PTR); |
3323 | 375ee38b | blueswir1 | tcg_gen_ld_ptr(r_tsptr, cpu_env, |
3324 | 375ee38b | blueswir1 | offsetof(CPUState, tsptr)); |
3325 | 375ee38b | blueswir1 | tcg_gen_st_tl(cpu_T[0], r_tsptr,
|
3326 | 375ee38b | blueswir1 | offsetof(trap_state, tnpc)); |
3327 | 0425bee5 | blueswir1 | tcg_gen_discard_ptr(r_tsptr); |
3328 | 375ee38b | blueswir1 | } |
3329 | 0f8a249a | blueswir1 | break;
|
3330 | 0f8a249a | blueswir1 | case 2: // tstate |
3331 | 375ee38b | blueswir1 | { |
3332 | 375ee38b | blueswir1 | TCGv r_tsptr; |
3333 | 375ee38b | blueswir1 | |
3334 | 375ee38b | blueswir1 | r_tsptr = tcg_temp_new(TCG_TYPE_PTR); |
3335 | 375ee38b | blueswir1 | tcg_gen_ld_ptr(r_tsptr, cpu_env, |
3336 | 375ee38b | blueswir1 | offsetof(CPUState, tsptr)); |
3337 | 375ee38b | blueswir1 | tcg_gen_st_tl(cpu_T[0], r_tsptr,
|
3338 | 375ee38b | blueswir1 | offsetof(trap_state, tstate)); |
3339 | 0425bee5 | blueswir1 | tcg_gen_discard_ptr(r_tsptr); |
3340 | 375ee38b | blueswir1 | } |
3341 | 0f8a249a | blueswir1 | break;
|
3342 | 0f8a249a | blueswir1 | case 3: // tt |
3343 | 375ee38b | blueswir1 | { |
3344 | 375ee38b | blueswir1 | TCGv r_tsptr; |
3345 | 375ee38b | blueswir1 | |
3346 | 375ee38b | blueswir1 | r_tsptr = tcg_temp_new(TCG_TYPE_PTR); |
3347 | 375ee38b | blueswir1 | tcg_gen_ld_ptr(r_tsptr, cpu_env, |
3348 | 375ee38b | blueswir1 | offsetof(CPUState, tsptr)); |
3349 | 375ee38b | blueswir1 | tcg_gen_st_i32(cpu_T[0], r_tsptr,
|
3350 | 375ee38b | blueswir1 | offsetof(trap_state, tt)); |
3351 | 0425bee5 | blueswir1 | tcg_gen_discard_ptr(r_tsptr); |
3352 | 375ee38b | blueswir1 | } |
3353 | 0f8a249a | blueswir1 | break;
|
3354 | 0f8a249a | blueswir1 | case 4: // tick |
3355 | ccd4a219 | blueswir1 | { |
3356 | ccd4a219 | blueswir1 | TCGv r_tickptr; |
3357 | ccd4a219 | blueswir1 | |
3358 | ccd4a219 | blueswir1 | r_tickptr = tcg_temp_new(TCG_TYPE_PTR); |
3359 | ccd4a219 | blueswir1 | tcg_gen_ld_ptr(r_tickptr, cpu_env, |
3360 | ccd4a219 | blueswir1 | offsetof(CPUState, tick)); |
3361 | ccd4a219 | blueswir1 | tcg_gen_helper_0_2(helper_tick_set_count, |
3362 | ccd4a219 | blueswir1 | r_tickptr, cpu_T[0]);
|
3363 | 0425bee5 | blueswir1 | tcg_gen_discard_ptr(r_tickptr); |
3364 | ccd4a219 | blueswir1 | } |
3365 | 0f8a249a | blueswir1 | break;
|
3366 | 0f8a249a | blueswir1 | case 5: // tba |
3367 | 0f8a249a | blueswir1 | gen_op_movtl_env_T0(offsetof(CPUSPARCState, tbr)); |
3368 | 0f8a249a | blueswir1 | break;
|
3369 | 0f8a249a | blueswir1 | case 6: // pstate |
3370 | ded3ab80 | pbrook | save_state(dc); |
3371 | 1a2fb1c0 | blueswir1 | tcg_gen_helper_0_1(helper_wrpstate, cpu_T[0]);
|
3372 | ded3ab80 | pbrook | gen_op_next_insn(); |
3373 | 57fec1fe | bellard | tcg_gen_exit_tb(0);
|
3374 | ded3ab80 | pbrook | dc->is_br = 1;
|
3375 | 0f8a249a | blueswir1 | break;
|
3376 | 0f8a249a | blueswir1 | case 7: // tl |
3377 | 0f8a249a | blueswir1 | gen_op_movl_env_T0(offsetof(CPUSPARCState, tl)); |
3378 | 0f8a249a | blueswir1 | break;
|
3379 | 0f8a249a | blueswir1 | case 8: // pil |
3380 | 0f8a249a | blueswir1 | gen_op_movl_env_T0(offsetof(CPUSPARCState, psrpil)); |
3381 | 0f8a249a | blueswir1 | break;
|
3382 | 0f8a249a | blueswir1 | case 9: // cwp |
3383 | d35527d9 | blueswir1 | tcg_gen_helper_0_1(helper_wrcwp, cpu_T[0]);
|
3384 | 0f8a249a | blueswir1 | break;
|
3385 | 0f8a249a | blueswir1 | case 10: // cansave |
3386 | 0f8a249a | blueswir1 | gen_op_movl_env_T0(offsetof(CPUSPARCState, cansave)); |
3387 | 0f8a249a | blueswir1 | break;
|
3388 | 0f8a249a | blueswir1 | case 11: // canrestore |
3389 | 0f8a249a | blueswir1 | gen_op_movl_env_T0(offsetof(CPUSPARCState, canrestore)); |
3390 | 0f8a249a | blueswir1 | break;
|
3391 | 0f8a249a | blueswir1 | case 12: // cleanwin |
3392 | 0f8a249a | blueswir1 | gen_op_movl_env_T0(offsetof(CPUSPARCState, cleanwin)); |
3393 | 0f8a249a | blueswir1 | break;
|
3394 | 0f8a249a | blueswir1 | case 13: // otherwin |
3395 | 0f8a249a | blueswir1 | gen_op_movl_env_T0(offsetof(CPUSPARCState, otherwin)); |
3396 | 0f8a249a | blueswir1 | break;
|
3397 | 0f8a249a | blueswir1 | case 14: // wstate |
3398 | 0f8a249a | blueswir1 | gen_op_movl_env_T0(offsetof(CPUSPARCState, wstate)); |
3399 | 0f8a249a | blueswir1 | break;
|
3400 | e9ebed4d | blueswir1 | case 16: // UA2005 gl |
3401 | e9ebed4d | blueswir1 | gen_op_movl_env_T0(offsetof(CPUSPARCState, gl)); |
3402 | e9ebed4d | blueswir1 | break;
|
3403 | e9ebed4d | blueswir1 | case 26: // UA2005 strand status |
3404 | e9ebed4d | blueswir1 | if (!hypervisor(dc))
|
3405 | e9ebed4d | blueswir1 | goto priv_insn;
|
3406 | e9ebed4d | blueswir1 | gen_op_movl_env_T0(offsetof(CPUSPARCState, ssr)); |
3407 | e9ebed4d | blueswir1 | break;
|
3408 | 0f8a249a | blueswir1 | default:
|
3409 | 0f8a249a | blueswir1 | goto illegal_insn;
|
3410 | 0f8a249a | blueswir1 | } |
3411 | 3475187d | bellard | #else
|
3412 | 8911f501 | blueswir1 | tcg_gen_andi_tl(cpu_T[0], cpu_T[0], ((1 << NWINDOWS) - 1)); |
3413 | 1a2fb1c0 | blueswir1 | gen_op_movl_env_T0(offsetof(CPUSPARCState, wim)); |
3414 | 3475187d | bellard | #endif
|
3415 | e8af50a3 | bellard | } |
3416 | e8af50a3 | bellard | break;
|
3417 | e9ebed4d | blueswir1 | case 0x33: /* wrtbr, UA2005 wrhpr */ |
3418 | e8af50a3 | bellard | { |
3419 | e9ebed4d | blueswir1 | #ifndef TARGET_SPARC64
|
3420 | 0f8a249a | blueswir1 | if (!supervisor(dc))
|
3421 | 0f8a249a | blueswir1 | goto priv_insn;
|
3422 | e8af50a3 | bellard | gen_op_xor_T1_T0(); |
3423 | e9ebed4d | blueswir1 | gen_op_movtl_env_T0(offsetof(CPUSPARCState, tbr)); |
3424 | e9ebed4d | blueswir1 | #else
|
3425 | e9ebed4d | blueswir1 | if (!hypervisor(dc))
|
3426 | e9ebed4d | blueswir1 | goto priv_insn;
|
3427 | e9ebed4d | blueswir1 | gen_op_xor_T1_T0(); |
3428 | e9ebed4d | blueswir1 | switch (rd) {
|
3429 | e9ebed4d | blueswir1 | case 0: // hpstate |
3430 | e9ebed4d | blueswir1 | // XXX gen_op_wrhpstate();
|
3431 | e9ebed4d | blueswir1 | save_state(dc); |
3432 | e9ebed4d | blueswir1 | gen_op_next_insn(); |
3433 | 57fec1fe | bellard | tcg_gen_exit_tb(0);
|
3434 | e9ebed4d | blueswir1 | dc->is_br = 1;
|
3435 | e9ebed4d | blueswir1 | break;
|
3436 | e9ebed4d | blueswir1 | case 1: // htstate |
3437 | e9ebed4d | blueswir1 | // XXX gen_op_wrhtstate();
|
3438 | e9ebed4d | blueswir1 | break;
|
3439 | e9ebed4d | blueswir1 | case 3: // hintp |
3440 | e9ebed4d | blueswir1 | gen_op_movl_env_T0(offsetof(CPUSPARCState, hintp)); |
3441 | e9ebed4d | blueswir1 | break;
|
3442 | e9ebed4d | blueswir1 | case 5: // htba |
3443 | e9ebed4d | blueswir1 | gen_op_movl_env_T0(offsetof(CPUSPARCState, htba)); |
3444 | e9ebed4d | blueswir1 | break;
|
3445 | e9ebed4d | blueswir1 | case 31: // hstick_cmpr |
3446 | ccd4a219 | blueswir1 | { |
3447 | ccd4a219 | blueswir1 | TCGv r_tickptr; |
3448 | ccd4a219 | blueswir1 | |
3449 | ccd4a219 | blueswir1 | gen_op_movtl_env_T0(offsetof(CPUSPARCState, |
3450 | ccd4a219 | blueswir1 | hstick_cmpr)); |
3451 | ccd4a219 | blueswir1 | r_tickptr = tcg_temp_new(TCG_TYPE_PTR); |
3452 | ccd4a219 | blueswir1 | tcg_gen_ld_ptr(r_tickptr, cpu_env, |
3453 | ccd4a219 | blueswir1 | offsetof(CPUState, hstick)); |
3454 | ccd4a219 | blueswir1 | tcg_gen_helper_0_2(helper_tick_set_limit, |
3455 | ccd4a219 | blueswir1 | r_tickptr, cpu_T[0]);
|
3456 | 0425bee5 | blueswir1 | tcg_gen_discard_ptr(r_tickptr); |
3457 | ccd4a219 | blueswir1 | } |
3458 | e9ebed4d | blueswir1 | break;
|
3459 | e9ebed4d | blueswir1 | case 6: // hver readonly |
3460 | e9ebed4d | blueswir1 | default:
|
3461 | e9ebed4d | blueswir1 | goto illegal_insn;
|
3462 | e9ebed4d | blueswir1 | } |
3463 | e9ebed4d | blueswir1 | #endif
|
3464 | e8af50a3 | bellard | } |
3465 | e8af50a3 | bellard | break;
|
3466 | e8af50a3 | bellard | #endif
|
3467 | 3475187d | bellard | #ifdef TARGET_SPARC64
|
3468 | 0f8a249a | blueswir1 | case 0x2c: /* V9 movcc */ |
3469 | 0f8a249a | blueswir1 | { |
3470 | 0f8a249a | blueswir1 | int cc = GET_FIELD_SP(insn, 11, 12); |
3471 | 0f8a249a | blueswir1 | int cond = GET_FIELD_SP(insn, 14, 17); |
3472 | 748b9d8e | blueswir1 | TCGv r_cond; |
3473 | 00f219bf | blueswir1 | int l1;
|
3474 | 00f219bf | blueswir1 | |
3475 | 748b9d8e | blueswir1 | r_cond = tcg_temp_new(TCG_TYPE_TL); |
3476 | 0f8a249a | blueswir1 | if (insn & (1 << 18)) { |
3477 | 0f8a249a | blueswir1 | if (cc == 0) |
3478 | 748b9d8e | blueswir1 | gen_cond(r_cond, 0, cond);
|
3479 | 0f8a249a | blueswir1 | else if (cc == 2) |
3480 | 748b9d8e | blueswir1 | gen_cond(r_cond, 1, cond);
|
3481 | 0f8a249a | blueswir1 | else
|
3482 | 0f8a249a | blueswir1 | goto illegal_insn;
|
3483 | 0f8a249a | blueswir1 | } else {
|
3484 | 748b9d8e | blueswir1 | gen_fcond(r_cond, cc, cond); |
3485 | 0f8a249a | blueswir1 | } |
3486 | 00f219bf | blueswir1 | |
3487 | 00f219bf | blueswir1 | l1 = gen_new_label(); |
3488 | 00f219bf | blueswir1 | |
3489 | 748b9d8e | blueswir1 | tcg_gen_brcond_tl(TCG_COND_EQ, r_cond, |
3490 | 748b9d8e | blueswir1 | tcg_const_tl(0), l1);
|
3491 | 00f219bf | blueswir1 | if (IS_IMM) { /* immediate */ |
3492 | 00f219bf | blueswir1 | rs2 = GET_FIELD_SPs(insn, 0, 10); |
3493 | 00f219bf | blueswir1 | gen_movl_simm_T1(rs2); |
3494 | 00f219bf | blueswir1 | } else {
|
3495 | 00f219bf | blueswir1 | rs2 = GET_FIELD_SP(insn, 0, 4); |
3496 | 00f219bf | blueswir1 | gen_movl_reg_T1(rs2); |
3497 | 00f219bf | blueswir1 | } |
3498 | 00f219bf | blueswir1 | gen_movl_T1_reg(rd); |
3499 | 00f219bf | blueswir1 | gen_set_label(l1); |
3500 | 0425bee5 | blueswir1 | tcg_gen_discard_tl(r_cond); |
3501 | 0f8a249a | blueswir1 | break;
|
3502 | 0f8a249a | blueswir1 | } |
3503 | 0f8a249a | blueswir1 | case 0x2d: /* V9 sdivx */ |
3504 | 3475187d | bellard | gen_op_sdivx_T1_T0(); |
3505 | 0f8a249a | blueswir1 | gen_movl_T0_reg(rd); |
3506 | 0f8a249a | blueswir1 | break;
|
3507 | 0f8a249a | blueswir1 | case 0x2e: /* V9 popc */ |
3508 | 0f8a249a | blueswir1 | { |
3509 | 0f8a249a | blueswir1 | if (IS_IMM) { /* immediate */ |
3510 | 0f8a249a | blueswir1 | rs2 = GET_FIELD_SPs(insn, 0, 12); |
3511 | 0f8a249a | blueswir1 | gen_movl_simm_T1(rs2); |
3512 | 0f8a249a | blueswir1 | // XXX optimize: popc(constant)
|
3513 | 0f8a249a | blueswir1 | } |
3514 | 0f8a249a | blueswir1 | else {
|
3515 | 0f8a249a | blueswir1 | rs2 = GET_FIELD_SP(insn, 0, 4); |
3516 | 0f8a249a | blueswir1 | gen_movl_reg_T1(rs2); |
3517 | 0f8a249a | blueswir1 | } |
3518 | 1a2fb1c0 | blueswir1 | tcg_gen_helper_1_1(helper_popc, cpu_T[0],
|
3519 | 1a2fb1c0 | blueswir1 | cpu_T[1]);
|
3520 | 0f8a249a | blueswir1 | gen_movl_T0_reg(rd); |
3521 | 0f8a249a | blueswir1 | } |
3522 | 0f8a249a | blueswir1 | case 0x2f: /* V9 movr */ |
3523 | 0f8a249a | blueswir1 | { |
3524 | 0f8a249a | blueswir1 | int cond = GET_FIELD_SP(insn, 10, 12); |
3525 | 00f219bf | blueswir1 | int l1;
|
3526 | 00f219bf | blueswir1 | |
3527 | 0f8a249a | blueswir1 | rs1 = GET_FIELD(insn, 13, 17); |
3528 | 0f8a249a | blueswir1 | gen_movl_reg_T0(rs1); |
3529 | 00f219bf | blueswir1 | |
3530 | 00f219bf | blueswir1 | l1 = gen_new_label(); |
3531 | 00f219bf | blueswir1 | |
3532 | 0425bee5 | blueswir1 | tcg_gen_brcond_tl(gen_tcg_cond_reg[cond], cpu_T[0],
|
3533 | 0425bee5 | blueswir1 | tcg_const_tl(0), l1);
|
3534 | 0f8a249a | blueswir1 | if (IS_IMM) { /* immediate */ |
3535 | 0f8a249a | blueswir1 | rs2 = GET_FIELD_SPs(insn, 0, 9); |
3536 | 0f8a249a | blueswir1 | gen_movl_simm_T1(rs2); |
3537 | 00f219bf | blueswir1 | } else {
|
3538 | 0f8a249a | blueswir1 | rs2 = GET_FIELD_SP(insn, 0, 4); |
3539 | 0f8a249a | blueswir1 | gen_movl_reg_T1(rs2); |
3540 | 0f8a249a | blueswir1 | } |
3541 | 00f219bf | blueswir1 | gen_movl_T1_reg(rd); |
3542 | 00f219bf | blueswir1 | gen_set_label(l1); |
3543 | 0f8a249a | blueswir1 | break;
|
3544 | 0f8a249a | blueswir1 | } |
3545 | 0f8a249a | blueswir1 | #endif
|
3546 | 0f8a249a | blueswir1 | default:
|
3547 | 0f8a249a | blueswir1 | goto illegal_insn;
|
3548 | 0f8a249a | blueswir1 | } |
3549 | 0f8a249a | blueswir1 | } |
3550 | 3299908c | blueswir1 | } else if (xop == 0x36) { /* UltraSparc shutdown, VIS, V8 CPop1 */ |
3551 | 3299908c | blueswir1 | #ifdef TARGET_SPARC64
|
3552 | 3299908c | blueswir1 | int opf = GET_FIELD_SP(insn, 5, 13); |
3553 | 3299908c | blueswir1 | rs1 = GET_FIELD(insn, 13, 17); |
3554 | 3299908c | blueswir1 | rs2 = GET_FIELD(insn, 27, 31); |
3555 | e9ebed4d | blueswir1 | if (gen_trap_ifnofpu(dc))
|
3556 | e9ebed4d | blueswir1 | goto jmp_insn;
|
3557 | 3299908c | blueswir1 | |
3558 | 3299908c | blueswir1 | switch (opf) {
|
3559 | e9ebed4d | blueswir1 | case 0x000: /* VIS I edge8cc */ |
3560 | e9ebed4d | blueswir1 | case 0x001: /* VIS II edge8n */ |
3561 | e9ebed4d | blueswir1 | case 0x002: /* VIS I edge8lcc */ |
3562 | e9ebed4d | blueswir1 | case 0x003: /* VIS II edge8ln */ |
3563 | e9ebed4d | blueswir1 | case 0x004: /* VIS I edge16cc */ |
3564 | e9ebed4d | blueswir1 | case 0x005: /* VIS II edge16n */ |
3565 | e9ebed4d | blueswir1 | case 0x006: /* VIS I edge16lcc */ |
3566 | e9ebed4d | blueswir1 | case 0x007: /* VIS II edge16ln */ |
3567 | e9ebed4d | blueswir1 | case 0x008: /* VIS I edge32cc */ |
3568 | e9ebed4d | blueswir1 | case 0x009: /* VIS II edge32n */ |
3569 | e9ebed4d | blueswir1 | case 0x00a: /* VIS I edge32lcc */ |
3570 | e9ebed4d | blueswir1 | case 0x00b: /* VIS II edge32ln */ |
3571 | e9ebed4d | blueswir1 | // XXX
|
3572 | e9ebed4d | blueswir1 | goto illegal_insn;
|
3573 | e9ebed4d | blueswir1 | case 0x010: /* VIS I array8 */ |
3574 | e9ebed4d | blueswir1 | gen_movl_reg_T0(rs1); |
3575 | e9ebed4d | blueswir1 | gen_movl_reg_T1(rs2); |
3576 | 1f5063fb | blueswir1 | tcg_gen_helper_1_2(helper_array8, cpu_T[0], cpu_T[0], |
3577 | 1f5063fb | blueswir1 | cpu_T[1]);
|
3578 | e9ebed4d | blueswir1 | gen_movl_T0_reg(rd); |
3579 | e9ebed4d | blueswir1 | break;
|
3580 | e9ebed4d | blueswir1 | case 0x012: /* VIS I array16 */ |
3581 | e9ebed4d | blueswir1 | gen_movl_reg_T0(rs1); |
3582 | e9ebed4d | blueswir1 | gen_movl_reg_T1(rs2); |
3583 | 1f5063fb | blueswir1 | tcg_gen_helper_1_2(helper_array8, cpu_T[0], cpu_T[0], |
3584 | 1f5063fb | blueswir1 | cpu_T[1]);
|
3585 | 1f5063fb | blueswir1 | tcg_gen_shli_i64(cpu_T[0], cpu_T[0], 1); |
3586 | e9ebed4d | blueswir1 | gen_movl_T0_reg(rd); |
3587 | e9ebed4d | blueswir1 | break;
|
3588 | e9ebed4d | blueswir1 | case 0x014: /* VIS I array32 */ |
3589 | e9ebed4d | blueswir1 | gen_movl_reg_T0(rs1); |
3590 | e9ebed4d | blueswir1 | gen_movl_reg_T1(rs2); |
3591 | 1f5063fb | blueswir1 | tcg_gen_helper_1_2(helper_array8, cpu_T[0], cpu_T[0], |
3592 | 1f5063fb | blueswir1 | cpu_T[1]);
|
3593 | 1f5063fb | blueswir1 | tcg_gen_shli_i64(cpu_T[0], cpu_T[0], 2); |
3594 | e9ebed4d | blueswir1 | gen_movl_T0_reg(rd); |
3595 | e9ebed4d | blueswir1 | break;
|
3596 | 3299908c | blueswir1 | case 0x018: /* VIS I alignaddr */ |
3597 | 3299908c | blueswir1 | gen_movl_reg_T0(rs1); |
3598 | 3299908c | blueswir1 | gen_movl_reg_T1(rs2); |
3599 | 1f5063fb | blueswir1 | tcg_gen_helper_1_2(helper_alignaddr, cpu_T[0], cpu_T[0], |
3600 | 1f5063fb | blueswir1 | cpu_T[1]);
|
3601 | 3299908c | blueswir1 | gen_movl_T0_reg(rd); |
3602 | 3299908c | blueswir1 | break;
|
3603 | e9ebed4d | blueswir1 | case 0x019: /* VIS II bmask */ |
3604 | 3299908c | blueswir1 | case 0x01a: /* VIS I alignaddrl */ |
3605 | 3299908c | blueswir1 | // XXX
|
3606 | e9ebed4d | blueswir1 | goto illegal_insn;
|
3607 | e9ebed4d | blueswir1 | case 0x020: /* VIS I fcmple16 */ |
3608 | 2382dc6b | blueswir1 | gen_op_load_fpr_DT0(DFPREG(rs1)); |
3609 | 2382dc6b | blueswir1 | gen_op_load_fpr_DT1(DFPREG(rs2)); |
3610 | 44e7757c | blueswir1 | tcg_gen_helper_0_0(helper_fcmple16); |
3611 | 2382dc6b | blueswir1 | gen_op_store_DT0_fpr(DFPREG(rd)); |
3612 | e9ebed4d | blueswir1 | break;
|
3613 | e9ebed4d | blueswir1 | case 0x022: /* VIS I fcmpne16 */ |
3614 | 2382dc6b | blueswir1 | gen_op_load_fpr_DT0(DFPREG(rs1)); |
3615 | 2382dc6b | blueswir1 | gen_op_load_fpr_DT1(DFPREG(rs2)); |
3616 | 44e7757c | blueswir1 | tcg_gen_helper_0_0(helper_fcmpne16); |
3617 | 2382dc6b | blueswir1 | gen_op_store_DT0_fpr(DFPREG(rd)); |
3618 | 3299908c | blueswir1 | break;
|
3619 | e9ebed4d | blueswir1 | case 0x024: /* VIS I fcmple32 */ |
3620 | 2382dc6b | blueswir1 | gen_op_load_fpr_DT0(DFPREG(rs1)); |
3621 | 2382dc6b | blueswir1 | gen_op_load_fpr_DT1(DFPREG(rs2)); |
3622 | 44e7757c | blueswir1 | tcg_gen_helper_0_0(helper_fcmple32); |
3623 | 2382dc6b | blueswir1 | gen_op_store_DT0_fpr(DFPREG(rd)); |
3624 | e9ebed4d | blueswir1 | break;
|
3625 | e9ebed4d | blueswir1 | case 0x026: /* VIS I fcmpne32 */ |
3626 | 2382dc6b | blueswir1 | gen_op_load_fpr_DT0(DFPREG(rs1)); |
3627 | 2382dc6b | blueswir1 | gen_op_load_fpr_DT1(DFPREG(rs2)); |
3628 | 44e7757c | blueswir1 | tcg_gen_helper_0_0(helper_fcmpne32); |
3629 | 2382dc6b | blueswir1 | gen_op_store_DT0_fpr(DFPREG(rd)); |
3630 | e9ebed4d | blueswir1 | break;
|
3631 | e9ebed4d | blueswir1 | case 0x028: /* VIS I fcmpgt16 */ |
3632 | 2382dc6b | blueswir1 | gen_op_load_fpr_DT0(DFPREG(rs1)); |
3633 | 2382dc6b | blueswir1 | gen_op_load_fpr_DT1(DFPREG(rs2)); |
3634 | 44e7757c | blueswir1 | tcg_gen_helper_0_0(helper_fcmpgt16); |
3635 | 2382dc6b | blueswir1 | gen_op_store_DT0_fpr(DFPREG(rd)); |
3636 | e9ebed4d | blueswir1 | break;
|
3637 | e9ebed4d | blueswir1 | case 0x02a: /* VIS I fcmpeq16 */ |
3638 | 2382dc6b | blueswir1 | gen_op_load_fpr_DT0(DFPREG(rs1)); |
3639 | 2382dc6b | blueswir1 | gen_op_load_fpr_DT1(DFPREG(rs2)); |
3640 | 44e7757c | blueswir1 | tcg_gen_helper_0_0(helper_fcmpeq16); |
3641 | 2382dc6b | blueswir1 | gen_op_store_DT0_fpr(DFPREG(rd)); |
3642 | e9ebed4d | blueswir1 | break;
|
3643 | e9ebed4d | blueswir1 | case 0x02c: /* VIS I fcmpgt32 */ |
3644 | 2382dc6b | blueswir1 | gen_op_load_fpr_DT0(DFPREG(rs1)); |
3645 | 2382dc6b | blueswir1 | gen_op_load_fpr_DT1(DFPREG(rs2)); |
3646 | 44e7757c | blueswir1 | tcg_gen_helper_0_0(helper_fcmpgt32); |
3647 | 2382dc6b | blueswir1 | gen_op_store_DT0_fpr(DFPREG(rd)); |
3648 | e9ebed4d | blueswir1 | break;
|
3649 | e9ebed4d | blueswir1 | case 0x02e: /* VIS I fcmpeq32 */ |
3650 | 2382dc6b | blueswir1 | gen_op_load_fpr_DT0(DFPREG(rs1)); |
3651 | 2382dc6b | blueswir1 | gen_op_load_fpr_DT1(DFPREG(rs2)); |
3652 | 44e7757c | blueswir1 | tcg_gen_helper_0_0(helper_fcmpeq32); |
3653 | 2382dc6b | blueswir1 | gen_op_store_DT0_fpr(DFPREG(rd)); |
3654 | e9ebed4d | blueswir1 | break;
|
3655 | e9ebed4d | blueswir1 | case 0x031: /* VIS I fmul8x16 */ |
3656 | 2382dc6b | blueswir1 | gen_op_load_fpr_DT0(DFPREG(rs1)); |
3657 | 2382dc6b | blueswir1 | gen_op_load_fpr_DT1(DFPREG(rs2)); |
3658 | 44e7757c | blueswir1 | tcg_gen_helper_0_0(helper_fmul8x16); |
3659 | 2382dc6b | blueswir1 | gen_op_store_DT0_fpr(DFPREG(rd)); |
3660 | e9ebed4d | blueswir1 | break;
|
3661 | e9ebed4d | blueswir1 | case 0x033: /* VIS I fmul8x16au */ |
3662 | 2382dc6b | blueswir1 | gen_op_load_fpr_DT0(DFPREG(rs1)); |
3663 | 2382dc6b | blueswir1 | gen_op_load_fpr_DT1(DFPREG(rs2)); |
3664 | 44e7757c | blueswir1 | tcg_gen_helper_0_0(helper_fmul8x16au); |
3665 | 2382dc6b | blueswir1 | gen_op_store_DT0_fpr(DFPREG(rd)); |
3666 | e9ebed4d | blueswir1 | break;
|
3667 | e9ebed4d | blueswir1 | case 0x035: /* VIS I fmul8x16al */ |
3668 | 2382dc6b | blueswir1 | gen_op_load_fpr_DT0(DFPREG(rs1)); |
3669 | 2382dc6b | blueswir1 | gen_op_load_fpr_DT1(DFPREG(rs2)); |
3670 | 44e7757c | blueswir1 | tcg_gen_helper_0_0(helper_fmul8x16al); |
3671 | 2382dc6b | blueswir1 | gen_op_store_DT0_fpr(DFPREG(rd)); |
3672 | e9ebed4d | blueswir1 | break;
|
3673 | e9ebed4d | blueswir1 | case 0x036: /* VIS I fmul8sux16 */ |
3674 | 2382dc6b | blueswir1 | gen_op_load_fpr_DT0(DFPREG(rs1)); |
3675 | 2382dc6b | blueswir1 | gen_op_load_fpr_DT1(DFPREG(rs2)); |
3676 | 44e7757c | blueswir1 | tcg_gen_helper_0_0(helper_fmul8sux16); |
3677 | 2382dc6b | blueswir1 | gen_op_store_DT0_fpr(DFPREG(rd)); |
3678 | e9ebed4d | blueswir1 | break;
|
3679 | e9ebed4d | blueswir1 | case 0x037: /* VIS I fmul8ulx16 */ |
3680 | 2382dc6b | blueswir1 | gen_op_load_fpr_DT0(DFPREG(rs1)); |
3681 | 2382dc6b | blueswir1 | gen_op_load_fpr_DT1(DFPREG(rs2)); |
3682 | 44e7757c | blueswir1 | tcg_gen_helper_0_0(helper_fmul8ulx16); |
3683 | 2382dc6b | blueswir1 | gen_op_store_DT0_fpr(DFPREG(rd)); |
3684 | e9ebed4d | blueswir1 | break;
|
3685 | e9ebed4d | blueswir1 | case 0x038: /* VIS I fmuld8sux16 */ |
3686 | 2382dc6b | blueswir1 | gen_op_load_fpr_DT0(DFPREG(rs1)); |
3687 | 2382dc6b | blueswir1 | gen_op_load_fpr_DT1(DFPREG(rs2)); |
3688 | 44e7757c | blueswir1 | tcg_gen_helper_0_0(helper_fmuld8sux16); |
3689 | 2382dc6b | blueswir1 | gen_op_store_DT0_fpr(DFPREG(rd)); |
3690 | e9ebed4d | blueswir1 | break;
|
3691 | e9ebed4d | blueswir1 | case 0x039: /* VIS I fmuld8ulx16 */ |
3692 | 2382dc6b | blueswir1 | gen_op_load_fpr_DT0(DFPREG(rs1)); |
3693 | 2382dc6b | blueswir1 | gen_op_load_fpr_DT1(DFPREG(rs2)); |
3694 | 44e7757c | blueswir1 | tcg_gen_helper_0_0(helper_fmuld8ulx16); |
3695 | 2382dc6b | blueswir1 | gen_op_store_DT0_fpr(DFPREG(rd)); |
3696 | e9ebed4d | blueswir1 | break;
|
3697 | e9ebed4d | blueswir1 | case 0x03a: /* VIS I fpack32 */ |
3698 | e9ebed4d | blueswir1 | case 0x03b: /* VIS I fpack16 */ |
3699 | e9ebed4d | blueswir1 | case 0x03d: /* VIS I fpackfix */ |
3700 | e9ebed4d | blueswir1 | case 0x03e: /* VIS I pdist */ |
3701 | e9ebed4d | blueswir1 | // XXX
|
3702 | e9ebed4d | blueswir1 | goto illegal_insn;
|
3703 | 3299908c | blueswir1 | case 0x048: /* VIS I faligndata */ |
3704 | 2382dc6b | blueswir1 | gen_op_load_fpr_DT0(DFPREG(rs1)); |
3705 | 2382dc6b | blueswir1 | gen_op_load_fpr_DT1(DFPREG(rs2)); |
3706 | 44e7757c | blueswir1 | tcg_gen_helper_0_0(helper_faligndata); |
3707 | 2382dc6b | blueswir1 | gen_op_store_DT0_fpr(DFPREG(rd)); |
3708 | 3299908c | blueswir1 | break;
|
3709 | e9ebed4d | blueswir1 | case 0x04b: /* VIS I fpmerge */ |
3710 | 2382dc6b | blueswir1 | gen_op_load_fpr_DT0(DFPREG(rs1)); |
3711 | 2382dc6b | blueswir1 | gen_op_load_fpr_DT1(DFPREG(rs2)); |
3712 | 44e7757c | blueswir1 | tcg_gen_helper_0_0(helper_fpmerge); |
3713 | 2382dc6b | blueswir1 | gen_op_store_DT0_fpr(DFPREG(rd)); |
3714 | e9ebed4d | blueswir1 | break;
|
3715 | e9ebed4d | blueswir1 | case 0x04c: /* VIS II bshuffle */ |
3716 | e9ebed4d | blueswir1 | // XXX
|
3717 | e9ebed4d | blueswir1 | goto illegal_insn;
|
3718 | e9ebed4d | blueswir1 | case 0x04d: /* VIS I fexpand */ |
3719 | 2382dc6b | blueswir1 | gen_op_load_fpr_DT0(DFPREG(rs1)); |
3720 | 2382dc6b | blueswir1 | gen_op_load_fpr_DT1(DFPREG(rs2)); |
3721 | 44e7757c | blueswir1 | tcg_gen_helper_0_0(helper_fexpand); |
3722 | 2382dc6b | blueswir1 | gen_op_store_DT0_fpr(DFPREG(rd)); |
3723 | e9ebed4d | blueswir1 | break;
|
3724 | e9ebed4d | blueswir1 | case 0x050: /* VIS I fpadd16 */ |
3725 | 2382dc6b | blueswir1 | gen_op_load_fpr_DT0(DFPREG(rs1)); |
3726 | 2382dc6b | blueswir1 | gen_op_load_fpr_DT1(DFPREG(rs2)); |
3727 | 44e7757c | blueswir1 | tcg_gen_helper_0_0(helper_fpadd16); |
3728 | 2382dc6b | blueswir1 | gen_op_store_DT0_fpr(DFPREG(rd)); |
3729 | e9ebed4d | blueswir1 | break;
|
3730 | e9ebed4d | blueswir1 | case 0x051: /* VIS I fpadd16s */ |
3731 | e9ebed4d | blueswir1 | gen_op_load_fpr_FT0(rs1); |
3732 | e9ebed4d | blueswir1 | gen_op_load_fpr_FT1(rs2); |
3733 | 44e7757c | blueswir1 | tcg_gen_helper_0_0(helper_fpadd16s); |
3734 | e9ebed4d | blueswir1 | gen_op_store_FT0_fpr(rd); |
3735 | e9ebed4d | blueswir1 | break;
|
3736 | e9ebed4d | blueswir1 | case 0x052: /* VIS I fpadd32 */ |
3737 | 2382dc6b | blueswir1 | gen_op_load_fpr_DT0(DFPREG(rs1)); |
3738 | 2382dc6b | blueswir1 | gen_op_load_fpr_DT1(DFPREG(rs2)); |
3739 | 44e7757c | blueswir1 | tcg_gen_helper_0_0(helper_fpadd32); |
3740 | 2382dc6b | blueswir1 | gen_op_store_DT0_fpr(DFPREG(rd)); |
3741 | e9ebed4d | blueswir1 | break;
|
3742 | e9ebed4d | blueswir1 | case 0x053: /* VIS I fpadd32s */ |
3743 | e9ebed4d | blueswir1 | gen_op_load_fpr_FT0(rs1); |
3744 | e9ebed4d | blueswir1 | gen_op_load_fpr_FT1(rs2); |
3745 | 44e7757c | blueswir1 | tcg_gen_helper_0_0(helper_fpadd32s); |
3746 | e9ebed4d | blueswir1 | gen_op_store_FT0_fpr(rd); |
3747 | e9ebed4d | blueswir1 | break;
|
3748 | e9ebed4d | blueswir1 | case 0x054: /* VIS I fpsub16 */ |
3749 | 2382dc6b | blueswir1 | gen_op_load_fpr_DT0(DFPREG(rs1)); |
3750 | 2382dc6b | blueswir1 | gen_op_load_fpr_DT1(DFPREG(rs2)); |
3751 | 44e7757c | blueswir1 | tcg_gen_helper_0_0(helper_fpsub16); |
3752 | 2382dc6b | blueswir1 | gen_op_store_DT0_fpr(DFPREG(rd)); |
3753 | e9ebed4d | blueswir1 | break;
|
3754 | e9ebed4d | blueswir1 | case 0x055: /* VIS I fpsub16s */ |
3755 | e9ebed4d | blueswir1 | gen_op_load_fpr_FT0(rs1); |
3756 | e9ebed4d | blueswir1 | gen_op_load_fpr_FT1(rs2); |
3757 | 44e7757c | blueswir1 | tcg_gen_helper_0_0(helper_fpsub16s); |
3758 | e9ebed4d | blueswir1 | gen_op_store_FT0_fpr(rd); |
3759 | e9ebed4d | blueswir1 | break;
|
3760 | e9ebed4d | blueswir1 | case 0x056: /* VIS I fpsub32 */ |
3761 | 2382dc6b | blueswir1 | gen_op_load_fpr_DT0(DFPREG(rs1)); |
3762 | 2382dc6b | blueswir1 | gen_op_load_fpr_DT1(DFPREG(rs2)); |
3763 | 44e7757c | blueswir1 | tcg_gen_helper_0_0(helper_fpadd32); |
3764 | 2382dc6b | blueswir1 | gen_op_store_DT0_fpr(DFPREG(rd)); |
3765 | e9ebed4d | blueswir1 | break;
|
3766 | e9ebed4d | blueswir1 | case 0x057: /* VIS I fpsub32s */ |
3767 | e9ebed4d | blueswir1 | gen_op_load_fpr_FT0(rs1); |
3768 | e9ebed4d | blueswir1 | gen_op_load_fpr_FT1(rs2); |
3769 | 44e7757c | blueswir1 | tcg_gen_helper_0_0(helper_fpsub32s); |
3770 | e9ebed4d | blueswir1 | gen_op_store_FT0_fpr(rd); |
3771 | e9ebed4d | blueswir1 | break;
|
3772 | 3299908c | blueswir1 | case 0x060: /* VIS I fzero */ |
3773 | 44e7757c | blueswir1 | tcg_gen_helper_0_0(helper_movl_DT0_0); |
3774 | 2382dc6b | blueswir1 | gen_op_store_DT0_fpr(DFPREG(rd)); |
3775 | 3299908c | blueswir1 | break;
|
3776 | 3299908c | blueswir1 | case 0x061: /* VIS I fzeros */ |
3777 | 44e7757c | blueswir1 | tcg_gen_helper_0_0(helper_movl_FT0_0); |
3778 | 3299908c | blueswir1 | gen_op_store_FT0_fpr(rd); |
3779 | 3299908c | blueswir1 | break;
|
3780 | e9ebed4d | blueswir1 | case 0x062: /* VIS I fnor */ |
3781 | 2382dc6b | blueswir1 | gen_op_load_fpr_DT0(DFPREG(rs1)); |
3782 | 2382dc6b | blueswir1 | gen_op_load_fpr_DT1(DFPREG(rs2)); |
3783 | 44e7757c | blueswir1 | tcg_gen_helper_0_0(helper_fnor); |
3784 | 2382dc6b | blueswir1 | gen_op_store_DT0_fpr(DFPREG(rd)); |
3785 | e9ebed4d | blueswir1 | break;
|
3786 | e9ebed4d | blueswir1 | case 0x063: /* VIS I fnors */ |
3787 | e9ebed4d | blueswir1 | gen_op_load_fpr_FT0(rs1); |
3788 | e9ebed4d | blueswir1 | gen_op_load_fpr_FT1(rs2); |
3789 | 44e7757c | blueswir1 | tcg_gen_helper_0_0(helper_fnors); |
3790 | e9ebed4d | blueswir1 | gen_op_store_FT0_fpr(rd); |
3791 | e9ebed4d | blueswir1 | break;
|
3792 | e9ebed4d | blueswir1 | case 0x064: /* VIS I fandnot2 */ |
3793 | 2382dc6b | blueswir1 | gen_op_load_fpr_DT1(DFPREG(rs1)); |
3794 | 2382dc6b | blueswir1 | gen_op_load_fpr_DT0(DFPREG(rs2)); |
3795 | 44e7757c | blueswir1 | tcg_gen_helper_0_0(helper_fandnot); |
3796 | 2382dc6b | blueswir1 | gen_op_store_DT0_fpr(DFPREG(rd)); |
3797 | e9ebed4d | blueswir1 | break;
|
3798 | e9ebed4d | blueswir1 | case 0x065: /* VIS I fandnot2s */ |
3799 | e9ebed4d | blueswir1 | gen_op_load_fpr_FT1(rs1); |
3800 | e9ebed4d | blueswir1 | gen_op_load_fpr_FT0(rs2); |
3801 | 44e7757c | blueswir1 | tcg_gen_helper_0_0(helper_fandnots); |
3802 | e9ebed4d | blueswir1 | gen_op_store_FT0_fpr(rd); |
3803 | e9ebed4d | blueswir1 | break;
|
3804 | e9ebed4d | blueswir1 | case 0x066: /* VIS I fnot2 */ |
3805 | 2382dc6b | blueswir1 | gen_op_load_fpr_DT1(DFPREG(rs2)); |
3806 | 44e7757c | blueswir1 | tcg_gen_helper_0_0(helper_fnot); |
3807 | 2382dc6b | blueswir1 | gen_op_store_DT0_fpr(DFPREG(rd)); |
3808 | e9ebed4d | blueswir1 | break;
|
3809 | e9ebed4d | blueswir1 | case 0x067: /* VIS I fnot2s */ |
3810 | e9ebed4d | blueswir1 | gen_op_load_fpr_FT1(rs2); |
3811 | 44e7757c | blueswir1 | tcg_gen_helper_0_0(helper_fnot); |
3812 | e9ebed4d | blueswir1 | gen_op_store_FT0_fpr(rd); |
3813 | e9ebed4d | blueswir1 | break;
|
3814 | e9ebed4d | blueswir1 | case 0x068: /* VIS I fandnot1 */ |
3815 | 2382dc6b | blueswir1 | gen_op_load_fpr_DT0(DFPREG(rs1)); |
3816 | 2382dc6b | blueswir1 | gen_op_load_fpr_DT1(DFPREG(rs2)); |
3817 | 44e7757c | blueswir1 | tcg_gen_helper_0_0(helper_fandnot); |
3818 | 2382dc6b | blueswir1 | gen_op_store_DT0_fpr(DFPREG(rd)); |
3819 | e9ebed4d | blueswir1 | break;
|
3820 | e9ebed4d | blueswir1 | case 0x069: /* VIS I fandnot1s */ |
3821 | e9ebed4d | blueswir1 | gen_op_load_fpr_FT0(rs1); |
3822 | e9ebed4d | blueswir1 | gen_op_load_fpr_FT1(rs2); |
3823 | 44e7757c | blueswir1 | tcg_gen_helper_0_0(helper_fandnots); |
3824 | e9ebed4d | blueswir1 | gen_op_store_FT0_fpr(rd); |
3825 | e9ebed4d | blueswir1 | break;
|
3826 | e9ebed4d | blueswir1 | case 0x06a: /* VIS I fnot1 */ |
3827 | 2382dc6b | blueswir1 | gen_op_load_fpr_DT1(DFPREG(rs1)); |
3828 | 44e7757c | blueswir1 | tcg_gen_helper_0_0(helper_fnot); |
3829 | 2382dc6b | blueswir1 | gen_op_store_DT0_fpr(DFPREG(rd)); |
3830 | e9ebed4d | blueswir1 | break;
|
3831 | e9ebed4d | blueswir1 | case 0x06b: /* VIS I fnot1s */ |
3832 | e9ebed4d | blueswir1 | gen_op_load_fpr_FT1(rs1); |
3833 | 44e7757c | blueswir1 | tcg_gen_helper_0_0(helper_fnot); |
3834 | e9ebed4d | blueswir1 | gen_op_store_FT0_fpr(rd); |
3835 | e9ebed4d | blueswir1 | break;
|
3836 | e9ebed4d | blueswir1 | case 0x06c: /* VIS I fxor */ |
3837 | 2382dc6b | blueswir1 | gen_op_load_fpr_DT0(DFPREG(rs1)); |
3838 | 2382dc6b | blueswir1 | gen_op_load_fpr_DT1(DFPREG(rs2)); |
3839 | 44e7757c | blueswir1 | tcg_gen_helper_0_0(helper_fxor); |
3840 | 2382dc6b | blueswir1 | gen_op_store_DT0_fpr(DFPREG(rd)); |
3841 | e9ebed4d | blueswir1 | break;
|
3842 | e9ebed4d | blueswir1 | case 0x06d: /* VIS I fxors */ |
3843 | e9ebed4d | blueswir1 | gen_op_load_fpr_FT0(rs1); |
3844 | e9ebed4d | blueswir1 | gen_op_load_fpr_FT1(rs2); |
3845 | 44e7757c | blueswir1 | tcg_gen_helper_0_0(helper_fxors); |
3846 | e9ebed4d | blueswir1 | gen_op_store_FT0_fpr(rd); |
3847 | e9ebed4d | blueswir1 | break;
|
3848 | e9ebed4d | blueswir1 | case 0x06e: /* VIS I fnand */ |
3849 | 2382dc6b | blueswir1 | gen_op_load_fpr_DT0(DFPREG(rs1)); |
3850 | 2382dc6b | blueswir1 | gen_op_load_fpr_DT1(DFPREG(rs2)); |
3851 | 44e7757c | blueswir1 | tcg_gen_helper_0_0(helper_fnand); |
3852 | 2382dc6b | blueswir1 | gen_op_store_DT0_fpr(DFPREG(rd)); |
3853 | e9ebed4d | blueswir1 | break;
|
3854 | e9ebed4d | blueswir1 | case 0x06f: /* VIS I fnands */ |
3855 | e9ebed4d | blueswir1 | gen_op_load_fpr_FT0(rs1); |
3856 | e9ebed4d | blueswir1 | gen_op_load_fpr_FT1(rs2); |
3857 | 44e7757c | blueswir1 | tcg_gen_helper_0_0(helper_fnands); |
3858 | e9ebed4d | blueswir1 | gen_op_store_FT0_fpr(rd); |
3859 | e9ebed4d | blueswir1 | break;
|
3860 | e9ebed4d | blueswir1 | case 0x070: /* VIS I fand */ |
3861 | 2382dc6b | blueswir1 | gen_op_load_fpr_DT0(DFPREG(rs1)); |
3862 | 2382dc6b | blueswir1 | gen_op_load_fpr_DT1(DFPREG(rs2)); |
3863 | 44e7757c | blueswir1 | tcg_gen_helper_0_0(helper_fand); |
3864 | 2382dc6b | blueswir1 | gen_op_store_DT0_fpr(DFPREG(rd)); |
3865 | e9ebed4d | blueswir1 | break;
|
3866 | e9ebed4d | blueswir1 | case 0x071: /* VIS I fands */ |
3867 | e9ebed4d | blueswir1 | gen_op_load_fpr_FT0(rs1); |
3868 | e9ebed4d | blueswir1 | gen_op_load_fpr_FT1(rs2); |
3869 | 44e7757c | blueswir1 | tcg_gen_helper_0_0(helper_fands); |
3870 | e9ebed4d | blueswir1 | gen_op_store_FT0_fpr(rd); |
3871 | e9ebed4d | blueswir1 | break;
|
3872 | e9ebed4d | blueswir1 | case 0x072: /* VIS I fxnor */ |
3873 | 2382dc6b | blueswir1 | gen_op_load_fpr_DT0(DFPREG(rs1)); |
3874 | 2382dc6b | blueswir1 | gen_op_load_fpr_DT1(DFPREG(rs2)); |
3875 | 44e7757c | blueswir1 | tcg_gen_helper_0_0(helper_fxnor); |
3876 | 2382dc6b | blueswir1 | gen_op_store_DT0_fpr(DFPREG(rd)); |
3877 | e9ebed4d | blueswir1 | break;
|
3878 | e9ebed4d | blueswir1 | case 0x073: /* VIS I fxnors */ |
3879 | e9ebed4d | blueswir1 | gen_op_load_fpr_FT0(rs1); |
3880 | e9ebed4d | blueswir1 | gen_op_load_fpr_FT1(rs2); |
3881 | 44e7757c | blueswir1 | tcg_gen_helper_0_0(helper_fxnors); |
3882 | e9ebed4d | blueswir1 | gen_op_store_FT0_fpr(rd); |
3883 | e9ebed4d | blueswir1 | break;
|
3884 | 3299908c | blueswir1 | case 0x074: /* VIS I fsrc1 */ |
3885 | 2382dc6b | blueswir1 | gen_op_load_fpr_DT0(DFPREG(rs1)); |
3886 | 2382dc6b | blueswir1 | gen_op_store_DT0_fpr(DFPREG(rd)); |
3887 | 3299908c | blueswir1 | break;
|
3888 | 3299908c | blueswir1 | case 0x075: /* VIS I fsrc1s */ |
3889 | 3299908c | blueswir1 | gen_op_load_fpr_FT0(rs1); |
3890 | 3299908c | blueswir1 | gen_op_store_FT0_fpr(rd); |
3891 | 3299908c | blueswir1 | break;
|
3892 | e9ebed4d | blueswir1 | case 0x076: /* VIS I fornot2 */ |
3893 | 2382dc6b | blueswir1 | gen_op_load_fpr_DT1(DFPREG(rs1)); |
3894 | 2382dc6b | blueswir1 | gen_op_load_fpr_DT0(DFPREG(rs2)); |
3895 | 44e7757c | blueswir1 | tcg_gen_helper_0_0(helper_fornot); |
3896 | 2382dc6b | blueswir1 | gen_op_store_DT0_fpr(DFPREG(rd)); |
3897 | e9ebed4d | blueswir1 | break;
|
3898 | e9ebed4d | blueswir1 | case 0x077: /* VIS I fornot2s */ |
3899 | e9ebed4d | blueswir1 | gen_op_load_fpr_FT1(rs1); |
3900 | e9ebed4d | blueswir1 | gen_op_load_fpr_FT0(rs2); |
3901 | 44e7757c | blueswir1 | tcg_gen_helper_0_0(helper_fornots); |
3902 | e9ebed4d | blueswir1 | gen_op_store_FT0_fpr(rd); |
3903 | e9ebed4d | blueswir1 | break;
|
3904 | 3299908c | blueswir1 | case 0x078: /* VIS I fsrc2 */ |
3905 | 2382dc6b | blueswir1 | gen_op_load_fpr_DT0(DFPREG(rs2)); |
3906 | 2382dc6b | blueswir1 | gen_op_store_DT0_fpr(DFPREG(rd)); |
3907 | 3299908c | blueswir1 | break;
|
3908 | 3299908c | blueswir1 | case 0x079: /* VIS I fsrc2s */ |
3909 | 3299908c | blueswir1 | gen_op_load_fpr_FT0(rs2); |
3910 | 3299908c | blueswir1 | gen_op_store_FT0_fpr(rd); |
3911 | 3299908c | blueswir1 | break;
|
3912 | e9ebed4d | blueswir1 | case 0x07a: /* VIS I fornot1 */ |
3913 | 2382dc6b | blueswir1 | gen_op_load_fpr_DT0(DFPREG(rs1)); |
3914 | 2382dc6b | blueswir1 | gen_op_load_fpr_DT1(DFPREG(rs2)); |
3915 | 44e7757c | blueswir1 | tcg_gen_helper_0_0(helper_fornot); |
3916 | 2382dc6b | blueswir1 | gen_op_store_DT0_fpr(DFPREG(rd)); |
3917 | e9ebed4d | blueswir1 | break;
|
3918 | e9ebed4d | blueswir1 | case 0x07b: /* VIS I fornot1s */ |
3919 | e9ebed4d | blueswir1 | gen_op_load_fpr_FT0(rs1); |
3920 | e9ebed4d | blueswir1 | gen_op_load_fpr_FT1(rs2); |
3921 | 44e7757c | blueswir1 | tcg_gen_helper_0_0(helper_fornots); |
3922 | e9ebed4d | blueswir1 | gen_op_store_FT0_fpr(rd); |
3923 | e9ebed4d | blueswir1 | break;
|
3924 | e9ebed4d | blueswir1 | case 0x07c: /* VIS I for */ |
3925 | 2382dc6b | blueswir1 | gen_op_load_fpr_DT0(DFPREG(rs1)); |
3926 | 2382dc6b | blueswir1 | gen_op_load_fpr_DT1(DFPREG(rs2)); |
3927 | 44e7757c | blueswir1 | tcg_gen_helper_0_0(helper_for); |
3928 | 2382dc6b | blueswir1 | gen_op_store_DT0_fpr(DFPREG(rd)); |
3929 | e9ebed4d | blueswir1 | break;
|
3930 | e9ebed4d | blueswir1 | case 0x07d: /* VIS I fors */ |
3931 | e9ebed4d | blueswir1 | gen_op_load_fpr_FT0(rs1); |
3932 | e9ebed4d | blueswir1 | gen_op_load_fpr_FT1(rs2); |
3933 | 44e7757c | blueswir1 | tcg_gen_helper_0_0(helper_fors); |
3934 | e9ebed4d | blueswir1 | gen_op_store_FT0_fpr(rd); |
3935 | e9ebed4d | blueswir1 | break;
|
3936 | 3299908c | blueswir1 | case 0x07e: /* VIS I fone */ |
3937 | 44e7757c | blueswir1 | tcg_gen_helper_0_0(helper_movl_DT0_1); |
3938 | 2382dc6b | blueswir1 | gen_op_store_DT0_fpr(DFPREG(rd)); |
3939 | 3299908c | blueswir1 | break;
|
3940 | 3299908c | blueswir1 | case 0x07f: /* VIS I fones */ |
3941 | 44e7757c | blueswir1 | tcg_gen_helper_0_0(helper_movl_FT0_1); |
3942 | 3299908c | blueswir1 | gen_op_store_FT0_fpr(rd); |
3943 | 3299908c | blueswir1 | break;
|
3944 | e9ebed4d | blueswir1 | case 0x080: /* VIS I shutdown */ |
3945 | e9ebed4d | blueswir1 | case 0x081: /* VIS II siam */ |
3946 | e9ebed4d | blueswir1 | // XXX
|
3947 | e9ebed4d | blueswir1 | goto illegal_insn;
|
3948 | 3299908c | blueswir1 | default:
|
3949 | 3299908c | blueswir1 | goto illegal_insn;
|
3950 | 3299908c | blueswir1 | } |
3951 | 3299908c | blueswir1 | #else
|
3952 | 0f8a249a | blueswir1 | goto ncp_insn;
|
3953 | 3299908c | blueswir1 | #endif
|
3954 | 3299908c | blueswir1 | } else if (xop == 0x37) { /* V8 CPop2, V9 impdep2 */ |
3955 | fcc72045 | blueswir1 | #ifdef TARGET_SPARC64
|
3956 | 0f8a249a | blueswir1 | goto illegal_insn;
|
3957 | fcc72045 | blueswir1 | #else
|
3958 | 0f8a249a | blueswir1 | goto ncp_insn;
|
3959 | fcc72045 | blueswir1 | #endif
|
3960 | 3475187d | bellard | #ifdef TARGET_SPARC64
|
3961 | 0f8a249a | blueswir1 | } else if (xop == 0x39) { /* V9 return */ |
3962 | 3475187d | bellard | rs1 = GET_FIELD(insn, 13, 17); |
3963 | 1ad21e69 | blueswir1 | save_state(dc); |
3964 | 0f8a249a | blueswir1 | gen_movl_reg_T0(rs1); |
3965 | 0f8a249a | blueswir1 | if (IS_IMM) { /* immediate */ |
3966 | 0f8a249a | blueswir1 | rs2 = GET_FIELDs(insn, 19, 31); |
3967 | 1a2fb1c0 | blueswir1 | tcg_gen_addi_tl(cpu_T[0], cpu_T[0], (int)rs2); |
3968 | 0f8a249a | blueswir1 | } else { /* register */ |
3969 | 3475187d | bellard | rs2 = GET_FIELD(insn, 27, 31); |
3970 | 3475187d | bellard | #if defined(OPTIM)
|
3971 | 0f8a249a | blueswir1 | if (rs2) {
|
3972 | 3475187d | bellard | #endif
|
3973 | 0f8a249a | blueswir1 | gen_movl_reg_T1(rs2); |
3974 | 0f8a249a | blueswir1 | gen_op_add_T1_T0(); |
3975 | 3475187d | bellard | #if defined(OPTIM)
|
3976 | 0f8a249a | blueswir1 | } |
3977 | 3475187d | bellard | #endif
|
3978 | 3475187d | bellard | } |
3979 | 72a9747b | blueswir1 | tcg_gen_helper_0_0(helper_restore); |
3980 | 0f8a249a | blueswir1 | gen_mov_pc_npc(dc); |
3981 | 6ea4a6c8 | blueswir1 | gen_op_check_align_T0_3(); |
3982 | 48d5c82b | blueswir1 | tcg_gen_mov_tl(cpu_npc, cpu_T[0]);
|
3983 | 0f8a249a | blueswir1 | dc->npc = DYNAMIC_PC; |
3984 | 0f8a249a | blueswir1 | goto jmp_insn;
|
3985 | 3475187d | bellard | #endif
|
3986 | 0f8a249a | blueswir1 | } else {
|
3987 | e80cfcfc | bellard | rs1 = GET_FIELD(insn, 13, 17); |
3988 | 0f8a249a | blueswir1 | gen_movl_reg_T0(rs1); |
3989 | 0f8a249a | blueswir1 | if (IS_IMM) { /* immediate */ |
3990 | 0f8a249a | blueswir1 | rs2 = GET_FIELDs(insn, 19, 31); |
3991 | 1a2fb1c0 | blueswir1 | tcg_gen_addi_tl(cpu_T[0], cpu_T[0], (int)rs2); |
3992 | 0f8a249a | blueswir1 | } else { /* register */ |
3993 | e80cfcfc | bellard | rs2 = GET_FIELD(insn, 27, 31); |
3994 | e80cfcfc | bellard | #if defined(OPTIM)
|
3995 | 0f8a249a | blueswir1 | if (rs2) {
|
3996 | e80cfcfc | bellard | #endif
|
3997 | 0f8a249a | blueswir1 | gen_movl_reg_T1(rs2); |
3998 | 0f8a249a | blueswir1 | gen_op_add_T1_T0(); |
3999 | e80cfcfc | bellard | #if defined(OPTIM)
|
4000 | 0f8a249a | blueswir1 | } |
4001 | e8af50a3 | bellard | #endif
|
4002 | cf495bcf | bellard | } |
4003 | 0f8a249a | blueswir1 | switch (xop) {
|
4004 | 0f8a249a | blueswir1 | case 0x38: /* jmpl */ |
4005 | 0f8a249a | blueswir1 | { |
4006 | 0f8a249a | blueswir1 | if (rd != 0) { |
4007 | 1a2fb1c0 | blueswir1 | tcg_gen_movi_tl(cpu_T[1], dc->pc);
|
4008 | 0f8a249a | blueswir1 | gen_movl_T1_reg(rd); |
4009 | 0f8a249a | blueswir1 | } |
4010 | 0bee699e | bellard | gen_mov_pc_npc(dc); |
4011 | 6ea4a6c8 | blueswir1 | gen_op_check_align_T0_3(); |
4012 | 48d5c82b | blueswir1 | tcg_gen_mov_tl(cpu_npc, cpu_T[0]);
|
4013 | 0f8a249a | blueswir1 | dc->npc = DYNAMIC_PC; |
4014 | 0f8a249a | blueswir1 | } |
4015 | 0f8a249a | blueswir1 | goto jmp_insn;
|
4016 | 3475187d | bellard | #if !defined(CONFIG_USER_ONLY) && !defined(TARGET_SPARC64)
|
4017 | 0f8a249a | blueswir1 | case 0x39: /* rett, V9 return */ |
4018 | 0f8a249a | blueswir1 | { |
4019 | 0f8a249a | blueswir1 | if (!supervisor(dc))
|
4020 | 0f8a249a | blueswir1 | goto priv_insn;
|
4021 | 0bee699e | bellard | gen_mov_pc_npc(dc); |
4022 | 6ea4a6c8 | blueswir1 | gen_op_check_align_T0_3(); |
4023 | 48d5c82b | blueswir1 | tcg_gen_mov_tl(cpu_npc, cpu_T[0]);
|
4024 | 0f8a249a | blueswir1 | dc->npc = DYNAMIC_PC; |
4025 | 1a2fb1c0 | blueswir1 | tcg_gen_helper_0_0(helper_rett); |
4026 | 0f8a249a | blueswir1 | } |
4027 | 0f8a249a | blueswir1 | goto jmp_insn;
|
4028 | 0f8a249a | blueswir1 | #endif
|
4029 | 0f8a249a | blueswir1 | case 0x3b: /* flush */ |
4030 | 1a2fb1c0 | blueswir1 | tcg_gen_helper_0_1(helper_flush, cpu_T[0]);
|
4031 | 0f8a249a | blueswir1 | break;
|
4032 | 0f8a249a | blueswir1 | case 0x3c: /* save */ |
4033 | 0f8a249a | blueswir1 | save_state(dc); |
4034 | 72a9747b | blueswir1 | tcg_gen_helper_0_0(helper_save); |
4035 | 0f8a249a | blueswir1 | gen_movl_T0_reg(rd); |
4036 | 0f8a249a | blueswir1 | break;
|
4037 | 0f8a249a | blueswir1 | case 0x3d: /* restore */ |
4038 | 0f8a249a | blueswir1 | save_state(dc); |
4039 | 72a9747b | blueswir1 | tcg_gen_helper_0_0(helper_restore); |
4040 | 0f8a249a | blueswir1 | gen_movl_T0_reg(rd); |
4041 | 0f8a249a | blueswir1 | break;
|
4042 | 3475187d | bellard | #if !defined(CONFIG_USER_ONLY) && defined(TARGET_SPARC64)
|
4043 | 0f8a249a | blueswir1 | case 0x3e: /* V9 done/retry */ |
4044 | 0f8a249a | blueswir1 | { |
4045 | 0f8a249a | blueswir1 | switch (rd) {
|
4046 | 0f8a249a | blueswir1 | case 0: |
4047 | 0f8a249a | blueswir1 | if (!supervisor(dc))
|
4048 | 0f8a249a | blueswir1 | goto priv_insn;
|
4049 | 0f8a249a | blueswir1 | dc->npc = DYNAMIC_PC; |
4050 | 0f8a249a | blueswir1 | dc->pc = DYNAMIC_PC; |
4051 | 1a2fb1c0 | blueswir1 | tcg_gen_helper_0_0(helper_done); |
4052 | 0f8a249a | blueswir1 | goto jmp_insn;
|
4053 | 0f8a249a | blueswir1 | case 1: |
4054 | 0f8a249a | blueswir1 | if (!supervisor(dc))
|
4055 | 0f8a249a | blueswir1 | goto priv_insn;
|
4056 | 0f8a249a | blueswir1 | dc->npc = DYNAMIC_PC; |
4057 | 0f8a249a | blueswir1 | dc->pc = DYNAMIC_PC; |
4058 | 1a2fb1c0 | blueswir1 | tcg_gen_helper_0_0(helper_retry); |
4059 | 0f8a249a | blueswir1 | goto jmp_insn;
|
4060 | 0f8a249a | blueswir1 | default:
|
4061 | 0f8a249a | blueswir1 | goto illegal_insn;
|
4062 | 0f8a249a | blueswir1 | } |
4063 | 0f8a249a | blueswir1 | } |
4064 | 0f8a249a | blueswir1 | break;
|
4065 | 0f8a249a | blueswir1 | #endif
|
4066 | 0f8a249a | blueswir1 | default:
|
4067 | 0f8a249a | blueswir1 | goto illegal_insn;
|
4068 | 0f8a249a | blueswir1 | } |
4069 | cf495bcf | bellard | } |
4070 | 0f8a249a | blueswir1 | break;
|
4071 | 0f8a249a | blueswir1 | } |
4072 | 0f8a249a | blueswir1 | break;
|
4073 | 0f8a249a | blueswir1 | case 3: /* load/store instructions */ |
4074 | 0f8a249a | blueswir1 | { |
4075 | 0f8a249a | blueswir1 | unsigned int xop = GET_FIELD(insn, 7, 12); |
4076 | 0f8a249a | blueswir1 | rs1 = GET_FIELD(insn, 13, 17); |
4077 | 2371aaa2 | blueswir1 | save_state(dc); |
4078 | 0f8a249a | blueswir1 | gen_movl_reg_T0(rs1); |
4079 | 81ad8ba2 | blueswir1 | if (xop == 0x3c || xop == 0x3e) |
4080 | 81ad8ba2 | blueswir1 | { |
4081 | 81ad8ba2 | blueswir1 | rs2 = GET_FIELD(insn, 27, 31); |
4082 | 81ad8ba2 | blueswir1 | gen_movl_reg_T1(rs2); |
4083 | 81ad8ba2 | blueswir1 | } |
4084 | 81ad8ba2 | blueswir1 | else if (IS_IMM) { /* immediate */ |
4085 | 0f8a249a | blueswir1 | rs2 = GET_FIELDs(insn, 19, 31); |
4086 | 1a2fb1c0 | blueswir1 | tcg_gen_addi_tl(cpu_T[0], cpu_T[0], (int)rs2); |
4087 | 0f8a249a | blueswir1 | } else { /* register */ |
4088 | 0f8a249a | blueswir1 | rs2 = GET_FIELD(insn, 27, 31); |
4089 | e80cfcfc | bellard | #if defined(OPTIM)
|
4090 | 0f8a249a | blueswir1 | if (rs2 != 0) { |
4091 | e80cfcfc | bellard | #endif
|
4092 | 0f8a249a | blueswir1 | gen_movl_reg_T1(rs2); |
4093 | 0f8a249a | blueswir1 | gen_op_add_T1_T0(); |
4094 | e80cfcfc | bellard | #if defined(OPTIM)
|
4095 | 0f8a249a | blueswir1 | } |
4096 | e80cfcfc | bellard | #endif
|
4097 | 0f8a249a | blueswir1 | } |
4098 | 2f2ecb83 | blueswir1 | if (xop < 4 || (xop > 7 && xop < 0x14 && xop != 0x0e) || |
4099 | 2f2ecb83 | blueswir1 | (xop > 0x17 && xop <= 0x1d ) || |
4100 | 2f2ecb83 | blueswir1 | (xop > 0x2c && xop <= 0x33) || xop == 0x1f || xop == 0x3d) { |
4101 | 0f8a249a | blueswir1 | switch (xop) {
|
4102 | 1a2fb1c0 | blueswir1 | case 0x0: /* load unsigned word */ |
4103 | 6ea4a6c8 | blueswir1 | gen_op_check_align_T0_3(); |
4104 | 1a2fb1c0 | blueswir1 | ABI32_MASK(cpu_T[0]);
|
4105 | 1a2fb1c0 | blueswir1 | tcg_gen_qemu_ld32u(cpu_T[1], cpu_T[0], dc->mem_idx); |
4106 | 0f8a249a | blueswir1 | break;
|
4107 | 0f8a249a | blueswir1 | case 0x1: /* load unsigned byte */ |
4108 | 1a2fb1c0 | blueswir1 | ABI32_MASK(cpu_T[0]);
|
4109 | 1a2fb1c0 | blueswir1 | tcg_gen_qemu_ld8u(cpu_T[1], cpu_T[0], dc->mem_idx); |
4110 | 0f8a249a | blueswir1 | break;
|
4111 | 0f8a249a | blueswir1 | case 0x2: /* load unsigned halfword */ |
4112 | 6ea4a6c8 | blueswir1 | gen_op_check_align_T0_1(); |
4113 | 1a2fb1c0 | blueswir1 | ABI32_MASK(cpu_T[0]);
|
4114 | 1a2fb1c0 | blueswir1 | tcg_gen_qemu_ld16u(cpu_T[1], cpu_T[0], dc->mem_idx); |
4115 | 0f8a249a | blueswir1 | break;
|
4116 | 0f8a249a | blueswir1 | case 0x3: /* load double word */ |
4117 | 0f8a249a | blueswir1 | if (rd & 1) |
4118 | d4218d99 | blueswir1 | goto illegal_insn;
|
4119 | 1a2fb1c0 | blueswir1 | else {
|
4120 | 1a2fb1c0 | blueswir1 | gen_op_check_align_T0_7(); |
4121 | 1a2fb1c0 | blueswir1 | ABI32_MASK(cpu_T[0]);
|
4122 | 8911f501 | blueswir1 | tcg_gen_qemu_ld64(cpu_tmp64, cpu_T[0], dc->mem_idx);
|
4123 | 8911f501 | blueswir1 | tcg_gen_trunc_i64_tl(cpu_T[0], cpu_tmp64);
|
4124 | 8911f501 | blueswir1 | tcg_gen_andi_tl(cpu_T[0], cpu_T[0], 0xffffffffULL); |
4125 | 1a2fb1c0 | blueswir1 | gen_movl_T0_reg(rd + 1);
|
4126 | 8911f501 | blueswir1 | tcg_gen_shri_i64(cpu_tmp64, cpu_tmp64, 32);
|
4127 | 8911f501 | blueswir1 | tcg_gen_trunc_i64_tl(cpu_T[1], cpu_tmp64);
|
4128 | 8911f501 | blueswir1 | tcg_gen_andi_tl(cpu_T[1], cpu_T[1], 0xffffffffULL); |
4129 | 1a2fb1c0 | blueswir1 | } |
4130 | 0f8a249a | blueswir1 | break;
|
4131 | 0f8a249a | blueswir1 | case 0x9: /* load signed byte */ |
4132 | 1a2fb1c0 | blueswir1 | ABI32_MASK(cpu_T[0]);
|
4133 | 1a2fb1c0 | blueswir1 | tcg_gen_qemu_ld8s(cpu_T[1], cpu_T[0], dc->mem_idx); |
4134 | 0f8a249a | blueswir1 | break;
|
4135 | 0f8a249a | blueswir1 | case 0xa: /* load signed halfword */ |
4136 | 6ea4a6c8 | blueswir1 | gen_op_check_align_T0_1(); |
4137 | 1a2fb1c0 | blueswir1 | ABI32_MASK(cpu_T[0]);
|
4138 | 1a2fb1c0 | blueswir1 | tcg_gen_qemu_ld16s(cpu_T[1], cpu_T[0], dc->mem_idx); |
4139 | 0f8a249a | blueswir1 | break;
|
4140 | 0f8a249a | blueswir1 | case 0xd: /* ldstub -- XXX: should be atomically */ |
4141 | 1a2fb1c0 | blueswir1 | ABI32_MASK(cpu_T[0]);
|
4142 | 1a2fb1c0 | blueswir1 | tcg_gen_qemu_ld8s(cpu_T[1], cpu_T[0], dc->mem_idx); |
4143 | 8911f501 | blueswir1 | tcg_gen_qemu_st8(tcg_const_tl(0xff), cpu_T[0], dc->mem_idx); |
4144 | 0f8a249a | blueswir1 | break;
|
4145 | 0f8a249a | blueswir1 | case 0x0f: /* swap register with memory. Also atomically */ |
4146 | 6ea4a6c8 | blueswir1 | gen_op_check_align_T0_3(); |
4147 | 0f8a249a | blueswir1 | gen_movl_reg_T1(rd); |
4148 | 1a2fb1c0 | blueswir1 | ABI32_MASK(cpu_T[0]);
|
4149 | 8911f501 | blueswir1 | tcg_gen_qemu_ld32u(cpu_tmp32, cpu_T[0], dc->mem_idx);
|
4150 | 1a2fb1c0 | blueswir1 | tcg_gen_qemu_st32(cpu_T[1], cpu_T[0], dc->mem_idx); |
4151 | 8911f501 | blueswir1 | tcg_gen_extu_i32_tl(cpu_T[1], cpu_tmp32);
|
4152 | 0f8a249a | blueswir1 | break;
|
4153 | 3475187d | bellard | #if !defined(CONFIG_USER_ONLY) || defined(TARGET_SPARC64)
|
4154 | 0f8a249a | blueswir1 | case 0x10: /* load word alternate */ |
4155 | 3475187d | bellard | #ifndef TARGET_SPARC64
|
4156 | 0f8a249a | blueswir1 | if (IS_IMM)
|
4157 | 0f8a249a | blueswir1 | goto illegal_insn;
|
4158 | 0f8a249a | blueswir1 | if (!supervisor(dc))
|
4159 | 0f8a249a | blueswir1 | goto priv_insn;
|
4160 | 6ea4a6c8 | blueswir1 | #endif
|
4161 | 8f577d3d | blueswir1 | gen_op_check_align_T0_3(); |
4162 | 81ad8ba2 | blueswir1 | gen_ld_asi(insn, 4, 0); |
4163 | 0f8a249a | blueswir1 | break;
|
4164 | 0f8a249a | blueswir1 | case 0x11: /* load unsigned byte alternate */ |
4165 | 3475187d | bellard | #ifndef TARGET_SPARC64
|
4166 | 0f8a249a | blueswir1 | if (IS_IMM)
|
4167 | 0f8a249a | blueswir1 | goto illegal_insn;
|
4168 | 0f8a249a | blueswir1 | if (!supervisor(dc))
|
4169 | 0f8a249a | blueswir1 | goto priv_insn;
|
4170 | 0f8a249a | blueswir1 | #endif
|
4171 | 81ad8ba2 | blueswir1 | gen_ld_asi(insn, 1, 0); |
4172 | 0f8a249a | blueswir1 | break;
|
4173 | 0f8a249a | blueswir1 | case 0x12: /* load unsigned halfword alternate */ |
4174 | 3475187d | bellard | #ifndef TARGET_SPARC64
|
4175 | 0f8a249a | blueswir1 | if (IS_IMM)
|
4176 | 0f8a249a | blueswir1 | goto illegal_insn;
|
4177 | 0f8a249a | blueswir1 | if (!supervisor(dc))
|
4178 | 0f8a249a | blueswir1 | goto priv_insn;
|
4179 | 6ea4a6c8 | blueswir1 | #endif
|
4180 | 8f577d3d | blueswir1 | gen_op_check_align_T0_1(); |
4181 | 81ad8ba2 | blueswir1 | gen_ld_asi(insn, 2, 0); |
4182 | 0f8a249a | blueswir1 | break;
|
4183 | 0f8a249a | blueswir1 | case 0x13: /* load double word alternate */ |
4184 | 3475187d | bellard | #ifndef TARGET_SPARC64
|
4185 | 0f8a249a | blueswir1 | if (IS_IMM)
|
4186 | 0f8a249a | blueswir1 | goto illegal_insn;
|
4187 | 0f8a249a | blueswir1 | if (!supervisor(dc))
|
4188 | 0f8a249a | blueswir1 | goto priv_insn;
|
4189 | 3475187d | bellard | #endif
|
4190 | 0f8a249a | blueswir1 | if (rd & 1) |
4191 | d4218d99 | blueswir1 | goto illegal_insn;
|
4192 | 6ea4a6c8 | blueswir1 | gen_op_check_align_T0_7(); |
4193 | 81ad8ba2 | blueswir1 | gen_ldda_asi(insn); |
4194 | 0f8a249a | blueswir1 | gen_movl_T0_reg(rd + 1);
|
4195 | 0f8a249a | blueswir1 | break;
|
4196 | 0f8a249a | blueswir1 | case 0x19: /* load signed byte alternate */ |
4197 | 3475187d | bellard | #ifndef TARGET_SPARC64
|
4198 | 0f8a249a | blueswir1 | if (IS_IMM)
|
4199 | 0f8a249a | blueswir1 | goto illegal_insn;
|
4200 | 0f8a249a | blueswir1 | if (!supervisor(dc))
|
4201 | 0f8a249a | blueswir1 | goto priv_insn;
|
4202 | 0f8a249a | blueswir1 | #endif
|
4203 | 81ad8ba2 | blueswir1 | gen_ld_asi(insn, 1, 1); |
4204 | 0f8a249a | blueswir1 | break;
|
4205 | 0f8a249a | blueswir1 | case 0x1a: /* load signed halfword alternate */ |
4206 | 3475187d | bellard | #ifndef TARGET_SPARC64
|
4207 | 0f8a249a | blueswir1 | if (IS_IMM)
|
4208 | 0f8a249a | blueswir1 | goto illegal_insn;
|
4209 | 0f8a249a | blueswir1 | if (!supervisor(dc))
|
4210 | 0f8a249a | blueswir1 | goto priv_insn;
|
4211 | 6ea4a6c8 | blueswir1 | #endif
|
4212 | 8f577d3d | blueswir1 | gen_op_check_align_T0_1(); |
4213 | 81ad8ba2 | blueswir1 | gen_ld_asi(insn, 2, 1); |
4214 | 0f8a249a | blueswir1 | break;
|
4215 | 0f8a249a | blueswir1 | case 0x1d: /* ldstuba -- XXX: should be atomically */ |
4216 | 3475187d | bellard | #ifndef TARGET_SPARC64
|
4217 | 0f8a249a | blueswir1 | if (IS_IMM)
|
4218 | 0f8a249a | blueswir1 | goto illegal_insn;
|
4219 | 0f8a249a | blueswir1 | if (!supervisor(dc))
|
4220 | 0f8a249a | blueswir1 | goto priv_insn;
|
4221 | 0f8a249a | blueswir1 | #endif
|
4222 | 81ad8ba2 | blueswir1 | gen_ldstub_asi(insn); |
4223 | 0f8a249a | blueswir1 | break;
|
4224 | 0f8a249a | blueswir1 | case 0x1f: /* swap reg with alt. memory. Also atomically */ |
4225 | 3475187d | bellard | #ifndef TARGET_SPARC64
|
4226 | 0f8a249a | blueswir1 | if (IS_IMM)
|
4227 | 0f8a249a | blueswir1 | goto illegal_insn;
|
4228 | 0f8a249a | blueswir1 | if (!supervisor(dc))
|
4229 | 0f8a249a | blueswir1 | goto priv_insn;
|
4230 | 6ea4a6c8 | blueswir1 | #endif
|
4231 | 8f577d3d | blueswir1 | gen_op_check_align_T0_3(); |
4232 | 81ad8ba2 | blueswir1 | gen_movl_reg_T1(rd); |
4233 | 81ad8ba2 | blueswir1 | gen_swap_asi(insn); |
4234 | 0f8a249a | blueswir1 | break;
|
4235 | 3475187d | bellard | |
4236 | 3475187d | bellard | #ifndef TARGET_SPARC64
|
4237 | 0f8a249a | blueswir1 | case 0x30: /* ldc */ |
4238 | 0f8a249a | blueswir1 | case 0x31: /* ldcsr */ |
4239 | 0f8a249a | blueswir1 | case 0x33: /* lddc */ |
4240 | 0f8a249a | blueswir1 | goto ncp_insn;
|
4241 | 3475187d | bellard | #endif
|
4242 | 3475187d | bellard | #endif
|
4243 | 3475187d | bellard | #ifdef TARGET_SPARC64
|
4244 | 0f8a249a | blueswir1 | case 0x08: /* V9 ldsw */ |
4245 | 6ea4a6c8 | blueswir1 | gen_op_check_align_T0_3(); |
4246 | 1a2fb1c0 | blueswir1 | ABI32_MASK(cpu_T[0]);
|
4247 | 1a2fb1c0 | blueswir1 | tcg_gen_qemu_ld32s(cpu_T[1], cpu_T[0], dc->mem_idx); |
4248 | 0f8a249a | blueswir1 | break;
|
4249 | 0f8a249a | blueswir1 | case 0x0b: /* V9 ldx */ |
4250 | 6ea4a6c8 | blueswir1 | gen_op_check_align_T0_7(); |
4251 | 1a2fb1c0 | blueswir1 | ABI32_MASK(cpu_T[0]);
|
4252 | 1a2fb1c0 | blueswir1 | tcg_gen_qemu_ld64(cpu_T[1], cpu_T[0], dc->mem_idx); |
4253 | 0f8a249a | blueswir1 | break;
|
4254 | 0f8a249a | blueswir1 | case 0x18: /* V9 ldswa */ |
4255 | 6ea4a6c8 | blueswir1 | gen_op_check_align_T0_3(); |
4256 | 81ad8ba2 | blueswir1 | gen_ld_asi(insn, 4, 1); |
4257 | 0f8a249a | blueswir1 | break;
|
4258 | 0f8a249a | blueswir1 | case 0x1b: /* V9 ldxa */ |
4259 | 6ea4a6c8 | blueswir1 | gen_op_check_align_T0_7(); |
4260 | 81ad8ba2 | blueswir1 | gen_ld_asi(insn, 8, 0); |
4261 | 0f8a249a | blueswir1 | break;
|
4262 | 0f8a249a | blueswir1 | case 0x2d: /* V9 prefetch, no effect */ |
4263 | 0f8a249a | blueswir1 | goto skip_move;
|
4264 | 0f8a249a | blueswir1 | case 0x30: /* V9 ldfa */ |
4265 | 6ea4a6c8 | blueswir1 | gen_op_check_align_T0_3(); |
4266 | 2382dc6b | blueswir1 | gen_ldf_asi(insn, 4, rd);
|
4267 | 81ad8ba2 | blueswir1 | goto skip_move;
|
4268 | 0f8a249a | blueswir1 | case 0x33: /* V9 lddfa */ |
4269 | 3391c818 | blueswir1 | gen_op_check_align_T0_3(); |
4270 | 2382dc6b | blueswir1 | gen_ldf_asi(insn, 8, DFPREG(rd));
|
4271 | 81ad8ba2 | blueswir1 | goto skip_move;
|
4272 | 0f8a249a | blueswir1 | case 0x3d: /* V9 prefetcha, no effect */ |
4273 | 0f8a249a | blueswir1 | goto skip_move;
|
4274 | 0f8a249a | blueswir1 | case 0x32: /* V9 ldqfa */ |
4275 | 1f587329 | blueswir1 | #if defined(CONFIG_USER_ONLY)
|
4276 | 1f587329 | blueswir1 | gen_op_check_align_T0_3(); |
4277 | 2382dc6b | blueswir1 | gen_ldf_asi(insn, 16, QFPREG(rd));
|
4278 | 1f587329 | blueswir1 | goto skip_move;
|
4279 | 1f587329 | blueswir1 | #else
|
4280 | 0f8a249a | blueswir1 | goto nfpu_insn;
|
4281 | 0f8a249a | blueswir1 | #endif
|
4282 | 1f587329 | blueswir1 | #endif
|
4283 | 0f8a249a | blueswir1 | default:
|
4284 | 0f8a249a | blueswir1 | goto illegal_insn;
|
4285 | 0f8a249a | blueswir1 | } |
4286 | 0f8a249a | blueswir1 | gen_movl_T1_reg(rd); |
4287 | 3475187d | bellard | #ifdef TARGET_SPARC64
|
4288 | 0f8a249a | blueswir1 | skip_move: ;
|
4289 | 3475187d | bellard | #endif
|
4290 | 0f8a249a | blueswir1 | } else if (xop >= 0x20 && xop < 0x24) { |
4291 | a80dde08 | bellard | if (gen_trap_ifnofpu(dc))
|
4292 | a80dde08 | bellard | goto jmp_insn;
|
4293 | 0f8a249a | blueswir1 | switch (xop) {
|
4294 | 0f8a249a | blueswir1 | case 0x20: /* load fpreg */ |
4295 | 6ea4a6c8 | blueswir1 | gen_op_check_align_T0_3(); |
4296 | ce8536e2 | blueswir1 | tcg_gen_qemu_ld32u(cpu_tmp32, cpu_T[0], dc->mem_idx);
|
4297 | ce8536e2 | blueswir1 | tcg_gen_st_i32(cpu_tmp32, cpu_env, |
4298 | ce8536e2 | blueswir1 | offsetof(CPUState, fpr[rd])); |
4299 | 0f8a249a | blueswir1 | break;
|
4300 | 0f8a249a | blueswir1 | case 0x21: /* load fsr */ |
4301 | 6ea4a6c8 | blueswir1 | gen_op_check_align_T0_3(); |
4302 | ce8536e2 | blueswir1 | tcg_gen_qemu_ld32u(cpu_tmp32, cpu_T[0], dc->mem_idx);
|
4303 | ce8536e2 | blueswir1 | tcg_gen_st_i32(cpu_tmp32, cpu_env, |
4304 | ce8536e2 | blueswir1 | offsetof(CPUState, ft0)); |
4305 | 7e8c2b6c | blueswir1 | tcg_gen_helper_0_0(helper_ldfsr); |
4306 | 0f8a249a | blueswir1 | break;
|
4307 | 0f8a249a | blueswir1 | case 0x22: /* load quad fpreg */ |
4308 | 1f587329 | blueswir1 | #if defined(CONFIG_USER_ONLY)
|
4309 | 1f587329 | blueswir1 | gen_op_check_align_T0_7(); |
4310 | 1f587329 | blueswir1 | gen_op_ldst(ldqf); |
4311 | 1f587329 | blueswir1 | gen_op_store_QT0_fpr(QFPREG(rd)); |
4312 | 1f587329 | blueswir1 | break;
|
4313 | 1f587329 | blueswir1 | #else
|
4314 | 0f8a249a | blueswir1 | goto nfpu_insn;
|
4315 | 1f587329 | blueswir1 | #endif
|
4316 | 0f8a249a | blueswir1 | case 0x23: /* load double fpreg */ |
4317 | 6ea4a6c8 | blueswir1 | gen_op_check_align_T0_7(); |
4318 | 0f8a249a | blueswir1 | gen_op_ldst(lddf); |
4319 | 0f8a249a | blueswir1 | gen_op_store_DT0_fpr(DFPREG(rd)); |
4320 | 0f8a249a | blueswir1 | break;
|
4321 | 0f8a249a | blueswir1 | default:
|
4322 | 0f8a249a | blueswir1 | goto illegal_insn;
|
4323 | 0f8a249a | blueswir1 | } |
4324 | 0f8a249a | blueswir1 | } else if (xop < 8 || (xop >= 0x14 && xop < 0x18) || \ |
4325 | 0f8a249a | blueswir1 | xop == 0xe || xop == 0x1e) { |
4326 | 0f8a249a | blueswir1 | gen_movl_reg_T1(rd); |
4327 | 0f8a249a | blueswir1 | switch (xop) {
|
4328 | 1a2fb1c0 | blueswir1 | case 0x4: /* store word */ |
4329 | 6ea4a6c8 | blueswir1 | gen_op_check_align_T0_3(); |
4330 | 1a2fb1c0 | blueswir1 | ABI32_MASK(cpu_T[0]);
|
4331 | 1a2fb1c0 | blueswir1 | tcg_gen_qemu_st32(cpu_T[1], cpu_T[0], dc->mem_idx); |
4332 | 0f8a249a | blueswir1 | break;
|
4333 | 1a2fb1c0 | blueswir1 | case 0x5: /* store byte */ |
4334 | 1a2fb1c0 | blueswir1 | ABI32_MASK(cpu_T[0]);
|
4335 | 1a2fb1c0 | blueswir1 | tcg_gen_qemu_st8(cpu_T[1], cpu_T[0], dc->mem_idx); |
4336 | 0f8a249a | blueswir1 | break;
|
4337 | 1a2fb1c0 | blueswir1 | case 0x6: /* store halfword */ |
4338 | 6ea4a6c8 | blueswir1 | gen_op_check_align_T0_1(); |
4339 | 1a2fb1c0 | blueswir1 | ABI32_MASK(cpu_T[0]);
|
4340 | 1a2fb1c0 | blueswir1 | tcg_gen_qemu_st16(cpu_T[1], cpu_T[0], dc->mem_idx); |
4341 | 0f8a249a | blueswir1 | break;
|
4342 | 1a2fb1c0 | blueswir1 | case 0x7: /* store double word */ |
4343 | 0f8a249a | blueswir1 | if (rd & 1) |
4344 | d4218d99 | blueswir1 | goto illegal_insn;
|
4345 | b25deda7 | blueswir1 | #ifndef __i386__
|
4346 | 1a2fb1c0 | blueswir1 | else {
|
4347 | 8911f501 | blueswir1 | TCGv r_low; |
4348 | 1a2fb1c0 | blueswir1 | |
4349 | 1a2fb1c0 | blueswir1 | gen_op_check_align_T0_7(); |
4350 | 1a2fb1c0 | blueswir1 | r_low = tcg_temp_new(TCG_TYPE_I32); |
4351 | 1a2fb1c0 | blueswir1 | gen_movl_reg_TN(rd + 1, r_low);
|
4352 | 8911f501 | blueswir1 | tcg_gen_helper_1_2(helper_pack64, cpu_tmp64, cpu_T[1],
|
4353 | 1a2fb1c0 | blueswir1 | r_low); |
4354 | 8911f501 | blueswir1 | tcg_gen_qemu_st64(cpu_tmp64, cpu_T[0], dc->mem_idx);
|
4355 | 1a2fb1c0 | blueswir1 | } |
4356 | b25deda7 | blueswir1 | #else /* __i386__ */ |
4357 | b25deda7 | blueswir1 | gen_op_check_align_T0_7(); |
4358 | b25deda7 | blueswir1 | flush_T2(dc); |
4359 | b25deda7 | blueswir1 | gen_movl_reg_T2(rd + 1);
|
4360 | b25deda7 | blueswir1 | gen_op_ldst(std); |
4361 | b25deda7 | blueswir1 | #endif /* __i386__ */ |
4362 | 0f8a249a | blueswir1 | break;
|
4363 | 3475187d | bellard | #if !defined(CONFIG_USER_ONLY) || defined(TARGET_SPARC64)
|
4364 | 1a2fb1c0 | blueswir1 | case 0x14: /* store word alternate */ |
4365 | 3475187d | bellard | #ifndef TARGET_SPARC64
|
4366 | 0f8a249a | blueswir1 | if (IS_IMM)
|
4367 | 0f8a249a | blueswir1 | goto illegal_insn;
|
4368 | 0f8a249a | blueswir1 | if (!supervisor(dc))
|
4369 | 0f8a249a | blueswir1 | goto priv_insn;
|
4370 | 3475187d | bellard | #endif
|
4371 | 6ea4a6c8 | blueswir1 | gen_op_check_align_T0_3(); |
4372 | 81ad8ba2 | blueswir1 | gen_st_asi(insn, 4);
|
4373 | d39c0b99 | bellard | break;
|
4374 | 1a2fb1c0 | blueswir1 | case 0x15: /* store byte alternate */ |
4375 | 3475187d | bellard | #ifndef TARGET_SPARC64
|
4376 | 0f8a249a | blueswir1 | if (IS_IMM)
|
4377 | 0f8a249a | blueswir1 | goto illegal_insn;
|
4378 | 0f8a249a | blueswir1 | if (!supervisor(dc))
|
4379 | 0f8a249a | blueswir1 | goto priv_insn;
|
4380 | 3475187d | bellard | #endif
|
4381 | 81ad8ba2 | blueswir1 | gen_st_asi(insn, 1);
|
4382 | d39c0b99 | bellard | break;
|
4383 | 1a2fb1c0 | blueswir1 | case 0x16: /* store halfword alternate */ |
4384 | 3475187d | bellard | #ifndef TARGET_SPARC64
|
4385 | 0f8a249a | blueswir1 | if (IS_IMM)
|
4386 | 0f8a249a | blueswir1 | goto illegal_insn;
|
4387 | 0f8a249a | blueswir1 | if (!supervisor(dc))
|
4388 | 0f8a249a | blueswir1 | goto priv_insn;
|
4389 | 3475187d | bellard | #endif
|
4390 | 6ea4a6c8 | blueswir1 | gen_op_check_align_T0_1(); |
4391 | 81ad8ba2 | blueswir1 | gen_st_asi(insn, 2);
|
4392 | d39c0b99 | bellard | break;
|
4393 | 1a2fb1c0 | blueswir1 | case 0x17: /* store double word alternate */ |
4394 | 3475187d | bellard | #ifndef TARGET_SPARC64
|
4395 | 0f8a249a | blueswir1 | if (IS_IMM)
|
4396 | 0f8a249a | blueswir1 | goto illegal_insn;
|
4397 | 0f8a249a | blueswir1 | if (!supervisor(dc))
|
4398 | 0f8a249a | blueswir1 | goto priv_insn;
|
4399 | 3475187d | bellard | #endif
|
4400 | 0f8a249a | blueswir1 | if (rd & 1) |
4401 | d4218d99 | blueswir1 | goto illegal_insn;
|
4402 | 1a2fb1c0 | blueswir1 | else {
|
4403 | 1a2fb1c0 | blueswir1 | gen_op_check_align_T0_7(); |
4404 | 0425bee5 | blueswir1 | gen_stda_asi(insn, rd); |
4405 | 1a2fb1c0 | blueswir1 | } |
4406 | d39c0b99 | bellard | break;
|
4407 | e80cfcfc | bellard | #endif
|
4408 | 3475187d | bellard | #ifdef TARGET_SPARC64
|
4409 | 0f8a249a | blueswir1 | case 0x0e: /* V9 stx */ |
4410 | 6ea4a6c8 | blueswir1 | gen_op_check_align_T0_7(); |
4411 | 1a2fb1c0 | blueswir1 | ABI32_MASK(cpu_T[0]);
|
4412 | 1a2fb1c0 | blueswir1 | tcg_gen_qemu_st64(cpu_T[1], cpu_T[0], dc->mem_idx); |
4413 | 0f8a249a | blueswir1 | break;
|
4414 | 0f8a249a | blueswir1 | case 0x1e: /* V9 stxa */ |
4415 | 6ea4a6c8 | blueswir1 | gen_op_check_align_T0_7(); |
4416 | 81ad8ba2 | blueswir1 | gen_st_asi(insn, 8);
|
4417 | 0f8a249a | blueswir1 | break;
|
4418 | 3475187d | bellard | #endif
|
4419 | 0f8a249a | blueswir1 | default:
|
4420 | 0f8a249a | blueswir1 | goto illegal_insn;
|
4421 | 0f8a249a | blueswir1 | } |
4422 | 0f8a249a | blueswir1 | } else if (xop > 0x23 && xop < 0x28) { |
4423 | a80dde08 | bellard | if (gen_trap_ifnofpu(dc))
|
4424 | a80dde08 | bellard | goto jmp_insn;
|
4425 | 0f8a249a | blueswir1 | switch (xop) {
|
4426 | ce8536e2 | blueswir1 | case 0x24: /* store fpreg */ |
4427 | 6ea4a6c8 | blueswir1 | gen_op_check_align_T0_3(); |
4428 | ce8536e2 | blueswir1 | tcg_gen_ld_i32(cpu_tmp32, cpu_env, |
4429 | ce8536e2 | blueswir1 | offsetof(CPUState, fpr[rd])); |
4430 | ce8536e2 | blueswir1 | tcg_gen_qemu_st32(cpu_tmp32, cpu_T[0], dc->mem_idx);
|
4431 | 0f8a249a | blueswir1 | break;
|
4432 | 0f8a249a | blueswir1 | case 0x25: /* stfsr, V9 stxfsr */ |
4433 | 6ea4a6c8 | blueswir1 | #ifdef CONFIG_USER_ONLY
|
4434 | 6ea4a6c8 | blueswir1 | gen_op_check_align_T0_3(); |
4435 | 6ea4a6c8 | blueswir1 | #endif
|
4436 | bb5529bb | blueswir1 | tcg_gen_helper_0_0(helper_stfsr); |
4437 | ce8536e2 | blueswir1 | tcg_gen_ld_i32(cpu_tmp32, cpu_env, |
4438 | ce8536e2 | blueswir1 | offsetof(CPUState, ft0)); |
4439 | ce8536e2 | blueswir1 | tcg_gen_qemu_st32(cpu_tmp32, cpu_T[0], dc->mem_idx);
|
4440 | 0f8a249a | blueswir1 | break;
|
4441 | 1f587329 | blueswir1 | case 0x26: |
4442 | 1f587329 | blueswir1 | #ifdef TARGET_SPARC64
|
4443 | 1f587329 | blueswir1 | #if defined(CONFIG_USER_ONLY)
|
4444 | 1f587329 | blueswir1 | /* V9 stqf, store quad fpreg */
|
4445 | 1f587329 | blueswir1 | gen_op_check_align_T0_7(); |
4446 | 1f587329 | blueswir1 | gen_op_load_fpr_QT0(QFPREG(rd)); |
4447 | 1f587329 | blueswir1 | gen_op_ldst(stqf); |
4448 | 1f587329 | blueswir1 | break;
|
4449 | 1f587329 | blueswir1 | #else
|
4450 | 1f587329 | blueswir1 | goto nfpu_insn;
|
4451 | 1f587329 | blueswir1 | #endif
|
4452 | 1f587329 | blueswir1 | #else /* !TARGET_SPARC64 */ |
4453 | 1f587329 | blueswir1 | /* stdfq, store floating point queue */
|
4454 | 1f587329 | blueswir1 | #if defined(CONFIG_USER_ONLY)
|
4455 | 1f587329 | blueswir1 | goto illegal_insn;
|
4456 | 1f587329 | blueswir1 | #else
|
4457 | 0f8a249a | blueswir1 | if (!supervisor(dc))
|
4458 | 0f8a249a | blueswir1 | goto priv_insn;
|
4459 | 0f8a249a | blueswir1 | if (gen_trap_ifnofpu(dc))
|
4460 | 0f8a249a | blueswir1 | goto jmp_insn;
|
4461 | 0f8a249a | blueswir1 | goto nfq_insn;
|
4462 | 0f8a249a | blueswir1 | #endif
|
4463 | 1f587329 | blueswir1 | #endif
|
4464 | 0f8a249a | blueswir1 | case 0x27: |
4465 | 6ea4a6c8 | blueswir1 | gen_op_check_align_T0_7(); |
4466 | 3475187d | bellard | gen_op_load_fpr_DT0(DFPREG(rd)); |
4467 | 0f8a249a | blueswir1 | gen_op_ldst(stdf); |
4468 | 0f8a249a | blueswir1 | break;
|
4469 | 0f8a249a | blueswir1 | default:
|
4470 | 0f8a249a | blueswir1 | goto illegal_insn;
|
4471 | 0f8a249a | blueswir1 | } |
4472 | 0f8a249a | blueswir1 | } else if (xop > 0x33 && xop < 0x3f) { |
4473 | 0f8a249a | blueswir1 | switch (xop) {
|
4474 | a4d17f19 | blueswir1 | #ifdef TARGET_SPARC64
|
4475 | 0f8a249a | blueswir1 | case 0x34: /* V9 stfa */ |
4476 | 6ea4a6c8 | blueswir1 | gen_op_check_align_T0_3(); |
4477 | 3391c818 | blueswir1 | gen_op_load_fpr_FT0(rd); |
4478 | 2382dc6b | blueswir1 | gen_stf_asi(insn, 4, rd);
|
4479 | 0f8a249a | blueswir1 | break;
|
4480 | 1f587329 | blueswir1 | case 0x36: /* V9 stqfa */ |
4481 | 1f587329 | blueswir1 | #if defined(CONFIG_USER_ONLY)
|
4482 | 1f587329 | blueswir1 | gen_op_check_align_T0_7(); |
4483 | 1f587329 | blueswir1 | gen_op_load_fpr_QT0(QFPREG(rd)); |
4484 | 2382dc6b | blueswir1 | gen_stf_asi(insn, 16, QFPREG(rd));
|
4485 | 1f587329 | blueswir1 | break;
|
4486 | 1f587329 | blueswir1 | #else
|
4487 | 1f587329 | blueswir1 | goto nfpu_insn;
|
4488 | 1f587329 | blueswir1 | #endif
|
4489 | 0f8a249a | blueswir1 | case 0x37: /* V9 stdfa */ |
4490 | 3391c818 | blueswir1 | gen_op_check_align_T0_3(); |
4491 | 3391c818 | blueswir1 | gen_op_load_fpr_DT0(DFPREG(rd)); |
4492 | 2382dc6b | blueswir1 | gen_stf_asi(insn, 8, DFPREG(rd));
|
4493 | 0f8a249a | blueswir1 | break;
|
4494 | 0f8a249a | blueswir1 | case 0x3c: /* V9 casa */ |
4495 | 6ea4a6c8 | blueswir1 | gen_op_check_align_T0_3(); |
4496 | 1a2fb1c0 | blueswir1 | gen_cas_asi(insn, rd); |
4497 | 81ad8ba2 | blueswir1 | gen_movl_T1_reg(rd); |
4498 | 0f8a249a | blueswir1 | break;
|
4499 | 0f8a249a | blueswir1 | case 0x3e: /* V9 casxa */ |
4500 | 6ea4a6c8 | blueswir1 | gen_op_check_align_T0_7(); |
4501 | 1a2fb1c0 | blueswir1 | gen_casx_asi(insn, rd); |
4502 | 81ad8ba2 | blueswir1 | gen_movl_T1_reg(rd); |
4503 | 0f8a249a | blueswir1 | break;
|
4504 | a4d17f19 | blueswir1 | #else
|
4505 | 0f8a249a | blueswir1 | case 0x34: /* stc */ |
4506 | 0f8a249a | blueswir1 | case 0x35: /* stcsr */ |
4507 | 0f8a249a | blueswir1 | case 0x36: /* stdcq */ |
4508 | 0f8a249a | blueswir1 | case 0x37: /* stdc */ |
4509 | 0f8a249a | blueswir1 | goto ncp_insn;
|
4510 | 0f8a249a | blueswir1 | #endif
|
4511 | 0f8a249a | blueswir1 | default:
|
4512 | 0f8a249a | blueswir1 | goto illegal_insn;
|
4513 | 0f8a249a | blueswir1 | } |
4514 | e8af50a3 | bellard | } |
4515 | 0f8a249a | blueswir1 | else
|
4516 | 0f8a249a | blueswir1 | goto illegal_insn;
|
4517 | 0f8a249a | blueswir1 | } |
4518 | 0f8a249a | blueswir1 | break;
|
4519 | cf495bcf | bellard | } |
4520 | cf495bcf | bellard | /* default case for non jump instructions */
|
4521 | 72cbca10 | bellard | if (dc->npc == DYNAMIC_PC) {
|
4522 | 0f8a249a | blueswir1 | dc->pc = DYNAMIC_PC; |
4523 | 0f8a249a | blueswir1 | gen_op_next_insn(); |
4524 | 72cbca10 | bellard | } else if (dc->npc == JUMP_PC) { |
4525 | 72cbca10 | bellard | /* we can do a static jump */
|
4526 | 19f329ad | blueswir1 | gen_branch2(dc, dc->jump_pc[0], dc->jump_pc[1], cpu_T[2]); |
4527 | 72cbca10 | bellard | dc->is_br = 1;
|
4528 | 72cbca10 | bellard | } else {
|
4529 | 0f8a249a | blueswir1 | dc->pc = dc->npc; |
4530 | 0f8a249a | blueswir1 | dc->npc = dc->npc + 4;
|
4531 | cf495bcf | bellard | } |
4532 | e80cfcfc | bellard | jmp_insn:
|
4533 | cf495bcf | bellard | return;
|
4534 | cf495bcf | bellard | illegal_insn:
|
4535 | 72cbca10 | bellard | save_state(dc); |
4536 | cf495bcf | bellard | gen_op_exception(TT_ILL_INSN); |
4537 | cf495bcf | bellard | dc->is_br = 1;
|
4538 | e8af50a3 | bellard | return;
|
4539 | e80cfcfc | bellard | #if !defined(CONFIG_USER_ONLY)
|
4540 | e8af50a3 | bellard | priv_insn:
|
4541 | e8af50a3 | bellard | save_state(dc); |
4542 | e8af50a3 | bellard | gen_op_exception(TT_PRIV_INSN); |
4543 | e8af50a3 | bellard | dc->is_br = 1;
|
4544 | e80cfcfc | bellard | return;
|
4545 | e80cfcfc | bellard | nfpu_insn:
|
4546 | e80cfcfc | bellard | save_state(dc); |
4547 | e80cfcfc | bellard | gen_op_fpexception_im(FSR_FTT_UNIMPFPOP); |
4548 | e80cfcfc | bellard | dc->is_br = 1;
|
4549 | fcc72045 | blueswir1 | return;
|
4550 | 1f587329 | blueswir1 | #ifndef TARGET_SPARC64
|
4551 | 9143e598 | blueswir1 | nfq_insn:
|
4552 | 9143e598 | blueswir1 | save_state(dc); |
4553 | 9143e598 | blueswir1 | gen_op_fpexception_im(FSR_FTT_SEQ_ERROR); |
4554 | 9143e598 | blueswir1 | dc->is_br = 1;
|
4555 | 9143e598 | blueswir1 | return;
|
4556 | 9143e598 | blueswir1 | #endif
|
4557 | 1f587329 | blueswir1 | #endif
|
4558 | fcc72045 | blueswir1 | #ifndef TARGET_SPARC64
|
4559 | fcc72045 | blueswir1 | ncp_insn:
|
4560 | fcc72045 | blueswir1 | save_state(dc); |
4561 | fcc72045 | blueswir1 | gen_op_exception(TT_NCP_INSN); |
4562 | fcc72045 | blueswir1 | dc->is_br = 1;
|
4563 | fcc72045 | blueswir1 | return;
|
4564 | fcc72045 | blueswir1 | #endif
|
4565 | 7a3f1944 | bellard | } |
4566 | 7a3f1944 | bellard | |
4567 | 1a2fb1c0 | blueswir1 | static void tcg_macro_func(TCGContext *s, int macro_id, const int *dead_args) |
4568 | 1a2fb1c0 | blueswir1 | { |
4569 | 1a2fb1c0 | blueswir1 | } |
4570 | 1a2fb1c0 | blueswir1 | |
4571 | cf495bcf | bellard | static inline int gen_intermediate_code_internal(TranslationBlock * tb, |
4572 | 0f8a249a | blueswir1 | int spc, CPUSPARCState *env)
|
4573 | 7a3f1944 | bellard | { |
4574 | 72cbca10 | bellard | target_ulong pc_start, last_pc; |
4575 | cf495bcf | bellard | uint16_t *gen_opc_end; |
4576 | cf495bcf | bellard | DisasContext dc1, *dc = &dc1; |
4577 | e8af50a3 | bellard | int j, lj = -1; |
4578 | cf495bcf | bellard | |
4579 | cf495bcf | bellard | memset(dc, 0, sizeof(DisasContext)); |
4580 | cf495bcf | bellard | dc->tb = tb; |
4581 | 72cbca10 | bellard | pc_start = tb->pc; |
4582 | cf495bcf | bellard | dc->pc = pc_start; |
4583 | e80cfcfc | bellard | last_pc = dc->pc; |
4584 | 72cbca10 | bellard | dc->npc = (target_ulong) tb->cs_base; |
4585 | 6f27aba6 | blueswir1 | dc->mem_idx = cpu_mmu_index(env); |
4586 | 6f27aba6 | blueswir1 | dc->fpu_enabled = cpu_fpu_enabled(env); |
4587 | cf495bcf | bellard | gen_opc_end = gen_opc_buf + OPC_MAX_SIZE; |
4588 | cf495bcf | bellard | |
4589 | 1a2fb1c0 | blueswir1 | cpu_tmp0 = tcg_temp_new(TCG_TYPE_TL); |
4590 | 8911f501 | blueswir1 | cpu_tmp32 = tcg_temp_new(TCG_TYPE_I32); |
4591 | 8911f501 | blueswir1 | cpu_tmp64 = tcg_temp_new(TCG_TYPE_I64); |
4592 | 1a2fb1c0 | blueswir1 | |
4593 | cf495bcf | bellard | do {
|
4594 | e8af50a3 | bellard | if (env->nb_breakpoints > 0) { |
4595 | e8af50a3 | bellard | for(j = 0; j < env->nb_breakpoints; j++) { |
4596 | e8af50a3 | bellard | if (env->breakpoints[j] == dc->pc) {
|
4597 | 0f8a249a | blueswir1 | if (dc->pc != pc_start)
|
4598 | 0f8a249a | blueswir1 | save_state(dc); |
4599 | 1a2fb1c0 | blueswir1 | tcg_gen_helper_0_0(helper_debug); |
4600 | 57fec1fe | bellard | tcg_gen_exit_tb(0);
|
4601 | 0f8a249a | blueswir1 | dc->is_br = 1;
|
4602 | e80cfcfc | bellard | goto exit_gen_loop;
|
4603 | e8af50a3 | bellard | } |
4604 | e8af50a3 | bellard | } |
4605 | e8af50a3 | bellard | } |
4606 | e8af50a3 | bellard | if (spc) {
|
4607 | e8af50a3 | bellard | if (loglevel > 0) |
4608 | e8af50a3 | bellard | fprintf(logfile, "Search PC...\n");
|
4609 | e8af50a3 | bellard | j = gen_opc_ptr - gen_opc_buf; |
4610 | e8af50a3 | bellard | if (lj < j) {
|
4611 | e8af50a3 | bellard | lj++; |
4612 | e8af50a3 | bellard | while (lj < j)
|
4613 | e8af50a3 | bellard | gen_opc_instr_start[lj++] = 0;
|
4614 | e8af50a3 | bellard | gen_opc_pc[lj] = dc->pc; |
4615 | e8af50a3 | bellard | gen_opc_npc[lj] = dc->npc; |
4616 | e8af50a3 | bellard | gen_opc_instr_start[lj] = 1;
|
4617 | e8af50a3 | bellard | } |
4618 | e8af50a3 | bellard | } |
4619 | 0f8a249a | blueswir1 | last_pc = dc->pc; |
4620 | 0f8a249a | blueswir1 | disas_sparc_insn(dc); |
4621 | 0f8a249a | blueswir1 | |
4622 | 0f8a249a | blueswir1 | if (dc->is_br)
|
4623 | 0f8a249a | blueswir1 | break;
|
4624 | 0f8a249a | blueswir1 | /* if the next PC is different, we abort now */
|
4625 | 0f8a249a | blueswir1 | if (dc->pc != (last_pc + 4)) |
4626 | 0f8a249a | blueswir1 | break;
|
4627 | d39c0b99 | bellard | /* if we reach a page boundary, we stop generation so that the
|
4628 | d39c0b99 | bellard | PC of a TT_TFAULT exception is always in the right page */
|
4629 | d39c0b99 | bellard | if ((dc->pc & (TARGET_PAGE_SIZE - 1)) == 0) |
4630 | d39c0b99 | bellard | break;
|
4631 | e80cfcfc | bellard | /* if single step mode, we generate only one instruction and
|
4632 | e80cfcfc | bellard | generate an exception */
|
4633 | e80cfcfc | bellard | if (env->singlestep_enabled) {
|
4634 | 3475187d | bellard | gen_jmp_im(dc->pc); |
4635 | 57fec1fe | bellard | tcg_gen_exit_tb(0);
|
4636 | e80cfcfc | bellard | break;
|
4637 | e80cfcfc | bellard | } |
4638 | cf495bcf | bellard | } while ((gen_opc_ptr < gen_opc_end) &&
|
4639 | 0f8a249a | blueswir1 | (dc->pc - pc_start) < (TARGET_PAGE_SIZE - 32));
|
4640 | e80cfcfc | bellard | |
4641 | e80cfcfc | bellard | exit_gen_loop:
|
4642 | 72cbca10 | bellard | if (!dc->is_br) {
|
4643 | 5fafdf24 | ths | if (dc->pc != DYNAMIC_PC &&
|
4644 | 72cbca10 | bellard | (dc->npc != DYNAMIC_PC && dc->npc != JUMP_PC)) { |
4645 | 72cbca10 | bellard | /* static PC and NPC: we can use direct chaining */
|
4646 | 46525e1f | blueswir1 | gen_branch(dc, dc->pc, dc->npc); |
4647 | 72cbca10 | bellard | } else {
|
4648 | 72cbca10 | bellard | if (dc->pc != DYNAMIC_PC)
|
4649 | 3475187d | bellard | gen_jmp_im(dc->pc); |
4650 | 72cbca10 | bellard | save_npc(dc); |
4651 | 57fec1fe | bellard | tcg_gen_exit_tb(0);
|
4652 | 72cbca10 | bellard | } |
4653 | 72cbca10 | bellard | } |
4654 | cf495bcf | bellard | *gen_opc_ptr = INDEX_op_end; |
4655 | e8af50a3 | bellard | if (spc) {
|
4656 | e8af50a3 | bellard | j = gen_opc_ptr - gen_opc_buf; |
4657 | e8af50a3 | bellard | lj++; |
4658 | e8af50a3 | bellard | while (lj <= j)
|
4659 | e8af50a3 | bellard | gen_opc_instr_start[lj++] = 0;
|
4660 | e8af50a3 | bellard | #if 0
|
4661 | e8af50a3 | bellard | if (loglevel > 0) {
|
4662 | e8af50a3 | bellard | page_dump(logfile);
|
4663 | e8af50a3 | bellard | }
|
4664 | e8af50a3 | bellard | #endif
|
4665 | c3278b7b | bellard | gen_opc_jump_pc[0] = dc->jump_pc[0]; |
4666 | c3278b7b | bellard | gen_opc_jump_pc[1] = dc->jump_pc[1]; |
4667 | e8af50a3 | bellard | } else {
|
4668 | e80cfcfc | bellard | tb->size = last_pc + 4 - pc_start;
|
4669 | e8af50a3 | bellard | } |
4670 | 7a3f1944 | bellard | #ifdef DEBUG_DISAS
|
4671 | e19e89a5 | bellard | if (loglevel & CPU_LOG_TB_IN_ASM) {
|
4672 | 0f8a249a | blueswir1 | fprintf(logfile, "--------------\n");
|
4673 | 0f8a249a | blueswir1 | fprintf(logfile, "IN: %s\n", lookup_symbol(pc_start));
|
4674 | 0f8a249a | blueswir1 | target_disas(logfile, pc_start, last_pc + 4 - pc_start, 0); |
4675 | 0f8a249a | blueswir1 | fprintf(logfile, "\n");
|
4676 | cf495bcf | bellard | } |
4677 | 7a3f1944 | bellard | #endif
|
4678 | cf495bcf | bellard | return 0; |
4679 | 7a3f1944 | bellard | } |
4680 | 7a3f1944 | bellard | |
4681 | cf495bcf | bellard | int gen_intermediate_code(CPUSPARCState * env, TranslationBlock * tb)
|
4682 | 7a3f1944 | bellard | { |
4683 | e8af50a3 | bellard | return gen_intermediate_code_internal(tb, 0, env); |
4684 | 7a3f1944 | bellard | } |
4685 | 7a3f1944 | bellard | |
4686 | cf495bcf | bellard | int gen_intermediate_code_pc(CPUSPARCState * env, TranslationBlock * tb)
|
4687 | 7a3f1944 | bellard | { |
4688 | e8af50a3 | bellard | return gen_intermediate_code_internal(tb, 1, env); |
4689 | 7a3f1944 | bellard | } |
4690 | 7a3f1944 | bellard | |
4691 | e80cfcfc | bellard | void cpu_reset(CPUSPARCState *env)
|
4692 | e80cfcfc | bellard | { |
4693 | bb05683b | bellard | tlb_flush(env, 1);
|
4694 | cf495bcf | bellard | env->cwp = 0;
|
4695 | cf495bcf | bellard | env->wim = 1;
|
4696 | cf495bcf | bellard | env->regwptr = env->regbase + (env->cwp * 16);
|
4697 | e8af50a3 | bellard | #if defined(CONFIG_USER_ONLY)
|
4698 | cf495bcf | bellard | env->user_mode_only = 1;
|
4699 | 5ef54116 | bellard | #ifdef TARGET_SPARC64
|
4700 | 6ef905f6 | blueswir1 | env->cleanwin = NWINDOWS - 2;
|
4701 | 6ef905f6 | blueswir1 | env->cansave = NWINDOWS - 2;
|
4702 | 6ef905f6 | blueswir1 | env->pstate = PS_RMO | PS_PEF | PS_IE; |
4703 | 6ef905f6 | blueswir1 | env->asi = 0x82; // Primary no-fault |
4704 | 5ef54116 | bellard | #endif
|
4705 | e8af50a3 | bellard | #else
|
4706 | 32af58f9 | blueswir1 | env->psret = 0;
|
4707 | e8af50a3 | bellard | env->psrs = 1;
|
4708 | 0bee699e | bellard | env->psrps = 1;
|
4709 | 3475187d | bellard | #ifdef TARGET_SPARC64
|
4710 | 83469015 | bellard | env->pstate = PS_PRIV; |
4711 | 6f27aba6 | blueswir1 | env->hpstate = HS_PRIV; |
4712 | 83469015 | bellard | env->pc = 0x1fff0000000ULL;
|
4713 | 375ee38b | blueswir1 | env->tsptr = &env->ts[env->tl]; |
4714 | 3475187d | bellard | #else
|
4715 | 40ce0a9a | blueswir1 | env->pc = 0;
|
4716 | 32af58f9 | blueswir1 | env->mmuregs[0] &= ~(MMU_E | MMU_NF);
|
4717 | 6d5f237a | blueswir1 | env->mmuregs[0] |= env->mmu_bm;
|
4718 | 3475187d | bellard | #endif
|
4719 | 83469015 | bellard | env->npc = env->pc + 4;
|
4720 | e8af50a3 | bellard | #endif
|
4721 | e80cfcfc | bellard | } |
4722 | e80cfcfc | bellard | |
4723 | aaed909a | bellard | CPUSPARCState *cpu_sparc_init(const char *cpu_model) |
4724 | e80cfcfc | bellard | { |
4725 | e80cfcfc | bellard | CPUSPARCState *env; |
4726 | aaed909a | bellard | const sparc_def_t *def;
|
4727 | 1a2fb1c0 | blueswir1 | static int inited; |
4728 | f5069b26 | blueswir1 | unsigned int i; |
4729 | f5069b26 | blueswir1 | static const char * const gregnames[8] = { |
4730 | f5069b26 | blueswir1 | NULL, // g0 not used |
4731 | f5069b26 | blueswir1 | "g1",
|
4732 | f5069b26 | blueswir1 | "g2",
|
4733 | f5069b26 | blueswir1 | "g3",
|
4734 | f5069b26 | blueswir1 | "g4",
|
4735 | f5069b26 | blueswir1 | "g5",
|
4736 | f5069b26 | blueswir1 | "g6",
|
4737 | f5069b26 | blueswir1 | "g7",
|
4738 | f5069b26 | blueswir1 | }; |
4739 | aaed909a | bellard | |
4740 | aaed909a | bellard | def = cpu_sparc_find_by_name(cpu_model); |
4741 | aaed909a | bellard | if (!def)
|
4742 | aaed909a | bellard | return NULL; |
4743 | e80cfcfc | bellard | |
4744 | c68ea704 | bellard | env = qemu_mallocz(sizeof(CPUSPARCState));
|
4745 | c68ea704 | bellard | if (!env)
|
4746 | 0f8a249a | blueswir1 | return NULL; |
4747 | c68ea704 | bellard | cpu_exec_init(env); |
4748 | 01ba9816 | ths | env->cpu_model_str = cpu_model; |
4749 | aaed909a | bellard | env->version = def->iu_version; |
4750 | aaed909a | bellard | env->fsr = def->fpu_version; |
4751 | aaed909a | bellard | #if !defined(TARGET_SPARC64)
|
4752 | aaed909a | bellard | env->mmu_bm = def->mmu_bm; |
4753 | 3deaeab7 | blueswir1 | env->mmu_ctpr_mask = def->mmu_ctpr_mask; |
4754 | 3deaeab7 | blueswir1 | env->mmu_cxr_mask = def->mmu_cxr_mask; |
4755 | 3deaeab7 | blueswir1 | env->mmu_sfsr_mask = def->mmu_sfsr_mask; |
4756 | 3deaeab7 | blueswir1 | env->mmu_trcr_mask = def->mmu_trcr_mask; |
4757 | aaed909a | bellard | env->mmuregs[0] |= def->mmu_version;
|
4758 | aaed909a | bellard | cpu_sparc_set_id(env, 0);
|
4759 | aaed909a | bellard | #endif
|
4760 | 1a2fb1c0 | blueswir1 | |
4761 | 1a2fb1c0 | blueswir1 | /* init various static tables */
|
4762 | 1a2fb1c0 | blueswir1 | if (!inited) {
|
4763 | 1a2fb1c0 | blueswir1 | inited = 1;
|
4764 | 1a2fb1c0 | blueswir1 | |
4765 | 1a2fb1c0 | blueswir1 | tcg_set_macro_func(&tcg_ctx, tcg_macro_func); |
4766 | 1a2fb1c0 | blueswir1 | cpu_env = tcg_global_reg_new(TCG_TYPE_PTR, TCG_AREG0, "env");
|
4767 | db4a4ea4 | blueswir1 | cpu_regwptr = tcg_global_mem_new(TCG_TYPE_PTR, TCG_AREG0, |
4768 | db4a4ea4 | blueswir1 | offsetof(CPUState, regwptr), |
4769 | db4a4ea4 | blueswir1 | "regwptr");
|
4770 | 1a2fb1c0 | blueswir1 | //#if TARGET_LONG_BITS > HOST_LONG_BITS
|
4771 | 1a2fb1c0 | blueswir1 | #ifdef TARGET_SPARC64
|
4772 | 1a2fb1c0 | blueswir1 | cpu_T[0] = tcg_global_mem_new(TCG_TYPE_TL,
|
4773 | 1a2fb1c0 | blueswir1 | TCG_AREG0, offsetof(CPUState, t0), "T0");
|
4774 | 1a2fb1c0 | blueswir1 | cpu_T[1] = tcg_global_mem_new(TCG_TYPE_TL,
|
4775 | 1a2fb1c0 | blueswir1 | TCG_AREG0, offsetof(CPUState, t1), "T1");
|
4776 | 1a2fb1c0 | blueswir1 | cpu_T[2] = tcg_global_mem_new(TCG_TYPE_TL,
|
4777 | 1a2fb1c0 | blueswir1 | TCG_AREG0, offsetof(CPUState, t2), "T2");
|
4778 | dc99a3f2 | blueswir1 | cpu_xcc = tcg_global_mem_new(TCG_TYPE_I32, |
4779 | dc99a3f2 | blueswir1 | TCG_AREG0, offsetof(CPUState, xcc), |
4780 | dc99a3f2 | blueswir1 | "xcc");
|
4781 | 1a2fb1c0 | blueswir1 | #else
|
4782 | 1a2fb1c0 | blueswir1 | cpu_T[0] = tcg_global_reg_new(TCG_TYPE_TL, TCG_AREG1, "T0"); |
4783 | 1a2fb1c0 | blueswir1 | cpu_T[1] = tcg_global_reg_new(TCG_TYPE_TL, TCG_AREG2, "T1"); |
4784 | 1a2fb1c0 | blueswir1 | cpu_T[2] = tcg_global_reg_new(TCG_TYPE_TL, TCG_AREG3, "T2"); |
4785 | 1a2fb1c0 | blueswir1 | #endif
|
4786 | dc99a3f2 | blueswir1 | cpu_cc_src = tcg_global_mem_new(TCG_TYPE_TL, |
4787 | dc99a3f2 | blueswir1 | TCG_AREG0, offsetof(CPUState, cc_src), |
4788 | dc99a3f2 | blueswir1 | "cc_src");
|
4789 | d9bdab86 | blueswir1 | cpu_cc_src2 = tcg_global_mem_new(TCG_TYPE_TL, TCG_AREG0, |
4790 | d9bdab86 | blueswir1 | offsetof(CPUState, cc_src2), |
4791 | d9bdab86 | blueswir1 | "cc_src2");
|
4792 | dc99a3f2 | blueswir1 | cpu_cc_dst = tcg_global_mem_new(TCG_TYPE_TL, |
4793 | dc99a3f2 | blueswir1 | TCG_AREG0, offsetof(CPUState, cc_dst), |
4794 | dc99a3f2 | blueswir1 | "cc_dst");
|
4795 | dc99a3f2 | blueswir1 | cpu_psr = tcg_global_mem_new(TCG_TYPE_I32, |
4796 | dc99a3f2 | blueswir1 | TCG_AREG0, offsetof(CPUState, psr), |
4797 | dc99a3f2 | blueswir1 | "psr");
|
4798 | 87e92502 | blueswir1 | cpu_fsr = tcg_global_mem_new(TCG_TYPE_TL, |
4799 | 87e92502 | blueswir1 | TCG_AREG0, offsetof(CPUState, fsr), |
4800 | 87e92502 | blueswir1 | "fsr");
|
4801 | 48d5c82b | blueswir1 | cpu_pc = tcg_global_mem_new(TCG_TYPE_TL, |
4802 | 48d5c82b | blueswir1 | TCG_AREG0, offsetof(CPUState, pc), |
4803 | 48d5c82b | blueswir1 | "pc");
|
4804 | 48d5c82b | blueswir1 | cpu_npc = tcg_global_mem_new(TCG_TYPE_TL, |
4805 | 48d5c82b | blueswir1 | TCG_AREG0, offsetof(CPUState, npc), |
4806 | 48d5c82b | blueswir1 | "npc");
|
4807 | f5069b26 | blueswir1 | for (i = 1; i < 8; i++) |
4808 | f5069b26 | blueswir1 | cpu_gregs[i] = tcg_global_mem_new(TCG_TYPE_TL, TCG_AREG0, |
4809 | f5069b26 | blueswir1 | offsetof(CPUState, gregs[i]), |
4810 | f5069b26 | blueswir1 | gregnames[i]); |
4811 | 1a2fb1c0 | blueswir1 | } |
4812 | 1a2fb1c0 | blueswir1 | |
4813 | aaed909a | bellard | cpu_reset(env); |
4814 | aaed909a | bellard | |
4815 | aaed909a | bellard | return env;
|
4816 | aaed909a | bellard | } |
4817 | aaed909a | bellard | |
4818 | aaed909a | bellard | void cpu_sparc_set_id(CPUSPARCState *env, unsigned int cpu) |
4819 | aaed909a | bellard | { |
4820 | aaed909a | bellard | #if !defined(TARGET_SPARC64)
|
4821 | aaed909a | bellard | env->mxccregs[7] = ((cpu + 8) & 0xf) << 24; |
4822 | aaed909a | bellard | #endif
|
4823 | 7a3f1944 | bellard | } |
4824 | 7a3f1944 | bellard | |
4825 | 62724a37 | blueswir1 | static const sparc_def_t sparc_defs[] = { |
4826 | 62724a37 | blueswir1 | #ifdef TARGET_SPARC64
|
4827 | 62724a37 | blueswir1 | { |
4828 | 7d77bf20 | blueswir1 | .name = "Fujitsu Sparc64",
|
4829 | 7d77bf20 | blueswir1 | .iu_version = ((0x04ULL << 48) | (0x02ULL << 32) | (0ULL << 24) |
4830 | 7d77bf20 | blueswir1 | | (MAXTL << 8) | (NWINDOWS - 1)), |
4831 | 7d77bf20 | blueswir1 | .fpu_version = 0x00000000,
|
4832 | 7d77bf20 | blueswir1 | .mmu_version = 0,
|
4833 | 7d77bf20 | blueswir1 | }, |
4834 | 7d77bf20 | blueswir1 | { |
4835 | 7d77bf20 | blueswir1 | .name = "Fujitsu Sparc64 III",
|
4836 | 7d77bf20 | blueswir1 | .iu_version = ((0x04ULL << 48) | (0x03ULL << 32) | (0ULL << 24) |
4837 | 7d77bf20 | blueswir1 | | (MAXTL << 8) | (NWINDOWS - 1)), |
4838 | 7d77bf20 | blueswir1 | .fpu_version = 0x00000000,
|
4839 | 7d77bf20 | blueswir1 | .mmu_version = 0,
|
4840 | 7d77bf20 | blueswir1 | }, |
4841 | 7d77bf20 | blueswir1 | { |
4842 | 7d77bf20 | blueswir1 | .name = "Fujitsu Sparc64 IV",
|
4843 | 7d77bf20 | blueswir1 | .iu_version = ((0x04ULL << 48) | (0x04ULL << 32) | (0ULL << 24) |
4844 | 7d77bf20 | blueswir1 | | (MAXTL << 8) | (NWINDOWS - 1)), |
4845 | 7d77bf20 | blueswir1 | .fpu_version = 0x00000000,
|
4846 | 7d77bf20 | blueswir1 | .mmu_version = 0,
|
4847 | 7d77bf20 | blueswir1 | }, |
4848 | 7d77bf20 | blueswir1 | { |
4849 | 7d77bf20 | blueswir1 | .name = "Fujitsu Sparc64 V",
|
4850 | 7d77bf20 | blueswir1 | .iu_version = ((0x04ULL << 48) | (0x05ULL << 32) | (0x51ULL << 24) |
4851 | 7d77bf20 | blueswir1 | | (MAXTL << 8) | (NWINDOWS - 1)), |
4852 | 7d77bf20 | blueswir1 | .fpu_version = 0x00000000,
|
4853 | 7d77bf20 | blueswir1 | .mmu_version = 0,
|
4854 | 7d77bf20 | blueswir1 | }, |
4855 | 7d77bf20 | blueswir1 | { |
4856 | 7d77bf20 | blueswir1 | .name = "TI UltraSparc I",
|
4857 | 7d77bf20 | blueswir1 | .iu_version = ((0x17ULL << 48) | (0x10ULL << 32) | (0x40ULL << 24) |
4858 | 7d77bf20 | blueswir1 | | (MAXTL << 8) | (NWINDOWS - 1)), |
4859 | 7d77bf20 | blueswir1 | .fpu_version = 0x00000000,
|
4860 | 7d77bf20 | blueswir1 | .mmu_version = 0,
|
4861 | 7d77bf20 | blueswir1 | }, |
4862 | 7d77bf20 | blueswir1 | { |
4863 | 62724a37 | blueswir1 | .name = "TI UltraSparc II",
|
4864 | 7d77bf20 | blueswir1 | .iu_version = ((0x17ULL << 48) | (0x11ULL << 32) | (0x20ULL << 24) |
4865 | 7d77bf20 | blueswir1 | | (MAXTL << 8) | (NWINDOWS - 1)), |
4866 | 7d77bf20 | blueswir1 | .fpu_version = 0x00000000,
|
4867 | 7d77bf20 | blueswir1 | .mmu_version = 0,
|
4868 | 7d77bf20 | blueswir1 | }, |
4869 | 7d77bf20 | blueswir1 | { |
4870 | 7d77bf20 | blueswir1 | .name = "TI UltraSparc IIi",
|
4871 | 7d77bf20 | blueswir1 | .iu_version = ((0x17ULL << 48) | (0x12ULL << 32) | (0x91ULL << 24) |
4872 | 7d77bf20 | blueswir1 | | (MAXTL << 8) | (NWINDOWS - 1)), |
4873 | 7d77bf20 | blueswir1 | .fpu_version = 0x00000000,
|
4874 | 7d77bf20 | blueswir1 | .mmu_version = 0,
|
4875 | 7d77bf20 | blueswir1 | }, |
4876 | 7d77bf20 | blueswir1 | { |
4877 | 7d77bf20 | blueswir1 | .name = "TI UltraSparc IIe",
|
4878 | 7d77bf20 | blueswir1 | .iu_version = ((0x17ULL << 48) | (0x13ULL << 32) | (0x14ULL << 24) |
4879 | 7d77bf20 | blueswir1 | | (MAXTL << 8) | (NWINDOWS - 1)), |
4880 | 7d77bf20 | blueswir1 | .fpu_version = 0x00000000,
|
4881 | 7d77bf20 | blueswir1 | .mmu_version = 0,
|
4882 | 7d77bf20 | blueswir1 | }, |
4883 | 7d77bf20 | blueswir1 | { |
4884 | 7d77bf20 | blueswir1 | .name = "Sun UltraSparc III",
|
4885 | 7d77bf20 | blueswir1 | .iu_version = ((0x3eULL << 48) | (0x14ULL << 32) | (0x34ULL << 24) |
4886 | 7d77bf20 | blueswir1 | | (MAXTL << 8) | (NWINDOWS - 1)), |
4887 | 7d77bf20 | blueswir1 | .fpu_version = 0x00000000,
|
4888 | 7d77bf20 | blueswir1 | .mmu_version = 0,
|
4889 | 7d77bf20 | blueswir1 | }, |
4890 | 7d77bf20 | blueswir1 | { |
4891 | 7d77bf20 | blueswir1 | .name = "Sun UltraSparc III Cu",
|
4892 | 7d77bf20 | blueswir1 | .iu_version = ((0x3eULL << 48) | (0x15ULL << 32) | (0x41ULL << 24) |
4893 | 7d77bf20 | blueswir1 | | (MAXTL << 8) | (NWINDOWS - 1)), |
4894 | 7d77bf20 | blueswir1 | .fpu_version = 0x00000000,
|
4895 | 7d77bf20 | blueswir1 | .mmu_version = 0,
|
4896 | 7d77bf20 | blueswir1 | }, |
4897 | 7d77bf20 | blueswir1 | { |
4898 | 7d77bf20 | blueswir1 | .name = "Sun UltraSparc IIIi",
|
4899 | 7d77bf20 | blueswir1 | .iu_version = ((0x3eULL << 48) | (0x16ULL << 32) | (0x34ULL << 24) |
4900 | 7d77bf20 | blueswir1 | | (MAXTL << 8) | (NWINDOWS - 1)), |
4901 | 7d77bf20 | blueswir1 | .fpu_version = 0x00000000,
|
4902 | 7d77bf20 | blueswir1 | .mmu_version = 0,
|
4903 | 7d77bf20 | blueswir1 | }, |
4904 | 7d77bf20 | blueswir1 | { |
4905 | 7d77bf20 | blueswir1 | .name = "Sun UltraSparc IV",
|
4906 | 7d77bf20 | blueswir1 | .iu_version = ((0x3eULL << 48) | (0x18ULL << 32) | (0x31ULL << 24) |
4907 | 7d77bf20 | blueswir1 | | (MAXTL << 8) | (NWINDOWS - 1)), |
4908 | 7d77bf20 | blueswir1 | .fpu_version = 0x00000000,
|
4909 | 7d77bf20 | blueswir1 | .mmu_version = 0,
|
4910 | 7d77bf20 | blueswir1 | }, |
4911 | 7d77bf20 | blueswir1 | { |
4912 | 7d77bf20 | blueswir1 | .name = "Sun UltraSparc IV+",
|
4913 | 7d77bf20 | blueswir1 | .iu_version = ((0x3eULL << 48) | (0x19ULL << 32) | (0x22ULL << 24) |
4914 | 7d77bf20 | blueswir1 | | (MAXTL << 8) | (NWINDOWS - 1)), |
4915 | 7d77bf20 | blueswir1 | .fpu_version = 0x00000000,
|
4916 | 7d77bf20 | blueswir1 | .mmu_version = 0,
|
4917 | 7d77bf20 | blueswir1 | }, |
4918 | 7d77bf20 | blueswir1 | { |
4919 | 7d77bf20 | blueswir1 | .name = "Sun UltraSparc IIIi+",
|
4920 | 7d77bf20 | blueswir1 | .iu_version = ((0x3eULL << 48) | (0x22ULL << 32) | (0ULL << 24) |
4921 | 7d77bf20 | blueswir1 | | (MAXTL << 8) | (NWINDOWS - 1)), |
4922 | 7d77bf20 | blueswir1 | .fpu_version = 0x00000000,
|
4923 | 7d77bf20 | blueswir1 | .mmu_version = 0,
|
4924 | 7d77bf20 | blueswir1 | }, |
4925 | 7d77bf20 | blueswir1 | { |
4926 | 7d77bf20 | blueswir1 | .name = "NEC UltraSparc I",
|
4927 | 7d77bf20 | blueswir1 | .iu_version = ((0x22ULL << 48) | (0x10ULL << 32) | (0x40ULL << 24) |
4928 | 62724a37 | blueswir1 | | (MAXTL << 8) | (NWINDOWS - 1)), |
4929 | 62724a37 | blueswir1 | .fpu_version = 0x00000000,
|
4930 | 62724a37 | blueswir1 | .mmu_version = 0,
|
4931 | 62724a37 | blueswir1 | }, |
4932 | 62724a37 | blueswir1 | #else
|
4933 | 62724a37 | blueswir1 | { |
4934 | 406f82e8 | blueswir1 | .name = "Fujitsu MB86900",
|
4935 | 406f82e8 | blueswir1 | .iu_version = 0x00 << 24, /* Impl 0, ver 0 */ |
4936 | 406f82e8 | blueswir1 | .fpu_version = 4 << 17, /* FPU version 4 (Meiko) */ |
4937 | 406f82e8 | blueswir1 | .mmu_version = 0x00 << 24, /* Impl 0, ver 0 */ |
4938 | 406f82e8 | blueswir1 | .mmu_bm = 0x00004000,
|
4939 | 3deaeab7 | blueswir1 | .mmu_ctpr_mask = 0x007ffff0,
|
4940 | 3deaeab7 | blueswir1 | .mmu_cxr_mask = 0x0000003f,
|
4941 | 3deaeab7 | blueswir1 | .mmu_sfsr_mask = 0xffffffff,
|
4942 | 3deaeab7 | blueswir1 | .mmu_trcr_mask = 0xffffffff,
|
4943 | 406f82e8 | blueswir1 | }, |
4944 | 406f82e8 | blueswir1 | { |
4945 | 62724a37 | blueswir1 | .name = "Fujitsu MB86904",
|
4946 | 62724a37 | blueswir1 | .iu_version = 0x04 << 24, /* Impl 0, ver 4 */ |
4947 | 62724a37 | blueswir1 | .fpu_version = 4 << 17, /* FPU version 4 (Meiko) */ |
4948 | 62724a37 | blueswir1 | .mmu_version = 0x04 << 24, /* Impl 0, ver 4 */ |
4949 | 6d5f237a | blueswir1 | .mmu_bm = 0x00004000,
|
4950 | 3deaeab7 | blueswir1 | .mmu_ctpr_mask = 0x00ffffc0,
|
4951 | 3deaeab7 | blueswir1 | .mmu_cxr_mask = 0x000000ff,
|
4952 | 3deaeab7 | blueswir1 | .mmu_sfsr_mask = 0x00016fff,
|
4953 | 3deaeab7 | blueswir1 | .mmu_trcr_mask = 0x00ffffff,
|
4954 | 62724a37 | blueswir1 | }, |
4955 | e0353fe2 | blueswir1 | { |
4956 | 5ef62c5c | blueswir1 | .name = "Fujitsu MB86907",
|
4957 | 5ef62c5c | blueswir1 | .iu_version = 0x05 << 24, /* Impl 0, ver 5 */ |
4958 | 5ef62c5c | blueswir1 | .fpu_version = 4 << 17, /* FPU version 4 (Meiko) */ |
4959 | 5ef62c5c | blueswir1 | .mmu_version = 0x05 << 24, /* Impl 0, ver 5 */ |
4960 | 6d5f237a | blueswir1 | .mmu_bm = 0x00004000,
|
4961 | 3deaeab7 | blueswir1 | .mmu_ctpr_mask = 0xffffffc0,
|
4962 | 3deaeab7 | blueswir1 | .mmu_cxr_mask = 0x000000ff,
|
4963 | 3deaeab7 | blueswir1 | .mmu_sfsr_mask = 0x00016fff,
|
4964 | 3deaeab7 | blueswir1 | .mmu_trcr_mask = 0xffffffff,
|
4965 | 5ef62c5c | blueswir1 | }, |
4966 | 5ef62c5c | blueswir1 | { |
4967 | 406f82e8 | blueswir1 | .name = "LSI L64811",
|
4968 | 406f82e8 | blueswir1 | .iu_version = 0x10 << 24, /* Impl 1, ver 0 */ |
4969 | 406f82e8 | blueswir1 | .fpu_version = 1 << 17, /* FPU version 1 (LSI L64814) */ |
4970 | 406f82e8 | blueswir1 | .mmu_version = 0x10 << 24, |
4971 | 406f82e8 | blueswir1 | .mmu_bm = 0x00004000,
|
4972 | 3deaeab7 | blueswir1 | .mmu_ctpr_mask = 0x007ffff0,
|
4973 | 3deaeab7 | blueswir1 | .mmu_cxr_mask = 0x0000003f,
|
4974 | 3deaeab7 | blueswir1 | .mmu_sfsr_mask = 0xffffffff,
|
4975 | 3deaeab7 | blueswir1 | .mmu_trcr_mask = 0xffffffff,
|
4976 | 406f82e8 | blueswir1 | }, |
4977 | 406f82e8 | blueswir1 | { |
4978 | 406f82e8 | blueswir1 | .name = "Cypress CY7C601",
|
4979 | 406f82e8 | blueswir1 | .iu_version = 0x11 << 24, /* Impl 1, ver 1 */ |
4980 | 406f82e8 | blueswir1 | .fpu_version = 3 << 17, /* FPU version 3 (Cypress CY7C602) */ |
4981 | 406f82e8 | blueswir1 | .mmu_version = 0x10 << 24, |
4982 | 406f82e8 | blueswir1 | .mmu_bm = 0x00004000,
|
4983 | 3deaeab7 | blueswir1 | .mmu_ctpr_mask = 0x007ffff0,
|
4984 | 3deaeab7 | blueswir1 | .mmu_cxr_mask = 0x0000003f,
|
4985 | 3deaeab7 | blueswir1 | .mmu_sfsr_mask = 0xffffffff,
|
4986 | 3deaeab7 | blueswir1 | .mmu_trcr_mask = 0xffffffff,
|
4987 | 406f82e8 | blueswir1 | }, |
4988 | 406f82e8 | blueswir1 | { |
4989 | 406f82e8 | blueswir1 | .name = "Cypress CY7C611",
|
4990 | 406f82e8 | blueswir1 | .iu_version = 0x13 << 24, /* Impl 1, ver 3 */ |
4991 | 406f82e8 | blueswir1 | .fpu_version = 3 << 17, /* FPU version 3 (Cypress CY7C602) */ |
4992 | 406f82e8 | blueswir1 | .mmu_version = 0x10 << 24, |
4993 | 406f82e8 | blueswir1 | .mmu_bm = 0x00004000,
|
4994 | 3deaeab7 | blueswir1 | .mmu_ctpr_mask = 0x007ffff0,
|
4995 | 3deaeab7 | blueswir1 | .mmu_cxr_mask = 0x0000003f,
|
4996 | 3deaeab7 | blueswir1 | .mmu_sfsr_mask = 0xffffffff,
|
4997 | 3deaeab7 | blueswir1 | .mmu_trcr_mask = 0xffffffff,
|
4998 | 406f82e8 | blueswir1 | }, |
4999 | 406f82e8 | blueswir1 | { |
5000 | 406f82e8 | blueswir1 | .name = "TI SuperSparc II",
|
5001 | 406f82e8 | blueswir1 | .iu_version = 0x40000000,
|
5002 | 406f82e8 | blueswir1 | .fpu_version = 0 << 17, |
5003 | 406f82e8 | blueswir1 | .mmu_version = 0x04000000,
|
5004 | 406f82e8 | blueswir1 | .mmu_bm = 0x00002000,
|
5005 | 3deaeab7 | blueswir1 | .mmu_ctpr_mask = 0xffffffc0,
|
5006 | 3deaeab7 | blueswir1 | .mmu_cxr_mask = 0x0000ffff,
|
5007 | 3deaeab7 | blueswir1 | .mmu_sfsr_mask = 0xffffffff,
|
5008 | 3deaeab7 | blueswir1 | .mmu_trcr_mask = 0xffffffff,
|
5009 | 406f82e8 | blueswir1 | }, |
5010 | 406f82e8 | blueswir1 | { |
5011 | 5ef62c5c | blueswir1 | .name = "TI MicroSparc I",
|
5012 | 5ef62c5c | blueswir1 | .iu_version = 0x41000000,
|
5013 | 5ef62c5c | blueswir1 | .fpu_version = 4 << 17, |
5014 | 5ef62c5c | blueswir1 | .mmu_version = 0x41000000,
|
5015 | 6d5f237a | blueswir1 | .mmu_bm = 0x00004000,
|
5016 | 3deaeab7 | blueswir1 | .mmu_ctpr_mask = 0x007ffff0,
|
5017 | 3deaeab7 | blueswir1 | .mmu_cxr_mask = 0x0000003f,
|
5018 | 3deaeab7 | blueswir1 | .mmu_sfsr_mask = 0x00016fff,
|
5019 | 3deaeab7 | blueswir1 | .mmu_trcr_mask = 0x0000003f,
|
5020 | 5ef62c5c | blueswir1 | }, |
5021 | 5ef62c5c | blueswir1 | { |
5022 | 406f82e8 | blueswir1 | .name = "TI MicroSparc II",
|
5023 | 406f82e8 | blueswir1 | .iu_version = 0x42000000,
|
5024 | 406f82e8 | blueswir1 | .fpu_version = 4 << 17, |
5025 | 406f82e8 | blueswir1 | .mmu_version = 0x02000000,
|
5026 | 406f82e8 | blueswir1 | .mmu_bm = 0x00004000,
|
5027 | 3deaeab7 | blueswir1 | .mmu_ctpr_mask = 0x00ffffc0,
|
5028 | 3deaeab7 | blueswir1 | .mmu_cxr_mask = 0x000000ff,
|
5029 | a3ffaf30 | blueswir1 | .mmu_sfsr_mask = 0x00016fff,
|
5030 | 3deaeab7 | blueswir1 | .mmu_trcr_mask = 0x00ffffff,
|
5031 | 406f82e8 | blueswir1 | }, |
5032 | 406f82e8 | blueswir1 | { |
5033 | 406f82e8 | blueswir1 | .name = "TI MicroSparc IIep",
|
5034 | 406f82e8 | blueswir1 | .iu_version = 0x42000000,
|
5035 | 406f82e8 | blueswir1 | .fpu_version = 4 << 17, |
5036 | 406f82e8 | blueswir1 | .mmu_version = 0x04000000,
|
5037 | 406f82e8 | blueswir1 | .mmu_bm = 0x00004000,
|
5038 | 3deaeab7 | blueswir1 | .mmu_ctpr_mask = 0x00ffffc0,
|
5039 | 3deaeab7 | blueswir1 | .mmu_cxr_mask = 0x000000ff,
|
5040 | 3deaeab7 | blueswir1 | .mmu_sfsr_mask = 0x00016bff,
|
5041 | 3deaeab7 | blueswir1 | .mmu_trcr_mask = 0x00ffffff,
|
5042 | 406f82e8 | blueswir1 | }, |
5043 | 406f82e8 | blueswir1 | { |
5044 | 406f82e8 | blueswir1 | .name = "TI SuperSparc 51",
|
5045 | 406f82e8 | blueswir1 | .iu_version = 0x43000000,
|
5046 | 5ef62c5c | blueswir1 | .fpu_version = 0 << 17, |
5047 | 5ef62c5c | blueswir1 | .mmu_version = 0x04000000,
|
5048 | 6d5f237a | blueswir1 | .mmu_bm = 0x00002000,
|
5049 | 3deaeab7 | blueswir1 | .mmu_ctpr_mask = 0xffffffc0,
|
5050 | 3deaeab7 | blueswir1 | .mmu_cxr_mask = 0x0000ffff,
|
5051 | 3deaeab7 | blueswir1 | .mmu_sfsr_mask = 0xffffffff,
|
5052 | 3deaeab7 | blueswir1 | .mmu_trcr_mask = 0xffffffff,
|
5053 | 5ef62c5c | blueswir1 | }, |
5054 | 5ef62c5c | blueswir1 | { |
5055 | 406f82e8 | blueswir1 | .name = "TI SuperSparc 61",
|
5056 | 406f82e8 | blueswir1 | .iu_version = 0x44000000,
|
5057 | 406f82e8 | blueswir1 | .fpu_version = 0 << 17, |
5058 | 406f82e8 | blueswir1 | .mmu_version = 0x04000000,
|
5059 | 406f82e8 | blueswir1 | .mmu_bm = 0x00002000,
|
5060 | 3deaeab7 | blueswir1 | .mmu_ctpr_mask = 0xffffffc0,
|
5061 | 3deaeab7 | blueswir1 | .mmu_cxr_mask = 0x0000ffff,
|
5062 | 3deaeab7 | blueswir1 | .mmu_sfsr_mask = 0xffffffff,
|
5063 | 3deaeab7 | blueswir1 | .mmu_trcr_mask = 0xffffffff,
|
5064 | 406f82e8 | blueswir1 | }, |
5065 | 406f82e8 | blueswir1 | { |
5066 | 406f82e8 | blueswir1 | .name = "Ross RT625",
|
5067 | 5ef62c5c | blueswir1 | .iu_version = 0x1e000000,
|
5068 | 5ef62c5c | blueswir1 | .fpu_version = 1 << 17, |
5069 | 406f82e8 | blueswir1 | .mmu_version = 0x1e000000,
|
5070 | 406f82e8 | blueswir1 | .mmu_bm = 0x00004000,
|
5071 | 3deaeab7 | blueswir1 | .mmu_ctpr_mask = 0x007ffff0,
|
5072 | 3deaeab7 | blueswir1 | .mmu_cxr_mask = 0x0000003f,
|
5073 | 3deaeab7 | blueswir1 | .mmu_sfsr_mask = 0xffffffff,
|
5074 | 3deaeab7 | blueswir1 | .mmu_trcr_mask = 0xffffffff,
|
5075 | 406f82e8 | blueswir1 | }, |
5076 | 406f82e8 | blueswir1 | { |
5077 | 406f82e8 | blueswir1 | .name = "Ross RT620",
|
5078 | 406f82e8 | blueswir1 | .iu_version = 0x1f000000,
|
5079 | 406f82e8 | blueswir1 | .fpu_version = 1 << 17, |
5080 | 406f82e8 | blueswir1 | .mmu_version = 0x1f000000,
|
5081 | 406f82e8 | blueswir1 | .mmu_bm = 0x00004000,
|
5082 | 3deaeab7 | blueswir1 | .mmu_ctpr_mask = 0x007ffff0,
|
5083 | 3deaeab7 | blueswir1 | .mmu_cxr_mask = 0x0000003f,
|
5084 | 3deaeab7 | blueswir1 | .mmu_sfsr_mask = 0xffffffff,
|
5085 | 3deaeab7 | blueswir1 | .mmu_trcr_mask = 0xffffffff,
|
5086 | 406f82e8 | blueswir1 | }, |
5087 | 406f82e8 | blueswir1 | { |
5088 | 406f82e8 | blueswir1 | .name = "BIT B5010",
|
5089 | 406f82e8 | blueswir1 | .iu_version = 0x20000000,
|
5090 | 406f82e8 | blueswir1 | .fpu_version = 0 << 17, /* B5010/B5110/B5120/B5210 */ |
5091 | 406f82e8 | blueswir1 | .mmu_version = 0x20000000,
|
5092 | 406f82e8 | blueswir1 | .mmu_bm = 0x00004000,
|
5093 | 3deaeab7 | blueswir1 | .mmu_ctpr_mask = 0x007ffff0,
|
5094 | 3deaeab7 | blueswir1 | .mmu_cxr_mask = 0x0000003f,
|
5095 | 3deaeab7 | blueswir1 | .mmu_sfsr_mask = 0xffffffff,
|
5096 | 3deaeab7 | blueswir1 | .mmu_trcr_mask = 0xffffffff,
|
5097 | 406f82e8 | blueswir1 | }, |
5098 | 406f82e8 | blueswir1 | { |
5099 | 406f82e8 | blueswir1 | .name = "Matsushita MN10501",
|
5100 | 406f82e8 | blueswir1 | .iu_version = 0x50000000,
|
5101 | 406f82e8 | blueswir1 | .fpu_version = 0 << 17, |
5102 | 406f82e8 | blueswir1 | .mmu_version = 0x50000000,
|
5103 | 406f82e8 | blueswir1 | .mmu_bm = 0x00004000,
|
5104 | 3deaeab7 | blueswir1 | .mmu_ctpr_mask = 0x007ffff0,
|
5105 | 3deaeab7 | blueswir1 | .mmu_cxr_mask = 0x0000003f,
|
5106 | 3deaeab7 | blueswir1 | .mmu_sfsr_mask = 0xffffffff,
|
5107 | 3deaeab7 | blueswir1 | .mmu_trcr_mask = 0xffffffff,
|
5108 | 406f82e8 | blueswir1 | }, |
5109 | 406f82e8 | blueswir1 | { |
5110 | 406f82e8 | blueswir1 | .name = "Weitek W8601",
|
5111 | 406f82e8 | blueswir1 | .iu_version = 0x90 << 24, /* Impl 9, ver 0 */ |
5112 | 406f82e8 | blueswir1 | .fpu_version = 3 << 17, /* FPU version 3 (Weitek WTL3170/2) */ |
5113 | 406f82e8 | blueswir1 | .mmu_version = 0x10 << 24, |
5114 | 406f82e8 | blueswir1 | .mmu_bm = 0x00004000,
|
5115 | 3deaeab7 | blueswir1 | .mmu_ctpr_mask = 0x007ffff0,
|
5116 | 3deaeab7 | blueswir1 | .mmu_cxr_mask = 0x0000003f,
|
5117 | 3deaeab7 | blueswir1 | .mmu_sfsr_mask = 0xffffffff,
|
5118 | 3deaeab7 | blueswir1 | .mmu_trcr_mask = 0xffffffff,
|
5119 | 406f82e8 | blueswir1 | }, |
5120 | 406f82e8 | blueswir1 | { |
5121 | 406f82e8 | blueswir1 | .name = "LEON2",
|
5122 | 406f82e8 | blueswir1 | .iu_version = 0xf2000000,
|
5123 | 406f82e8 | blueswir1 | .fpu_version = 4 << 17, /* FPU version 4 (Meiko) */ |
5124 | 406f82e8 | blueswir1 | .mmu_version = 0xf2000000,
|
5125 | 406f82e8 | blueswir1 | .mmu_bm = 0x00004000,
|
5126 | 3deaeab7 | blueswir1 | .mmu_ctpr_mask = 0x007ffff0,
|
5127 | 3deaeab7 | blueswir1 | .mmu_cxr_mask = 0x0000003f,
|
5128 | 3deaeab7 | blueswir1 | .mmu_sfsr_mask = 0xffffffff,
|
5129 | 3deaeab7 | blueswir1 | .mmu_trcr_mask = 0xffffffff,
|
5130 | 406f82e8 | blueswir1 | }, |
5131 | 406f82e8 | blueswir1 | { |
5132 | 406f82e8 | blueswir1 | .name = "LEON3",
|
5133 | 406f82e8 | blueswir1 | .iu_version = 0xf3000000,
|
5134 | 406f82e8 | blueswir1 | .fpu_version = 4 << 17, /* FPU version 4 (Meiko) */ |
5135 | 406f82e8 | blueswir1 | .mmu_version = 0xf3000000,
|
5136 | 6d5f237a | blueswir1 | .mmu_bm = 0x00004000,
|
5137 | 3deaeab7 | blueswir1 | .mmu_ctpr_mask = 0x007ffff0,
|
5138 | 3deaeab7 | blueswir1 | .mmu_cxr_mask = 0x0000003f,
|
5139 | 3deaeab7 | blueswir1 | .mmu_sfsr_mask = 0xffffffff,
|
5140 | 3deaeab7 | blueswir1 | .mmu_trcr_mask = 0xffffffff,
|
5141 | e0353fe2 | blueswir1 | }, |
5142 | 62724a37 | blueswir1 | #endif
|
5143 | 62724a37 | blueswir1 | }; |
5144 | 62724a37 | blueswir1 | |
5145 | aaed909a | bellard | static const sparc_def_t *cpu_sparc_find_by_name(const unsigned char *name) |
5146 | 62724a37 | blueswir1 | { |
5147 | 62724a37 | blueswir1 | unsigned int i; |
5148 | 62724a37 | blueswir1 | |
5149 | 62724a37 | blueswir1 | for (i = 0; i < sizeof(sparc_defs) / sizeof(sparc_def_t); i++) { |
5150 | 62724a37 | blueswir1 | if (strcasecmp(name, sparc_defs[i].name) == 0) { |
5151 | aaed909a | bellard | return &sparc_defs[i];
|
5152 | 62724a37 | blueswir1 | } |
5153 | 62724a37 | blueswir1 | } |
5154 | aaed909a | bellard | return NULL; |
5155 | 62724a37 | blueswir1 | } |
5156 | 62724a37 | blueswir1 | |
5157 | 62724a37 | blueswir1 | void sparc_cpu_list (FILE *f, int (*cpu_fprintf)(FILE *f, const char *fmt, ...)) |
5158 | 62724a37 | blueswir1 | { |
5159 | 62724a37 | blueswir1 | unsigned int i; |
5160 | 62724a37 | blueswir1 | |
5161 | 62724a37 | blueswir1 | for (i = 0; i < sizeof(sparc_defs) / sizeof(sparc_def_t); i++) { |
5162 | 62724a37 | blueswir1 | (*cpu_fprintf)(f, "Sparc %16s IU " TARGET_FMT_lx " FPU %08x MMU %08x\n", |
5163 | 62724a37 | blueswir1 | sparc_defs[i].name, |
5164 | 62724a37 | blueswir1 | sparc_defs[i].iu_version, |
5165 | 62724a37 | blueswir1 | sparc_defs[i].fpu_version, |
5166 | 62724a37 | blueswir1 | sparc_defs[i].mmu_version); |
5167 | 62724a37 | blueswir1 | } |
5168 | 62724a37 | blueswir1 | } |
5169 | 62724a37 | blueswir1 | |
5170 | 7a3f1944 | bellard | #define GET_FLAG(a,b) ((env->psr & a)?b:'-') |
5171 | 7a3f1944 | bellard | |
5172 | 5fafdf24 | ths | void cpu_dump_state(CPUState *env, FILE *f,
|
5173 | 7fe48483 | bellard | int (*cpu_fprintf)(FILE *f, const char *fmt, ...), |
5174 | 7fe48483 | bellard | int flags)
|
5175 | 7a3f1944 | bellard | { |
5176 | cf495bcf | bellard | int i, x;
|
5177 | cf495bcf | bellard | |
5178 | af7bf89b | bellard | cpu_fprintf(f, "pc: " TARGET_FMT_lx " npc: " TARGET_FMT_lx "\n", env->pc, env->npc); |
5179 | 7fe48483 | bellard | cpu_fprintf(f, "General Registers:\n");
|
5180 | cf495bcf | bellard | for (i = 0; i < 4; i++) |
5181 | 0f8a249a | blueswir1 | cpu_fprintf(f, "%%g%c: " TARGET_FMT_lx "\t", i + '0', env->gregs[i]); |
5182 | 7fe48483 | bellard | cpu_fprintf(f, "\n");
|
5183 | cf495bcf | bellard | for (; i < 8; i++) |
5184 | 0f8a249a | blueswir1 | cpu_fprintf(f, "%%g%c: " TARGET_FMT_lx "\t", i + '0', env->gregs[i]); |
5185 | 7fe48483 | bellard | cpu_fprintf(f, "\nCurrent Register Window:\n");
|
5186 | cf495bcf | bellard | for (x = 0; x < 3; x++) { |
5187 | 0f8a249a | blueswir1 | for (i = 0; i < 4; i++) |
5188 | 0f8a249a | blueswir1 | cpu_fprintf(f, "%%%c%d: " TARGET_FMT_lx "\t", |
5189 | 0f8a249a | blueswir1 | (x == 0 ? 'o' : (x == 1 ? 'l' : 'i')), i, |
5190 | 0f8a249a | blueswir1 | env->regwptr[i + x * 8]);
|
5191 | 0f8a249a | blueswir1 | cpu_fprintf(f, "\n");
|
5192 | 0f8a249a | blueswir1 | for (; i < 8; i++) |
5193 | 0f8a249a | blueswir1 | cpu_fprintf(f, "%%%c%d: " TARGET_FMT_lx "\t", |
5194 | 0f8a249a | blueswir1 | (x == 0 ? 'o' : x == 1 ? 'l' : 'i'), i, |
5195 | 0f8a249a | blueswir1 | env->regwptr[i + x * 8]);
|
5196 | 0f8a249a | blueswir1 | cpu_fprintf(f, "\n");
|
5197 | cf495bcf | bellard | } |
5198 | 7fe48483 | bellard | cpu_fprintf(f, "\nFloating Point Registers:\n");
|
5199 | e8af50a3 | bellard | for (i = 0; i < 32; i++) { |
5200 | e8af50a3 | bellard | if ((i & 3) == 0) |
5201 | 7fe48483 | bellard | cpu_fprintf(f, "%%f%02d:", i);
|
5202 | 7fe48483 | bellard | cpu_fprintf(f, " %016lf", env->fpr[i]);
|
5203 | e8af50a3 | bellard | if ((i & 3) == 3) |
5204 | 7fe48483 | bellard | cpu_fprintf(f, "\n");
|
5205 | e8af50a3 | bellard | } |
5206 | ded3ab80 | pbrook | #ifdef TARGET_SPARC64
|
5207 | 3299908c | blueswir1 | cpu_fprintf(f, "pstate: 0x%08x ccr: 0x%02x asi: 0x%02x tl: %d fprs: %d\n",
|
5208 | 0f8a249a | blueswir1 | env->pstate, GET_CCR(env), env->asi, env->tl, env->fprs); |
5209 | ded3ab80 | pbrook | cpu_fprintf(f, "cansave: %d canrestore: %d otherwin: %d wstate %d cleanwin %d cwp %d\n",
|
5210 | 0f8a249a | blueswir1 | env->cansave, env->canrestore, env->otherwin, env->wstate, |
5211 | 0f8a249a | blueswir1 | env->cleanwin, NWINDOWS - 1 - env->cwp);
|
5212 | ded3ab80 | pbrook | #else
|
5213 | 7fe48483 | bellard | cpu_fprintf(f, "psr: 0x%08x -> %c%c%c%c %c%c%c wim: 0x%08x\n", GET_PSR(env),
|
5214 | 0f8a249a | blueswir1 | GET_FLAG(PSR_ZERO, 'Z'), GET_FLAG(PSR_OVF, 'V'), |
5215 | 0f8a249a | blueswir1 | GET_FLAG(PSR_NEG, 'N'), GET_FLAG(PSR_CARRY, 'C'), |
5216 | 0f8a249a | blueswir1 | env->psrs?'S':'-', env->psrps?'P':'-', |
5217 | 0f8a249a | blueswir1 | env->psret?'E':'-', env->wim); |
5218 | ded3ab80 | pbrook | #endif
|
5219 | 3475187d | bellard | cpu_fprintf(f, "fsr: 0x%08x\n", GET_FSR32(env));
|
5220 | 7a3f1944 | bellard | } |
5221 | edfcbd99 | bellard | |
5222 | e80cfcfc | bellard | #if defined(CONFIG_USER_ONLY)
|
5223 | 9b3c35e0 | j_mayer | target_phys_addr_t cpu_get_phys_page_debug(CPUState *env, target_ulong addr) |
5224 | edfcbd99 | bellard | { |
5225 | edfcbd99 | bellard | return addr;
|
5226 | edfcbd99 | bellard | } |
5227 | 658138bc | bellard | |
5228 | e80cfcfc | bellard | #else
|
5229 | af7bf89b | bellard | extern int get_physical_address (CPUState *env, target_phys_addr_t *physical, int *prot, |
5230 | af7bf89b | bellard | int *access_index, target_ulong address, int rw, |
5231 | 6ebbf390 | j_mayer | int mmu_idx);
|
5232 | 0fa85d43 | bellard | |
5233 | 9b3c35e0 | j_mayer | target_phys_addr_t cpu_get_phys_page_debug(CPUState *env, target_ulong addr) |
5234 | e80cfcfc | bellard | { |
5235 | af7bf89b | bellard | target_phys_addr_t phys_addr; |
5236 | e80cfcfc | bellard | int prot, access_index;
|
5237 | e80cfcfc | bellard | |
5238 | 9e31b9e2 | blueswir1 | if (get_physical_address(env, &phys_addr, &prot, &access_index, addr, 2, |
5239 | 9e31b9e2 | blueswir1 | MMU_KERNEL_IDX) != 0)
|
5240 | 9e31b9e2 | blueswir1 | if (get_physical_address(env, &phys_addr, &prot, &access_index, addr,
|
5241 | 9e31b9e2 | blueswir1 | 0, MMU_KERNEL_IDX) != 0) |
5242 | 6b1575b7 | bellard | return -1; |
5243 | 6c36d3fa | blueswir1 | if (cpu_get_physical_page_desc(phys_addr) == IO_MEM_UNASSIGNED)
|
5244 | 6c36d3fa | blueswir1 | return -1; |
5245 | e80cfcfc | bellard | return phys_addr;
|
5246 | e80cfcfc | bellard | } |
5247 | e80cfcfc | bellard | #endif
|
5248 | e80cfcfc | bellard | |
5249 | 658138bc | bellard | void helper_flush(target_ulong addr)
|
5250 | 658138bc | bellard | { |
5251 | 658138bc | bellard | addr &= ~7;
|
5252 | 658138bc | bellard | tb_invalidate_page_range(addr, addr + 8);
|
5253 | 658138bc | bellard | } |