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1 | 24859b68 | balrog | /*
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2 | 24859b68 | balrog | * Marvell MV88W8618 / Freecom MusicPal emulation.
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3 | 24859b68 | balrog | *
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4 | 24859b68 | balrog | * Copyright (c) 2008 Jan Kiszka
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5 | 24859b68 | balrog | *
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6 | 24859b68 | balrog | * This code is licenced under the GNU GPL v2.
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7 | 24859b68 | balrog | */
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8 | 24859b68 | balrog | |
9 | b47b50fa | Paul Brook | #include "sysbus.h" |
10 | 24859b68 | balrog | #include "arm-misc.h" |
11 | 24859b68 | balrog | #include "devices.h" |
12 | 24859b68 | balrog | #include "net.h" |
13 | 24859b68 | balrog | #include "sysemu.h" |
14 | 24859b68 | balrog | #include "boards.h" |
15 | 24859b68 | balrog | #include "pc.h" |
16 | 24859b68 | balrog | #include "qemu-timer.h" |
17 | 24859b68 | balrog | #include "block.h" |
18 | 24859b68 | balrog | #include "flash.h" |
19 | 24859b68 | balrog | #include "console.h" |
20 | 24859b68 | balrog | #include "i2c.h" |
21 | 24859b68 | balrog | |
22 | 718ec0be | malc | #define MP_MISC_BASE 0x80002000 |
23 | 718ec0be | malc | #define MP_MISC_SIZE 0x00001000 |
24 | 718ec0be | malc | |
25 | 24859b68 | balrog | #define MP_ETH_BASE 0x80008000 |
26 | 24859b68 | balrog | #define MP_ETH_SIZE 0x00001000 |
27 | 24859b68 | balrog | |
28 | 718ec0be | malc | #define MP_WLAN_BASE 0x8000C000 |
29 | 718ec0be | malc | #define MP_WLAN_SIZE 0x00000800 |
30 | 718ec0be | malc | |
31 | 24859b68 | balrog | #define MP_UART1_BASE 0x8000C840 |
32 | 24859b68 | balrog | #define MP_UART2_BASE 0x8000C940 |
33 | 24859b68 | balrog | |
34 | 718ec0be | malc | #define MP_GPIO_BASE 0x8000D000 |
35 | 718ec0be | malc | #define MP_GPIO_SIZE 0x00001000 |
36 | 718ec0be | malc | |
37 | 24859b68 | balrog | #define MP_FLASHCFG_BASE 0x90006000 |
38 | 24859b68 | balrog | #define MP_FLASHCFG_SIZE 0x00001000 |
39 | 24859b68 | balrog | |
40 | 24859b68 | balrog | #define MP_AUDIO_BASE 0x90007000 |
41 | 24859b68 | balrog | |
42 | 24859b68 | balrog | #define MP_PIC_BASE 0x90008000 |
43 | 24859b68 | balrog | #define MP_PIC_SIZE 0x00001000 |
44 | 24859b68 | balrog | |
45 | 24859b68 | balrog | #define MP_PIT_BASE 0x90009000 |
46 | 24859b68 | balrog | #define MP_PIT_SIZE 0x00001000 |
47 | 24859b68 | balrog | |
48 | 24859b68 | balrog | #define MP_LCD_BASE 0x9000c000 |
49 | 24859b68 | balrog | #define MP_LCD_SIZE 0x00001000 |
50 | 24859b68 | balrog | |
51 | 24859b68 | balrog | #define MP_SRAM_BASE 0xC0000000 |
52 | 24859b68 | balrog | #define MP_SRAM_SIZE 0x00020000 |
53 | 24859b68 | balrog | |
54 | 24859b68 | balrog | #define MP_RAM_DEFAULT_SIZE 32*1024*1024 |
55 | 24859b68 | balrog | #define MP_FLASH_SIZE_MAX 32*1024*1024 |
56 | 24859b68 | balrog | |
57 | 24859b68 | balrog | #define MP_TIMER1_IRQ 4 |
58 | b47b50fa | Paul Brook | #define MP_TIMER2_IRQ 5 |
59 | b47b50fa | Paul Brook | #define MP_TIMER3_IRQ 6 |
60 | 24859b68 | balrog | #define MP_TIMER4_IRQ 7 |
61 | 24859b68 | balrog | #define MP_EHCI_IRQ 8 |
62 | 24859b68 | balrog | #define MP_ETH_IRQ 9 |
63 | 24859b68 | balrog | #define MP_UART1_IRQ 11 |
64 | 24859b68 | balrog | #define MP_UART2_IRQ 11 |
65 | 24859b68 | balrog | #define MP_GPIO_IRQ 12 |
66 | 24859b68 | balrog | #define MP_RTC_IRQ 28 |
67 | 24859b68 | balrog | #define MP_AUDIO_IRQ 30 |
68 | 24859b68 | balrog | |
69 | 24859b68 | balrog | /* Wolfson 8750 I2C address */
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70 | 24859b68 | balrog | #define MP_WM_ADDR 0x34 |
71 | 24859b68 | balrog | |
72 | 24859b68 | balrog | /* Ethernet register offsets */
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73 | 24859b68 | balrog | #define MP_ETH_SMIR 0x010 |
74 | 24859b68 | balrog | #define MP_ETH_PCXR 0x408 |
75 | 24859b68 | balrog | #define MP_ETH_SDCMR 0x448 |
76 | 24859b68 | balrog | #define MP_ETH_ICR 0x450 |
77 | 24859b68 | balrog | #define MP_ETH_IMR 0x458 |
78 | 24859b68 | balrog | #define MP_ETH_FRDP0 0x480 |
79 | 24859b68 | balrog | #define MP_ETH_FRDP1 0x484 |
80 | 24859b68 | balrog | #define MP_ETH_FRDP2 0x488 |
81 | 24859b68 | balrog | #define MP_ETH_FRDP3 0x48C |
82 | 24859b68 | balrog | #define MP_ETH_CRDP0 0x4A0 |
83 | 24859b68 | balrog | #define MP_ETH_CRDP1 0x4A4 |
84 | 24859b68 | balrog | #define MP_ETH_CRDP2 0x4A8 |
85 | 24859b68 | balrog | #define MP_ETH_CRDP3 0x4AC |
86 | 24859b68 | balrog | #define MP_ETH_CTDP0 0x4E0 |
87 | 24859b68 | balrog | #define MP_ETH_CTDP1 0x4E4 |
88 | 24859b68 | balrog | #define MP_ETH_CTDP2 0x4E8 |
89 | 24859b68 | balrog | #define MP_ETH_CTDP3 0x4EC |
90 | 24859b68 | balrog | |
91 | 24859b68 | balrog | /* MII PHY access */
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92 | 24859b68 | balrog | #define MP_ETH_SMIR_DATA 0x0000FFFF |
93 | 24859b68 | balrog | #define MP_ETH_SMIR_ADDR 0x03FF0000 |
94 | 24859b68 | balrog | #define MP_ETH_SMIR_OPCODE (1 << 26) /* Read value */ |
95 | 24859b68 | balrog | #define MP_ETH_SMIR_RDVALID (1 << 27) |
96 | 24859b68 | balrog | |
97 | 24859b68 | balrog | /* PHY registers */
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98 | 24859b68 | balrog | #define MP_ETH_PHY1_BMSR 0x00210000 |
99 | 24859b68 | balrog | #define MP_ETH_PHY1_PHYSID1 0x00410000 |
100 | 24859b68 | balrog | #define MP_ETH_PHY1_PHYSID2 0x00610000 |
101 | 24859b68 | balrog | |
102 | 24859b68 | balrog | #define MP_PHY_BMSR_LINK 0x0004 |
103 | 24859b68 | balrog | #define MP_PHY_BMSR_AUTONEG 0x0008 |
104 | 24859b68 | balrog | |
105 | 24859b68 | balrog | #define MP_PHY_88E3015 0x01410E20 |
106 | 24859b68 | balrog | |
107 | 24859b68 | balrog | /* TX descriptor status */
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108 | 24859b68 | balrog | #define MP_ETH_TX_OWN (1 << 31) |
109 | 24859b68 | balrog | |
110 | 24859b68 | balrog | /* RX descriptor status */
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111 | 24859b68 | balrog | #define MP_ETH_RX_OWN (1 << 31) |
112 | 24859b68 | balrog | |
113 | 24859b68 | balrog | /* Interrupt cause/mask bits */
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114 | 24859b68 | balrog | #define MP_ETH_IRQ_RX_BIT 0 |
115 | 24859b68 | balrog | #define MP_ETH_IRQ_RX (1 << MP_ETH_IRQ_RX_BIT) |
116 | 24859b68 | balrog | #define MP_ETH_IRQ_TXHI_BIT 2 |
117 | 24859b68 | balrog | #define MP_ETH_IRQ_TXLO_BIT 3 |
118 | 24859b68 | balrog | |
119 | 24859b68 | balrog | /* Port config bits */
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120 | 24859b68 | balrog | #define MP_ETH_PCXR_2BSM_BIT 28 /* 2-byte incoming suffix */ |
121 | 24859b68 | balrog | |
122 | 24859b68 | balrog | /* SDMA command bits */
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123 | 24859b68 | balrog | #define MP_ETH_CMD_TXHI (1 << 23) |
124 | 24859b68 | balrog | #define MP_ETH_CMD_TXLO (1 << 22) |
125 | 24859b68 | balrog | |
126 | 24859b68 | balrog | typedef struct mv88w8618_tx_desc { |
127 | 24859b68 | balrog | uint32_t cmdstat; |
128 | 24859b68 | balrog | uint16_t res; |
129 | 24859b68 | balrog | uint16_t bytes; |
130 | 24859b68 | balrog | uint32_t buffer; |
131 | 24859b68 | balrog | uint32_t next; |
132 | 24859b68 | balrog | } mv88w8618_tx_desc; |
133 | 24859b68 | balrog | |
134 | 24859b68 | balrog | typedef struct mv88w8618_rx_desc { |
135 | 24859b68 | balrog | uint32_t cmdstat; |
136 | 24859b68 | balrog | uint16_t bytes; |
137 | 24859b68 | balrog | uint16_t buffer_size; |
138 | 24859b68 | balrog | uint32_t buffer; |
139 | 24859b68 | balrog | uint32_t next; |
140 | 24859b68 | balrog | } mv88w8618_rx_desc; |
141 | 24859b68 | balrog | |
142 | 24859b68 | balrog | typedef struct mv88w8618_eth_state { |
143 | b47b50fa | Paul Brook | SysBusDevice busdev; |
144 | 24859b68 | balrog | qemu_irq irq; |
145 | 24859b68 | balrog | uint32_t smir; |
146 | 24859b68 | balrog | uint32_t icr; |
147 | 24859b68 | balrog | uint32_t imr; |
148 | b946a153 | aliguori | int mmio_index;
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149 | d5b61ddd | Jan Kiszka | uint32_t vlan_header; |
150 | 930c8682 | pbrook | uint32_t tx_queue[2];
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151 | 930c8682 | pbrook | uint32_t rx_queue[4];
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152 | 930c8682 | pbrook | uint32_t frx_queue[4];
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153 | 930c8682 | pbrook | uint32_t cur_rx[4];
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154 | 24859b68 | balrog | VLANClientState *vc; |
155 | 24859b68 | balrog | } mv88w8618_eth_state; |
156 | 24859b68 | balrog | |
157 | 930c8682 | pbrook | static void eth_rx_desc_put(uint32_t addr, mv88w8618_rx_desc *desc) |
158 | 930c8682 | pbrook | { |
159 | 930c8682 | pbrook | cpu_to_le32s(&desc->cmdstat); |
160 | 930c8682 | pbrook | cpu_to_le16s(&desc->bytes); |
161 | 930c8682 | pbrook | cpu_to_le16s(&desc->buffer_size); |
162 | 930c8682 | pbrook | cpu_to_le32s(&desc->buffer); |
163 | 930c8682 | pbrook | cpu_to_le32s(&desc->next); |
164 | 930c8682 | pbrook | cpu_physical_memory_write(addr, (void *)desc, sizeof(*desc)); |
165 | 930c8682 | pbrook | } |
166 | 930c8682 | pbrook | |
167 | 930c8682 | pbrook | static void eth_rx_desc_get(uint32_t addr, mv88w8618_rx_desc *desc) |
168 | 930c8682 | pbrook | { |
169 | 930c8682 | pbrook | cpu_physical_memory_read(addr, (void *)desc, sizeof(*desc)); |
170 | 930c8682 | pbrook | le32_to_cpus(&desc->cmdstat); |
171 | 930c8682 | pbrook | le16_to_cpus(&desc->bytes); |
172 | 930c8682 | pbrook | le16_to_cpus(&desc->buffer_size); |
173 | 930c8682 | pbrook | le32_to_cpus(&desc->buffer); |
174 | 930c8682 | pbrook | le32_to_cpus(&desc->next); |
175 | 930c8682 | pbrook | } |
176 | 930c8682 | pbrook | |
177 | e3f5ec2b | Mark McLoughlin | static int eth_can_receive(VLANClientState *vc) |
178 | 24859b68 | balrog | { |
179 | 24859b68 | balrog | return 1; |
180 | 24859b68 | balrog | } |
181 | 24859b68 | balrog | |
182 | 4f1c942b | Mark McLoughlin | static ssize_t eth_receive(VLANClientState *vc, const uint8_t *buf, size_t size) |
183 | 24859b68 | balrog | { |
184 | e3f5ec2b | Mark McLoughlin | mv88w8618_eth_state *s = vc->opaque; |
185 | 930c8682 | pbrook | uint32_t desc_addr; |
186 | 930c8682 | pbrook | mv88w8618_rx_desc desc; |
187 | 24859b68 | balrog | int i;
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188 | 24859b68 | balrog | |
189 | 24859b68 | balrog | for (i = 0; i < 4; i++) { |
190 | 930c8682 | pbrook | desc_addr = s->cur_rx[i]; |
191 | 49fedd0d | Jan Kiszka | if (!desc_addr) {
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192 | 24859b68 | balrog | continue;
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193 | 49fedd0d | Jan Kiszka | } |
194 | 24859b68 | balrog | do {
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195 | 930c8682 | pbrook | eth_rx_desc_get(desc_addr, &desc); |
196 | 930c8682 | pbrook | if ((desc.cmdstat & MP_ETH_RX_OWN) && desc.buffer_size >= size) {
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197 | 930c8682 | pbrook | cpu_physical_memory_write(desc.buffer + s->vlan_header, |
198 | 930c8682 | pbrook | buf, size); |
199 | 930c8682 | pbrook | desc.bytes = size + s->vlan_header; |
200 | 930c8682 | pbrook | desc.cmdstat &= ~MP_ETH_RX_OWN; |
201 | 930c8682 | pbrook | s->cur_rx[i] = desc.next; |
202 | 24859b68 | balrog | |
203 | 24859b68 | balrog | s->icr |= MP_ETH_IRQ_RX; |
204 | 49fedd0d | Jan Kiszka | if (s->icr & s->imr) {
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205 | 24859b68 | balrog | qemu_irq_raise(s->irq); |
206 | 49fedd0d | Jan Kiszka | } |
207 | 930c8682 | pbrook | eth_rx_desc_put(desc_addr, &desc); |
208 | 4f1c942b | Mark McLoughlin | return size;
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209 | 24859b68 | balrog | } |
210 | 930c8682 | pbrook | desc_addr = desc.next; |
211 | 930c8682 | pbrook | } while (desc_addr != s->rx_queue[i]);
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212 | 24859b68 | balrog | } |
213 | 4f1c942b | Mark McLoughlin | return size;
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214 | 24859b68 | balrog | } |
215 | 24859b68 | balrog | |
216 | 930c8682 | pbrook | static void eth_tx_desc_put(uint32_t addr, mv88w8618_tx_desc *desc) |
217 | 930c8682 | pbrook | { |
218 | 930c8682 | pbrook | cpu_to_le32s(&desc->cmdstat); |
219 | 930c8682 | pbrook | cpu_to_le16s(&desc->res); |
220 | 930c8682 | pbrook | cpu_to_le16s(&desc->bytes); |
221 | 930c8682 | pbrook | cpu_to_le32s(&desc->buffer); |
222 | 930c8682 | pbrook | cpu_to_le32s(&desc->next); |
223 | 930c8682 | pbrook | cpu_physical_memory_write(addr, (void *)desc, sizeof(*desc)); |
224 | 930c8682 | pbrook | } |
225 | 930c8682 | pbrook | |
226 | 930c8682 | pbrook | static void eth_tx_desc_get(uint32_t addr, mv88w8618_tx_desc *desc) |
227 | 930c8682 | pbrook | { |
228 | 930c8682 | pbrook | cpu_physical_memory_read(addr, (void *)desc, sizeof(*desc)); |
229 | 930c8682 | pbrook | le32_to_cpus(&desc->cmdstat); |
230 | 930c8682 | pbrook | le16_to_cpus(&desc->res); |
231 | 930c8682 | pbrook | le16_to_cpus(&desc->bytes); |
232 | 930c8682 | pbrook | le32_to_cpus(&desc->buffer); |
233 | 930c8682 | pbrook | le32_to_cpus(&desc->next); |
234 | 930c8682 | pbrook | } |
235 | 930c8682 | pbrook | |
236 | 24859b68 | balrog | static void eth_send(mv88w8618_eth_state *s, int queue_index) |
237 | 24859b68 | balrog | { |
238 | 930c8682 | pbrook | uint32_t desc_addr = s->tx_queue[queue_index]; |
239 | 930c8682 | pbrook | mv88w8618_tx_desc desc; |
240 | 930c8682 | pbrook | uint8_t buf[2048];
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241 | 930c8682 | pbrook | int len;
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242 | 930c8682 | pbrook | |
243 | 2e87c5b9 | Jan Kiszka | if (!desc_addr) {
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244 | 2e87c5b9 | Jan Kiszka | return;
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245 | 2e87c5b9 | Jan Kiszka | } |
246 | 24859b68 | balrog | do {
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247 | 930c8682 | pbrook | eth_tx_desc_get(desc_addr, &desc); |
248 | 930c8682 | pbrook | if (desc.cmdstat & MP_ETH_TX_OWN) {
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249 | 930c8682 | pbrook | len = desc.bytes; |
250 | 930c8682 | pbrook | if (len < 2048) { |
251 | 930c8682 | pbrook | cpu_physical_memory_read(desc.buffer, buf, len); |
252 | 930c8682 | pbrook | qemu_send_packet(s->vc, buf, len); |
253 | 930c8682 | pbrook | } |
254 | 930c8682 | pbrook | desc.cmdstat &= ~MP_ETH_TX_OWN; |
255 | 24859b68 | balrog | s->icr |= 1 << (MP_ETH_IRQ_TXLO_BIT - queue_index);
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256 | 930c8682 | pbrook | eth_tx_desc_put(desc_addr, &desc); |
257 | 24859b68 | balrog | } |
258 | 930c8682 | pbrook | desc_addr = desc.next; |
259 | 930c8682 | pbrook | } while (desc_addr != s->tx_queue[queue_index]);
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260 | 24859b68 | balrog | } |
261 | 24859b68 | balrog | |
262 | c227f099 | Anthony Liguori | static uint32_t mv88w8618_eth_read(void *opaque, target_phys_addr_t offset) |
263 | 24859b68 | balrog | { |
264 | 24859b68 | balrog | mv88w8618_eth_state *s = opaque; |
265 | 24859b68 | balrog | |
266 | 24859b68 | balrog | switch (offset) {
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267 | 24859b68 | balrog | case MP_ETH_SMIR:
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268 | 24859b68 | balrog | if (s->smir & MP_ETH_SMIR_OPCODE) {
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269 | 24859b68 | balrog | switch (s->smir & MP_ETH_SMIR_ADDR) {
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270 | 24859b68 | balrog | case MP_ETH_PHY1_BMSR:
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271 | 24859b68 | balrog | return MP_PHY_BMSR_LINK | MP_PHY_BMSR_AUTONEG |
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272 | 24859b68 | balrog | MP_ETH_SMIR_RDVALID; |
273 | 24859b68 | balrog | case MP_ETH_PHY1_PHYSID1:
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274 | 24859b68 | balrog | return (MP_PHY_88E3015 >> 16) | MP_ETH_SMIR_RDVALID; |
275 | 24859b68 | balrog | case MP_ETH_PHY1_PHYSID2:
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276 | 24859b68 | balrog | return (MP_PHY_88E3015 & 0xFFFF) | MP_ETH_SMIR_RDVALID; |
277 | 24859b68 | balrog | default:
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278 | 24859b68 | balrog | return MP_ETH_SMIR_RDVALID;
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279 | 24859b68 | balrog | } |
280 | 24859b68 | balrog | } |
281 | 24859b68 | balrog | return 0; |
282 | 24859b68 | balrog | |
283 | 24859b68 | balrog | case MP_ETH_ICR:
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284 | 24859b68 | balrog | return s->icr;
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285 | 24859b68 | balrog | |
286 | 24859b68 | balrog | case MP_ETH_IMR:
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287 | 24859b68 | balrog | return s->imr;
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288 | 24859b68 | balrog | |
289 | 24859b68 | balrog | case MP_ETH_FRDP0 ... MP_ETH_FRDP3:
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290 | 930c8682 | pbrook | return s->frx_queue[(offset - MP_ETH_FRDP0)/4]; |
291 | 24859b68 | balrog | |
292 | 24859b68 | balrog | case MP_ETH_CRDP0 ... MP_ETH_CRDP3:
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293 | 930c8682 | pbrook | return s->rx_queue[(offset - MP_ETH_CRDP0)/4]; |
294 | 24859b68 | balrog | |
295 | 24859b68 | balrog | case MP_ETH_CTDP0 ... MP_ETH_CTDP3:
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296 | 930c8682 | pbrook | return s->tx_queue[(offset - MP_ETH_CTDP0)/4]; |
297 | 24859b68 | balrog | |
298 | 24859b68 | balrog | default:
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299 | 24859b68 | balrog | return 0; |
300 | 24859b68 | balrog | } |
301 | 24859b68 | balrog | } |
302 | 24859b68 | balrog | |
303 | c227f099 | Anthony Liguori | static void mv88w8618_eth_write(void *opaque, target_phys_addr_t offset, |
304 | 24859b68 | balrog | uint32_t value) |
305 | 24859b68 | balrog | { |
306 | 24859b68 | balrog | mv88w8618_eth_state *s = opaque; |
307 | 24859b68 | balrog | |
308 | 24859b68 | balrog | switch (offset) {
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309 | 24859b68 | balrog | case MP_ETH_SMIR:
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310 | 24859b68 | balrog | s->smir = value; |
311 | 24859b68 | balrog | break;
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312 | 24859b68 | balrog | |
313 | 24859b68 | balrog | case MP_ETH_PCXR:
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314 | 24859b68 | balrog | s->vlan_header = ((value >> MP_ETH_PCXR_2BSM_BIT) & 1) * 2; |
315 | 24859b68 | balrog | break;
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316 | 24859b68 | balrog | |
317 | 24859b68 | balrog | case MP_ETH_SDCMR:
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318 | 49fedd0d | Jan Kiszka | if (value & MP_ETH_CMD_TXHI) {
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319 | 24859b68 | balrog | eth_send(s, 1);
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320 | 49fedd0d | Jan Kiszka | } |
321 | 49fedd0d | Jan Kiszka | if (value & MP_ETH_CMD_TXLO) {
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322 | 24859b68 | balrog | eth_send(s, 0);
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323 | 49fedd0d | Jan Kiszka | } |
324 | 49fedd0d | Jan Kiszka | if (value & (MP_ETH_CMD_TXHI | MP_ETH_CMD_TXLO) && s->icr & s->imr) {
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325 | 24859b68 | balrog | qemu_irq_raise(s->irq); |
326 | 49fedd0d | Jan Kiszka | } |
327 | 24859b68 | balrog | break;
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328 | 24859b68 | balrog | |
329 | 24859b68 | balrog | case MP_ETH_ICR:
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330 | 24859b68 | balrog | s->icr &= value; |
331 | 24859b68 | balrog | break;
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332 | 24859b68 | balrog | |
333 | 24859b68 | balrog | case MP_ETH_IMR:
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334 | 24859b68 | balrog | s->imr = value; |
335 | 49fedd0d | Jan Kiszka | if (s->icr & s->imr) {
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336 | 24859b68 | balrog | qemu_irq_raise(s->irq); |
337 | 49fedd0d | Jan Kiszka | } |
338 | 24859b68 | balrog | break;
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339 | 24859b68 | balrog | |
340 | 24859b68 | balrog | case MP_ETH_FRDP0 ... MP_ETH_FRDP3:
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341 | 930c8682 | pbrook | s->frx_queue[(offset - MP_ETH_FRDP0)/4] = value;
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342 | 24859b68 | balrog | break;
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343 | 24859b68 | balrog | |
344 | 24859b68 | balrog | case MP_ETH_CRDP0 ... MP_ETH_CRDP3:
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345 | 24859b68 | balrog | s->rx_queue[(offset - MP_ETH_CRDP0)/4] =
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346 | 930c8682 | pbrook | s->cur_rx[(offset - MP_ETH_CRDP0)/4] = value;
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347 | 24859b68 | balrog | break;
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348 | 24859b68 | balrog | |
349 | 24859b68 | balrog | case MP_ETH_CTDP0 ... MP_ETH_CTDP3:
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350 | 930c8682 | pbrook | s->tx_queue[(offset - MP_ETH_CTDP0)/4] = value;
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351 | 24859b68 | balrog | break;
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352 | 24859b68 | balrog | } |
353 | 24859b68 | balrog | } |
354 | 24859b68 | balrog | |
355 | d60efc6b | Blue Swirl | static CPUReadMemoryFunc * const mv88w8618_eth_readfn[] = { |
356 | 24859b68 | balrog | mv88w8618_eth_read, |
357 | 24859b68 | balrog | mv88w8618_eth_read, |
358 | 24859b68 | balrog | mv88w8618_eth_read |
359 | 24859b68 | balrog | }; |
360 | 24859b68 | balrog | |
361 | d60efc6b | Blue Swirl | static CPUWriteMemoryFunc * const mv88w8618_eth_writefn[] = { |
362 | 24859b68 | balrog | mv88w8618_eth_write, |
363 | 24859b68 | balrog | mv88w8618_eth_write, |
364 | 24859b68 | balrog | mv88w8618_eth_write |
365 | 24859b68 | balrog | }; |
366 | 24859b68 | balrog | |
367 | b946a153 | aliguori | static void eth_cleanup(VLANClientState *vc) |
368 | b946a153 | aliguori | { |
369 | b946a153 | aliguori | mv88w8618_eth_state *s = vc->opaque; |
370 | b946a153 | aliguori | |
371 | b946a153 | aliguori | cpu_unregister_io_memory(s->mmio_index); |
372 | b946a153 | aliguori | |
373 | b946a153 | aliguori | qemu_free(s); |
374 | b946a153 | aliguori | } |
375 | b946a153 | aliguori | |
376 | 81a322d4 | Gerd Hoffmann | static int mv88w8618_eth_init(SysBusDevice *dev) |
377 | 24859b68 | balrog | { |
378 | b47b50fa | Paul Brook | mv88w8618_eth_state *s = FROM_SYSBUS(mv88w8618_eth_state, dev); |
379 | 0ae18cee | aliguori | |
380 | b47b50fa | Paul Brook | sysbus_init_irq(dev, &s->irq); |
381 | b47b50fa | Paul Brook | s->vc = qdev_get_vlan_client(&dev->qdev, |
382 | 463af534 | Mark McLoughlin | eth_can_receive, eth_receive, NULL,
|
383 | b946a153 | aliguori | eth_cleanup, s); |
384 | 1eed09cb | Avi Kivity | s->mmio_index = cpu_register_io_memory(mv88w8618_eth_readfn, |
385 | b946a153 | aliguori | mv88w8618_eth_writefn, s); |
386 | b47b50fa | Paul Brook | sysbus_init_mmio(dev, MP_ETH_SIZE, s->mmio_index); |
387 | 81a322d4 | Gerd Hoffmann | return 0; |
388 | 24859b68 | balrog | } |
389 | 24859b68 | balrog | |
390 | d5b61ddd | Jan Kiszka | static const VMStateDescription mv88w8618_eth_vmsd = { |
391 | d5b61ddd | Jan Kiszka | .name = "mv88w8618_eth",
|
392 | d5b61ddd | Jan Kiszka | .version_id = 1,
|
393 | d5b61ddd | Jan Kiszka | .minimum_version_id = 1,
|
394 | d5b61ddd | Jan Kiszka | .minimum_version_id_old = 1,
|
395 | d5b61ddd | Jan Kiszka | .fields = (VMStateField[]) { |
396 | d5b61ddd | Jan Kiszka | VMSTATE_UINT32(smir, mv88w8618_eth_state), |
397 | d5b61ddd | Jan Kiszka | VMSTATE_UINT32(icr, mv88w8618_eth_state), |
398 | d5b61ddd | Jan Kiszka | VMSTATE_UINT32(imr, mv88w8618_eth_state), |
399 | d5b61ddd | Jan Kiszka | VMSTATE_UINT32(vlan_header, mv88w8618_eth_state), |
400 | d5b61ddd | Jan Kiszka | VMSTATE_UINT32_ARRAY(tx_queue, mv88w8618_eth_state, 2),
|
401 | d5b61ddd | Jan Kiszka | VMSTATE_UINT32_ARRAY(rx_queue, mv88w8618_eth_state, 4),
|
402 | d5b61ddd | Jan Kiszka | VMSTATE_UINT32_ARRAY(frx_queue, mv88w8618_eth_state, 4),
|
403 | d5b61ddd | Jan Kiszka | VMSTATE_UINT32_ARRAY(cur_rx, mv88w8618_eth_state, 4),
|
404 | d5b61ddd | Jan Kiszka | VMSTATE_END_OF_LIST() |
405 | d5b61ddd | Jan Kiszka | } |
406 | d5b61ddd | Jan Kiszka | }; |
407 | d5b61ddd | Jan Kiszka | |
408 | d5b61ddd | Jan Kiszka | static SysBusDeviceInfo mv88w8618_eth_info = {
|
409 | d5b61ddd | Jan Kiszka | .init = mv88w8618_eth_init, |
410 | d5b61ddd | Jan Kiszka | .qdev.name = "mv88w8618_eth",
|
411 | d5b61ddd | Jan Kiszka | .qdev.size = sizeof(mv88w8618_eth_state),
|
412 | d5b61ddd | Jan Kiszka | .qdev.vmsd = &mv88w8618_eth_vmsd, |
413 | d5b61ddd | Jan Kiszka | }; |
414 | d5b61ddd | Jan Kiszka | |
415 | 24859b68 | balrog | /* LCD register offsets */
|
416 | 24859b68 | balrog | #define MP_LCD_IRQCTRL 0x180 |
417 | 24859b68 | balrog | #define MP_LCD_IRQSTAT 0x184 |
418 | 24859b68 | balrog | #define MP_LCD_SPICTRL 0x1ac |
419 | 24859b68 | balrog | #define MP_LCD_INST 0x1bc |
420 | 24859b68 | balrog | #define MP_LCD_DATA 0x1c0 |
421 | 24859b68 | balrog | |
422 | 24859b68 | balrog | /* Mode magics */
|
423 | 24859b68 | balrog | #define MP_LCD_SPI_DATA 0x00100011 |
424 | 24859b68 | balrog | #define MP_LCD_SPI_CMD 0x00104011 |
425 | 24859b68 | balrog | #define MP_LCD_SPI_INVALID 0x00000000 |
426 | 24859b68 | balrog | |
427 | 24859b68 | balrog | /* Commmands */
|
428 | 24859b68 | balrog | #define MP_LCD_INST_SETPAGE0 0xB0 |
429 | 24859b68 | balrog | /* ... */
|
430 | 24859b68 | balrog | #define MP_LCD_INST_SETPAGE7 0xB7 |
431 | 24859b68 | balrog | |
432 | 24859b68 | balrog | #define MP_LCD_TEXTCOLOR 0xe0e0ff /* RRGGBB */ |
433 | 24859b68 | balrog | |
434 | 24859b68 | balrog | typedef struct musicpal_lcd_state { |
435 | b47b50fa | Paul Brook | SysBusDevice busdev; |
436 | 343ec8e4 | Benoit Canet | uint32_t brightness; |
437 | 24859b68 | balrog | uint32_t mode; |
438 | 24859b68 | balrog | uint32_t irqctrl; |
439 | d5b61ddd | Jan Kiszka | uint32_t page; |
440 | d5b61ddd | Jan Kiszka | uint32_t page_off; |
441 | 24859b68 | balrog | DisplayState *ds; |
442 | 24859b68 | balrog | uint8_t video_ram[128*64/8]; |
443 | 24859b68 | balrog | } musicpal_lcd_state; |
444 | 24859b68 | balrog | |
445 | 343ec8e4 | Benoit Canet | static uint8_t scale_lcd_color(musicpal_lcd_state *s, uint8_t col)
|
446 | 24859b68 | balrog | { |
447 | 343ec8e4 | Benoit Canet | switch (s->brightness) {
|
448 | 343ec8e4 | Benoit Canet | case 7: |
449 | 343ec8e4 | Benoit Canet | return col;
|
450 | 343ec8e4 | Benoit Canet | case 0: |
451 | 24859b68 | balrog | return 0; |
452 | 24859b68 | balrog | default:
|
453 | 343ec8e4 | Benoit Canet | return (col * s->brightness) / 7; |
454 | 24859b68 | balrog | } |
455 | 24859b68 | balrog | } |
456 | 24859b68 | balrog | |
457 | 0266f2c7 | balrog | #define SET_LCD_PIXEL(depth, type) \
|
458 | 0266f2c7 | balrog | static inline void glue(set_lcd_pixel, depth) \ |
459 | 0266f2c7 | balrog | (musicpal_lcd_state *s, int x, int y, type col) \ |
460 | 0266f2c7 | balrog | { \ |
461 | 0266f2c7 | balrog | int dx, dy; \
|
462 | 0e1f5a0c | aliguori | type *pixel = &((type *) ds_get_data(s->ds))[(y * 128 * 3 + x) * 3]; \ |
463 | 0266f2c7 | balrog | \ |
464 | 0266f2c7 | balrog | for (dy = 0; dy < 3; dy++, pixel += 127 * 3) \ |
465 | 0266f2c7 | balrog | for (dx = 0; dx < 3; dx++, pixel++) \ |
466 | 0266f2c7 | balrog | *pixel = col; \ |
467 | 24859b68 | balrog | } |
468 | 0266f2c7 | balrog | SET_LCD_PIXEL(8, uint8_t)
|
469 | 0266f2c7 | balrog | SET_LCD_PIXEL(16, uint16_t)
|
470 | 0266f2c7 | balrog | SET_LCD_PIXEL(32, uint32_t)
|
471 | 0266f2c7 | balrog | |
472 | 0266f2c7 | balrog | #include "pixel_ops.h" |
473 | 24859b68 | balrog | |
474 | 24859b68 | balrog | static void lcd_refresh(void *opaque) |
475 | 24859b68 | balrog | { |
476 | 24859b68 | balrog | musicpal_lcd_state *s = opaque; |
477 | 0266f2c7 | balrog | int x, y, col;
|
478 | 24859b68 | balrog | |
479 | 0e1f5a0c | aliguori | switch (ds_get_bits_per_pixel(s->ds)) {
|
480 | 0266f2c7 | balrog | case 0: |
481 | 0266f2c7 | balrog | return;
|
482 | 0266f2c7 | balrog | #define LCD_REFRESH(depth, func) \
|
483 | 0266f2c7 | balrog | case depth: \
|
484 | 343ec8e4 | Benoit Canet | col = func(scale_lcd_color(s, (MP_LCD_TEXTCOLOR >> 16) & 0xff), \ |
485 | 343ec8e4 | Benoit Canet | scale_lcd_color(s, (MP_LCD_TEXTCOLOR >> 8) & 0xff), \ |
486 | 343ec8e4 | Benoit Canet | scale_lcd_color(s, MP_LCD_TEXTCOLOR & 0xff)); \
|
487 | 49fedd0d | Jan Kiszka | for (x = 0; x < 128; x++) { \ |
488 | 49fedd0d | Jan Kiszka | for (y = 0; y < 64; y++) { \ |
489 | 49fedd0d | Jan Kiszka | if (s->video_ram[x + (y/8)*128] & (1 << (y % 8))) { \ |
490 | 0266f2c7 | balrog | glue(set_lcd_pixel, depth)(s, x, y, col); \ |
491 | 49fedd0d | Jan Kiszka | } else { \
|
492 | 0266f2c7 | balrog | glue(set_lcd_pixel, depth)(s, x, y, 0); \
|
493 | 49fedd0d | Jan Kiszka | } \ |
494 | 49fedd0d | Jan Kiszka | } \ |
495 | 49fedd0d | Jan Kiszka | } \ |
496 | 0266f2c7 | balrog | break;
|
497 | 0266f2c7 | balrog | LCD_REFRESH(8, rgb_to_pixel8)
|
498 | 0266f2c7 | balrog | LCD_REFRESH(16, rgb_to_pixel16)
|
499 | bf9b48af | aliguori | LCD_REFRESH(32, (is_surface_bgr(s->ds->surface) ?
|
500 | bf9b48af | aliguori | rgb_to_pixel32bgr : rgb_to_pixel32)) |
501 | 0266f2c7 | balrog | default:
|
502 | 2ac71179 | Paul Brook | hw_error("unsupported colour depth %i\n",
|
503 | 0e1f5a0c | aliguori | ds_get_bits_per_pixel(s->ds)); |
504 | 0266f2c7 | balrog | } |
505 | 24859b68 | balrog | |
506 | 24859b68 | balrog | dpy_update(s->ds, 0, 0, 128*3, 64*3); |
507 | 24859b68 | balrog | } |
508 | 24859b68 | balrog | |
509 | 167bc3d2 | balrog | static void lcd_invalidate(void *opaque) |
510 | 167bc3d2 | balrog | { |
511 | 167bc3d2 | balrog | } |
512 | 167bc3d2 | balrog | |
513 | 343ec8e4 | Benoit Canet | static void musicpal_lcd_gpio_brigthness_in(void *opaque, int irq, int level) |
514 | 343ec8e4 | Benoit Canet | { |
515 | 243cd13c | Jan Kiszka | musicpal_lcd_state *s = opaque; |
516 | 343ec8e4 | Benoit Canet | s->brightness &= ~(1 << irq);
|
517 | 343ec8e4 | Benoit Canet | s->brightness |= level << irq; |
518 | 343ec8e4 | Benoit Canet | } |
519 | 343ec8e4 | Benoit Canet | |
520 | c227f099 | Anthony Liguori | static uint32_t musicpal_lcd_read(void *opaque, target_phys_addr_t offset) |
521 | 24859b68 | balrog | { |
522 | 24859b68 | balrog | musicpal_lcd_state *s = opaque; |
523 | 24859b68 | balrog | |
524 | 24859b68 | balrog | switch (offset) {
|
525 | 24859b68 | balrog | case MP_LCD_IRQCTRL:
|
526 | 24859b68 | balrog | return s->irqctrl;
|
527 | 24859b68 | balrog | |
528 | 24859b68 | balrog | default:
|
529 | 24859b68 | balrog | return 0; |
530 | 24859b68 | balrog | } |
531 | 24859b68 | balrog | } |
532 | 24859b68 | balrog | |
533 | c227f099 | Anthony Liguori | static void musicpal_lcd_write(void *opaque, target_phys_addr_t offset, |
534 | 24859b68 | balrog | uint32_t value) |
535 | 24859b68 | balrog | { |
536 | 24859b68 | balrog | musicpal_lcd_state *s = opaque; |
537 | 24859b68 | balrog | |
538 | 24859b68 | balrog | switch (offset) {
|
539 | 24859b68 | balrog | case MP_LCD_IRQCTRL:
|
540 | 24859b68 | balrog | s->irqctrl = value; |
541 | 24859b68 | balrog | break;
|
542 | 24859b68 | balrog | |
543 | 24859b68 | balrog | case MP_LCD_SPICTRL:
|
544 | 49fedd0d | Jan Kiszka | if (value == MP_LCD_SPI_DATA || value == MP_LCD_SPI_CMD) {
|
545 | 24859b68 | balrog | s->mode = value; |
546 | 49fedd0d | Jan Kiszka | } else {
|
547 | 24859b68 | balrog | s->mode = MP_LCD_SPI_INVALID; |
548 | 49fedd0d | Jan Kiszka | } |
549 | 24859b68 | balrog | break;
|
550 | 24859b68 | balrog | |
551 | 24859b68 | balrog | case MP_LCD_INST:
|
552 | 24859b68 | balrog | if (value >= MP_LCD_INST_SETPAGE0 && value <= MP_LCD_INST_SETPAGE7) {
|
553 | 24859b68 | balrog | s->page = value - MP_LCD_INST_SETPAGE0; |
554 | 24859b68 | balrog | s->page_off = 0;
|
555 | 24859b68 | balrog | } |
556 | 24859b68 | balrog | break;
|
557 | 24859b68 | balrog | |
558 | 24859b68 | balrog | case MP_LCD_DATA:
|
559 | 24859b68 | balrog | if (s->mode == MP_LCD_SPI_CMD) {
|
560 | 24859b68 | balrog | if (value >= MP_LCD_INST_SETPAGE0 &&
|
561 | 24859b68 | balrog | value <= MP_LCD_INST_SETPAGE7) { |
562 | 24859b68 | balrog | s->page = value - MP_LCD_INST_SETPAGE0; |
563 | 24859b68 | balrog | s->page_off = 0;
|
564 | 24859b68 | balrog | } |
565 | 24859b68 | balrog | } else if (s->mode == MP_LCD_SPI_DATA) { |
566 | 24859b68 | balrog | s->video_ram[s->page*128 + s->page_off] = value;
|
567 | 24859b68 | balrog | s->page_off = (s->page_off + 1) & 127; |
568 | 24859b68 | balrog | } |
569 | 24859b68 | balrog | break;
|
570 | 24859b68 | balrog | } |
571 | 24859b68 | balrog | } |
572 | 24859b68 | balrog | |
573 | d60efc6b | Blue Swirl | static CPUReadMemoryFunc * const musicpal_lcd_readfn[] = { |
574 | 24859b68 | balrog | musicpal_lcd_read, |
575 | 24859b68 | balrog | musicpal_lcd_read, |
576 | 24859b68 | balrog | musicpal_lcd_read |
577 | 24859b68 | balrog | }; |
578 | 24859b68 | balrog | |
579 | d60efc6b | Blue Swirl | static CPUWriteMemoryFunc * const musicpal_lcd_writefn[] = { |
580 | 24859b68 | balrog | musicpal_lcd_write, |
581 | 24859b68 | balrog | musicpal_lcd_write, |
582 | 24859b68 | balrog | musicpal_lcd_write |
583 | 24859b68 | balrog | }; |
584 | 24859b68 | balrog | |
585 | 81a322d4 | Gerd Hoffmann | static int musicpal_lcd_init(SysBusDevice *dev) |
586 | 24859b68 | balrog | { |
587 | b47b50fa | Paul Brook | musicpal_lcd_state *s = FROM_SYSBUS(musicpal_lcd_state, dev); |
588 | 24859b68 | balrog | int iomemtype;
|
589 | 24859b68 | balrog | |
590 | 343ec8e4 | Benoit Canet | s->brightness = 7;
|
591 | 343ec8e4 | Benoit Canet | |
592 | 1eed09cb | Avi Kivity | iomemtype = cpu_register_io_memory(musicpal_lcd_readfn, |
593 | 24859b68 | balrog | musicpal_lcd_writefn, s); |
594 | b47b50fa | Paul Brook | sysbus_init_mmio(dev, MP_LCD_SIZE, iomemtype); |
595 | 24859b68 | balrog | |
596 | 3023f332 | aliguori | s->ds = graphic_console_init(lcd_refresh, lcd_invalidate, |
597 | 3023f332 | aliguori | NULL, NULL, s); |
598 | 3023f332 | aliguori | qemu_console_resize(s->ds, 128*3, 64*3); |
599 | 343ec8e4 | Benoit Canet | |
600 | 343ec8e4 | Benoit Canet | qdev_init_gpio_in(&dev->qdev, musicpal_lcd_gpio_brigthness_in, 3);
|
601 | 81a322d4 | Gerd Hoffmann | |
602 | 81a322d4 | Gerd Hoffmann | return 0; |
603 | 24859b68 | balrog | } |
604 | 24859b68 | balrog | |
605 | d5b61ddd | Jan Kiszka | static const VMStateDescription musicpal_lcd_vmsd = { |
606 | d5b61ddd | Jan Kiszka | .name = "musicpal_lcd",
|
607 | d5b61ddd | Jan Kiszka | .version_id = 1,
|
608 | d5b61ddd | Jan Kiszka | .minimum_version_id = 1,
|
609 | d5b61ddd | Jan Kiszka | .minimum_version_id_old = 1,
|
610 | d5b61ddd | Jan Kiszka | .fields = (VMStateField[]) { |
611 | d5b61ddd | Jan Kiszka | VMSTATE_UINT32(brightness, musicpal_lcd_state), |
612 | d5b61ddd | Jan Kiszka | VMSTATE_UINT32(mode, musicpal_lcd_state), |
613 | d5b61ddd | Jan Kiszka | VMSTATE_UINT32(irqctrl, musicpal_lcd_state), |
614 | d5b61ddd | Jan Kiszka | VMSTATE_UINT32(page, musicpal_lcd_state), |
615 | d5b61ddd | Jan Kiszka | VMSTATE_UINT32(page_off, musicpal_lcd_state), |
616 | d5b61ddd | Jan Kiszka | VMSTATE_BUFFER(video_ram, musicpal_lcd_state), |
617 | d5b61ddd | Jan Kiszka | VMSTATE_END_OF_LIST() |
618 | d5b61ddd | Jan Kiszka | } |
619 | d5b61ddd | Jan Kiszka | }; |
620 | d5b61ddd | Jan Kiszka | |
621 | d5b61ddd | Jan Kiszka | static SysBusDeviceInfo musicpal_lcd_info = {
|
622 | d5b61ddd | Jan Kiszka | .init = musicpal_lcd_init, |
623 | d5b61ddd | Jan Kiszka | .qdev.name = "musicpal_lcd",
|
624 | d5b61ddd | Jan Kiszka | .qdev.size = sizeof(musicpal_lcd_state),
|
625 | d5b61ddd | Jan Kiszka | .qdev.vmsd = &musicpal_lcd_vmsd, |
626 | d5b61ddd | Jan Kiszka | }; |
627 | d5b61ddd | Jan Kiszka | |
628 | 24859b68 | balrog | /* PIC register offsets */
|
629 | 24859b68 | balrog | #define MP_PIC_STATUS 0x00 |
630 | 24859b68 | balrog | #define MP_PIC_ENABLE_SET 0x08 |
631 | 24859b68 | balrog | #define MP_PIC_ENABLE_CLR 0x0C |
632 | 24859b68 | balrog | |
633 | 24859b68 | balrog | typedef struct mv88w8618_pic_state |
634 | 24859b68 | balrog | { |
635 | b47b50fa | Paul Brook | SysBusDevice busdev; |
636 | 24859b68 | balrog | uint32_t level; |
637 | 24859b68 | balrog | uint32_t enabled; |
638 | 24859b68 | balrog | qemu_irq parent_irq; |
639 | 24859b68 | balrog | } mv88w8618_pic_state; |
640 | 24859b68 | balrog | |
641 | 24859b68 | balrog | static void mv88w8618_pic_update(mv88w8618_pic_state *s) |
642 | 24859b68 | balrog | { |
643 | 24859b68 | balrog | qemu_set_irq(s->parent_irq, (s->level & s->enabled)); |
644 | 24859b68 | balrog | } |
645 | 24859b68 | balrog | |
646 | 24859b68 | balrog | static void mv88w8618_pic_set_irq(void *opaque, int irq, int level) |
647 | 24859b68 | balrog | { |
648 | 24859b68 | balrog | mv88w8618_pic_state *s = opaque; |
649 | 24859b68 | balrog | |
650 | 49fedd0d | Jan Kiszka | if (level) {
|
651 | 24859b68 | balrog | s->level |= 1 << irq;
|
652 | 49fedd0d | Jan Kiszka | } else {
|
653 | 24859b68 | balrog | s->level &= ~(1 << irq);
|
654 | 49fedd0d | Jan Kiszka | } |
655 | 24859b68 | balrog | mv88w8618_pic_update(s); |
656 | 24859b68 | balrog | } |
657 | 24859b68 | balrog | |
658 | c227f099 | Anthony Liguori | static uint32_t mv88w8618_pic_read(void *opaque, target_phys_addr_t offset) |
659 | 24859b68 | balrog | { |
660 | 24859b68 | balrog | mv88w8618_pic_state *s = opaque; |
661 | 24859b68 | balrog | |
662 | 24859b68 | balrog | switch (offset) {
|
663 | 24859b68 | balrog | case MP_PIC_STATUS:
|
664 | 24859b68 | balrog | return s->level & s->enabled;
|
665 | 24859b68 | balrog | |
666 | 24859b68 | balrog | default:
|
667 | 24859b68 | balrog | return 0; |
668 | 24859b68 | balrog | } |
669 | 24859b68 | balrog | } |
670 | 24859b68 | balrog | |
671 | c227f099 | Anthony Liguori | static void mv88w8618_pic_write(void *opaque, target_phys_addr_t offset, |
672 | 24859b68 | balrog | uint32_t value) |
673 | 24859b68 | balrog | { |
674 | 24859b68 | balrog | mv88w8618_pic_state *s = opaque; |
675 | 24859b68 | balrog | |
676 | 24859b68 | balrog | switch (offset) {
|
677 | 24859b68 | balrog | case MP_PIC_ENABLE_SET:
|
678 | 24859b68 | balrog | s->enabled |= value; |
679 | 24859b68 | balrog | break;
|
680 | 24859b68 | balrog | |
681 | 24859b68 | balrog | case MP_PIC_ENABLE_CLR:
|
682 | 24859b68 | balrog | s->enabled &= ~value; |
683 | 24859b68 | balrog | s->level &= ~value; |
684 | 24859b68 | balrog | break;
|
685 | 24859b68 | balrog | } |
686 | 24859b68 | balrog | mv88w8618_pic_update(s); |
687 | 24859b68 | balrog | } |
688 | 24859b68 | balrog | |
689 | d5b61ddd | Jan Kiszka | static void mv88w8618_pic_reset(DeviceState *d) |
690 | 24859b68 | balrog | { |
691 | d5b61ddd | Jan Kiszka | mv88w8618_pic_state *s = FROM_SYSBUS(mv88w8618_pic_state, |
692 | d5b61ddd | Jan Kiszka | sysbus_from_qdev(d)); |
693 | 24859b68 | balrog | |
694 | 24859b68 | balrog | s->level = 0;
|
695 | 24859b68 | balrog | s->enabled = 0;
|
696 | 24859b68 | balrog | } |
697 | 24859b68 | balrog | |
698 | d60efc6b | Blue Swirl | static CPUReadMemoryFunc * const mv88w8618_pic_readfn[] = { |
699 | 24859b68 | balrog | mv88w8618_pic_read, |
700 | 24859b68 | balrog | mv88w8618_pic_read, |
701 | 24859b68 | balrog | mv88w8618_pic_read |
702 | 24859b68 | balrog | }; |
703 | 24859b68 | balrog | |
704 | d60efc6b | Blue Swirl | static CPUWriteMemoryFunc * const mv88w8618_pic_writefn[] = { |
705 | 24859b68 | balrog | mv88w8618_pic_write, |
706 | 24859b68 | balrog | mv88w8618_pic_write, |
707 | 24859b68 | balrog | mv88w8618_pic_write |
708 | 24859b68 | balrog | }; |
709 | 24859b68 | balrog | |
710 | 81a322d4 | Gerd Hoffmann | static int mv88w8618_pic_init(SysBusDevice *dev) |
711 | 24859b68 | balrog | { |
712 | b47b50fa | Paul Brook | mv88w8618_pic_state *s = FROM_SYSBUS(mv88w8618_pic_state, dev); |
713 | 24859b68 | balrog | int iomemtype;
|
714 | 24859b68 | balrog | |
715 | 067a3ddc | Paul Brook | qdev_init_gpio_in(&dev->qdev, mv88w8618_pic_set_irq, 32);
|
716 | b47b50fa | Paul Brook | sysbus_init_irq(dev, &s->parent_irq); |
717 | 1eed09cb | Avi Kivity | iomemtype = cpu_register_io_memory(mv88w8618_pic_readfn, |
718 | 24859b68 | balrog | mv88w8618_pic_writefn, s); |
719 | b47b50fa | Paul Brook | sysbus_init_mmio(dev, MP_PIC_SIZE, iomemtype); |
720 | 81a322d4 | Gerd Hoffmann | return 0; |
721 | 24859b68 | balrog | } |
722 | 24859b68 | balrog | |
723 | d5b61ddd | Jan Kiszka | static const VMStateDescription mv88w8618_pic_vmsd = { |
724 | d5b61ddd | Jan Kiszka | .name = "mv88w8618_pic",
|
725 | d5b61ddd | Jan Kiszka | .version_id = 1,
|
726 | d5b61ddd | Jan Kiszka | .minimum_version_id = 1,
|
727 | d5b61ddd | Jan Kiszka | .minimum_version_id_old = 1,
|
728 | d5b61ddd | Jan Kiszka | .fields = (VMStateField[]) { |
729 | d5b61ddd | Jan Kiszka | VMSTATE_UINT32(level, mv88w8618_pic_state), |
730 | d5b61ddd | Jan Kiszka | VMSTATE_UINT32(enabled, mv88w8618_pic_state), |
731 | d5b61ddd | Jan Kiszka | VMSTATE_END_OF_LIST() |
732 | d5b61ddd | Jan Kiszka | } |
733 | d5b61ddd | Jan Kiszka | }; |
734 | d5b61ddd | Jan Kiszka | |
735 | d5b61ddd | Jan Kiszka | static SysBusDeviceInfo mv88w8618_pic_info = {
|
736 | d5b61ddd | Jan Kiszka | .init = mv88w8618_pic_init, |
737 | d5b61ddd | Jan Kiszka | .qdev.name = "mv88w8618_pic",
|
738 | d5b61ddd | Jan Kiszka | .qdev.size = sizeof(mv88w8618_pic_state),
|
739 | d5b61ddd | Jan Kiszka | .qdev.reset = mv88w8618_pic_reset, |
740 | d5b61ddd | Jan Kiszka | .qdev.vmsd = &mv88w8618_pic_vmsd, |
741 | d5b61ddd | Jan Kiszka | }; |
742 | d5b61ddd | Jan Kiszka | |
743 | 24859b68 | balrog | /* PIT register offsets */
|
744 | 24859b68 | balrog | #define MP_PIT_TIMER1_LENGTH 0x00 |
745 | 24859b68 | balrog | /* ... */
|
746 | 24859b68 | balrog | #define MP_PIT_TIMER4_LENGTH 0x0C |
747 | 24859b68 | balrog | #define MP_PIT_CONTROL 0x10 |
748 | 24859b68 | balrog | #define MP_PIT_TIMER1_VALUE 0x14 |
749 | 24859b68 | balrog | /* ... */
|
750 | 24859b68 | balrog | #define MP_PIT_TIMER4_VALUE 0x20 |
751 | 24859b68 | balrog | #define MP_BOARD_RESET 0x34 |
752 | 24859b68 | balrog | |
753 | 24859b68 | balrog | /* Magic board reset value (probably some watchdog behind it) */
|
754 | 24859b68 | balrog | #define MP_BOARD_RESET_MAGIC 0x10000 |
755 | 24859b68 | balrog | |
756 | 24859b68 | balrog | typedef struct mv88w8618_timer_state { |
757 | b47b50fa | Paul Brook | ptimer_state *ptimer; |
758 | 24859b68 | balrog | uint32_t limit; |
759 | 24859b68 | balrog | int freq;
|
760 | 24859b68 | balrog | qemu_irq irq; |
761 | 24859b68 | balrog | } mv88w8618_timer_state; |
762 | 24859b68 | balrog | |
763 | 24859b68 | balrog | typedef struct mv88w8618_pit_state { |
764 | b47b50fa | Paul Brook | SysBusDevice busdev; |
765 | b47b50fa | Paul Brook | mv88w8618_timer_state timer[4];
|
766 | 24859b68 | balrog | } mv88w8618_pit_state; |
767 | 24859b68 | balrog | |
768 | 24859b68 | balrog | static void mv88w8618_timer_tick(void *opaque) |
769 | 24859b68 | balrog | { |
770 | 24859b68 | balrog | mv88w8618_timer_state *s = opaque; |
771 | 24859b68 | balrog | |
772 | 24859b68 | balrog | qemu_irq_raise(s->irq); |
773 | 24859b68 | balrog | } |
774 | 24859b68 | balrog | |
775 | b47b50fa | Paul Brook | static void mv88w8618_timer_init(SysBusDevice *dev, mv88w8618_timer_state *s, |
776 | b47b50fa | Paul Brook | uint32_t freq) |
777 | 24859b68 | balrog | { |
778 | 24859b68 | balrog | QEMUBH *bh; |
779 | 24859b68 | balrog | |
780 | b47b50fa | Paul Brook | sysbus_init_irq(dev, &s->irq); |
781 | 24859b68 | balrog | s->freq = freq; |
782 | 24859b68 | balrog | |
783 | 24859b68 | balrog | bh = qemu_bh_new(mv88w8618_timer_tick, s); |
784 | b47b50fa | Paul Brook | s->ptimer = ptimer_init(bh); |
785 | 24859b68 | balrog | } |
786 | 24859b68 | balrog | |
787 | c227f099 | Anthony Liguori | static uint32_t mv88w8618_pit_read(void *opaque, target_phys_addr_t offset) |
788 | 24859b68 | balrog | { |
789 | 24859b68 | balrog | mv88w8618_pit_state *s = opaque; |
790 | 24859b68 | balrog | mv88w8618_timer_state *t; |
791 | 24859b68 | balrog | |
792 | 24859b68 | balrog | switch (offset) {
|
793 | 24859b68 | balrog | case MP_PIT_TIMER1_VALUE ... MP_PIT_TIMER4_VALUE:
|
794 | b47b50fa | Paul Brook | t = &s->timer[(offset-MP_PIT_TIMER1_VALUE) >> 2];
|
795 | b47b50fa | Paul Brook | return ptimer_get_count(t->ptimer);
|
796 | 24859b68 | balrog | |
797 | 24859b68 | balrog | default:
|
798 | 24859b68 | balrog | return 0; |
799 | 24859b68 | balrog | } |
800 | 24859b68 | balrog | } |
801 | 24859b68 | balrog | |
802 | c227f099 | Anthony Liguori | static void mv88w8618_pit_write(void *opaque, target_phys_addr_t offset, |
803 | 24859b68 | balrog | uint32_t value) |
804 | 24859b68 | balrog | { |
805 | 24859b68 | balrog | mv88w8618_pit_state *s = opaque; |
806 | 24859b68 | balrog | mv88w8618_timer_state *t; |
807 | 24859b68 | balrog | int i;
|
808 | 24859b68 | balrog | |
809 | 24859b68 | balrog | switch (offset) {
|
810 | 24859b68 | balrog | case MP_PIT_TIMER1_LENGTH ... MP_PIT_TIMER4_LENGTH:
|
811 | b47b50fa | Paul Brook | t = &s->timer[offset >> 2];
|
812 | 24859b68 | balrog | t->limit = value; |
813 | c88d6bde | Jan Kiszka | if (t->limit > 0) { |
814 | c88d6bde | Jan Kiszka | ptimer_set_limit(t->ptimer, t->limit, 1);
|
815 | c88d6bde | Jan Kiszka | } else {
|
816 | c88d6bde | Jan Kiszka | ptimer_stop(t->ptimer); |
817 | c88d6bde | Jan Kiszka | } |
818 | 24859b68 | balrog | break;
|
819 | 24859b68 | balrog | |
820 | 24859b68 | balrog | case MP_PIT_CONTROL:
|
821 | 24859b68 | balrog | for (i = 0; i < 4; i++) { |
822 | c88d6bde | Jan Kiszka | t = &s->timer[i]; |
823 | c88d6bde | Jan Kiszka | if (value & 0xf && t->limit > 0) { |
824 | b47b50fa | Paul Brook | ptimer_set_limit(t->ptimer, t->limit, 0);
|
825 | b47b50fa | Paul Brook | ptimer_set_freq(t->ptimer, t->freq); |
826 | b47b50fa | Paul Brook | ptimer_run(t->ptimer, 0);
|
827 | c88d6bde | Jan Kiszka | } else {
|
828 | c88d6bde | Jan Kiszka | ptimer_stop(t->ptimer); |
829 | 24859b68 | balrog | } |
830 | 24859b68 | balrog | value >>= 4;
|
831 | 24859b68 | balrog | } |
832 | 24859b68 | balrog | break;
|
833 | 24859b68 | balrog | |
834 | 24859b68 | balrog | case MP_BOARD_RESET:
|
835 | 49fedd0d | Jan Kiszka | if (value == MP_BOARD_RESET_MAGIC) {
|
836 | 24859b68 | balrog | qemu_system_reset_request(); |
837 | 49fedd0d | Jan Kiszka | } |
838 | 24859b68 | balrog | break;
|
839 | 24859b68 | balrog | } |
840 | 24859b68 | balrog | } |
841 | 24859b68 | balrog | |
842 | d5b61ddd | Jan Kiszka | static void mv88w8618_pit_reset(DeviceState *d) |
843 | c88d6bde | Jan Kiszka | { |
844 | d5b61ddd | Jan Kiszka | mv88w8618_pit_state *s = FROM_SYSBUS(mv88w8618_pit_state, |
845 | d5b61ddd | Jan Kiszka | sysbus_from_qdev(d)); |
846 | c88d6bde | Jan Kiszka | int i;
|
847 | c88d6bde | Jan Kiszka | |
848 | c88d6bde | Jan Kiszka | for (i = 0; i < 4; i++) { |
849 | c88d6bde | Jan Kiszka | ptimer_stop(s->timer[i].ptimer); |
850 | c88d6bde | Jan Kiszka | s->timer[i].limit = 0;
|
851 | c88d6bde | Jan Kiszka | } |
852 | c88d6bde | Jan Kiszka | } |
853 | c88d6bde | Jan Kiszka | |
854 | d60efc6b | Blue Swirl | static CPUReadMemoryFunc * const mv88w8618_pit_readfn[] = { |
855 | 24859b68 | balrog | mv88w8618_pit_read, |
856 | 24859b68 | balrog | mv88w8618_pit_read, |
857 | 24859b68 | balrog | mv88w8618_pit_read |
858 | 24859b68 | balrog | }; |
859 | 24859b68 | balrog | |
860 | d60efc6b | Blue Swirl | static CPUWriteMemoryFunc * const mv88w8618_pit_writefn[] = { |
861 | 24859b68 | balrog | mv88w8618_pit_write, |
862 | 24859b68 | balrog | mv88w8618_pit_write, |
863 | 24859b68 | balrog | mv88w8618_pit_write |
864 | 24859b68 | balrog | }; |
865 | 24859b68 | balrog | |
866 | 81a322d4 | Gerd Hoffmann | static int mv88w8618_pit_init(SysBusDevice *dev) |
867 | 24859b68 | balrog | { |
868 | 24859b68 | balrog | int iomemtype;
|
869 | b47b50fa | Paul Brook | mv88w8618_pit_state *s = FROM_SYSBUS(mv88w8618_pit_state, dev); |
870 | b47b50fa | Paul Brook | int i;
|
871 | 24859b68 | balrog | |
872 | 24859b68 | balrog | /* Letting them all run at 1 MHz is likely just a pragmatic
|
873 | 24859b68 | balrog | * simplification. */
|
874 | b47b50fa | Paul Brook | for (i = 0; i < 4; i++) { |
875 | b47b50fa | Paul Brook | mv88w8618_timer_init(dev, &s->timer[i], 1000000);
|
876 | b47b50fa | Paul Brook | } |
877 | 24859b68 | balrog | |
878 | 1eed09cb | Avi Kivity | iomemtype = cpu_register_io_memory(mv88w8618_pit_readfn, |
879 | 24859b68 | balrog | mv88w8618_pit_writefn, s); |
880 | b47b50fa | Paul Brook | sysbus_init_mmio(dev, MP_PIT_SIZE, iomemtype); |
881 | 81a322d4 | Gerd Hoffmann | return 0; |
882 | 24859b68 | balrog | } |
883 | 24859b68 | balrog | |
884 | d5b61ddd | Jan Kiszka | static const VMStateDescription mv88w8618_timer_vmsd = { |
885 | d5b61ddd | Jan Kiszka | .name = "timer",
|
886 | d5b61ddd | Jan Kiszka | .version_id = 1,
|
887 | d5b61ddd | Jan Kiszka | .minimum_version_id = 1,
|
888 | d5b61ddd | Jan Kiszka | .minimum_version_id_old = 1,
|
889 | d5b61ddd | Jan Kiszka | .fields = (VMStateField[]) { |
890 | d5b61ddd | Jan Kiszka | VMSTATE_PTIMER(ptimer, mv88w8618_timer_state), |
891 | d5b61ddd | Jan Kiszka | VMSTATE_UINT32(limit, mv88w8618_timer_state), |
892 | d5b61ddd | Jan Kiszka | VMSTATE_END_OF_LIST() |
893 | d5b61ddd | Jan Kiszka | } |
894 | d5b61ddd | Jan Kiszka | }; |
895 | d5b61ddd | Jan Kiszka | |
896 | d5b61ddd | Jan Kiszka | static const VMStateDescription mv88w8618_pit_vmsd = { |
897 | d5b61ddd | Jan Kiszka | .name = "mv88w8618_pit",
|
898 | d5b61ddd | Jan Kiszka | .version_id = 1,
|
899 | d5b61ddd | Jan Kiszka | .minimum_version_id = 1,
|
900 | d5b61ddd | Jan Kiszka | .minimum_version_id_old = 1,
|
901 | d5b61ddd | Jan Kiszka | .fields = (VMStateField[]) { |
902 | d5b61ddd | Jan Kiszka | VMSTATE_STRUCT_ARRAY(timer, mv88w8618_pit_state, 4, 1, |
903 | d5b61ddd | Jan Kiszka | mv88w8618_timer_vmsd, mv88w8618_timer_state), |
904 | d5b61ddd | Jan Kiszka | VMSTATE_END_OF_LIST() |
905 | d5b61ddd | Jan Kiszka | } |
906 | d5b61ddd | Jan Kiszka | }; |
907 | d5b61ddd | Jan Kiszka | |
908 | c88d6bde | Jan Kiszka | static SysBusDeviceInfo mv88w8618_pit_info = {
|
909 | c88d6bde | Jan Kiszka | .init = mv88w8618_pit_init, |
910 | c88d6bde | Jan Kiszka | .qdev.name = "mv88w8618_pit",
|
911 | c88d6bde | Jan Kiszka | .qdev.size = sizeof(mv88w8618_pit_state),
|
912 | c88d6bde | Jan Kiszka | .qdev.reset = mv88w8618_pit_reset, |
913 | d5b61ddd | Jan Kiszka | .qdev.vmsd = &mv88w8618_pit_vmsd, |
914 | c88d6bde | Jan Kiszka | }; |
915 | c88d6bde | Jan Kiszka | |
916 | 24859b68 | balrog | /* Flash config register offsets */
|
917 | 24859b68 | balrog | #define MP_FLASHCFG_CFGR0 0x04 |
918 | 24859b68 | balrog | |
919 | 24859b68 | balrog | typedef struct mv88w8618_flashcfg_state { |
920 | b47b50fa | Paul Brook | SysBusDevice busdev; |
921 | 24859b68 | balrog | uint32_t cfgr0; |
922 | 24859b68 | balrog | } mv88w8618_flashcfg_state; |
923 | 24859b68 | balrog | |
924 | 24859b68 | balrog | static uint32_t mv88w8618_flashcfg_read(void *opaque, |
925 | c227f099 | Anthony Liguori | target_phys_addr_t offset) |
926 | 24859b68 | balrog | { |
927 | 24859b68 | balrog | mv88w8618_flashcfg_state *s = opaque; |
928 | 24859b68 | balrog | |
929 | 24859b68 | balrog | switch (offset) {
|
930 | 24859b68 | balrog | case MP_FLASHCFG_CFGR0:
|
931 | 24859b68 | balrog | return s->cfgr0;
|
932 | 24859b68 | balrog | |
933 | 24859b68 | balrog | default:
|
934 | 24859b68 | balrog | return 0; |
935 | 24859b68 | balrog | } |
936 | 24859b68 | balrog | } |
937 | 24859b68 | balrog | |
938 | c227f099 | Anthony Liguori | static void mv88w8618_flashcfg_write(void *opaque, target_phys_addr_t offset, |
939 | 24859b68 | balrog | uint32_t value) |
940 | 24859b68 | balrog | { |
941 | 24859b68 | balrog | mv88w8618_flashcfg_state *s = opaque; |
942 | 24859b68 | balrog | |
943 | 24859b68 | balrog | switch (offset) {
|
944 | 24859b68 | balrog | case MP_FLASHCFG_CFGR0:
|
945 | 24859b68 | balrog | s->cfgr0 = value; |
946 | 24859b68 | balrog | break;
|
947 | 24859b68 | balrog | } |
948 | 24859b68 | balrog | } |
949 | 24859b68 | balrog | |
950 | d60efc6b | Blue Swirl | static CPUReadMemoryFunc * const mv88w8618_flashcfg_readfn[] = { |
951 | 24859b68 | balrog | mv88w8618_flashcfg_read, |
952 | 24859b68 | balrog | mv88w8618_flashcfg_read, |
953 | 24859b68 | balrog | mv88w8618_flashcfg_read |
954 | 24859b68 | balrog | }; |
955 | 24859b68 | balrog | |
956 | d60efc6b | Blue Swirl | static CPUWriteMemoryFunc * const mv88w8618_flashcfg_writefn[] = { |
957 | 24859b68 | balrog | mv88w8618_flashcfg_write, |
958 | 24859b68 | balrog | mv88w8618_flashcfg_write, |
959 | 24859b68 | balrog | mv88w8618_flashcfg_write |
960 | 24859b68 | balrog | }; |
961 | 24859b68 | balrog | |
962 | 81a322d4 | Gerd Hoffmann | static int mv88w8618_flashcfg_init(SysBusDevice *dev) |
963 | 24859b68 | balrog | { |
964 | 24859b68 | balrog | int iomemtype;
|
965 | b47b50fa | Paul Brook | mv88w8618_flashcfg_state *s = FROM_SYSBUS(mv88w8618_flashcfg_state, dev); |
966 | 24859b68 | balrog | |
967 | 24859b68 | balrog | s->cfgr0 = 0xfffe4285; /* Default as set by U-Boot for 8 MB flash */ |
968 | 1eed09cb | Avi Kivity | iomemtype = cpu_register_io_memory(mv88w8618_flashcfg_readfn, |
969 | 49fedd0d | Jan Kiszka | mv88w8618_flashcfg_writefn, s); |
970 | b47b50fa | Paul Brook | sysbus_init_mmio(dev, MP_FLASHCFG_SIZE, iomemtype); |
971 | 81a322d4 | Gerd Hoffmann | return 0; |
972 | 24859b68 | balrog | } |
973 | 24859b68 | balrog | |
974 | d5b61ddd | Jan Kiszka | static const VMStateDescription mv88w8618_flashcfg_vmsd = { |
975 | d5b61ddd | Jan Kiszka | .name = "mv88w8618_flashcfg",
|
976 | d5b61ddd | Jan Kiszka | .version_id = 1,
|
977 | d5b61ddd | Jan Kiszka | .minimum_version_id = 1,
|
978 | d5b61ddd | Jan Kiszka | .minimum_version_id_old = 1,
|
979 | d5b61ddd | Jan Kiszka | .fields = (VMStateField[]) { |
980 | d5b61ddd | Jan Kiszka | VMSTATE_UINT32(cfgr0, mv88w8618_flashcfg_state), |
981 | d5b61ddd | Jan Kiszka | VMSTATE_END_OF_LIST() |
982 | d5b61ddd | Jan Kiszka | } |
983 | d5b61ddd | Jan Kiszka | }; |
984 | d5b61ddd | Jan Kiszka | |
985 | d5b61ddd | Jan Kiszka | static SysBusDeviceInfo mv88w8618_flashcfg_info = {
|
986 | d5b61ddd | Jan Kiszka | .init = mv88w8618_flashcfg_init, |
987 | d5b61ddd | Jan Kiszka | .qdev.name = "mv88w8618_flashcfg",
|
988 | d5b61ddd | Jan Kiszka | .qdev.size = sizeof(mv88w8618_flashcfg_state),
|
989 | d5b61ddd | Jan Kiszka | .qdev.vmsd = &mv88w8618_flashcfg_vmsd, |
990 | d5b61ddd | Jan Kiszka | }; |
991 | d5b61ddd | Jan Kiszka | |
992 | 718ec0be | malc | /* Misc register offsets */
|
993 | 718ec0be | malc | #define MP_MISC_BOARD_REVISION 0x18 |
994 | 718ec0be | malc | |
995 | 718ec0be | malc | #define MP_BOARD_REVISION 0x31 |
996 | 718ec0be | malc | |
997 | c227f099 | Anthony Liguori | static uint32_t musicpal_misc_read(void *opaque, target_phys_addr_t offset) |
998 | 718ec0be | malc | { |
999 | 718ec0be | malc | switch (offset) {
|
1000 | 718ec0be | malc | case MP_MISC_BOARD_REVISION:
|
1001 | 718ec0be | malc | return MP_BOARD_REVISION;
|
1002 | 718ec0be | malc | |
1003 | 718ec0be | malc | default:
|
1004 | 718ec0be | malc | return 0; |
1005 | 718ec0be | malc | } |
1006 | 718ec0be | malc | } |
1007 | 718ec0be | malc | |
1008 | c227f099 | Anthony Liguori | static void musicpal_misc_write(void *opaque, target_phys_addr_t offset, |
1009 | 718ec0be | malc | uint32_t value) |
1010 | 718ec0be | malc | { |
1011 | 718ec0be | malc | } |
1012 | 718ec0be | malc | |
1013 | d60efc6b | Blue Swirl | static CPUReadMemoryFunc * const musicpal_misc_readfn[] = { |
1014 | 718ec0be | malc | musicpal_misc_read, |
1015 | 718ec0be | malc | musicpal_misc_read, |
1016 | 718ec0be | malc | musicpal_misc_read, |
1017 | 718ec0be | malc | }; |
1018 | 718ec0be | malc | |
1019 | d60efc6b | Blue Swirl | static CPUWriteMemoryFunc * const musicpal_misc_writefn[] = { |
1020 | 718ec0be | malc | musicpal_misc_write, |
1021 | 718ec0be | malc | musicpal_misc_write, |
1022 | 718ec0be | malc | musicpal_misc_write, |
1023 | 718ec0be | malc | }; |
1024 | 718ec0be | malc | |
1025 | 718ec0be | malc | static void musicpal_misc_init(void) |
1026 | 718ec0be | malc | { |
1027 | 718ec0be | malc | int iomemtype;
|
1028 | 718ec0be | malc | |
1029 | 1eed09cb | Avi Kivity | iomemtype = cpu_register_io_memory(musicpal_misc_readfn, |
1030 | 718ec0be | malc | musicpal_misc_writefn, NULL);
|
1031 | 718ec0be | malc | cpu_register_physical_memory(MP_MISC_BASE, MP_MISC_SIZE, iomemtype); |
1032 | 718ec0be | malc | } |
1033 | 718ec0be | malc | |
1034 | 718ec0be | malc | /* WLAN register offsets */
|
1035 | 718ec0be | malc | #define MP_WLAN_MAGIC1 0x11c |
1036 | 718ec0be | malc | #define MP_WLAN_MAGIC2 0x124 |
1037 | 718ec0be | malc | |
1038 | c227f099 | Anthony Liguori | static uint32_t mv88w8618_wlan_read(void *opaque, target_phys_addr_t offset) |
1039 | 718ec0be | malc | { |
1040 | 718ec0be | malc | switch (offset) {
|
1041 | 718ec0be | malc | /* Workaround to allow loading the binary-only wlandrv.ko crap
|
1042 | 718ec0be | malc | * from the original Freecom firmware. */
|
1043 | 718ec0be | malc | case MP_WLAN_MAGIC1:
|
1044 | 718ec0be | malc | return ~3; |
1045 | 718ec0be | malc | case MP_WLAN_MAGIC2:
|
1046 | 718ec0be | malc | return -1; |
1047 | 718ec0be | malc | |
1048 | 718ec0be | malc | default:
|
1049 | 718ec0be | malc | return 0; |
1050 | 718ec0be | malc | } |
1051 | 718ec0be | malc | } |
1052 | 718ec0be | malc | |
1053 | c227f099 | Anthony Liguori | static void mv88w8618_wlan_write(void *opaque, target_phys_addr_t offset, |
1054 | 718ec0be | malc | uint32_t value) |
1055 | 718ec0be | malc | { |
1056 | 718ec0be | malc | } |
1057 | 718ec0be | malc | |
1058 | d60efc6b | Blue Swirl | static CPUReadMemoryFunc * const mv88w8618_wlan_readfn[] = { |
1059 | 718ec0be | malc | mv88w8618_wlan_read, |
1060 | 718ec0be | malc | mv88w8618_wlan_read, |
1061 | 718ec0be | malc | mv88w8618_wlan_read, |
1062 | 718ec0be | malc | }; |
1063 | 718ec0be | malc | |
1064 | d60efc6b | Blue Swirl | static CPUWriteMemoryFunc * const mv88w8618_wlan_writefn[] = { |
1065 | 718ec0be | malc | mv88w8618_wlan_write, |
1066 | 718ec0be | malc | mv88w8618_wlan_write, |
1067 | 718ec0be | malc | mv88w8618_wlan_write, |
1068 | 718ec0be | malc | }; |
1069 | 718ec0be | malc | |
1070 | 81a322d4 | Gerd Hoffmann | static int mv88w8618_wlan_init(SysBusDevice *dev) |
1071 | 718ec0be | malc | { |
1072 | 718ec0be | malc | int iomemtype;
|
1073 | 24859b68 | balrog | |
1074 | 1eed09cb | Avi Kivity | iomemtype = cpu_register_io_memory(mv88w8618_wlan_readfn, |
1075 | 718ec0be | malc | mv88w8618_wlan_writefn, NULL);
|
1076 | b47b50fa | Paul Brook | sysbus_init_mmio(dev, MP_WLAN_SIZE, iomemtype); |
1077 | 81a322d4 | Gerd Hoffmann | return 0; |
1078 | 718ec0be | malc | } |
1079 | 24859b68 | balrog | |
1080 | 718ec0be | malc | /* GPIO register offsets */
|
1081 | 718ec0be | malc | #define MP_GPIO_OE_LO 0x008 |
1082 | 718ec0be | malc | #define MP_GPIO_OUT_LO 0x00c |
1083 | 718ec0be | malc | #define MP_GPIO_IN_LO 0x010 |
1084 | 708afdf3 | Jan Kiszka | #define MP_GPIO_IER_LO 0x014 |
1085 | 708afdf3 | Jan Kiszka | #define MP_GPIO_IMR_LO 0x018 |
1086 | 718ec0be | malc | #define MP_GPIO_ISR_LO 0x020 |
1087 | 718ec0be | malc | #define MP_GPIO_OE_HI 0x508 |
1088 | 718ec0be | malc | #define MP_GPIO_OUT_HI 0x50c |
1089 | 718ec0be | malc | #define MP_GPIO_IN_HI 0x510 |
1090 | 708afdf3 | Jan Kiszka | #define MP_GPIO_IER_HI 0x514 |
1091 | 708afdf3 | Jan Kiszka | #define MP_GPIO_IMR_HI 0x518 |
1092 | 718ec0be | malc | #define MP_GPIO_ISR_HI 0x520 |
1093 | 24859b68 | balrog | |
1094 | 24859b68 | balrog | /* GPIO bits & masks */
|
1095 | 24859b68 | balrog | #define MP_GPIO_LCD_BRIGHTNESS 0x00070000 |
1096 | 24859b68 | balrog | #define MP_GPIO_I2C_DATA_BIT 29 |
1097 | 24859b68 | balrog | #define MP_GPIO_I2C_CLOCK_BIT 30 |
1098 | 24859b68 | balrog | |
1099 | 24859b68 | balrog | /* LCD brightness bits in GPIO_OE_HI */
|
1100 | 24859b68 | balrog | #define MP_OE_LCD_BRIGHTNESS 0x0007 |
1101 | 24859b68 | balrog | |
1102 | 343ec8e4 | Benoit Canet | typedef struct musicpal_gpio_state { |
1103 | 343ec8e4 | Benoit Canet | SysBusDevice busdev; |
1104 | 343ec8e4 | Benoit Canet | uint32_t lcd_brightness; |
1105 | 343ec8e4 | Benoit Canet | uint32_t out_state; |
1106 | 343ec8e4 | Benoit Canet | uint32_t in_state; |
1107 | 708afdf3 | Jan Kiszka | uint32_t ier; |
1108 | 708afdf3 | Jan Kiszka | uint32_t imr; |
1109 | 343ec8e4 | Benoit Canet | uint32_t isr; |
1110 | 343ec8e4 | Benoit Canet | qemu_irq irq; |
1111 | 708afdf3 | Jan Kiszka | qemu_irq out[5]; /* 3 brightness out + 2 lcd (data and clock ) */ |
1112 | 343ec8e4 | Benoit Canet | } musicpal_gpio_state; |
1113 | 343ec8e4 | Benoit Canet | |
1114 | 343ec8e4 | Benoit Canet | static void musicpal_gpio_brightness_update(musicpal_gpio_state *s) { |
1115 | 343ec8e4 | Benoit Canet | int i;
|
1116 | 343ec8e4 | Benoit Canet | uint32_t brightness; |
1117 | 343ec8e4 | Benoit Canet | |
1118 | 343ec8e4 | Benoit Canet | /* compute brightness ratio */
|
1119 | 343ec8e4 | Benoit Canet | switch (s->lcd_brightness) {
|
1120 | 343ec8e4 | Benoit Canet | case 0x00000007: |
1121 | 343ec8e4 | Benoit Canet | brightness = 0;
|
1122 | 343ec8e4 | Benoit Canet | break;
|
1123 | 343ec8e4 | Benoit Canet | |
1124 | 343ec8e4 | Benoit Canet | case 0x00020000: |
1125 | 343ec8e4 | Benoit Canet | brightness = 1;
|
1126 | 343ec8e4 | Benoit Canet | break;
|
1127 | 343ec8e4 | Benoit Canet | |
1128 | 343ec8e4 | Benoit Canet | case 0x00020001: |
1129 | 343ec8e4 | Benoit Canet | brightness = 2;
|
1130 | 343ec8e4 | Benoit Canet | break;
|
1131 | 343ec8e4 | Benoit Canet | |
1132 | 343ec8e4 | Benoit Canet | case 0x00040000: |
1133 | 343ec8e4 | Benoit Canet | brightness = 3;
|
1134 | 343ec8e4 | Benoit Canet | break;
|
1135 | 343ec8e4 | Benoit Canet | |
1136 | 343ec8e4 | Benoit Canet | case 0x00010006: |
1137 | 343ec8e4 | Benoit Canet | brightness = 4;
|
1138 | 343ec8e4 | Benoit Canet | break;
|
1139 | 343ec8e4 | Benoit Canet | |
1140 | 343ec8e4 | Benoit Canet | case 0x00020005: |
1141 | 343ec8e4 | Benoit Canet | brightness = 5;
|
1142 | 343ec8e4 | Benoit Canet | break;
|
1143 | 343ec8e4 | Benoit Canet | |
1144 | 343ec8e4 | Benoit Canet | case 0x00040003: |
1145 | 343ec8e4 | Benoit Canet | brightness = 6;
|
1146 | 343ec8e4 | Benoit Canet | break;
|
1147 | 343ec8e4 | Benoit Canet | |
1148 | 343ec8e4 | Benoit Canet | case 0x00030004: |
1149 | 343ec8e4 | Benoit Canet | default:
|
1150 | 343ec8e4 | Benoit Canet | brightness = 7;
|
1151 | 343ec8e4 | Benoit Canet | } |
1152 | 343ec8e4 | Benoit Canet | |
1153 | 343ec8e4 | Benoit Canet | /* set lcd brightness GPIOs */
|
1154 | 49fedd0d | Jan Kiszka | for (i = 0; i <= 2; i++) { |
1155 | 343ec8e4 | Benoit Canet | qemu_set_irq(s->out[i], (brightness >> i) & 1);
|
1156 | 49fedd0d | Jan Kiszka | } |
1157 | 343ec8e4 | Benoit Canet | } |
1158 | 343ec8e4 | Benoit Canet | |
1159 | 708afdf3 | Jan Kiszka | static void musicpal_gpio_pin_event(void *opaque, int pin, int level) |
1160 | 343ec8e4 | Benoit Canet | { |
1161 | 243cd13c | Jan Kiszka | musicpal_gpio_state *s = opaque; |
1162 | 708afdf3 | Jan Kiszka | uint32_t mask = 1 << pin;
|
1163 | 708afdf3 | Jan Kiszka | uint32_t delta = level << pin; |
1164 | 708afdf3 | Jan Kiszka | uint32_t old = s->in_state & mask; |
1165 | 343ec8e4 | Benoit Canet | |
1166 | 708afdf3 | Jan Kiszka | s->in_state &= ~mask; |
1167 | 708afdf3 | Jan Kiszka | s->in_state |= delta; |
1168 | 343ec8e4 | Benoit Canet | |
1169 | 708afdf3 | Jan Kiszka | if ((old ^ delta) &&
|
1170 | 708afdf3 | Jan Kiszka | ((level && (s->imr & mask)) || (!level && (s->ier & mask)))) { |
1171 | 708afdf3 | Jan Kiszka | s->isr = mask; |
1172 | 708afdf3 | Jan Kiszka | qemu_irq_raise(s->irq); |
1173 | 343ec8e4 | Benoit Canet | } |
1174 | 343ec8e4 | Benoit Canet | } |
1175 | 343ec8e4 | Benoit Canet | |
1176 | c227f099 | Anthony Liguori | static uint32_t musicpal_gpio_read(void *opaque, target_phys_addr_t offset) |
1177 | 24859b68 | balrog | { |
1178 | 243cd13c | Jan Kiszka | musicpal_gpio_state *s = opaque; |
1179 | 343ec8e4 | Benoit Canet | |
1180 | 24859b68 | balrog | switch (offset) {
|
1181 | 24859b68 | balrog | case MP_GPIO_OE_HI: /* used for LCD brightness control */ |
1182 | 343ec8e4 | Benoit Canet | return s->lcd_brightness & MP_OE_LCD_BRIGHTNESS;
|
1183 | 24859b68 | balrog | |
1184 | 24859b68 | balrog | case MP_GPIO_OUT_LO:
|
1185 | 343ec8e4 | Benoit Canet | return s->out_state & 0xFFFF; |
1186 | 24859b68 | balrog | case MP_GPIO_OUT_HI:
|
1187 | 343ec8e4 | Benoit Canet | return s->out_state >> 16; |
1188 | 24859b68 | balrog | |
1189 | 24859b68 | balrog | case MP_GPIO_IN_LO:
|
1190 | 343ec8e4 | Benoit Canet | return s->in_state & 0xFFFF; |
1191 | 24859b68 | balrog | case MP_GPIO_IN_HI:
|
1192 | 343ec8e4 | Benoit Canet | return s->in_state >> 16; |
1193 | 24859b68 | balrog | |
1194 | 708afdf3 | Jan Kiszka | case MP_GPIO_IER_LO:
|
1195 | 708afdf3 | Jan Kiszka | return s->ier & 0xFFFF; |
1196 | 708afdf3 | Jan Kiszka | case MP_GPIO_IER_HI:
|
1197 | 708afdf3 | Jan Kiszka | return s->ier >> 16; |
1198 | 708afdf3 | Jan Kiszka | |
1199 | 708afdf3 | Jan Kiszka | case MP_GPIO_IMR_LO:
|
1200 | 708afdf3 | Jan Kiszka | return s->imr & 0xFFFF; |
1201 | 708afdf3 | Jan Kiszka | case MP_GPIO_IMR_HI:
|
1202 | 708afdf3 | Jan Kiszka | return s->imr >> 16; |
1203 | 708afdf3 | Jan Kiszka | |
1204 | 24859b68 | balrog | case MP_GPIO_ISR_LO:
|
1205 | 343ec8e4 | Benoit Canet | return s->isr & 0xFFFF; |
1206 | 24859b68 | balrog | case MP_GPIO_ISR_HI:
|
1207 | 343ec8e4 | Benoit Canet | return s->isr >> 16; |
1208 | 24859b68 | balrog | |
1209 | 24859b68 | balrog | default:
|
1210 | 24859b68 | balrog | return 0; |
1211 | 24859b68 | balrog | } |
1212 | 24859b68 | balrog | } |
1213 | 24859b68 | balrog | |
1214 | c227f099 | Anthony Liguori | static void musicpal_gpio_write(void *opaque, target_phys_addr_t offset, |
1215 | 718ec0be | malc | uint32_t value) |
1216 | 24859b68 | balrog | { |
1217 | 243cd13c | Jan Kiszka | musicpal_gpio_state *s = opaque; |
1218 | 24859b68 | balrog | switch (offset) {
|
1219 | 24859b68 | balrog | case MP_GPIO_OE_HI: /* used for LCD brightness control */ |
1220 | 343ec8e4 | Benoit Canet | s->lcd_brightness = (s->lcd_brightness & MP_GPIO_LCD_BRIGHTNESS) | |
1221 | 24859b68 | balrog | (value & MP_OE_LCD_BRIGHTNESS); |
1222 | 343ec8e4 | Benoit Canet | musicpal_gpio_brightness_update(s); |
1223 | 24859b68 | balrog | break;
|
1224 | 24859b68 | balrog | |
1225 | 24859b68 | balrog | case MP_GPIO_OUT_LO:
|
1226 | 343ec8e4 | Benoit Canet | s->out_state = (s->out_state & 0xFFFF0000) | (value & 0xFFFF); |
1227 | 24859b68 | balrog | break;
|
1228 | 24859b68 | balrog | case MP_GPIO_OUT_HI:
|
1229 | 343ec8e4 | Benoit Canet | s->out_state = (s->out_state & 0xFFFF) | (value << 16); |
1230 | 343ec8e4 | Benoit Canet | s->lcd_brightness = (s->lcd_brightness & 0xFFFF) |
|
1231 | 343ec8e4 | Benoit Canet | (s->out_state & MP_GPIO_LCD_BRIGHTNESS); |
1232 | 343ec8e4 | Benoit Canet | musicpal_gpio_brightness_update(s); |
1233 | d074769c | Andrzej Zaborowski | qemu_set_irq(s->out[3], (s->out_state >> MP_GPIO_I2C_DATA_BIT) & 1); |
1234 | d074769c | Andrzej Zaborowski | qemu_set_irq(s->out[4], (s->out_state >> MP_GPIO_I2C_CLOCK_BIT) & 1); |
1235 | 24859b68 | balrog | break;
|
1236 | 24859b68 | balrog | |
1237 | 708afdf3 | Jan Kiszka | case MP_GPIO_IER_LO:
|
1238 | 708afdf3 | Jan Kiszka | s->ier = (s->ier & 0xFFFF0000) | (value & 0xFFFF); |
1239 | 708afdf3 | Jan Kiszka | break;
|
1240 | 708afdf3 | Jan Kiszka | case MP_GPIO_IER_HI:
|
1241 | 708afdf3 | Jan Kiszka | s->ier = (s->ier & 0xFFFF) | (value << 16); |
1242 | 708afdf3 | Jan Kiszka | break;
|
1243 | 708afdf3 | Jan Kiszka | |
1244 | 708afdf3 | Jan Kiszka | case MP_GPIO_IMR_LO:
|
1245 | 708afdf3 | Jan Kiszka | s->imr = (s->imr & 0xFFFF0000) | (value & 0xFFFF); |
1246 | 708afdf3 | Jan Kiszka | break;
|
1247 | 708afdf3 | Jan Kiszka | case MP_GPIO_IMR_HI:
|
1248 | 708afdf3 | Jan Kiszka | s->imr = (s->imr & 0xFFFF) | (value << 16); |
1249 | 708afdf3 | Jan Kiszka | break;
|
1250 | 24859b68 | balrog | } |
1251 | 24859b68 | balrog | } |
1252 | 24859b68 | balrog | |
1253 | d60efc6b | Blue Swirl | static CPUReadMemoryFunc * const musicpal_gpio_readfn[] = { |
1254 | 718ec0be | malc | musicpal_gpio_read, |
1255 | 718ec0be | malc | musicpal_gpio_read, |
1256 | 718ec0be | malc | musicpal_gpio_read, |
1257 | 718ec0be | malc | }; |
1258 | 718ec0be | malc | |
1259 | d60efc6b | Blue Swirl | static CPUWriteMemoryFunc * const musicpal_gpio_writefn[] = { |
1260 | 718ec0be | malc | musicpal_gpio_write, |
1261 | 718ec0be | malc | musicpal_gpio_write, |
1262 | 718ec0be | malc | musicpal_gpio_write, |
1263 | 718ec0be | malc | }; |
1264 | 718ec0be | malc | |
1265 | d5b61ddd | Jan Kiszka | static void musicpal_gpio_reset(DeviceState *d) |
1266 | 718ec0be | malc | { |
1267 | d5b61ddd | Jan Kiszka | musicpal_gpio_state *s = FROM_SYSBUS(musicpal_gpio_state, |
1268 | d5b61ddd | Jan Kiszka | sysbus_from_qdev(d)); |
1269 | 30624c92 | Jan Kiszka | |
1270 | 30624c92 | Jan Kiszka | s->lcd_brightness = 0;
|
1271 | 30624c92 | Jan Kiszka | s->out_state = 0;
|
1272 | 343ec8e4 | Benoit Canet | s->in_state = 0xffffffff;
|
1273 | 708afdf3 | Jan Kiszka | s->ier = 0;
|
1274 | 708afdf3 | Jan Kiszka | s->imr = 0;
|
1275 | 343ec8e4 | Benoit Canet | s->isr = 0;
|
1276 | 343ec8e4 | Benoit Canet | } |
1277 | 343ec8e4 | Benoit Canet | |
1278 | 81a322d4 | Gerd Hoffmann | static int musicpal_gpio_init(SysBusDevice *dev) |
1279 | 343ec8e4 | Benoit Canet | { |
1280 | 343ec8e4 | Benoit Canet | musicpal_gpio_state *s = FROM_SYSBUS(musicpal_gpio_state, dev); |
1281 | 718ec0be | malc | int iomemtype;
|
1282 | 718ec0be | malc | |
1283 | 343ec8e4 | Benoit Canet | sysbus_init_irq(dev, &s->irq); |
1284 | 343ec8e4 | Benoit Canet | |
1285 | 1eed09cb | Avi Kivity | iomemtype = cpu_register_io_memory(musicpal_gpio_readfn, |
1286 | 343ec8e4 | Benoit Canet | musicpal_gpio_writefn, s); |
1287 | 343ec8e4 | Benoit Canet | sysbus_init_mmio(dev, MP_GPIO_SIZE, iomemtype); |
1288 | 343ec8e4 | Benoit Canet | |
1289 | d5b61ddd | Jan Kiszka | musicpal_gpio_reset(&dev->qdev); |
1290 | 343ec8e4 | Benoit Canet | |
1291 | 708afdf3 | Jan Kiszka | qdev_init_gpio_out(&dev->qdev, s->out, ARRAY_SIZE(s->out)); |
1292 | 708afdf3 | Jan Kiszka | |
1293 | 708afdf3 | Jan Kiszka | qdev_init_gpio_in(&dev->qdev, musicpal_gpio_pin_event, 32);
|
1294 | 81a322d4 | Gerd Hoffmann | |
1295 | 81a322d4 | Gerd Hoffmann | return 0; |
1296 | 718ec0be | malc | } |
1297 | 718ec0be | malc | |
1298 | d5b61ddd | Jan Kiszka | static const VMStateDescription musicpal_gpio_vmsd = { |
1299 | d5b61ddd | Jan Kiszka | .name = "musicpal_gpio",
|
1300 | d5b61ddd | Jan Kiszka | .version_id = 1,
|
1301 | d5b61ddd | Jan Kiszka | .minimum_version_id = 1,
|
1302 | d5b61ddd | Jan Kiszka | .minimum_version_id_old = 1,
|
1303 | d5b61ddd | Jan Kiszka | .fields = (VMStateField[]) { |
1304 | d5b61ddd | Jan Kiszka | VMSTATE_UINT32(lcd_brightness, musicpal_gpio_state), |
1305 | d5b61ddd | Jan Kiszka | VMSTATE_UINT32(out_state, musicpal_gpio_state), |
1306 | d5b61ddd | Jan Kiszka | VMSTATE_UINT32(in_state, musicpal_gpio_state), |
1307 | d5b61ddd | Jan Kiszka | VMSTATE_UINT32(ier, musicpal_gpio_state), |
1308 | d5b61ddd | Jan Kiszka | VMSTATE_UINT32(imr, musicpal_gpio_state), |
1309 | d5b61ddd | Jan Kiszka | VMSTATE_UINT32(isr, musicpal_gpio_state), |
1310 | d5b61ddd | Jan Kiszka | VMSTATE_END_OF_LIST() |
1311 | d5b61ddd | Jan Kiszka | } |
1312 | d5b61ddd | Jan Kiszka | }; |
1313 | d5b61ddd | Jan Kiszka | |
1314 | 30624c92 | Jan Kiszka | static SysBusDeviceInfo musicpal_gpio_info = {
|
1315 | 30624c92 | Jan Kiszka | .init = musicpal_gpio_init, |
1316 | 30624c92 | Jan Kiszka | .qdev.name = "musicpal_gpio",
|
1317 | 30624c92 | Jan Kiszka | .qdev.size = sizeof(musicpal_gpio_state),
|
1318 | 30624c92 | Jan Kiszka | .qdev.reset = musicpal_gpio_reset, |
1319 | d5b61ddd | Jan Kiszka | .qdev.vmsd = &musicpal_gpio_vmsd, |
1320 | 30624c92 | Jan Kiszka | }; |
1321 | 30624c92 | Jan Kiszka | |
1322 | 24859b68 | balrog | /* Keyboard codes & masks */
|
1323 | 7c6ce4ba | balrog | #define KEY_RELEASED 0x80 |
1324 | 24859b68 | balrog | #define KEY_CODE 0x7f |
1325 | 24859b68 | balrog | |
1326 | 24859b68 | balrog | #define KEYCODE_TAB 0x0f |
1327 | 24859b68 | balrog | #define KEYCODE_ENTER 0x1c |
1328 | 24859b68 | balrog | #define KEYCODE_F 0x21 |
1329 | 24859b68 | balrog | #define KEYCODE_M 0x32 |
1330 | 24859b68 | balrog | |
1331 | 24859b68 | balrog | #define KEYCODE_EXTENDED 0xe0 |
1332 | 24859b68 | balrog | #define KEYCODE_UP 0x48 |
1333 | 24859b68 | balrog | #define KEYCODE_DOWN 0x50 |
1334 | 24859b68 | balrog | #define KEYCODE_LEFT 0x4b |
1335 | 24859b68 | balrog | #define KEYCODE_RIGHT 0x4d |
1336 | 24859b68 | balrog | |
1337 | 708afdf3 | Jan Kiszka | #define MP_KEY_WHEEL_VOL (1 << 0) |
1338 | 343ec8e4 | Benoit Canet | #define MP_KEY_WHEEL_VOL_INV (1 << 1) |
1339 | 343ec8e4 | Benoit Canet | #define MP_KEY_WHEEL_NAV (1 << 2) |
1340 | 343ec8e4 | Benoit Canet | #define MP_KEY_WHEEL_NAV_INV (1 << 3) |
1341 | 343ec8e4 | Benoit Canet | #define MP_KEY_BTN_FAVORITS (1 << 4) |
1342 | 343ec8e4 | Benoit Canet | #define MP_KEY_BTN_MENU (1 << 5) |
1343 | 343ec8e4 | Benoit Canet | #define MP_KEY_BTN_VOLUME (1 << 6) |
1344 | 343ec8e4 | Benoit Canet | #define MP_KEY_BTN_NAVIGATION (1 << 7) |
1345 | 343ec8e4 | Benoit Canet | |
1346 | 343ec8e4 | Benoit Canet | typedef struct musicpal_key_state { |
1347 | 343ec8e4 | Benoit Canet | SysBusDevice busdev; |
1348 | 343ec8e4 | Benoit Canet | uint32_t kbd_extended; |
1349 | 708afdf3 | Jan Kiszka | uint32_t pressed_keys; |
1350 | 708afdf3 | Jan Kiszka | qemu_irq out[8];
|
1351 | 343ec8e4 | Benoit Canet | } musicpal_key_state; |
1352 | 343ec8e4 | Benoit Canet | |
1353 | 24859b68 | balrog | static void musicpal_key_event(void *opaque, int keycode) |
1354 | 24859b68 | balrog | { |
1355 | 243cd13c | Jan Kiszka | musicpal_key_state *s = opaque; |
1356 | 24859b68 | balrog | uint32_t event = 0;
|
1357 | 343ec8e4 | Benoit Canet | int i;
|
1358 | 24859b68 | balrog | |
1359 | 24859b68 | balrog | if (keycode == KEYCODE_EXTENDED) {
|
1360 | 343ec8e4 | Benoit Canet | s->kbd_extended = 1;
|
1361 | 24859b68 | balrog | return;
|
1362 | 24859b68 | balrog | } |
1363 | 24859b68 | balrog | |
1364 | 49fedd0d | Jan Kiszka | if (s->kbd_extended) {
|
1365 | 24859b68 | balrog | switch (keycode & KEY_CODE) {
|
1366 | 24859b68 | balrog | case KEYCODE_UP:
|
1367 | 343ec8e4 | Benoit Canet | event = MP_KEY_WHEEL_NAV | MP_KEY_WHEEL_NAV_INV; |
1368 | 24859b68 | balrog | break;
|
1369 | 24859b68 | balrog | |
1370 | 24859b68 | balrog | case KEYCODE_DOWN:
|
1371 | 343ec8e4 | Benoit Canet | event = MP_KEY_WHEEL_NAV; |
1372 | 24859b68 | balrog | break;
|
1373 | 24859b68 | balrog | |
1374 | 24859b68 | balrog | case KEYCODE_LEFT:
|
1375 | 343ec8e4 | Benoit Canet | event = MP_KEY_WHEEL_VOL | MP_KEY_WHEEL_VOL_INV; |
1376 | 24859b68 | balrog | break;
|
1377 | 24859b68 | balrog | |
1378 | 24859b68 | balrog | case KEYCODE_RIGHT:
|
1379 | 343ec8e4 | Benoit Canet | event = MP_KEY_WHEEL_VOL; |
1380 | 24859b68 | balrog | break;
|
1381 | 24859b68 | balrog | } |
1382 | 49fedd0d | Jan Kiszka | } else {
|
1383 | 24859b68 | balrog | switch (keycode & KEY_CODE) {
|
1384 | 24859b68 | balrog | case KEYCODE_F:
|
1385 | 343ec8e4 | Benoit Canet | event = MP_KEY_BTN_FAVORITS; |
1386 | 24859b68 | balrog | break;
|
1387 | 24859b68 | balrog | |
1388 | 24859b68 | balrog | case KEYCODE_TAB:
|
1389 | 343ec8e4 | Benoit Canet | event = MP_KEY_BTN_VOLUME; |
1390 | 24859b68 | balrog | break;
|
1391 | 24859b68 | balrog | |
1392 | 24859b68 | balrog | case KEYCODE_ENTER:
|
1393 | 343ec8e4 | Benoit Canet | event = MP_KEY_BTN_NAVIGATION; |
1394 | 24859b68 | balrog | break;
|
1395 | 24859b68 | balrog | |
1396 | 24859b68 | balrog | case KEYCODE_M:
|
1397 | 343ec8e4 | Benoit Canet | event = MP_KEY_BTN_MENU; |
1398 | 24859b68 | balrog | break;
|
1399 | 24859b68 | balrog | } |
1400 | 7c6ce4ba | balrog | /* Do not repeat already pressed buttons */
|
1401 | 708afdf3 | Jan Kiszka | if (!(keycode & KEY_RELEASED) && (s->pressed_keys & event)) {
|
1402 | 7c6ce4ba | balrog | event = 0;
|
1403 | 708afdf3 | Jan Kiszka | } |
1404 | 7c6ce4ba | balrog | } |
1405 | 24859b68 | balrog | |
1406 | 7c6ce4ba | balrog | if (event) {
|
1407 | 708afdf3 | Jan Kiszka | /* Raise GPIO pin first if repeating a key */
|
1408 | 708afdf3 | Jan Kiszka | if (!(keycode & KEY_RELEASED) && (s->pressed_keys & event)) {
|
1409 | 708afdf3 | Jan Kiszka | for (i = 0; i <= 7; i++) { |
1410 | 708afdf3 | Jan Kiszka | if (event & (1 << i)) { |
1411 | 708afdf3 | Jan Kiszka | qemu_set_irq(s->out[i], 1);
|
1412 | 708afdf3 | Jan Kiszka | } |
1413 | 708afdf3 | Jan Kiszka | } |
1414 | 708afdf3 | Jan Kiszka | } |
1415 | 708afdf3 | Jan Kiszka | for (i = 0; i <= 7; i++) { |
1416 | 708afdf3 | Jan Kiszka | if (event & (1 << i)) { |
1417 | 708afdf3 | Jan Kiszka | qemu_set_irq(s->out[i], !!(keycode & KEY_RELEASED)); |
1418 | 708afdf3 | Jan Kiszka | } |
1419 | 708afdf3 | Jan Kiszka | } |
1420 | 7c6ce4ba | balrog | if (keycode & KEY_RELEASED) {
|
1421 | 708afdf3 | Jan Kiszka | s->pressed_keys &= ~event; |
1422 | 7c6ce4ba | balrog | } else {
|
1423 | 708afdf3 | Jan Kiszka | s->pressed_keys |= event; |
1424 | 7c6ce4ba | balrog | } |
1425 | 24859b68 | balrog | } |
1426 | 24859b68 | balrog | |
1427 | 343ec8e4 | Benoit Canet | s->kbd_extended = 0;
|
1428 | 343ec8e4 | Benoit Canet | } |
1429 | 343ec8e4 | Benoit Canet | |
1430 | 81a322d4 | Gerd Hoffmann | static int musicpal_key_init(SysBusDevice *dev) |
1431 | 343ec8e4 | Benoit Canet | { |
1432 | 343ec8e4 | Benoit Canet | musicpal_key_state *s = FROM_SYSBUS(musicpal_key_state, dev); |
1433 | 343ec8e4 | Benoit Canet | |
1434 | 343ec8e4 | Benoit Canet | sysbus_init_mmio(dev, 0x0, 0); |
1435 | 343ec8e4 | Benoit Canet | |
1436 | 343ec8e4 | Benoit Canet | s->kbd_extended = 0;
|
1437 | 708afdf3 | Jan Kiszka | s->pressed_keys = 0;
|
1438 | 343ec8e4 | Benoit Canet | |
1439 | 708afdf3 | Jan Kiszka | qdev_init_gpio_out(&dev->qdev, s->out, ARRAY_SIZE(s->out)); |
1440 | 343ec8e4 | Benoit Canet | |
1441 | 343ec8e4 | Benoit Canet | qemu_add_kbd_event_handler(musicpal_key_event, s); |
1442 | 81a322d4 | Gerd Hoffmann | |
1443 | 81a322d4 | Gerd Hoffmann | return 0; |
1444 | 24859b68 | balrog | } |
1445 | 24859b68 | balrog | |
1446 | d5b61ddd | Jan Kiszka | static const VMStateDescription musicpal_key_vmsd = { |
1447 | d5b61ddd | Jan Kiszka | .name = "musicpal_key",
|
1448 | d5b61ddd | Jan Kiszka | .version_id = 1,
|
1449 | d5b61ddd | Jan Kiszka | .minimum_version_id = 1,
|
1450 | d5b61ddd | Jan Kiszka | .minimum_version_id_old = 1,
|
1451 | d5b61ddd | Jan Kiszka | .fields = (VMStateField[]) { |
1452 | d5b61ddd | Jan Kiszka | VMSTATE_UINT32(kbd_extended, musicpal_key_state), |
1453 | d5b61ddd | Jan Kiszka | VMSTATE_UINT32(pressed_keys, musicpal_key_state), |
1454 | d5b61ddd | Jan Kiszka | VMSTATE_END_OF_LIST() |
1455 | d5b61ddd | Jan Kiszka | } |
1456 | d5b61ddd | Jan Kiszka | }; |
1457 | d5b61ddd | Jan Kiszka | |
1458 | d5b61ddd | Jan Kiszka | static SysBusDeviceInfo musicpal_key_info = {
|
1459 | d5b61ddd | Jan Kiszka | .init = musicpal_key_init, |
1460 | d5b61ddd | Jan Kiszka | .qdev.name = "musicpal_key",
|
1461 | d5b61ddd | Jan Kiszka | .qdev.size = sizeof(musicpal_key_state),
|
1462 | d5b61ddd | Jan Kiszka | .qdev.vmsd = &musicpal_key_vmsd, |
1463 | d5b61ddd | Jan Kiszka | }; |
1464 | d5b61ddd | Jan Kiszka | |
1465 | 24859b68 | balrog | static struct arm_boot_info musicpal_binfo = { |
1466 | 24859b68 | balrog | .loader_start = 0x0,
|
1467 | 24859b68 | balrog | .board_id = 0x20e,
|
1468 | 24859b68 | balrog | }; |
1469 | 24859b68 | balrog | |
1470 | c227f099 | Anthony Liguori | static void musicpal_init(ram_addr_t ram_size, |
1471 | 3023f332 | aliguori | const char *boot_device, |
1472 | 24859b68 | balrog | const char *kernel_filename, const char *kernel_cmdline, |
1473 | 24859b68 | balrog | const char *initrd_filename, const char *cpu_model) |
1474 | 24859b68 | balrog | { |
1475 | 24859b68 | balrog | CPUState *env; |
1476 | b47b50fa | Paul Brook | qemu_irq *cpu_pic; |
1477 | b47b50fa | Paul Brook | qemu_irq pic[32];
|
1478 | b47b50fa | Paul Brook | DeviceState *dev; |
1479 | d074769c | Andrzej Zaborowski | DeviceState *i2c_dev; |
1480 | 343ec8e4 | Benoit Canet | DeviceState *lcd_dev; |
1481 | 343ec8e4 | Benoit Canet | DeviceState *key_dev; |
1482 | d074769c | Andrzej Zaborowski | #ifdef HAS_AUDIO
|
1483 | d074769c | Andrzej Zaborowski | DeviceState *wm8750_dev; |
1484 | d074769c | Andrzej Zaborowski | SysBusDevice *s; |
1485 | d074769c | Andrzej Zaborowski | #endif
|
1486 | d074769c | Andrzej Zaborowski | i2c_bus *i2c; |
1487 | b47b50fa | Paul Brook | int i;
|
1488 | 24859b68 | balrog | unsigned long flash_size; |
1489 | 751c6a17 | Gerd Hoffmann | DriveInfo *dinfo; |
1490 | c227f099 | Anthony Liguori | ram_addr_t sram_off; |
1491 | 24859b68 | balrog | |
1492 | 49fedd0d | Jan Kiszka | if (!cpu_model) {
|
1493 | 24859b68 | balrog | cpu_model = "arm926";
|
1494 | 49fedd0d | Jan Kiszka | } |
1495 | 24859b68 | balrog | env = cpu_init(cpu_model); |
1496 | 24859b68 | balrog | if (!env) {
|
1497 | 24859b68 | balrog | fprintf(stderr, "Unable to find CPU definition\n");
|
1498 | 24859b68 | balrog | exit(1);
|
1499 | 24859b68 | balrog | } |
1500 | b47b50fa | Paul Brook | cpu_pic = arm_pic_init_cpu(env); |
1501 | 24859b68 | balrog | |
1502 | 24859b68 | balrog | /* For now we use a fixed - the original - RAM size */
|
1503 | 24859b68 | balrog | cpu_register_physical_memory(0, MP_RAM_DEFAULT_SIZE,
|
1504 | 24859b68 | balrog | qemu_ram_alloc(MP_RAM_DEFAULT_SIZE)); |
1505 | 24859b68 | balrog | |
1506 | 24859b68 | balrog | sram_off = qemu_ram_alloc(MP_SRAM_SIZE); |
1507 | 24859b68 | balrog | cpu_register_physical_memory(MP_SRAM_BASE, MP_SRAM_SIZE, sram_off); |
1508 | 24859b68 | balrog | |
1509 | b47b50fa | Paul Brook | dev = sysbus_create_simple("mv88w8618_pic", MP_PIC_BASE,
|
1510 | b47b50fa | Paul Brook | cpu_pic[ARM_PIC_CPU_IRQ]); |
1511 | b47b50fa | Paul Brook | for (i = 0; i < 32; i++) { |
1512 | 067a3ddc | Paul Brook | pic[i] = qdev_get_gpio_in(dev, i); |
1513 | b47b50fa | Paul Brook | } |
1514 | b47b50fa | Paul Brook | sysbus_create_varargs("mv88w8618_pit", MP_PIT_BASE, pic[MP_TIMER1_IRQ],
|
1515 | b47b50fa | Paul Brook | pic[MP_TIMER2_IRQ], pic[MP_TIMER3_IRQ], |
1516 | b47b50fa | Paul Brook | pic[MP_TIMER4_IRQ], NULL);
|
1517 | 24859b68 | balrog | |
1518 | 49fedd0d | Jan Kiszka | if (serial_hds[0]) { |
1519 | b6cd0ea1 | aurel32 | serial_mm_init(MP_UART1_BASE, 2, pic[MP_UART1_IRQ], 1825000, |
1520 | 24859b68 | balrog | serial_hds[0], 1); |
1521 | 49fedd0d | Jan Kiszka | } |
1522 | 49fedd0d | Jan Kiszka | if (serial_hds[1]) { |
1523 | b6cd0ea1 | aurel32 | serial_mm_init(MP_UART2_BASE, 2, pic[MP_UART2_IRQ], 1825000, |
1524 | 24859b68 | balrog | serial_hds[1], 1); |
1525 | 49fedd0d | Jan Kiszka | } |
1526 | 24859b68 | balrog | |
1527 | 24859b68 | balrog | /* Register flash */
|
1528 | 751c6a17 | Gerd Hoffmann | dinfo = drive_get(IF_PFLASH, 0, 0); |
1529 | 751c6a17 | Gerd Hoffmann | if (dinfo) {
|
1530 | 751c6a17 | Gerd Hoffmann | flash_size = bdrv_getlength(dinfo->bdrv); |
1531 | 24859b68 | balrog | if (flash_size != 8*1024*1024 && flash_size != 16*1024*1024 && |
1532 | 24859b68 | balrog | flash_size != 32*1024*1024) { |
1533 | 24859b68 | balrog | fprintf(stderr, "Invalid flash image size\n");
|
1534 | 24859b68 | balrog | exit(1);
|
1535 | 24859b68 | balrog | } |
1536 | 24859b68 | balrog | |
1537 | 24859b68 | balrog | /*
|
1538 | 24859b68 | balrog | * The original U-Boot accesses the flash at 0xFE000000 instead of
|
1539 | 24859b68 | balrog | * 0xFF800000 (if there is 8 MB flash). So remap flash access if the
|
1540 | 24859b68 | balrog | * image is smaller than 32 MB.
|
1541 | 24859b68 | balrog | */
|
1542 | 24859b68 | balrog | pflash_cfi02_register(0-MP_FLASH_SIZE_MAX, qemu_ram_alloc(flash_size),
|
1543 | 751c6a17 | Gerd Hoffmann | dinfo->bdrv, 0x10000,
|
1544 | 24859b68 | balrog | (flash_size + 0xffff) >> 16, |
1545 | 24859b68 | balrog | MP_FLASH_SIZE_MAX / flash_size, |
1546 | 24859b68 | balrog | 2, 0x00BF, 0x236D, 0x0000, 0x0000, |
1547 | 24859b68 | balrog | 0x5555, 0x2AAA); |
1548 | 24859b68 | balrog | } |
1549 | b47b50fa | Paul Brook | sysbus_create_simple("mv88w8618_flashcfg", MP_FLASHCFG_BASE, NULL); |
1550 | 24859b68 | balrog | |
1551 | b47b50fa | Paul Brook | qemu_check_nic_model(&nd_table[0], "mv88w8618"); |
1552 | b47b50fa | Paul Brook | dev = qdev_create(NULL, "mv88w8618_eth"); |
1553 | ee6847d1 | Gerd Hoffmann | dev->nd = &nd_table[0];
|
1554 | e23a1b33 | Markus Armbruster | qdev_init_nofail(dev); |
1555 | b47b50fa | Paul Brook | sysbus_mmio_map(sysbus_from_qdev(dev), 0, MP_ETH_BASE);
|
1556 | b47b50fa | Paul Brook | sysbus_connect_irq(sysbus_from_qdev(dev), 0, pic[MP_ETH_IRQ]);
|
1557 | 24859b68 | balrog | |
1558 | b47b50fa | Paul Brook | sysbus_create_simple("mv88w8618_wlan", MP_WLAN_BASE, NULL); |
1559 | 718ec0be | malc | |
1560 | 718ec0be | malc | musicpal_misc_init(); |
1561 | 343ec8e4 | Benoit Canet | |
1562 | 343ec8e4 | Benoit Canet | dev = sysbus_create_simple("musicpal_gpio", MP_GPIO_BASE, pic[MP_GPIO_IRQ]);
|
1563 | d074769c | Andrzej Zaborowski | i2c_dev = sysbus_create_simple("bitbang_i2c", 0, NULL); |
1564 | d074769c | Andrzej Zaborowski | i2c = (i2c_bus *)qdev_get_child_bus(i2c_dev, "i2c");
|
1565 | d074769c | Andrzej Zaborowski | |
1566 | 343ec8e4 | Benoit Canet | lcd_dev = sysbus_create_simple("musicpal_lcd", MP_LCD_BASE, NULL); |
1567 | 343ec8e4 | Benoit Canet | key_dev = sysbus_create_simple("musicpal_key", 0, NULL); |
1568 | 343ec8e4 | Benoit Canet | |
1569 | d074769c | Andrzej Zaborowski | /* I2C read data */
|
1570 | 708afdf3 | Jan Kiszka | qdev_connect_gpio_out(i2c_dev, 0,
|
1571 | 708afdf3 | Jan Kiszka | qdev_get_gpio_in(dev, MP_GPIO_I2C_DATA_BIT)); |
1572 | d074769c | Andrzej Zaborowski | /* I2C data */
|
1573 | d074769c | Andrzej Zaborowski | qdev_connect_gpio_out(dev, 3, qdev_get_gpio_in(i2c_dev, 0)); |
1574 | d074769c | Andrzej Zaborowski | /* I2C clock */
|
1575 | d074769c | Andrzej Zaborowski | qdev_connect_gpio_out(dev, 4, qdev_get_gpio_in(i2c_dev, 1)); |
1576 | d074769c | Andrzej Zaborowski | |
1577 | 49fedd0d | Jan Kiszka | for (i = 0; i < 3; i++) { |
1578 | 343ec8e4 | Benoit Canet | qdev_connect_gpio_out(dev, i, qdev_get_gpio_in(lcd_dev, i)); |
1579 | 49fedd0d | Jan Kiszka | } |
1580 | 708afdf3 | Jan Kiszka | for (i = 0; i < 4; i++) { |
1581 | 708afdf3 | Jan Kiszka | qdev_connect_gpio_out(key_dev, i, qdev_get_gpio_in(dev, i + 8));
|
1582 | 708afdf3 | Jan Kiszka | } |
1583 | 708afdf3 | Jan Kiszka | for (i = 4; i < 8; i++) { |
1584 | 708afdf3 | Jan Kiszka | qdev_connect_gpio_out(key_dev, i, qdev_get_gpio_in(dev, i + 15));
|
1585 | 708afdf3 | Jan Kiszka | } |
1586 | 24859b68 | balrog | |
1587 | d074769c | Andrzej Zaborowski | #ifdef HAS_AUDIO
|
1588 | d074769c | Andrzej Zaborowski | wm8750_dev = i2c_create_slave(i2c, "wm8750", MP_WM_ADDR);
|
1589 | d074769c | Andrzej Zaborowski | dev = qdev_create(NULL, "mv88w8618_audio"); |
1590 | d074769c | Andrzej Zaborowski | s = sysbus_from_qdev(dev); |
1591 | d074769c | Andrzej Zaborowski | qdev_prop_set_ptr(dev, "wm8750", wm8750_dev);
|
1592 | e23a1b33 | Markus Armbruster | qdev_init_nofail(dev); |
1593 | d074769c | Andrzej Zaborowski | sysbus_mmio_map(s, 0, MP_AUDIO_BASE);
|
1594 | d074769c | Andrzej Zaborowski | sysbus_connect_irq(s, 0, pic[MP_AUDIO_IRQ]);
|
1595 | d074769c | Andrzej Zaborowski | #endif
|
1596 | d074769c | Andrzej Zaborowski | |
1597 | 24859b68 | balrog | musicpal_binfo.ram_size = MP_RAM_DEFAULT_SIZE; |
1598 | 24859b68 | balrog | musicpal_binfo.kernel_filename = kernel_filename; |
1599 | 24859b68 | balrog | musicpal_binfo.kernel_cmdline = kernel_cmdline; |
1600 | 24859b68 | balrog | musicpal_binfo.initrd_filename = initrd_filename; |
1601 | b0f6edb1 | balrog | arm_load_kernel(env, &musicpal_binfo); |
1602 | 24859b68 | balrog | } |
1603 | 24859b68 | balrog | |
1604 | f80f9ec9 | Anthony Liguori | static QEMUMachine musicpal_machine = {
|
1605 | 4b32e168 | aliguori | .name = "musicpal",
|
1606 | 4b32e168 | aliguori | .desc = "Marvell 88w8618 / MusicPal (ARM926EJ-S)",
|
1607 | 4b32e168 | aliguori | .init = musicpal_init, |
1608 | 24859b68 | balrog | }; |
1609 | b47b50fa | Paul Brook | |
1610 | f80f9ec9 | Anthony Liguori | static void musicpal_machine_init(void) |
1611 | f80f9ec9 | Anthony Liguori | { |
1612 | f80f9ec9 | Anthony Liguori | qemu_register_machine(&musicpal_machine); |
1613 | f80f9ec9 | Anthony Liguori | } |
1614 | f80f9ec9 | Anthony Liguori | |
1615 | f80f9ec9 | Anthony Liguori | machine_init(musicpal_machine_init); |
1616 | f80f9ec9 | Anthony Liguori | |
1617 | b47b50fa | Paul Brook | static void musicpal_register_devices(void) |
1618 | b47b50fa | Paul Brook | { |
1619 | d5b61ddd | Jan Kiszka | sysbus_register_withprop(&mv88w8618_pic_info); |
1620 | c88d6bde | Jan Kiszka | sysbus_register_withprop(&mv88w8618_pit_info); |
1621 | d5b61ddd | Jan Kiszka | sysbus_register_withprop(&mv88w8618_flashcfg_info); |
1622 | d5b61ddd | Jan Kiszka | sysbus_register_withprop(&mv88w8618_eth_info); |
1623 | b47b50fa | Paul Brook | sysbus_register_dev("mv88w8618_wlan", sizeof(SysBusDevice), |
1624 | b47b50fa | Paul Brook | mv88w8618_wlan_init); |
1625 | d5b61ddd | Jan Kiszka | sysbus_register_withprop(&musicpal_lcd_info); |
1626 | 30624c92 | Jan Kiszka | sysbus_register_withprop(&musicpal_gpio_info); |
1627 | d5b61ddd | Jan Kiszka | sysbus_register_withprop(&musicpal_key_info); |
1628 | b47b50fa | Paul Brook | } |
1629 | b47b50fa | Paul Brook | |
1630 | b47b50fa | Paul Brook | device_init(musicpal_register_devices) |