Revision cef3017c hw/pci.h

b/hw/pci.h
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#define PCI_DEVICE_ID_VMWARE_SCSI        0x0730
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#define PCI_DEVICE_ID_VMWARE_IDE         0x1729
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#define PCI_VENDOR_ID_INTEL              0x8086


  		





  
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/* Intel (0x8086) */


  		





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#define PCI_DEVICE_ID_INTEL_82551IT      0x1209


  		





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/* Red Hat / Qumranet (for QEMU) -- see pci-ids.txt */


  		





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#define PCI_DEVICES_MAX 64


  		





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/* Declarations from linux/pci_regs.h */


  		





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#define PCI_VENDOR_ID		0x00	/* 16 bits */


  		





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#define PCI_DEVICE_ID		0x02	/* 16 bits */


  		





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#define PCI_COMMAND		0x04	/* 16 bits */


  		





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#define  PCI_COMMAND_IO		0x1	/* Enable response in I/O space */


  		





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#define  PCI_COMMAND_MEMORY	0x2	/* Enable response in Memory space */


  		





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#define PCI_REVISION            0x08


  		





  
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#define PCI_STATUS              0x06    /* 16 bits */


  		





  
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#define PCI_REVISION_ID         0x08    /* 8 bits  */


  		





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#define PCI_CLASS_DEVICE        0x0a    /* Device class */


  		





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#define PCI_SUBVENDOR_ID	0x2c	/* 16 bits */


  		





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#define PCI_SUBDEVICE_ID	0x2e	/* 16 bits */


  		





  
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#define PCI_HEADER_TYPE         0x0e    /* 8 bits */


  		





  
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#define PCI_SUBSYSTEM_VENDOR_ID 0x2c    /* 16 bits */


  		





  
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#define PCI_SUBSYSTEM_ID        0x2e    /* 16 bits */


  		





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#define PCI_INTERRUPT_LINE	0x3c	/* 8 bits */


  		





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#define PCI_INTERRUPT_PIN	0x3d	/* 8 bits */


  		





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#define PCI_MIN_GNT		0x3e	/* 8 bits */


  		





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#define PCI_MAX_LAT		0x3f	/* 8 bits */


  		





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#define PCI_REVISION            0x08    /* obsolete, use PCI_REVISION_ID */


  		





  
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#define PCI_SUBVENDOR_ID        0x2c    /* obsolete, use PCI_SUBSYSTEM_VENDOR_ID */


  		





  
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#define PCI_SUBDEVICE_ID        0x2e    /* obsolete, use PCI_SUBSYSTEM_ID */


  		





  
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/* Bits in the PCI Status Register (PCI 2.3 spec) */


  		





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#define PCI_STATUS_RESERVED1	0x007


  		





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#define PCI_STATUS_INT_STATUS	0x008


  		












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