root / hw / omap_gptimer.c @ cf4c01fd
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/*
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* TI OMAP2 general purpose timers emulation.
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*
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* Copyright (C) 2007-2008 Nokia Corporation
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* Written by Andrzej Zaborowski <andrew@openedhand.com>
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 or
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* (at your option) any later version of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License along
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* with this program; if not, see <http://www.gnu.org/licenses/>.
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*/
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#include "hw.h" |
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#include "qemu-timer.h" |
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#include "omap.h" |
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/* GP timers */
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struct omap_gp_timer_s {
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qemu_irq irq; |
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qemu_irq wkup; |
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qemu_irq in; |
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qemu_irq out; |
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omap_clk clk; |
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QEMUTimer *timer; |
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QEMUTimer *match; |
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struct omap_target_agent_s *ta;
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int in_val;
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int out_val;
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int64_t time; |
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int64_t rate; |
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int64_t ticks_per_sec; |
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int16_t config; |
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int status;
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int it_ena;
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int wu_ena;
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int enable;
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int inout;
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int capt2;
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int pt;
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enum {
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gpt_trigger_none, gpt_trigger_overflow, gpt_trigger_both |
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} trigger; |
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enum {
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gpt_capture_none, gpt_capture_rising, |
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gpt_capture_falling, gpt_capture_both |
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} capture; |
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int scpwm;
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int ce;
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int pre;
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int ptv;
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int ar;
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int st;
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int posted;
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uint32_t val; |
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uint32_t load_val; |
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uint32_t capture_val[2];
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uint32_t match_val; |
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int capt_num;
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uint16_t writeh; /* LSB */
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uint16_t readh; /* MSB */
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}; |
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#define GPT_TCAR_IT (1 << 2) |
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#define GPT_OVF_IT (1 << 1) |
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#define GPT_MAT_IT (1 << 0) |
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static inline void omap_gp_timer_intr(struct omap_gp_timer_s *timer, int it) |
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{ |
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if (timer->it_ena & it) {
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if (!timer->status)
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qemu_irq_raise(timer->irq); |
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timer->status |= it; |
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/* Or are the status bits set even when masked?
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* i.e. is masking applied before or after the status register? */
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} |
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if (timer->wu_ena & it)
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qemu_irq_pulse(timer->wkup); |
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} |
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static inline void omap_gp_timer_out(struct omap_gp_timer_s *timer, int level) |
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{ |
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if (!timer->inout && timer->out_val != level) {
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timer->out_val = level; |
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qemu_set_irq(timer->out, level); |
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} |
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} |
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static inline uint32_t omap_gp_timer_read(struct omap_gp_timer_s *timer) |
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{ |
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uint64_t distance; |
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if (timer->st && timer->rate) {
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distance = qemu_get_clock(vm_clock) - timer->time; |
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distance = muldiv64(distance, timer->rate, timer->ticks_per_sec); |
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if (distance >= 0xffffffff - timer->val) |
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return 0xffffffff; |
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else
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return timer->val + distance;
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} else
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return timer->val;
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} |
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static inline void omap_gp_timer_sync(struct omap_gp_timer_s *timer) |
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{ |
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if (timer->st) {
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timer->val = omap_gp_timer_read(timer); |
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timer->time = qemu_get_clock(vm_clock); |
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} |
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} |
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static inline void omap_gp_timer_update(struct omap_gp_timer_s *timer) |
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{ |
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int64_t expires, matches; |
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if (timer->st && timer->rate) {
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expires = muldiv64(0x100000000ll - timer->val,
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timer->ticks_per_sec, timer->rate); |
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qemu_mod_timer(timer->timer, timer->time + expires); |
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if (timer->ce && timer->match_val >= timer->val) {
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matches = muldiv64(timer->match_val - timer->val, |
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timer->ticks_per_sec, timer->rate); |
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qemu_mod_timer(timer->match, timer->time + matches); |
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} else
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qemu_del_timer(timer->match); |
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} else {
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qemu_del_timer(timer->timer); |
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qemu_del_timer(timer->match); |
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omap_gp_timer_out(timer, timer->scpwm); |
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} |
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} |
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static inline void omap_gp_timer_trigger(struct omap_gp_timer_s *timer) |
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{ |
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if (timer->pt)
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/* TODO in overflow-and-match mode if the first event to
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* occur is the match, don't toggle. */
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omap_gp_timer_out(timer, !timer->out_val); |
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else
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/* TODO inverted pulse on timer->out_val == 1? */
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qemu_irq_pulse(timer->out); |
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} |
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static void omap_gp_timer_tick(void *opaque) |
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{ |
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struct omap_gp_timer_s *timer = (struct omap_gp_timer_s *) opaque; |
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if (!timer->ar) {
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timer->st = 0;
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timer->val = 0;
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} else {
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timer->val = timer->load_val; |
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timer->time = qemu_get_clock(vm_clock); |
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} |
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if (timer->trigger == gpt_trigger_overflow ||
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timer->trigger == gpt_trigger_both) |
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omap_gp_timer_trigger(timer); |
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omap_gp_timer_intr(timer, GPT_OVF_IT); |
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omap_gp_timer_update(timer); |
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} |
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static void omap_gp_timer_match(void *opaque) |
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{ |
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struct omap_gp_timer_s *timer = (struct omap_gp_timer_s *) opaque; |
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if (timer->trigger == gpt_trigger_both)
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omap_gp_timer_trigger(timer); |
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omap_gp_timer_intr(timer, GPT_MAT_IT); |
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} |
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static void omap_gp_timer_input(void *opaque, int line, int on) |
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{ |
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struct omap_gp_timer_s *s = (struct omap_gp_timer_s *) opaque; |
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int trigger;
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switch (s->capture) {
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default:
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case gpt_capture_none:
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trigger = 0;
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break;
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case gpt_capture_rising:
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trigger = !s->in_val && on; |
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break;
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case gpt_capture_falling:
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trigger = s->in_val && !on; |
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break;
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case gpt_capture_both:
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trigger = (s->in_val == !on); |
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break;
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} |
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s->in_val = on; |
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if (s->inout && trigger && s->capt_num < 2) { |
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s->capture_val[s->capt_num] = omap_gp_timer_read(s); |
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if (s->capt2 == s->capt_num ++)
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omap_gp_timer_intr(s, GPT_TCAR_IT); |
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} |
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} |
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static void omap_gp_timer_clk_update(void *opaque, int line, int on) |
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{ |
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struct omap_gp_timer_s *timer = (struct omap_gp_timer_s *) opaque; |
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omap_gp_timer_sync(timer); |
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timer->rate = on ? omap_clk_getrate(timer->clk) : 0;
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omap_gp_timer_update(timer); |
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} |
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static void omap_gp_timer_clk_setup(struct omap_gp_timer_s *timer) |
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{ |
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omap_clk_adduser(timer->clk, |
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qemu_allocate_irqs(omap_gp_timer_clk_update, timer, 1)[0]); |
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timer->rate = omap_clk_getrate(timer->clk); |
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} |
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void omap_gp_timer_reset(struct omap_gp_timer_s *s) |
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{ |
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s->config = 0x000;
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s->status = 0;
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s->it_ena = 0;
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s->wu_ena = 0;
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s->inout = 0;
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s->capt2 = 0;
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s->capt_num = 0;
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s->pt = 0;
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s->trigger = gpt_trigger_none; |
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s->capture = gpt_capture_none; |
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s->scpwm = 0;
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s->ce = 0;
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s->pre = 0;
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s->ptv = 0;
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s->ar = 0;
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s->st = 0;
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s->posted = 1;
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s->val = 0x00000000;
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s->load_val = 0x00000000;
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s->capture_val[0] = 0x00000000; |
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s->capture_val[1] = 0x00000000; |
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s->match_val = 0x00000000;
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omap_gp_timer_update(s); |
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} |
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static uint32_t omap_gp_timer_readw(void *opaque, target_phys_addr_t addr) |
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{ |
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struct omap_gp_timer_s *s = (struct omap_gp_timer_s *) opaque; |
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switch (addr) {
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case 0x00: /* TIDR */ |
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return 0x21; |
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case 0x10: /* TIOCP_CFG */ |
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return s->config;
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case 0x14: /* TISTAT */ |
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/* ??? When's this bit reset? */
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return 1; /* RESETDONE */ |
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case 0x18: /* TISR */ |
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return s->status;
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case 0x1c: /* TIER */ |
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return s->it_ena;
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case 0x20: /* TWER */ |
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return s->wu_ena;
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case 0x24: /* TCLR */ |
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return (s->inout << 14) | |
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(s->capt2 << 13) |
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(s->pt << 12) |
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(s->trigger << 10) |
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(s->capture << 8) |
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(s->scpwm << 7) |
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(s->ce << 6) |
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(s->pre << 5) |
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(s->ptv << 2) |
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(s->ar << 1) |
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(s->st << 0);
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case 0x28: /* TCRR */ |
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return omap_gp_timer_read(s);
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case 0x2c: /* TLDR */ |
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return s->load_val;
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case 0x30: /* TTGR */ |
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return 0xffffffff; |
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case 0x34: /* TWPS */ |
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return 0x00000000; /* No posted writes pending. */ |
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case 0x38: /* TMAR */ |
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return s->match_val;
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case 0x3c: /* TCAR1 */ |
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return s->capture_val[0]; |
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case 0x40: /* TSICR */ |
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return s->posted << 2; |
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case 0x44: /* TCAR2 */ |
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return s->capture_val[1]; |
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} |
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OMAP_BAD_REG(addr); |
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return 0; |
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} |
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static uint32_t omap_gp_timer_readh(void *opaque, target_phys_addr_t addr) |
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{ |
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struct omap_gp_timer_s *s = (struct omap_gp_timer_s *) opaque; |
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uint32_t ret; |
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if (addr & 2) |
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return s->readh;
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else {
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ret = omap_gp_timer_readw(opaque, addr); |
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s->readh = ret >> 16;
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return ret & 0xffff; |
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} |
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} |
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static CPUReadMemoryFunc * const omap_gp_timer_readfn[] = { |
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omap_badwidth_read32, |
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omap_gp_timer_readh, |
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omap_gp_timer_readw, |
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}; |
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static void omap_gp_timer_write(void *opaque, target_phys_addr_t addr, |
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uint32_t value) |
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{ |
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struct omap_gp_timer_s *s = (struct omap_gp_timer_s *) opaque; |
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switch (addr) {
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case 0x00: /* TIDR */ |
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case 0x14: /* TISTAT */ |
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case 0x34: /* TWPS */ |
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case 0x3c: /* TCAR1 */ |
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case 0x44: /* TCAR2 */ |
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OMAP_RO_REG(addr); |
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break;
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case 0x10: /* TIOCP_CFG */ |
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s->config = value & 0x33d;
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if (((value >> 3) & 3) == 3) /* IDLEMODE */ |
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fprintf(stderr, "%s: illegal IDLEMODE value in TIOCP_CFG\n",
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__FUNCTION__); |
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if (value & 2) /* SOFTRESET */ |
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omap_gp_timer_reset(s); |
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break;
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case 0x18: /* TISR */ |
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if (value & GPT_TCAR_IT)
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s->capt_num = 0;
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if (s->status && !(s->status &= ~value))
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qemu_irq_lower(s->irq); |
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break;
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case 0x1c: /* TIER */ |
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s->it_ena = value & 7;
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break;
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case 0x20: /* TWER */ |
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s->wu_ena = value & 7;
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break;
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case 0x24: /* TCLR */ |
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omap_gp_timer_sync(s); |
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s->inout = (value >> 14) & 1; |
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s->capt2 = (value >> 13) & 1; |
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s->pt = (value >> 12) & 1; |
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s->trigger = (value >> 10) & 3; |
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if (s->capture == gpt_capture_none &&
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((value >> 8) & 3) != gpt_capture_none) |
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s->capt_num = 0;
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s->capture = (value >> 8) & 3; |
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s->scpwm = (value >> 7) & 1; |
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s->ce = (value >> 6) & 1; |
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s->pre = (value >> 5) & 1; |
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s->ptv = (value >> 2) & 7; |
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s->ar = (value >> 1) & 1; |
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s->st = (value >> 0) & 1; |
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if (s->inout && s->trigger != gpt_trigger_none)
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fprintf(stderr, "%s: GP timer pin must be an output "
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"for this trigger mode\n", __FUNCTION__);
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if (!s->inout && s->capture != gpt_capture_none)
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fprintf(stderr, "%s: GP timer pin must be an input "
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"for this capture mode\n", __FUNCTION__);
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if (s->trigger == gpt_trigger_none)
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omap_gp_timer_out(s, s->scpwm); |
408 |
/* TODO: make sure this doesn't overflow 32-bits */
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s->ticks_per_sec = get_ticks_per_sec() << (s->pre ? s->ptv + 1 : 0); |
410 |
omap_gp_timer_update(s); |
411 |
break;
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|
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case 0x28: /* TCRR */ |
414 |
s->time = qemu_get_clock(vm_clock); |
415 |
s->val = value; |
416 |
omap_gp_timer_update(s); |
417 |
break;
|
418 |
|
419 |
case 0x2c: /* TLDR */ |
420 |
s->load_val = value; |
421 |
break;
|
422 |
|
423 |
case 0x30: /* TTGR */ |
424 |
s->time = qemu_get_clock(vm_clock); |
425 |
s->val = s->load_val; |
426 |
omap_gp_timer_update(s); |
427 |
break;
|
428 |
|
429 |
case 0x38: /* TMAR */ |
430 |
omap_gp_timer_sync(s); |
431 |
s->match_val = value; |
432 |
omap_gp_timer_update(s); |
433 |
break;
|
434 |
|
435 |
case 0x40: /* TSICR */ |
436 |
s->posted = (value >> 2) & 1; |
437 |
if (value & 2) /* How much exactly are we supposed to reset? */ |
438 |
omap_gp_timer_reset(s); |
439 |
break;
|
440 |
|
441 |
default:
|
442 |
OMAP_BAD_REG(addr); |
443 |
} |
444 |
} |
445 |
|
446 |
static void omap_gp_timer_writeh(void *opaque, target_phys_addr_t addr, |
447 |
uint32_t value) |
448 |
{ |
449 |
struct omap_gp_timer_s *s = (struct omap_gp_timer_s *) opaque; |
450 |
|
451 |
if (addr & 2) |
452 |
return omap_gp_timer_write(opaque, addr, (value << 16) | s->writeh); |
453 |
else
|
454 |
s->writeh = (uint16_t) value; |
455 |
} |
456 |
|
457 |
static CPUWriteMemoryFunc * const omap_gp_timer_writefn[] = { |
458 |
omap_badwidth_write32, |
459 |
omap_gp_timer_writeh, |
460 |
omap_gp_timer_write, |
461 |
}; |
462 |
|
463 |
struct omap_gp_timer_s *omap_gp_timer_init(struct omap_target_agent_s *ta, |
464 |
qemu_irq irq, omap_clk fclk, omap_clk iclk) |
465 |
{ |
466 |
int iomemtype;
|
467 |
struct omap_gp_timer_s *s = (struct omap_gp_timer_s *) |
468 |
qemu_mallocz(sizeof(struct omap_gp_timer_s)); |
469 |
|
470 |
s->ta = ta; |
471 |
s->irq = irq; |
472 |
s->clk = fclk; |
473 |
s->timer = qemu_new_timer(vm_clock, omap_gp_timer_tick, s); |
474 |
s->match = qemu_new_timer(vm_clock, omap_gp_timer_match, s); |
475 |
s->in = qemu_allocate_irqs(omap_gp_timer_input, s, 1)[0]; |
476 |
omap_gp_timer_reset(s); |
477 |
omap_gp_timer_clk_setup(s); |
478 |
|
479 |
iomemtype = l4_register_io_memory(omap_gp_timer_readfn, |
480 |
omap_gp_timer_writefn, s); |
481 |
omap_l4_attach(ta, 0, iomemtype);
|
482 |
|
483 |
return s;
|
484 |
} |