root / hw / omap1.c @ cfb0a50a
History | View | Annotate | Download (108.5 kB)
1 | c3d2689d | balrog | /*
|
---|---|---|---|
2 | c3d2689d | balrog | * TI OMAP processors emulation.
|
3 | c3d2689d | balrog | *
|
4 | b4e3104b | balrog | * Copyright (C) 2006-2008 Andrzej Zaborowski <balrog@zabor.org>
|
5 | c3d2689d | balrog | *
|
6 | c3d2689d | balrog | * This program is free software; you can redistribute it and/or
|
7 | c3d2689d | balrog | * modify it under the terms of the GNU General Public License as
|
8 | 827df9f3 | balrog | * published by the Free Software Foundation; either version 2 or
|
9 | 827df9f3 | balrog | * (at your option) version 3 of the License.
|
10 | c3d2689d | balrog | *
|
11 | c3d2689d | balrog | * This program is distributed in the hope that it will be useful,
|
12 | c3d2689d | balrog | * but WITHOUT ANY WARRANTY; without even the implied warranty of
|
13 | c3d2689d | balrog | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
14 | c3d2689d | balrog | * GNU General Public License for more details.
|
15 | c3d2689d | balrog | *
|
16 | fad6cb1a | aurel32 | * You should have received a copy of the GNU General Public License along
|
17 | 8167ee88 | Blue Swirl | * with this program; if not, see <http://www.gnu.org/licenses/>.
|
18 | c3d2689d | balrog | */
|
19 | 87ecb68b | pbrook | #include "hw.h" |
20 | 87ecb68b | pbrook | #include "arm-misc.h" |
21 | 87ecb68b | pbrook | #include "omap.h" |
22 | 87ecb68b | pbrook | #include "sysemu.h" |
23 | 87ecb68b | pbrook | #include "qemu-timer.h" |
24 | 827df9f3 | balrog | #include "qemu-char.h" |
25 | afbb5194 | balrog | #include "soc_dma.h" |
26 | 87ecb68b | pbrook | /* We use pc-style serial ports. */
|
27 | 87ecb68b | pbrook | #include "pc.h" |
28 | c3d2689d | balrog | |
29 | 827df9f3 | balrog | /* Should signal the TCMI/GPMC */
|
30 | c227f099 | Anthony Liguori | uint32_t omap_badwidth_read8(void *opaque, target_phys_addr_t addr)
|
31 | 66450b15 | balrog | { |
32 | 02645926 | balrog | uint8_t ret; |
33 | 02645926 | balrog | |
34 | 66450b15 | balrog | OMAP_8B_REG(addr); |
35 | b854bc19 | balrog | cpu_physical_memory_read(addr, (void *) &ret, 1); |
36 | 02645926 | balrog | return ret;
|
37 | 66450b15 | balrog | } |
38 | 66450b15 | balrog | |
39 | c227f099 | Anthony Liguori | void omap_badwidth_write8(void *opaque, target_phys_addr_t addr, |
40 | 66450b15 | balrog | uint32_t value) |
41 | 66450b15 | balrog | { |
42 | b854bc19 | balrog | uint8_t val8 = value; |
43 | b854bc19 | balrog | |
44 | 66450b15 | balrog | OMAP_8B_REG(addr); |
45 | b854bc19 | balrog | cpu_physical_memory_write(addr, (void *) &val8, 1); |
46 | 66450b15 | balrog | } |
47 | 66450b15 | balrog | |
48 | c227f099 | Anthony Liguori | uint32_t omap_badwidth_read16(void *opaque, target_phys_addr_t addr)
|
49 | c3d2689d | balrog | { |
50 | b854bc19 | balrog | uint16_t ret; |
51 | b854bc19 | balrog | |
52 | c3d2689d | balrog | OMAP_16B_REG(addr); |
53 | b854bc19 | balrog | cpu_physical_memory_read(addr, (void *) &ret, 2); |
54 | b854bc19 | balrog | return ret;
|
55 | c3d2689d | balrog | } |
56 | c3d2689d | balrog | |
57 | c227f099 | Anthony Liguori | void omap_badwidth_write16(void *opaque, target_phys_addr_t addr, |
58 | c3d2689d | balrog | uint32_t value) |
59 | c3d2689d | balrog | { |
60 | b854bc19 | balrog | uint16_t val16 = value; |
61 | b854bc19 | balrog | |
62 | c3d2689d | balrog | OMAP_16B_REG(addr); |
63 | b854bc19 | balrog | cpu_physical_memory_write(addr, (void *) &val16, 2); |
64 | c3d2689d | balrog | } |
65 | c3d2689d | balrog | |
66 | c227f099 | Anthony Liguori | uint32_t omap_badwidth_read32(void *opaque, target_phys_addr_t addr)
|
67 | c3d2689d | balrog | { |
68 | b854bc19 | balrog | uint32_t ret; |
69 | b854bc19 | balrog | |
70 | c3d2689d | balrog | OMAP_32B_REG(addr); |
71 | b854bc19 | balrog | cpu_physical_memory_read(addr, (void *) &ret, 4); |
72 | b854bc19 | balrog | return ret;
|
73 | c3d2689d | balrog | } |
74 | c3d2689d | balrog | |
75 | c227f099 | Anthony Liguori | void omap_badwidth_write32(void *opaque, target_phys_addr_t addr, |
76 | c3d2689d | balrog | uint32_t value) |
77 | c3d2689d | balrog | { |
78 | c3d2689d | balrog | OMAP_32B_REG(addr); |
79 | b854bc19 | balrog | cpu_physical_memory_write(addr, (void *) &value, 4); |
80 | c3d2689d | balrog | } |
81 | c3d2689d | balrog | |
82 | c3d2689d | balrog | /* MPU OS timers */
|
83 | c3d2689d | balrog | struct omap_mpu_timer_s {
|
84 | c3d2689d | balrog | qemu_irq irq; |
85 | c3d2689d | balrog | omap_clk clk; |
86 | c3d2689d | balrog | uint32_t val; |
87 | c3d2689d | balrog | int64_t time; |
88 | c3d2689d | balrog | QEMUTimer *timer; |
89 | e856f2ad | balrog | QEMUBH *tick; |
90 | c3d2689d | balrog | int64_t rate; |
91 | c3d2689d | balrog | int it_ena;
|
92 | c3d2689d | balrog | |
93 | c3d2689d | balrog | int enable;
|
94 | c3d2689d | balrog | int ptv;
|
95 | c3d2689d | balrog | int ar;
|
96 | c3d2689d | balrog | int st;
|
97 | c3d2689d | balrog | uint32_t reset_val; |
98 | c3d2689d | balrog | }; |
99 | c3d2689d | balrog | |
100 | c3d2689d | balrog | static inline uint32_t omap_timer_read(struct omap_mpu_timer_s *timer) |
101 | c3d2689d | balrog | { |
102 | c3d2689d | balrog | uint64_t distance = qemu_get_clock(vm_clock) - timer->time; |
103 | c3d2689d | balrog | |
104 | c3d2689d | balrog | if (timer->st && timer->enable && timer->rate)
|
105 | c3d2689d | balrog | return timer->val - muldiv64(distance >> (timer->ptv + 1), |
106 | 6ee093c9 | Juan Quintela | timer->rate, get_ticks_per_sec()); |
107 | c3d2689d | balrog | else
|
108 | c3d2689d | balrog | return timer->val;
|
109 | c3d2689d | balrog | } |
110 | c3d2689d | balrog | |
111 | c3d2689d | balrog | static inline void omap_timer_sync(struct omap_mpu_timer_s *timer) |
112 | c3d2689d | balrog | { |
113 | c3d2689d | balrog | timer->val = omap_timer_read(timer); |
114 | c3d2689d | balrog | timer->time = qemu_get_clock(vm_clock); |
115 | c3d2689d | balrog | } |
116 | c3d2689d | balrog | |
117 | c3d2689d | balrog | static inline void omap_timer_update(struct omap_mpu_timer_s *timer) |
118 | c3d2689d | balrog | { |
119 | c3d2689d | balrog | int64_t expires; |
120 | c3d2689d | balrog | |
121 | c3d2689d | balrog | if (timer->enable && timer->st && timer->rate) {
|
122 | c3d2689d | balrog | timer->val = timer->reset_val; /* Should skip this on clk enable */
|
123 | b8b137d6 | balrog | expires = muldiv64((uint64_t) timer->val << (timer->ptv + 1),
|
124 | 6ee093c9 | Juan Quintela | get_ticks_per_sec(), timer->rate); |
125 | b854bc19 | balrog | |
126 | b854bc19 | balrog | /* If timer expiry would be sooner than in about 1 ms and
|
127 | b854bc19 | balrog | * auto-reload isn't set, then fire immediately. This is a hack
|
128 | b854bc19 | balrog | * to make systems like PalmOS run in acceptable time. PalmOS
|
129 | b854bc19 | balrog | * sets the interval to a very low value and polls the status bit
|
130 | b854bc19 | balrog | * in a busy loop when it wants to sleep just a couple of CPU
|
131 | b854bc19 | balrog | * ticks. */
|
132 | 6ee093c9 | Juan Quintela | if (expires > (get_ticks_per_sec() >> 10) || timer->ar) |
133 | b854bc19 | balrog | qemu_mod_timer(timer->timer, timer->time + expires); |
134 | e856f2ad | balrog | else
|
135 | e856f2ad | balrog | qemu_bh_schedule(timer->tick); |
136 | c3d2689d | balrog | } else
|
137 | c3d2689d | balrog | qemu_del_timer(timer->timer); |
138 | c3d2689d | balrog | } |
139 | c3d2689d | balrog | |
140 | e856f2ad | balrog | static void omap_timer_fire(void *opaque) |
141 | c3d2689d | balrog | { |
142 | e856f2ad | balrog | struct omap_mpu_timer_s *timer = opaque;
|
143 | c3d2689d | balrog | |
144 | c3d2689d | balrog | if (!timer->ar) {
|
145 | c3d2689d | balrog | timer->val = 0;
|
146 | c3d2689d | balrog | timer->st = 0;
|
147 | c3d2689d | balrog | } |
148 | c3d2689d | balrog | |
149 | c3d2689d | balrog | if (timer->it_ena)
|
150 | 106627d0 | balrog | /* Edge-triggered irq */
|
151 | 106627d0 | balrog | qemu_irq_pulse(timer->irq); |
152 | e856f2ad | balrog | } |
153 | e856f2ad | balrog | |
154 | e856f2ad | balrog | static void omap_timer_tick(void *opaque) |
155 | e856f2ad | balrog | { |
156 | e856f2ad | balrog | struct omap_mpu_timer_s *timer = (struct omap_mpu_timer_s *) opaque; |
157 | e856f2ad | balrog | |
158 | e856f2ad | balrog | omap_timer_sync(timer); |
159 | e856f2ad | balrog | omap_timer_fire(timer); |
160 | c3d2689d | balrog | omap_timer_update(timer); |
161 | c3d2689d | balrog | } |
162 | c3d2689d | balrog | |
163 | c3d2689d | balrog | static void omap_timer_clk_update(void *opaque, int line, int on) |
164 | c3d2689d | balrog | { |
165 | c3d2689d | balrog | struct omap_mpu_timer_s *timer = (struct omap_mpu_timer_s *) opaque; |
166 | c3d2689d | balrog | |
167 | c3d2689d | balrog | omap_timer_sync(timer); |
168 | c3d2689d | balrog | timer->rate = on ? omap_clk_getrate(timer->clk) : 0;
|
169 | c3d2689d | balrog | omap_timer_update(timer); |
170 | c3d2689d | balrog | } |
171 | c3d2689d | balrog | |
172 | c3d2689d | balrog | static void omap_timer_clk_setup(struct omap_mpu_timer_s *timer) |
173 | c3d2689d | balrog | { |
174 | c3d2689d | balrog | omap_clk_adduser(timer->clk, |
175 | c3d2689d | balrog | qemu_allocate_irqs(omap_timer_clk_update, timer, 1)[0]); |
176 | c3d2689d | balrog | timer->rate = omap_clk_getrate(timer->clk); |
177 | c3d2689d | balrog | } |
178 | c3d2689d | balrog | |
179 | c227f099 | Anthony Liguori | static uint32_t omap_mpu_timer_read(void *opaque, target_phys_addr_t addr) |
180 | c3d2689d | balrog | { |
181 | c3d2689d | balrog | struct omap_mpu_timer_s *s = (struct omap_mpu_timer_s *) opaque; |
182 | c3d2689d | balrog | |
183 | 8da3ff18 | pbrook | switch (addr) {
|
184 | c3d2689d | balrog | case 0x00: /* CNTL_TIMER */ |
185 | c3d2689d | balrog | return (s->enable << 5) | (s->ptv << 2) | (s->ar << 1) | s->st; |
186 | c3d2689d | balrog | |
187 | c3d2689d | balrog | case 0x04: /* LOAD_TIM */ |
188 | c3d2689d | balrog | break;
|
189 | c3d2689d | balrog | |
190 | c3d2689d | balrog | case 0x08: /* READ_TIM */ |
191 | c3d2689d | balrog | return omap_timer_read(s);
|
192 | c3d2689d | balrog | } |
193 | c3d2689d | balrog | |
194 | c3d2689d | balrog | OMAP_BAD_REG(addr); |
195 | c3d2689d | balrog | return 0; |
196 | c3d2689d | balrog | } |
197 | c3d2689d | balrog | |
198 | c227f099 | Anthony Liguori | static void omap_mpu_timer_write(void *opaque, target_phys_addr_t addr, |
199 | c3d2689d | balrog | uint32_t value) |
200 | c3d2689d | balrog | { |
201 | c3d2689d | balrog | struct omap_mpu_timer_s *s = (struct omap_mpu_timer_s *) opaque; |
202 | c3d2689d | balrog | |
203 | 8da3ff18 | pbrook | switch (addr) {
|
204 | c3d2689d | balrog | case 0x00: /* CNTL_TIMER */ |
205 | c3d2689d | balrog | omap_timer_sync(s); |
206 | c3d2689d | balrog | s->enable = (value >> 5) & 1; |
207 | c3d2689d | balrog | s->ptv = (value >> 2) & 7; |
208 | c3d2689d | balrog | s->ar = (value >> 1) & 1; |
209 | c3d2689d | balrog | s->st = value & 1;
|
210 | c3d2689d | balrog | omap_timer_update(s); |
211 | c3d2689d | balrog | return;
|
212 | c3d2689d | balrog | |
213 | c3d2689d | balrog | case 0x04: /* LOAD_TIM */ |
214 | c3d2689d | balrog | s->reset_val = value; |
215 | c3d2689d | balrog | return;
|
216 | c3d2689d | balrog | |
217 | c3d2689d | balrog | case 0x08: /* READ_TIM */ |
218 | c3d2689d | balrog | OMAP_RO_REG(addr); |
219 | c3d2689d | balrog | break;
|
220 | c3d2689d | balrog | |
221 | c3d2689d | balrog | default:
|
222 | c3d2689d | balrog | OMAP_BAD_REG(addr); |
223 | c3d2689d | balrog | } |
224 | c3d2689d | balrog | } |
225 | c3d2689d | balrog | |
226 | d60efc6b | Blue Swirl | static CPUReadMemoryFunc * const omap_mpu_timer_readfn[] = { |
227 | c3d2689d | balrog | omap_badwidth_read32, |
228 | c3d2689d | balrog | omap_badwidth_read32, |
229 | c3d2689d | balrog | omap_mpu_timer_read, |
230 | c3d2689d | balrog | }; |
231 | c3d2689d | balrog | |
232 | d60efc6b | Blue Swirl | static CPUWriteMemoryFunc * const omap_mpu_timer_writefn[] = { |
233 | c3d2689d | balrog | omap_badwidth_write32, |
234 | c3d2689d | balrog | omap_badwidth_write32, |
235 | c3d2689d | balrog | omap_mpu_timer_write, |
236 | c3d2689d | balrog | }; |
237 | c3d2689d | balrog | |
238 | c3d2689d | balrog | static void omap_mpu_timer_reset(struct omap_mpu_timer_s *s) |
239 | c3d2689d | balrog | { |
240 | c3d2689d | balrog | qemu_del_timer(s->timer); |
241 | c3d2689d | balrog | s->enable = 0;
|
242 | c3d2689d | balrog | s->reset_val = 31337;
|
243 | c3d2689d | balrog | s->val = 0;
|
244 | c3d2689d | balrog | s->ptv = 0;
|
245 | c3d2689d | balrog | s->ar = 0;
|
246 | c3d2689d | balrog | s->st = 0;
|
247 | c3d2689d | balrog | s->it_ena = 1;
|
248 | c3d2689d | balrog | } |
249 | c3d2689d | balrog | |
250 | c1ff227b | cmchao | static struct omap_mpu_timer_s *omap_mpu_timer_init(target_phys_addr_t base, |
251 | c3d2689d | balrog | qemu_irq irq, omap_clk clk) |
252 | c3d2689d | balrog | { |
253 | c3d2689d | balrog | int iomemtype;
|
254 | c3d2689d | balrog | struct omap_mpu_timer_s *s = (struct omap_mpu_timer_s *) |
255 | c3d2689d | balrog | qemu_mallocz(sizeof(struct omap_mpu_timer_s)); |
256 | c3d2689d | balrog | |
257 | c3d2689d | balrog | s->irq = irq; |
258 | c3d2689d | balrog | s->clk = clk; |
259 | c3d2689d | balrog | s->timer = qemu_new_timer(vm_clock, omap_timer_tick, s); |
260 | e856f2ad | balrog | s->tick = qemu_bh_new(omap_timer_fire, s); |
261 | c3d2689d | balrog | omap_mpu_timer_reset(s); |
262 | c3d2689d | balrog | omap_timer_clk_setup(s); |
263 | c3d2689d | balrog | |
264 | 1eed09cb | Avi Kivity | iomemtype = cpu_register_io_memory(omap_mpu_timer_readfn, |
265 | c3d2689d | balrog | omap_mpu_timer_writefn, s); |
266 | 8da3ff18 | pbrook | cpu_register_physical_memory(base, 0x100, iomemtype);
|
267 | c3d2689d | balrog | |
268 | c3d2689d | balrog | return s;
|
269 | c3d2689d | balrog | } |
270 | c3d2689d | balrog | |
271 | c3d2689d | balrog | /* Watchdog timer */
|
272 | c3d2689d | balrog | struct omap_watchdog_timer_s {
|
273 | c3d2689d | balrog | struct omap_mpu_timer_s timer;
|
274 | c3d2689d | balrog | uint8_t last_wr; |
275 | c3d2689d | balrog | int mode;
|
276 | c3d2689d | balrog | int free;
|
277 | c3d2689d | balrog | int reset;
|
278 | c3d2689d | balrog | }; |
279 | c3d2689d | balrog | |
280 | c227f099 | Anthony Liguori | static uint32_t omap_wd_timer_read(void *opaque, target_phys_addr_t addr) |
281 | c3d2689d | balrog | { |
282 | c3d2689d | balrog | struct omap_watchdog_timer_s *s = (struct omap_watchdog_timer_s *) opaque; |
283 | c3d2689d | balrog | |
284 | 8da3ff18 | pbrook | switch (addr) {
|
285 | c3d2689d | balrog | case 0x00: /* CNTL_TIMER */ |
286 | c3d2689d | balrog | return (s->timer.ptv << 9) | (s->timer.ar << 8) | |
287 | c3d2689d | balrog | (s->timer.st << 7) | (s->free << 1); |
288 | c3d2689d | balrog | |
289 | c3d2689d | balrog | case 0x04: /* READ_TIMER */ |
290 | c3d2689d | balrog | return omap_timer_read(&s->timer);
|
291 | c3d2689d | balrog | |
292 | c3d2689d | balrog | case 0x08: /* TIMER_MODE */ |
293 | c3d2689d | balrog | return s->mode << 15; |
294 | c3d2689d | balrog | } |
295 | c3d2689d | balrog | |
296 | c3d2689d | balrog | OMAP_BAD_REG(addr); |
297 | c3d2689d | balrog | return 0; |
298 | c3d2689d | balrog | } |
299 | c3d2689d | balrog | |
300 | c227f099 | Anthony Liguori | static void omap_wd_timer_write(void *opaque, target_phys_addr_t addr, |
301 | c3d2689d | balrog | uint32_t value) |
302 | c3d2689d | balrog | { |
303 | c3d2689d | balrog | struct omap_watchdog_timer_s *s = (struct omap_watchdog_timer_s *) opaque; |
304 | c3d2689d | balrog | |
305 | 8da3ff18 | pbrook | switch (addr) {
|
306 | c3d2689d | balrog | case 0x00: /* CNTL_TIMER */ |
307 | c3d2689d | balrog | omap_timer_sync(&s->timer); |
308 | c3d2689d | balrog | s->timer.ptv = (value >> 9) & 7; |
309 | c3d2689d | balrog | s->timer.ar = (value >> 8) & 1; |
310 | c3d2689d | balrog | s->timer.st = (value >> 7) & 1; |
311 | c3d2689d | balrog | s->free = (value >> 1) & 1; |
312 | c3d2689d | balrog | omap_timer_update(&s->timer); |
313 | c3d2689d | balrog | break;
|
314 | c3d2689d | balrog | |
315 | c3d2689d | balrog | case 0x04: /* LOAD_TIMER */ |
316 | c3d2689d | balrog | s->timer.reset_val = value & 0xffff;
|
317 | c3d2689d | balrog | break;
|
318 | c3d2689d | balrog | |
319 | c3d2689d | balrog | case 0x08: /* TIMER_MODE */ |
320 | c3d2689d | balrog | if (!s->mode && ((value >> 15) & 1)) |
321 | c3d2689d | balrog | omap_clk_get(s->timer.clk); |
322 | c3d2689d | balrog | s->mode |= (value >> 15) & 1; |
323 | c3d2689d | balrog | if (s->last_wr == 0xf5) { |
324 | c3d2689d | balrog | if ((value & 0xff) == 0xa0) { |
325 | d8f699cb | balrog | if (s->mode) {
|
326 | d8f699cb | balrog | s->mode = 0;
|
327 | d8f699cb | balrog | omap_clk_put(s->timer.clk); |
328 | d8f699cb | balrog | } |
329 | c3d2689d | balrog | } else {
|
330 | c3d2689d | balrog | /* XXX: on T|E hardware somehow this has no effect,
|
331 | c3d2689d | balrog | * on Zire 71 it works as specified. */
|
332 | c3d2689d | balrog | s->reset = 1;
|
333 | c3d2689d | balrog | qemu_system_reset_request(); |
334 | c3d2689d | balrog | } |
335 | c3d2689d | balrog | } |
336 | c3d2689d | balrog | s->last_wr = value & 0xff;
|
337 | c3d2689d | balrog | break;
|
338 | c3d2689d | balrog | |
339 | c3d2689d | balrog | default:
|
340 | c3d2689d | balrog | OMAP_BAD_REG(addr); |
341 | c3d2689d | balrog | } |
342 | c3d2689d | balrog | } |
343 | c3d2689d | balrog | |
344 | d60efc6b | Blue Swirl | static CPUReadMemoryFunc * const omap_wd_timer_readfn[] = { |
345 | c3d2689d | balrog | omap_badwidth_read16, |
346 | c3d2689d | balrog | omap_wd_timer_read, |
347 | c3d2689d | balrog | omap_badwidth_read16, |
348 | c3d2689d | balrog | }; |
349 | c3d2689d | balrog | |
350 | d60efc6b | Blue Swirl | static CPUWriteMemoryFunc * const omap_wd_timer_writefn[] = { |
351 | c3d2689d | balrog | omap_badwidth_write16, |
352 | c3d2689d | balrog | omap_wd_timer_write, |
353 | c3d2689d | balrog | omap_badwidth_write16, |
354 | c3d2689d | balrog | }; |
355 | c3d2689d | balrog | |
356 | c3d2689d | balrog | static void omap_wd_timer_reset(struct omap_watchdog_timer_s *s) |
357 | c3d2689d | balrog | { |
358 | c3d2689d | balrog | qemu_del_timer(s->timer.timer); |
359 | c3d2689d | balrog | if (!s->mode)
|
360 | c3d2689d | balrog | omap_clk_get(s->timer.clk); |
361 | c3d2689d | balrog | s->mode = 1;
|
362 | c3d2689d | balrog | s->free = 1;
|
363 | c3d2689d | balrog | s->reset = 0;
|
364 | c3d2689d | balrog | s->timer.enable = 1;
|
365 | c3d2689d | balrog | s->timer.it_ena = 1;
|
366 | c3d2689d | balrog | s->timer.reset_val = 0xffff;
|
367 | c3d2689d | balrog | s->timer.val = 0;
|
368 | c3d2689d | balrog | s->timer.st = 0;
|
369 | c3d2689d | balrog | s->timer.ptv = 0;
|
370 | c3d2689d | balrog | s->timer.ar = 0;
|
371 | c3d2689d | balrog | omap_timer_update(&s->timer); |
372 | c3d2689d | balrog | } |
373 | c3d2689d | balrog | |
374 | c1ff227b | cmchao | static struct omap_watchdog_timer_s *omap_wd_timer_init(target_phys_addr_t base, |
375 | c3d2689d | balrog | qemu_irq irq, omap_clk clk) |
376 | c3d2689d | balrog | { |
377 | c3d2689d | balrog | int iomemtype;
|
378 | c3d2689d | balrog | struct omap_watchdog_timer_s *s = (struct omap_watchdog_timer_s *) |
379 | c3d2689d | balrog | qemu_mallocz(sizeof(struct omap_watchdog_timer_s)); |
380 | c3d2689d | balrog | |
381 | c3d2689d | balrog | s->timer.irq = irq; |
382 | c3d2689d | balrog | s->timer.clk = clk; |
383 | c3d2689d | balrog | s->timer.timer = qemu_new_timer(vm_clock, omap_timer_tick, &s->timer); |
384 | c3d2689d | balrog | omap_wd_timer_reset(s); |
385 | c3d2689d | balrog | omap_timer_clk_setup(&s->timer); |
386 | c3d2689d | balrog | |
387 | 1eed09cb | Avi Kivity | iomemtype = cpu_register_io_memory(omap_wd_timer_readfn, |
388 | c3d2689d | balrog | omap_wd_timer_writefn, s); |
389 | 8da3ff18 | pbrook | cpu_register_physical_memory(base, 0x100, iomemtype);
|
390 | c3d2689d | balrog | |
391 | c3d2689d | balrog | return s;
|
392 | c3d2689d | balrog | } |
393 | c3d2689d | balrog | |
394 | c3d2689d | balrog | /* 32-kHz timer */
|
395 | c3d2689d | balrog | struct omap_32khz_timer_s {
|
396 | c3d2689d | balrog | struct omap_mpu_timer_s timer;
|
397 | c3d2689d | balrog | }; |
398 | c3d2689d | balrog | |
399 | c227f099 | Anthony Liguori | static uint32_t omap_os_timer_read(void *opaque, target_phys_addr_t addr) |
400 | c3d2689d | balrog | { |
401 | c3d2689d | balrog | struct omap_32khz_timer_s *s = (struct omap_32khz_timer_s *) opaque; |
402 | cf965d24 | balrog | int offset = addr & OMAP_MPUI_REG_MASK;
|
403 | c3d2689d | balrog | |
404 | c3d2689d | balrog | switch (offset) {
|
405 | c3d2689d | balrog | case 0x00: /* TVR */ |
406 | c3d2689d | balrog | return s->timer.reset_val;
|
407 | c3d2689d | balrog | |
408 | c3d2689d | balrog | case 0x04: /* TCR */ |
409 | c3d2689d | balrog | return omap_timer_read(&s->timer);
|
410 | c3d2689d | balrog | |
411 | c3d2689d | balrog | case 0x08: /* CR */ |
412 | c3d2689d | balrog | return (s->timer.ar << 3) | (s->timer.it_ena << 2) | s->timer.st; |
413 | c3d2689d | balrog | |
414 | c3d2689d | balrog | default:
|
415 | c3d2689d | balrog | break;
|
416 | c3d2689d | balrog | } |
417 | c3d2689d | balrog | OMAP_BAD_REG(addr); |
418 | c3d2689d | balrog | return 0; |
419 | c3d2689d | balrog | } |
420 | c3d2689d | balrog | |
421 | c227f099 | Anthony Liguori | static void omap_os_timer_write(void *opaque, target_phys_addr_t addr, |
422 | c3d2689d | balrog | uint32_t value) |
423 | c3d2689d | balrog | { |
424 | c3d2689d | balrog | struct omap_32khz_timer_s *s = (struct omap_32khz_timer_s *) opaque; |
425 | cf965d24 | balrog | int offset = addr & OMAP_MPUI_REG_MASK;
|
426 | c3d2689d | balrog | |
427 | c3d2689d | balrog | switch (offset) {
|
428 | c3d2689d | balrog | case 0x00: /* TVR */ |
429 | c3d2689d | balrog | s->timer.reset_val = value & 0x00ffffff;
|
430 | c3d2689d | balrog | break;
|
431 | c3d2689d | balrog | |
432 | c3d2689d | balrog | case 0x04: /* TCR */ |
433 | c3d2689d | balrog | OMAP_RO_REG(addr); |
434 | c3d2689d | balrog | break;
|
435 | c3d2689d | balrog | |
436 | c3d2689d | balrog | case 0x08: /* CR */ |
437 | c3d2689d | balrog | s->timer.ar = (value >> 3) & 1; |
438 | c3d2689d | balrog | s->timer.it_ena = (value >> 2) & 1; |
439 | c3d2689d | balrog | if (s->timer.st != (value & 1) || (value & 2)) { |
440 | c3d2689d | balrog | omap_timer_sync(&s->timer); |
441 | c3d2689d | balrog | s->timer.enable = value & 1;
|
442 | c3d2689d | balrog | s->timer.st = value & 1;
|
443 | c3d2689d | balrog | omap_timer_update(&s->timer); |
444 | c3d2689d | balrog | } |
445 | c3d2689d | balrog | break;
|
446 | c3d2689d | balrog | |
447 | c3d2689d | balrog | default:
|
448 | c3d2689d | balrog | OMAP_BAD_REG(addr); |
449 | c3d2689d | balrog | } |
450 | c3d2689d | balrog | } |
451 | c3d2689d | balrog | |
452 | d60efc6b | Blue Swirl | static CPUReadMemoryFunc * const omap_os_timer_readfn[] = { |
453 | c3d2689d | balrog | omap_badwidth_read32, |
454 | c3d2689d | balrog | omap_badwidth_read32, |
455 | c3d2689d | balrog | omap_os_timer_read, |
456 | c3d2689d | balrog | }; |
457 | c3d2689d | balrog | |
458 | d60efc6b | Blue Swirl | static CPUWriteMemoryFunc * const omap_os_timer_writefn[] = { |
459 | c3d2689d | balrog | omap_badwidth_write32, |
460 | c3d2689d | balrog | omap_badwidth_write32, |
461 | c3d2689d | balrog | omap_os_timer_write, |
462 | c3d2689d | balrog | }; |
463 | c3d2689d | balrog | |
464 | c3d2689d | balrog | static void omap_os_timer_reset(struct omap_32khz_timer_s *s) |
465 | c3d2689d | balrog | { |
466 | c3d2689d | balrog | qemu_del_timer(s->timer.timer); |
467 | c3d2689d | balrog | s->timer.enable = 0;
|
468 | c3d2689d | balrog | s->timer.it_ena = 0;
|
469 | c3d2689d | balrog | s->timer.reset_val = 0x00ffffff;
|
470 | c3d2689d | balrog | s->timer.val = 0;
|
471 | c3d2689d | balrog | s->timer.st = 0;
|
472 | c3d2689d | balrog | s->timer.ptv = 0;
|
473 | c3d2689d | balrog | s->timer.ar = 1;
|
474 | c3d2689d | balrog | } |
475 | c3d2689d | balrog | |
476 | c1ff227b | cmchao | static struct omap_32khz_timer_s *omap_os_timer_init(target_phys_addr_t base, |
477 | c3d2689d | balrog | qemu_irq irq, omap_clk clk) |
478 | c3d2689d | balrog | { |
479 | c3d2689d | balrog | int iomemtype;
|
480 | c3d2689d | balrog | struct omap_32khz_timer_s *s = (struct omap_32khz_timer_s *) |
481 | c3d2689d | balrog | qemu_mallocz(sizeof(struct omap_32khz_timer_s)); |
482 | c3d2689d | balrog | |
483 | c3d2689d | balrog | s->timer.irq = irq; |
484 | c3d2689d | balrog | s->timer.clk = clk; |
485 | c3d2689d | balrog | s->timer.timer = qemu_new_timer(vm_clock, omap_timer_tick, &s->timer); |
486 | c3d2689d | balrog | omap_os_timer_reset(s); |
487 | c3d2689d | balrog | omap_timer_clk_setup(&s->timer); |
488 | c3d2689d | balrog | |
489 | 1eed09cb | Avi Kivity | iomemtype = cpu_register_io_memory(omap_os_timer_readfn, |
490 | c3d2689d | balrog | omap_os_timer_writefn, s); |
491 | 8da3ff18 | pbrook | cpu_register_physical_memory(base, 0x800, iomemtype);
|
492 | c3d2689d | balrog | |
493 | c3d2689d | balrog | return s;
|
494 | c3d2689d | balrog | } |
495 | c3d2689d | balrog | |
496 | c3d2689d | balrog | /* Ultra Low-Power Device Module */
|
497 | c227f099 | Anthony Liguori | static uint32_t omap_ulpd_pm_read(void *opaque, target_phys_addr_t addr) |
498 | c3d2689d | balrog | { |
499 | c3d2689d | balrog | struct omap_mpu_state_s *s = (struct omap_mpu_state_s *) opaque; |
500 | c3d2689d | balrog | uint16_t ret; |
501 | c3d2689d | balrog | |
502 | 8da3ff18 | pbrook | switch (addr) {
|
503 | c3d2689d | balrog | case 0x14: /* IT_STATUS */ |
504 | 8da3ff18 | pbrook | ret = s->ulpd_pm_regs[addr >> 2];
|
505 | 8da3ff18 | pbrook | s->ulpd_pm_regs[addr >> 2] = 0; |
506 | c3d2689d | balrog | qemu_irq_lower(s->irq[1][OMAP_INT_GAUGE_32K]);
|
507 | c3d2689d | balrog | return ret;
|
508 | c3d2689d | balrog | |
509 | c3d2689d | balrog | case 0x18: /* Reserved */ |
510 | c3d2689d | balrog | case 0x1c: /* Reserved */ |
511 | c3d2689d | balrog | case 0x20: /* Reserved */ |
512 | c3d2689d | balrog | case 0x28: /* Reserved */ |
513 | c3d2689d | balrog | case 0x2c: /* Reserved */ |
514 | c3d2689d | balrog | OMAP_BAD_REG(addr); |
515 | c3d2689d | balrog | case 0x00: /* COUNTER_32_LSB */ |
516 | c3d2689d | balrog | case 0x04: /* COUNTER_32_MSB */ |
517 | c3d2689d | balrog | case 0x08: /* COUNTER_HIGH_FREQ_LSB */ |
518 | c3d2689d | balrog | case 0x0c: /* COUNTER_HIGH_FREQ_MSB */ |
519 | c3d2689d | balrog | case 0x10: /* GAUGING_CTRL */ |
520 | c3d2689d | balrog | case 0x24: /* SETUP_ANALOG_CELL3_ULPD1 */ |
521 | c3d2689d | balrog | case 0x30: /* CLOCK_CTRL */ |
522 | c3d2689d | balrog | case 0x34: /* SOFT_REQ */ |
523 | c3d2689d | balrog | case 0x38: /* COUNTER_32_FIQ */ |
524 | c3d2689d | balrog | case 0x3c: /* DPLL_CTRL */ |
525 | c3d2689d | balrog | case 0x40: /* STATUS_REQ */ |
526 | c3d2689d | balrog | /* XXX: check clk::usecount state for every clock */
|
527 | c3d2689d | balrog | case 0x48: /* LOCL_TIME */ |
528 | c3d2689d | balrog | case 0x4c: /* APLL_CTRL */ |
529 | c3d2689d | balrog | case 0x50: /* POWER_CTRL */ |
530 | 8da3ff18 | pbrook | return s->ulpd_pm_regs[addr >> 2]; |
531 | c3d2689d | balrog | } |
532 | c3d2689d | balrog | |
533 | c3d2689d | balrog | OMAP_BAD_REG(addr); |
534 | c3d2689d | balrog | return 0; |
535 | c3d2689d | balrog | } |
536 | c3d2689d | balrog | |
537 | c3d2689d | balrog | static inline void omap_ulpd_clk_update(struct omap_mpu_state_s *s, |
538 | c3d2689d | balrog | uint16_t diff, uint16_t value) |
539 | c3d2689d | balrog | { |
540 | c3d2689d | balrog | if (diff & (1 << 4)) /* USB_MCLK_EN */ |
541 | c3d2689d | balrog | omap_clk_onoff(omap_findclk(s, "usb_clk0"), (value >> 4) & 1); |
542 | c3d2689d | balrog | if (diff & (1 << 5)) /* DIS_USB_PVCI_CLK */ |
543 | c3d2689d | balrog | omap_clk_onoff(omap_findclk(s, "usb_w2fc_ck"), (~value >> 5) & 1); |
544 | c3d2689d | balrog | } |
545 | c3d2689d | balrog | |
546 | c3d2689d | balrog | static inline void omap_ulpd_req_update(struct omap_mpu_state_s *s, |
547 | c3d2689d | balrog | uint16_t diff, uint16_t value) |
548 | c3d2689d | balrog | { |
549 | c3d2689d | balrog | if (diff & (1 << 0)) /* SOFT_DPLL_REQ */ |
550 | c3d2689d | balrog | omap_clk_canidle(omap_findclk(s, "dpll4"), (~value >> 0) & 1); |
551 | c3d2689d | balrog | if (diff & (1 << 1)) /* SOFT_COM_REQ */ |
552 | c3d2689d | balrog | omap_clk_canidle(omap_findclk(s, "com_mclk_out"), (~value >> 1) & 1); |
553 | c3d2689d | balrog | if (diff & (1 << 2)) /* SOFT_SDW_REQ */ |
554 | c3d2689d | balrog | omap_clk_canidle(omap_findclk(s, "bt_mclk_out"), (~value >> 2) & 1); |
555 | c3d2689d | balrog | if (diff & (1 << 3)) /* SOFT_USB_REQ */ |
556 | c3d2689d | balrog | omap_clk_canidle(omap_findclk(s, "usb_clk0"), (~value >> 3) & 1); |
557 | c3d2689d | balrog | } |
558 | c3d2689d | balrog | |
559 | c227f099 | Anthony Liguori | static void omap_ulpd_pm_write(void *opaque, target_phys_addr_t addr, |
560 | c3d2689d | balrog | uint32_t value) |
561 | c3d2689d | balrog | { |
562 | c3d2689d | balrog | struct omap_mpu_state_s *s = (struct omap_mpu_state_s *) opaque; |
563 | c3d2689d | balrog | int64_t now, ticks; |
564 | c3d2689d | balrog | int div, mult;
|
565 | c3d2689d | balrog | static const int bypass_div[4] = { 1, 2, 4, 4 }; |
566 | c3d2689d | balrog | uint16_t diff; |
567 | c3d2689d | balrog | |
568 | 8da3ff18 | pbrook | switch (addr) {
|
569 | c3d2689d | balrog | case 0x00: /* COUNTER_32_LSB */ |
570 | c3d2689d | balrog | case 0x04: /* COUNTER_32_MSB */ |
571 | c3d2689d | balrog | case 0x08: /* COUNTER_HIGH_FREQ_LSB */ |
572 | c3d2689d | balrog | case 0x0c: /* COUNTER_HIGH_FREQ_MSB */ |
573 | c3d2689d | balrog | case 0x14: /* IT_STATUS */ |
574 | c3d2689d | balrog | case 0x40: /* STATUS_REQ */ |
575 | c3d2689d | balrog | OMAP_RO_REG(addr); |
576 | c3d2689d | balrog | break;
|
577 | c3d2689d | balrog | |
578 | c3d2689d | balrog | case 0x10: /* GAUGING_CTRL */ |
579 | c3d2689d | balrog | /* Bits 0 and 1 seem to be confused in the OMAP 310 TRM */
|
580 | 8da3ff18 | pbrook | if ((s->ulpd_pm_regs[addr >> 2] ^ value) & 1) { |
581 | c3d2689d | balrog | now = qemu_get_clock(vm_clock); |
582 | c3d2689d | balrog | |
583 | c3d2689d | balrog | if (value & 1) |
584 | c3d2689d | balrog | s->ulpd_gauge_start = now; |
585 | c3d2689d | balrog | else {
|
586 | c3d2689d | balrog | now -= s->ulpd_gauge_start; |
587 | c3d2689d | balrog | |
588 | c3d2689d | balrog | /* 32-kHz ticks */
|
589 | 6ee093c9 | Juan Quintela | ticks = muldiv64(now, 32768, get_ticks_per_sec());
|
590 | c3d2689d | balrog | s->ulpd_pm_regs[0x00 >> 2] = (ticks >> 0) & 0xffff; |
591 | c3d2689d | balrog | s->ulpd_pm_regs[0x04 >> 2] = (ticks >> 16) & 0xffff; |
592 | c3d2689d | balrog | if (ticks >> 32) /* OVERFLOW_32K */ |
593 | c3d2689d | balrog | s->ulpd_pm_regs[0x14 >> 2] |= 1 << 2; |
594 | c3d2689d | balrog | |
595 | c3d2689d | balrog | /* High frequency ticks */
|
596 | 6ee093c9 | Juan Quintela | ticks = muldiv64(now, 12000000, get_ticks_per_sec());
|
597 | c3d2689d | balrog | s->ulpd_pm_regs[0x08 >> 2] = (ticks >> 0) & 0xffff; |
598 | c3d2689d | balrog | s->ulpd_pm_regs[0x0c >> 2] = (ticks >> 16) & 0xffff; |
599 | c3d2689d | balrog | if (ticks >> 32) /* OVERFLOW_HI_FREQ */ |
600 | c3d2689d | balrog | s->ulpd_pm_regs[0x14 >> 2] |= 1 << 1; |
601 | c3d2689d | balrog | |
602 | c3d2689d | balrog | s->ulpd_pm_regs[0x14 >> 2] |= 1 << 0; /* IT_GAUGING */ |
603 | c3d2689d | balrog | qemu_irq_raise(s->irq[1][OMAP_INT_GAUGE_32K]);
|
604 | c3d2689d | balrog | } |
605 | c3d2689d | balrog | } |
606 | 8da3ff18 | pbrook | s->ulpd_pm_regs[addr >> 2] = value;
|
607 | c3d2689d | balrog | break;
|
608 | c3d2689d | balrog | |
609 | c3d2689d | balrog | case 0x18: /* Reserved */ |
610 | c3d2689d | balrog | case 0x1c: /* Reserved */ |
611 | c3d2689d | balrog | case 0x20: /* Reserved */ |
612 | c3d2689d | balrog | case 0x28: /* Reserved */ |
613 | c3d2689d | balrog | case 0x2c: /* Reserved */ |
614 | c3d2689d | balrog | OMAP_BAD_REG(addr); |
615 | c3d2689d | balrog | case 0x24: /* SETUP_ANALOG_CELL3_ULPD1 */ |
616 | c3d2689d | balrog | case 0x38: /* COUNTER_32_FIQ */ |
617 | c3d2689d | balrog | case 0x48: /* LOCL_TIME */ |
618 | c3d2689d | balrog | case 0x50: /* POWER_CTRL */ |
619 | 8da3ff18 | pbrook | s->ulpd_pm_regs[addr >> 2] = value;
|
620 | c3d2689d | balrog | break;
|
621 | c3d2689d | balrog | |
622 | c3d2689d | balrog | case 0x30: /* CLOCK_CTRL */ |
623 | 8da3ff18 | pbrook | diff = s->ulpd_pm_regs[addr >> 2] ^ value;
|
624 | 8da3ff18 | pbrook | s->ulpd_pm_regs[addr >> 2] = value & 0x3f; |
625 | c3d2689d | balrog | omap_ulpd_clk_update(s, diff, value); |
626 | c3d2689d | balrog | break;
|
627 | c3d2689d | balrog | |
628 | c3d2689d | balrog | case 0x34: /* SOFT_REQ */ |
629 | 8da3ff18 | pbrook | diff = s->ulpd_pm_regs[addr >> 2] ^ value;
|
630 | 8da3ff18 | pbrook | s->ulpd_pm_regs[addr >> 2] = value & 0x1f; |
631 | c3d2689d | balrog | omap_ulpd_req_update(s, diff, value); |
632 | c3d2689d | balrog | break;
|
633 | c3d2689d | balrog | |
634 | c3d2689d | balrog | case 0x3c: /* DPLL_CTRL */ |
635 | c3d2689d | balrog | /* XXX: OMAP310 TRM claims bit 3 is PLL_ENABLE, and bit 4 is
|
636 | c3d2689d | balrog | * omitted altogether, probably a typo. */
|
637 | c3d2689d | balrog | /* This register has identical semantics with DPLL(1:3) control
|
638 | c3d2689d | balrog | * registers, see omap_dpll_write() */
|
639 | 8da3ff18 | pbrook | diff = s->ulpd_pm_regs[addr >> 2] & value;
|
640 | 8da3ff18 | pbrook | s->ulpd_pm_regs[addr >> 2] = value & 0x2fff; |
641 | c3d2689d | balrog | if (diff & (0x3ff << 2)) { |
642 | c3d2689d | balrog | if (value & (1 << 4)) { /* PLL_ENABLE */ |
643 | c3d2689d | balrog | div = ((value >> 5) & 3) + 1; /* PLL_DIV */ |
644 | c3d2689d | balrog | mult = MIN((value >> 7) & 0x1f, 1); /* PLL_MULT */ |
645 | c3d2689d | balrog | } else {
|
646 | c3d2689d | balrog | div = bypass_div[((value >> 2) & 3)]; /* BYPASS_DIV */ |
647 | c3d2689d | balrog | mult = 1;
|
648 | c3d2689d | balrog | } |
649 | c3d2689d | balrog | omap_clk_setrate(omap_findclk(s, "dpll4"), div, mult);
|
650 | c3d2689d | balrog | } |
651 | c3d2689d | balrog | |
652 | c3d2689d | balrog | /* Enter the desired mode. */
|
653 | 8da3ff18 | pbrook | s->ulpd_pm_regs[addr >> 2] =
|
654 | 8da3ff18 | pbrook | (s->ulpd_pm_regs[addr >> 2] & 0xfffe) | |
655 | 8da3ff18 | pbrook | ((s->ulpd_pm_regs[addr >> 2] >> 4) & 1); |
656 | c3d2689d | balrog | |
657 | c3d2689d | balrog | /* Act as if the lock is restored. */
|
658 | 8da3ff18 | pbrook | s->ulpd_pm_regs[addr >> 2] |= 2; |
659 | c3d2689d | balrog | break;
|
660 | c3d2689d | balrog | |
661 | c3d2689d | balrog | case 0x4c: /* APLL_CTRL */ |
662 | 8da3ff18 | pbrook | diff = s->ulpd_pm_regs[addr >> 2] & value;
|
663 | 8da3ff18 | pbrook | s->ulpd_pm_regs[addr >> 2] = value & 0xf; |
664 | c3d2689d | balrog | if (diff & (1 << 0)) /* APLL_NDPLL_SWITCH */ |
665 | c3d2689d | balrog | omap_clk_reparent(omap_findclk(s, "ck_48m"), omap_findclk(s,
|
666 | c3d2689d | balrog | (value & (1 << 0)) ? "apll" : "dpll4")); |
667 | c3d2689d | balrog | break;
|
668 | c3d2689d | balrog | |
669 | c3d2689d | balrog | default:
|
670 | c3d2689d | balrog | OMAP_BAD_REG(addr); |
671 | c3d2689d | balrog | } |
672 | c3d2689d | balrog | } |
673 | c3d2689d | balrog | |
674 | d60efc6b | Blue Swirl | static CPUReadMemoryFunc * const omap_ulpd_pm_readfn[] = { |
675 | c3d2689d | balrog | omap_badwidth_read16, |
676 | c3d2689d | balrog | omap_ulpd_pm_read, |
677 | c3d2689d | balrog | omap_badwidth_read16, |
678 | c3d2689d | balrog | }; |
679 | c3d2689d | balrog | |
680 | d60efc6b | Blue Swirl | static CPUWriteMemoryFunc * const omap_ulpd_pm_writefn[] = { |
681 | c3d2689d | balrog | omap_badwidth_write16, |
682 | c3d2689d | balrog | omap_ulpd_pm_write, |
683 | c3d2689d | balrog | omap_badwidth_write16, |
684 | c3d2689d | balrog | }; |
685 | c3d2689d | balrog | |
686 | c3d2689d | balrog | static void omap_ulpd_pm_reset(struct omap_mpu_state_s *mpu) |
687 | c3d2689d | balrog | { |
688 | c3d2689d | balrog | mpu->ulpd_pm_regs[0x00 >> 2] = 0x0001; |
689 | c3d2689d | balrog | mpu->ulpd_pm_regs[0x04 >> 2] = 0x0000; |
690 | c3d2689d | balrog | mpu->ulpd_pm_regs[0x08 >> 2] = 0x0001; |
691 | c3d2689d | balrog | mpu->ulpd_pm_regs[0x0c >> 2] = 0x0000; |
692 | c3d2689d | balrog | mpu->ulpd_pm_regs[0x10 >> 2] = 0x0000; |
693 | c3d2689d | balrog | mpu->ulpd_pm_regs[0x18 >> 2] = 0x01; |
694 | c3d2689d | balrog | mpu->ulpd_pm_regs[0x1c >> 2] = 0x01; |
695 | c3d2689d | balrog | mpu->ulpd_pm_regs[0x20 >> 2] = 0x01; |
696 | c3d2689d | balrog | mpu->ulpd_pm_regs[0x24 >> 2] = 0x03ff; |
697 | c3d2689d | balrog | mpu->ulpd_pm_regs[0x28 >> 2] = 0x01; |
698 | c3d2689d | balrog | mpu->ulpd_pm_regs[0x2c >> 2] = 0x01; |
699 | c3d2689d | balrog | omap_ulpd_clk_update(mpu, mpu->ulpd_pm_regs[0x30 >> 2], 0x0000); |
700 | c3d2689d | balrog | mpu->ulpd_pm_regs[0x30 >> 2] = 0x0000; |
701 | c3d2689d | balrog | omap_ulpd_req_update(mpu, mpu->ulpd_pm_regs[0x34 >> 2], 0x0000); |
702 | c3d2689d | balrog | mpu->ulpd_pm_regs[0x34 >> 2] = 0x0000; |
703 | c3d2689d | balrog | mpu->ulpd_pm_regs[0x38 >> 2] = 0x0001; |
704 | c3d2689d | balrog | mpu->ulpd_pm_regs[0x3c >> 2] = 0x2211; |
705 | c3d2689d | balrog | mpu->ulpd_pm_regs[0x40 >> 2] = 0x0000; /* FIXME: dump a real STATUS_REQ */ |
706 | c3d2689d | balrog | mpu->ulpd_pm_regs[0x48 >> 2] = 0x960; |
707 | c3d2689d | balrog | mpu->ulpd_pm_regs[0x4c >> 2] = 0x08; |
708 | c3d2689d | balrog | mpu->ulpd_pm_regs[0x50 >> 2] = 0x08; |
709 | c3d2689d | balrog | omap_clk_setrate(omap_findclk(mpu, "dpll4"), 1, 4); |
710 | c3d2689d | balrog | omap_clk_reparent(omap_findclk(mpu, "ck_48m"), omap_findclk(mpu, "dpll4")); |
711 | c3d2689d | balrog | } |
712 | c3d2689d | balrog | |
713 | c227f099 | Anthony Liguori | static void omap_ulpd_pm_init(target_phys_addr_t base, |
714 | c3d2689d | balrog | struct omap_mpu_state_s *mpu)
|
715 | c3d2689d | balrog | { |
716 | 1eed09cb | Avi Kivity | int iomemtype = cpu_register_io_memory(omap_ulpd_pm_readfn,
|
717 | c3d2689d | balrog | omap_ulpd_pm_writefn, mpu); |
718 | c3d2689d | balrog | |
719 | 8da3ff18 | pbrook | cpu_register_physical_memory(base, 0x800, iomemtype);
|
720 | c3d2689d | balrog | omap_ulpd_pm_reset(mpu); |
721 | c3d2689d | balrog | } |
722 | c3d2689d | balrog | |
723 | c3d2689d | balrog | /* OMAP Pin Configuration */
|
724 | c227f099 | Anthony Liguori | static uint32_t omap_pin_cfg_read(void *opaque, target_phys_addr_t addr) |
725 | c3d2689d | balrog | { |
726 | c3d2689d | balrog | struct omap_mpu_state_s *s = (struct omap_mpu_state_s *) opaque; |
727 | c3d2689d | balrog | |
728 | 8da3ff18 | pbrook | switch (addr) {
|
729 | c3d2689d | balrog | case 0x00: /* FUNC_MUX_CTRL_0 */ |
730 | c3d2689d | balrog | case 0x04: /* FUNC_MUX_CTRL_1 */ |
731 | c3d2689d | balrog | case 0x08: /* FUNC_MUX_CTRL_2 */ |
732 | 8da3ff18 | pbrook | return s->func_mux_ctrl[addr >> 2]; |
733 | c3d2689d | balrog | |
734 | c3d2689d | balrog | case 0x0c: /* COMP_MODE_CTRL_0 */ |
735 | c3d2689d | balrog | return s->comp_mode_ctrl[0]; |
736 | c3d2689d | balrog | |
737 | c3d2689d | balrog | case 0x10: /* FUNC_MUX_CTRL_3 */ |
738 | c3d2689d | balrog | case 0x14: /* FUNC_MUX_CTRL_4 */ |
739 | c3d2689d | balrog | case 0x18: /* FUNC_MUX_CTRL_5 */ |
740 | c3d2689d | balrog | case 0x1c: /* FUNC_MUX_CTRL_6 */ |
741 | c3d2689d | balrog | case 0x20: /* FUNC_MUX_CTRL_7 */ |
742 | c3d2689d | balrog | case 0x24: /* FUNC_MUX_CTRL_8 */ |
743 | c3d2689d | balrog | case 0x28: /* FUNC_MUX_CTRL_9 */ |
744 | c3d2689d | balrog | case 0x2c: /* FUNC_MUX_CTRL_A */ |
745 | c3d2689d | balrog | case 0x30: /* FUNC_MUX_CTRL_B */ |
746 | c3d2689d | balrog | case 0x34: /* FUNC_MUX_CTRL_C */ |
747 | c3d2689d | balrog | case 0x38: /* FUNC_MUX_CTRL_D */ |
748 | 8da3ff18 | pbrook | return s->func_mux_ctrl[(addr >> 2) - 1]; |
749 | c3d2689d | balrog | |
750 | c3d2689d | balrog | case 0x40: /* PULL_DWN_CTRL_0 */ |
751 | c3d2689d | balrog | case 0x44: /* PULL_DWN_CTRL_1 */ |
752 | c3d2689d | balrog | case 0x48: /* PULL_DWN_CTRL_2 */ |
753 | c3d2689d | balrog | case 0x4c: /* PULL_DWN_CTRL_3 */ |
754 | 8da3ff18 | pbrook | return s->pull_dwn_ctrl[(addr & 0xf) >> 2]; |
755 | c3d2689d | balrog | |
756 | c3d2689d | balrog | case 0x50: /* GATE_INH_CTRL_0 */ |
757 | c3d2689d | balrog | return s->gate_inh_ctrl[0]; |
758 | c3d2689d | balrog | |
759 | c3d2689d | balrog | case 0x60: /* VOLTAGE_CTRL_0 */ |
760 | c3d2689d | balrog | return s->voltage_ctrl[0]; |
761 | c3d2689d | balrog | |
762 | c3d2689d | balrog | case 0x70: /* TEST_DBG_CTRL_0 */ |
763 | c3d2689d | balrog | return s->test_dbg_ctrl[0]; |
764 | c3d2689d | balrog | |
765 | c3d2689d | balrog | case 0x80: /* MOD_CONF_CTRL_0 */ |
766 | c3d2689d | balrog | return s->mod_conf_ctrl[0]; |
767 | c3d2689d | balrog | } |
768 | c3d2689d | balrog | |
769 | c3d2689d | balrog | OMAP_BAD_REG(addr); |
770 | c3d2689d | balrog | return 0; |
771 | c3d2689d | balrog | } |
772 | c3d2689d | balrog | |
773 | c3d2689d | balrog | static inline void omap_pin_funcmux0_update(struct omap_mpu_state_s *s, |
774 | c3d2689d | balrog | uint32_t diff, uint32_t value) |
775 | c3d2689d | balrog | { |
776 | c3d2689d | balrog | if (s->compat1509) {
|
777 | c3d2689d | balrog | if (diff & (1 << 9)) /* BLUETOOTH */ |
778 | c3d2689d | balrog | omap_clk_onoff(omap_findclk(s, "bt_mclk_out"),
|
779 | c3d2689d | balrog | (~value >> 9) & 1); |
780 | c3d2689d | balrog | if (diff & (1 << 7)) /* USB.CLKO */ |
781 | c3d2689d | balrog | omap_clk_onoff(omap_findclk(s, "usb.clko"),
|
782 | c3d2689d | balrog | (value >> 7) & 1); |
783 | c3d2689d | balrog | } |
784 | c3d2689d | balrog | } |
785 | c3d2689d | balrog | |
786 | c3d2689d | balrog | static inline void omap_pin_funcmux1_update(struct omap_mpu_state_s *s, |
787 | c3d2689d | balrog | uint32_t diff, uint32_t value) |
788 | c3d2689d | balrog | { |
789 | c3d2689d | balrog | if (s->compat1509) {
|
790 | c3d2689d | balrog | if (diff & (1 << 31)) /* MCBSP3_CLK_HIZ_DI */ |
791 | c3d2689d | balrog | omap_clk_onoff(omap_findclk(s, "mcbsp3.clkx"),
|
792 | c3d2689d | balrog | (value >> 31) & 1); |
793 | c3d2689d | balrog | if (diff & (1 << 1)) /* CLK32K */ |
794 | c3d2689d | balrog | omap_clk_onoff(omap_findclk(s, "clk32k_out"),
|
795 | c3d2689d | balrog | (~value >> 1) & 1); |
796 | c3d2689d | balrog | } |
797 | c3d2689d | balrog | } |
798 | c3d2689d | balrog | |
799 | c3d2689d | balrog | static inline void omap_pin_modconf1_update(struct omap_mpu_state_s *s, |
800 | c3d2689d | balrog | uint32_t diff, uint32_t value) |
801 | c3d2689d | balrog | { |
802 | c3d2689d | balrog | if (diff & (1 << 31)) /* CONF_MOD_UART3_CLK_MODE_R */ |
803 | c3d2689d | balrog | omap_clk_reparent(omap_findclk(s, "uart3_ck"),
|
804 | c3d2689d | balrog | omap_findclk(s, ((value >> 31) & 1) ? |
805 | c3d2689d | balrog | "ck_48m" : "armper_ck")); |
806 | c3d2689d | balrog | if (diff & (1 << 30)) /* CONF_MOD_UART2_CLK_MODE_R */ |
807 | c3d2689d | balrog | omap_clk_reparent(omap_findclk(s, "uart2_ck"),
|
808 | c3d2689d | balrog | omap_findclk(s, ((value >> 30) & 1) ? |
809 | c3d2689d | balrog | "ck_48m" : "armper_ck")); |
810 | c3d2689d | balrog | if (diff & (1 << 29)) /* CONF_MOD_UART1_CLK_MODE_R */ |
811 | c3d2689d | balrog | omap_clk_reparent(omap_findclk(s, "uart1_ck"),
|
812 | c3d2689d | balrog | omap_findclk(s, ((value >> 29) & 1) ? |
813 | c3d2689d | balrog | "ck_48m" : "armper_ck")); |
814 | c3d2689d | balrog | if (diff & (1 << 23)) /* CONF_MOD_MMC_SD_CLK_REQ_R */ |
815 | c3d2689d | balrog | omap_clk_reparent(omap_findclk(s, "mmc_ck"),
|
816 | c3d2689d | balrog | omap_findclk(s, ((value >> 23) & 1) ? |
817 | c3d2689d | balrog | "ck_48m" : "armper_ck")); |
818 | c3d2689d | balrog | if (diff & (1 << 12)) /* CONF_MOD_COM_MCLK_12_48_S */ |
819 | c3d2689d | balrog | omap_clk_reparent(omap_findclk(s, "com_mclk_out"),
|
820 | c3d2689d | balrog | omap_findclk(s, ((value >> 12) & 1) ? |
821 | c3d2689d | balrog | "ck_48m" : "armper_ck")); |
822 | c3d2689d | balrog | if (diff & (1 << 9)) /* CONF_MOD_USB_HOST_HHC_UHO */ |
823 | c3d2689d | balrog | omap_clk_onoff(omap_findclk(s, "usb_hhc_ck"), (value >> 9) & 1); |
824 | c3d2689d | balrog | } |
825 | c3d2689d | balrog | |
826 | c227f099 | Anthony Liguori | static void omap_pin_cfg_write(void *opaque, target_phys_addr_t addr, |
827 | c3d2689d | balrog | uint32_t value) |
828 | c3d2689d | balrog | { |
829 | c3d2689d | balrog | struct omap_mpu_state_s *s = (struct omap_mpu_state_s *) opaque; |
830 | c3d2689d | balrog | uint32_t diff; |
831 | c3d2689d | balrog | |
832 | 8da3ff18 | pbrook | switch (addr) {
|
833 | c3d2689d | balrog | case 0x00: /* FUNC_MUX_CTRL_0 */ |
834 | 8da3ff18 | pbrook | diff = s->func_mux_ctrl[addr >> 2] ^ value;
|
835 | 8da3ff18 | pbrook | s->func_mux_ctrl[addr >> 2] = value;
|
836 | c3d2689d | balrog | omap_pin_funcmux0_update(s, diff, value); |
837 | c3d2689d | balrog | return;
|
838 | c3d2689d | balrog | |
839 | c3d2689d | balrog | case 0x04: /* FUNC_MUX_CTRL_1 */ |
840 | 8da3ff18 | pbrook | diff = s->func_mux_ctrl[addr >> 2] ^ value;
|
841 | 8da3ff18 | pbrook | s->func_mux_ctrl[addr >> 2] = value;
|
842 | c3d2689d | balrog | omap_pin_funcmux1_update(s, diff, value); |
843 | c3d2689d | balrog | return;
|
844 | c3d2689d | balrog | |
845 | c3d2689d | balrog | case 0x08: /* FUNC_MUX_CTRL_2 */ |
846 | 8da3ff18 | pbrook | s->func_mux_ctrl[addr >> 2] = value;
|
847 | c3d2689d | balrog | return;
|
848 | c3d2689d | balrog | |
849 | c3d2689d | balrog | case 0x0c: /* COMP_MODE_CTRL_0 */ |
850 | c3d2689d | balrog | s->comp_mode_ctrl[0] = value;
|
851 | c3d2689d | balrog | s->compat1509 = (value != 0x0000eaef);
|
852 | c3d2689d | balrog | omap_pin_funcmux0_update(s, ~0, s->func_mux_ctrl[0]); |
853 | c3d2689d | balrog | omap_pin_funcmux1_update(s, ~0, s->func_mux_ctrl[1]); |
854 | c3d2689d | balrog | return;
|
855 | c3d2689d | balrog | |
856 | c3d2689d | balrog | case 0x10: /* FUNC_MUX_CTRL_3 */ |
857 | c3d2689d | balrog | case 0x14: /* FUNC_MUX_CTRL_4 */ |
858 | c3d2689d | balrog | case 0x18: /* FUNC_MUX_CTRL_5 */ |
859 | c3d2689d | balrog | case 0x1c: /* FUNC_MUX_CTRL_6 */ |
860 | c3d2689d | balrog | case 0x20: /* FUNC_MUX_CTRL_7 */ |
861 | c3d2689d | balrog | case 0x24: /* FUNC_MUX_CTRL_8 */ |
862 | c3d2689d | balrog | case 0x28: /* FUNC_MUX_CTRL_9 */ |
863 | c3d2689d | balrog | case 0x2c: /* FUNC_MUX_CTRL_A */ |
864 | c3d2689d | balrog | case 0x30: /* FUNC_MUX_CTRL_B */ |
865 | c3d2689d | balrog | case 0x34: /* FUNC_MUX_CTRL_C */ |
866 | c3d2689d | balrog | case 0x38: /* FUNC_MUX_CTRL_D */ |
867 | 8da3ff18 | pbrook | s->func_mux_ctrl[(addr >> 2) - 1] = value; |
868 | c3d2689d | balrog | return;
|
869 | c3d2689d | balrog | |
870 | c3d2689d | balrog | case 0x40: /* PULL_DWN_CTRL_0 */ |
871 | c3d2689d | balrog | case 0x44: /* PULL_DWN_CTRL_1 */ |
872 | c3d2689d | balrog | case 0x48: /* PULL_DWN_CTRL_2 */ |
873 | c3d2689d | balrog | case 0x4c: /* PULL_DWN_CTRL_3 */ |
874 | 8da3ff18 | pbrook | s->pull_dwn_ctrl[(addr & 0xf) >> 2] = value; |
875 | c3d2689d | balrog | return;
|
876 | c3d2689d | balrog | |
877 | c3d2689d | balrog | case 0x50: /* GATE_INH_CTRL_0 */ |
878 | c3d2689d | balrog | s->gate_inh_ctrl[0] = value;
|
879 | c3d2689d | balrog | return;
|
880 | c3d2689d | balrog | |
881 | c3d2689d | balrog | case 0x60: /* VOLTAGE_CTRL_0 */ |
882 | c3d2689d | balrog | s->voltage_ctrl[0] = value;
|
883 | c3d2689d | balrog | return;
|
884 | c3d2689d | balrog | |
885 | c3d2689d | balrog | case 0x70: /* TEST_DBG_CTRL_0 */ |
886 | c3d2689d | balrog | s->test_dbg_ctrl[0] = value;
|
887 | c3d2689d | balrog | return;
|
888 | c3d2689d | balrog | |
889 | c3d2689d | balrog | case 0x80: /* MOD_CONF_CTRL_0 */ |
890 | c3d2689d | balrog | diff = s->mod_conf_ctrl[0] ^ value;
|
891 | c3d2689d | balrog | s->mod_conf_ctrl[0] = value;
|
892 | c3d2689d | balrog | omap_pin_modconf1_update(s, diff, value); |
893 | c3d2689d | balrog | return;
|
894 | c3d2689d | balrog | |
895 | c3d2689d | balrog | default:
|
896 | c3d2689d | balrog | OMAP_BAD_REG(addr); |
897 | c3d2689d | balrog | } |
898 | c3d2689d | balrog | } |
899 | c3d2689d | balrog | |
900 | d60efc6b | Blue Swirl | static CPUReadMemoryFunc * const omap_pin_cfg_readfn[] = { |
901 | c3d2689d | balrog | omap_badwidth_read32, |
902 | c3d2689d | balrog | omap_badwidth_read32, |
903 | c3d2689d | balrog | omap_pin_cfg_read, |
904 | c3d2689d | balrog | }; |
905 | c3d2689d | balrog | |
906 | d60efc6b | Blue Swirl | static CPUWriteMemoryFunc * const omap_pin_cfg_writefn[] = { |
907 | c3d2689d | balrog | omap_badwidth_write32, |
908 | c3d2689d | balrog | omap_badwidth_write32, |
909 | c3d2689d | balrog | omap_pin_cfg_write, |
910 | c3d2689d | balrog | }; |
911 | c3d2689d | balrog | |
912 | c3d2689d | balrog | static void omap_pin_cfg_reset(struct omap_mpu_state_s *mpu) |
913 | c3d2689d | balrog | { |
914 | c3d2689d | balrog | /* Start in Compatibility Mode. */
|
915 | c3d2689d | balrog | mpu->compat1509 = 1;
|
916 | c3d2689d | balrog | omap_pin_funcmux0_update(mpu, mpu->func_mux_ctrl[0], 0); |
917 | c3d2689d | balrog | omap_pin_funcmux1_update(mpu, mpu->func_mux_ctrl[1], 0); |
918 | c3d2689d | balrog | omap_pin_modconf1_update(mpu, mpu->mod_conf_ctrl[0], 0); |
919 | c3d2689d | balrog | memset(mpu->func_mux_ctrl, 0, sizeof(mpu->func_mux_ctrl)); |
920 | c3d2689d | balrog | memset(mpu->comp_mode_ctrl, 0, sizeof(mpu->comp_mode_ctrl)); |
921 | c3d2689d | balrog | memset(mpu->pull_dwn_ctrl, 0, sizeof(mpu->pull_dwn_ctrl)); |
922 | c3d2689d | balrog | memset(mpu->gate_inh_ctrl, 0, sizeof(mpu->gate_inh_ctrl)); |
923 | c3d2689d | balrog | memset(mpu->voltage_ctrl, 0, sizeof(mpu->voltage_ctrl)); |
924 | c3d2689d | balrog | memset(mpu->test_dbg_ctrl, 0, sizeof(mpu->test_dbg_ctrl)); |
925 | c3d2689d | balrog | memset(mpu->mod_conf_ctrl, 0, sizeof(mpu->mod_conf_ctrl)); |
926 | c3d2689d | balrog | } |
927 | c3d2689d | balrog | |
928 | c227f099 | Anthony Liguori | static void omap_pin_cfg_init(target_phys_addr_t base, |
929 | c3d2689d | balrog | struct omap_mpu_state_s *mpu)
|
930 | c3d2689d | balrog | { |
931 | 1eed09cb | Avi Kivity | int iomemtype = cpu_register_io_memory(omap_pin_cfg_readfn,
|
932 | c3d2689d | balrog | omap_pin_cfg_writefn, mpu); |
933 | c3d2689d | balrog | |
934 | 8da3ff18 | pbrook | cpu_register_physical_memory(base, 0x800, iomemtype);
|
935 | c3d2689d | balrog | omap_pin_cfg_reset(mpu); |
936 | c3d2689d | balrog | } |
937 | c3d2689d | balrog | |
938 | c3d2689d | balrog | /* Device Identification, Die Identification */
|
939 | c227f099 | Anthony Liguori | static uint32_t omap_id_read(void *opaque, target_phys_addr_t addr) |
940 | c3d2689d | balrog | { |
941 | c3d2689d | balrog | struct omap_mpu_state_s *s = (struct omap_mpu_state_s *) opaque; |
942 | c3d2689d | balrog | |
943 | c3d2689d | balrog | switch (addr) {
|
944 | c3d2689d | balrog | case 0xfffe1800: /* DIE_ID_LSB */ |
945 | c3d2689d | balrog | return 0xc9581f0e; |
946 | c3d2689d | balrog | case 0xfffe1804: /* DIE_ID_MSB */ |
947 | c3d2689d | balrog | return 0xa8858bfa; |
948 | c3d2689d | balrog | |
949 | c3d2689d | balrog | case 0xfffe2000: /* PRODUCT_ID_LSB */ |
950 | c3d2689d | balrog | return 0x00aaaafc; |
951 | c3d2689d | balrog | case 0xfffe2004: /* PRODUCT_ID_MSB */ |
952 | c3d2689d | balrog | return 0xcafeb574; |
953 | c3d2689d | balrog | |
954 | c3d2689d | balrog | case 0xfffed400: /* JTAG_ID_LSB */ |
955 | c3d2689d | balrog | switch (s->mpu_model) {
|
956 | c3d2689d | balrog | case omap310:
|
957 | c3d2689d | balrog | return 0x03310315; |
958 | c3d2689d | balrog | case omap1510:
|
959 | c3d2689d | balrog | return 0x03310115; |
960 | 827df9f3 | balrog | default:
|
961 | 2ac71179 | Paul Brook | hw_error("%s: bad mpu model\n", __FUNCTION__);
|
962 | c3d2689d | balrog | } |
963 | c3d2689d | balrog | break;
|
964 | c3d2689d | balrog | |
965 | c3d2689d | balrog | case 0xfffed404: /* JTAG_ID_MSB */ |
966 | c3d2689d | balrog | switch (s->mpu_model) {
|
967 | c3d2689d | balrog | case omap310:
|
968 | c3d2689d | balrog | return 0xfb57402f; |
969 | c3d2689d | balrog | case omap1510:
|
970 | c3d2689d | balrog | return 0xfb47002f; |
971 | 827df9f3 | balrog | default:
|
972 | 2ac71179 | Paul Brook | hw_error("%s: bad mpu model\n", __FUNCTION__);
|
973 | c3d2689d | balrog | } |
974 | c3d2689d | balrog | break;
|
975 | c3d2689d | balrog | } |
976 | c3d2689d | balrog | |
977 | c3d2689d | balrog | OMAP_BAD_REG(addr); |
978 | c3d2689d | balrog | return 0; |
979 | c3d2689d | balrog | } |
980 | c3d2689d | balrog | |
981 | c227f099 | Anthony Liguori | static void omap_id_write(void *opaque, target_phys_addr_t addr, |
982 | c3d2689d | balrog | uint32_t value) |
983 | c3d2689d | balrog | { |
984 | c3d2689d | balrog | OMAP_BAD_REG(addr); |
985 | c3d2689d | balrog | } |
986 | c3d2689d | balrog | |
987 | d60efc6b | Blue Swirl | static CPUReadMemoryFunc * const omap_id_readfn[] = { |
988 | c3d2689d | balrog | omap_badwidth_read32, |
989 | c3d2689d | balrog | omap_badwidth_read32, |
990 | c3d2689d | balrog | omap_id_read, |
991 | c3d2689d | balrog | }; |
992 | c3d2689d | balrog | |
993 | d60efc6b | Blue Swirl | static CPUWriteMemoryFunc * const omap_id_writefn[] = { |
994 | c3d2689d | balrog | omap_badwidth_write32, |
995 | c3d2689d | balrog | omap_badwidth_write32, |
996 | c3d2689d | balrog | omap_id_write, |
997 | c3d2689d | balrog | }; |
998 | c3d2689d | balrog | |
999 | c3d2689d | balrog | static void omap_id_init(struct omap_mpu_state_s *mpu) |
1000 | c3d2689d | balrog | { |
1001 | 1eed09cb | Avi Kivity | int iomemtype = cpu_register_io_memory(omap_id_readfn,
|
1002 | c3d2689d | balrog | omap_id_writefn, mpu); |
1003 | 8da3ff18 | pbrook | cpu_register_physical_memory_offset(0xfffe1800, 0x800, iomemtype, 0xfffe1800); |
1004 | 8da3ff18 | pbrook | cpu_register_physical_memory_offset(0xfffed400, 0x100, iomemtype, 0xfffed400); |
1005 | c3d2689d | balrog | if (!cpu_is_omap15xx(mpu))
|
1006 | 8da3ff18 | pbrook | cpu_register_physical_memory_offset(0xfffe2000, 0x800, iomemtype, 0xfffe2000); |
1007 | c3d2689d | balrog | } |
1008 | c3d2689d | balrog | |
1009 | c3d2689d | balrog | /* MPUI Control (Dummy) */
|
1010 | c227f099 | Anthony Liguori | static uint32_t omap_mpui_read(void *opaque, target_phys_addr_t addr) |
1011 | c3d2689d | balrog | { |
1012 | c3d2689d | balrog | struct omap_mpu_state_s *s = (struct omap_mpu_state_s *) opaque; |
1013 | c3d2689d | balrog | |
1014 | 8da3ff18 | pbrook | switch (addr) {
|
1015 | c3d2689d | balrog | case 0x00: /* CTRL */ |
1016 | c3d2689d | balrog | return s->mpui_ctrl;
|
1017 | c3d2689d | balrog | case 0x04: /* DEBUG_ADDR */ |
1018 | c3d2689d | balrog | return 0x01ffffff; |
1019 | c3d2689d | balrog | case 0x08: /* DEBUG_DATA */ |
1020 | c3d2689d | balrog | return 0xffffffff; |
1021 | c3d2689d | balrog | case 0x0c: /* DEBUG_FLAG */ |
1022 | c3d2689d | balrog | return 0x00000800; |
1023 | c3d2689d | balrog | case 0x10: /* STATUS */ |
1024 | c3d2689d | balrog | return 0x00000000; |
1025 | c3d2689d | balrog | |
1026 | c3d2689d | balrog | /* Not in OMAP310 */
|
1027 | c3d2689d | balrog | case 0x14: /* DSP_STATUS */ |
1028 | c3d2689d | balrog | case 0x18: /* DSP_BOOT_CONFIG */ |
1029 | c3d2689d | balrog | return 0x00000000; |
1030 | c3d2689d | balrog | case 0x1c: /* DSP_MPUI_CONFIG */ |
1031 | c3d2689d | balrog | return 0x0000ffff; |
1032 | c3d2689d | balrog | } |
1033 | c3d2689d | balrog | |
1034 | c3d2689d | balrog | OMAP_BAD_REG(addr); |
1035 | c3d2689d | balrog | return 0; |
1036 | c3d2689d | balrog | } |
1037 | c3d2689d | balrog | |
1038 | c227f099 | Anthony Liguori | static void omap_mpui_write(void *opaque, target_phys_addr_t addr, |
1039 | c3d2689d | balrog | uint32_t value) |
1040 | c3d2689d | balrog | { |
1041 | c3d2689d | balrog | struct omap_mpu_state_s *s = (struct omap_mpu_state_s *) opaque; |
1042 | c3d2689d | balrog | |
1043 | 8da3ff18 | pbrook | switch (addr) {
|
1044 | c3d2689d | balrog | case 0x00: /* CTRL */ |
1045 | c3d2689d | balrog | s->mpui_ctrl = value & 0x007fffff;
|
1046 | c3d2689d | balrog | break;
|
1047 | c3d2689d | balrog | |
1048 | c3d2689d | balrog | case 0x04: /* DEBUG_ADDR */ |
1049 | c3d2689d | balrog | case 0x08: /* DEBUG_DATA */ |
1050 | c3d2689d | balrog | case 0x0c: /* DEBUG_FLAG */ |
1051 | c3d2689d | balrog | case 0x10: /* STATUS */ |
1052 | c3d2689d | balrog | /* Not in OMAP310 */
|
1053 | c3d2689d | balrog | case 0x14: /* DSP_STATUS */ |
1054 | c3d2689d | balrog | OMAP_RO_REG(addr); |
1055 | c3d2689d | balrog | case 0x18: /* DSP_BOOT_CONFIG */ |
1056 | c3d2689d | balrog | case 0x1c: /* DSP_MPUI_CONFIG */ |
1057 | c3d2689d | balrog | break;
|
1058 | c3d2689d | balrog | |
1059 | c3d2689d | balrog | default:
|
1060 | c3d2689d | balrog | OMAP_BAD_REG(addr); |
1061 | c3d2689d | balrog | } |
1062 | c3d2689d | balrog | } |
1063 | c3d2689d | balrog | |
1064 | d60efc6b | Blue Swirl | static CPUReadMemoryFunc * const omap_mpui_readfn[] = { |
1065 | c3d2689d | balrog | omap_badwidth_read32, |
1066 | c3d2689d | balrog | omap_badwidth_read32, |
1067 | c3d2689d | balrog | omap_mpui_read, |
1068 | c3d2689d | balrog | }; |
1069 | c3d2689d | balrog | |
1070 | d60efc6b | Blue Swirl | static CPUWriteMemoryFunc * const omap_mpui_writefn[] = { |
1071 | c3d2689d | balrog | omap_badwidth_write32, |
1072 | c3d2689d | balrog | omap_badwidth_write32, |
1073 | c3d2689d | balrog | omap_mpui_write, |
1074 | c3d2689d | balrog | }; |
1075 | c3d2689d | balrog | |
1076 | c3d2689d | balrog | static void omap_mpui_reset(struct omap_mpu_state_s *s) |
1077 | c3d2689d | balrog | { |
1078 | c3d2689d | balrog | s->mpui_ctrl = 0x0003ff1b;
|
1079 | c3d2689d | balrog | } |
1080 | c3d2689d | balrog | |
1081 | c227f099 | Anthony Liguori | static void omap_mpui_init(target_phys_addr_t base, |
1082 | c3d2689d | balrog | struct omap_mpu_state_s *mpu)
|
1083 | c3d2689d | balrog | { |
1084 | 1eed09cb | Avi Kivity | int iomemtype = cpu_register_io_memory(omap_mpui_readfn,
|
1085 | c3d2689d | balrog | omap_mpui_writefn, mpu); |
1086 | c3d2689d | balrog | |
1087 | 8da3ff18 | pbrook | cpu_register_physical_memory(base, 0x100, iomemtype);
|
1088 | c3d2689d | balrog | |
1089 | c3d2689d | balrog | omap_mpui_reset(mpu); |
1090 | c3d2689d | balrog | } |
1091 | c3d2689d | balrog | |
1092 | c3d2689d | balrog | /* TIPB Bridges */
|
1093 | c3d2689d | balrog | struct omap_tipb_bridge_s {
|
1094 | c3d2689d | balrog | qemu_irq abort; |
1095 | c3d2689d | balrog | |
1096 | c3d2689d | balrog | int width_intr;
|
1097 | c3d2689d | balrog | uint16_t control; |
1098 | c3d2689d | balrog | uint16_t alloc; |
1099 | c3d2689d | balrog | uint16_t buffer; |
1100 | c3d2689d | balrog | uint16_t enh_control; |
1101 | c3d2689d | balrog | }; |
1102 | c3d2689d | balrog | |
1103 | c227f099 | Anthony Liguori | static uint32_t omap_tipb_bridge_read(void *opaque, target_phys_addr_t addr) |
1104 | c3d2689d | balrog | { |
1105 | c3d2689d | balrog | struct omap_tipb_bridge_s *s = (struct omap_tipb_bridge_s *) opaque; |
1106 | c3d2689d | balrog | |
1107 | 8da3ff18 | pbrook | switch (addr) {
|
1108 | c3d2689d | balrog | case 0x00: /* TIPB_CNTL */ |
1109 | c3d2689d | balrog | return s->control;
|
1110 | c3d2689d | balrog | case 0x04: /* TIPB_BUS_ALLOC */ |
1111 | c3d2689d | balrog | return s->alloc;
|
1112 | c3d2689d | balrog | case 0x08: /* MPU_TIPB_CNTL */ |
1113 | c3d2689d | balrog | return s->buffer;
|
1114 | c3d2689d | balrog | case 0x0c: /* ENHANCED_TIPB_CNTL */ |
1115 | c3d2689d | balrog | return s->enh_control;
|
1116 | c3d2689d | balrog | case 0x10: /* ADDRESS_DBG */ |
1117 | c3d2689d | balrog | case 0x14: /* DATA_DEBUG_LOW */ |
1118 | c3d2689d | balrog | case 0x18: /* DATA_DEBUG_HIGH */ |
1119 | c3d2689d | balrog | return 0xffff; |
1120 | c3d2689d | balrog | case 0x1c: /* DEBUG_CNTR_SIG */ |
1121 | c3d2689d | balrog | return 0x00f8; |
1122 | c3d2689d | balrog | } |
1123 | c3d2689d | balrog | |
1124 | c3d2689d | balrog | OMAP_BAD_REG(addr); |
1125 | c3d2689d | balrog | return 0; |
1126 | c3d2689d | balrog | } |
1127 | c3d2689d | balrog | |
1128 | c227f099 | Anthony Liguori | static void omap_tipb_bridge_write(void *opaque, target_phys_addr_t addr, |
1129 | c3d2689d | balrog | uint32_t value) |
1130 | c3d2689d | balrog | { |
1131 | c3d2689d | balrog | struct omap_tipb_bridge_s *s = (struct omap_tipb_bridge_s *) opaque; |
1132 | c3d2689d | balrog | |
1133 | 8da3ff18 | pbrook | switch (addr) {
|
1134 | c3d2689d | balrog | case 0x00: /* TIPB_CNTL */ |
1135 | c3d2689d | balrog | s->control = value & 0xffff;
|
1136 | c3d2689d | balrog | break;
|
1137 | c3d2689d | balrog | |
1138 | c3d2689d | balrog | case 0x04: /* TIPB_BUS_ALLOC */ |
1139 | c3d2689d | balrog | s->alloc = value & 0x003f;
|
1140 | c3d2689d | balrog | break;
|
1141 | c3d2689d | balrog | |
1142 | c3d2689d | balrog | case 0x08: /* MPU_TIPB_CNTL */ |
1143 | c3d2689d | balrog | s->buffer = value & 0x0003;
|
1144 | c3d2689d | balrog | break;
|
1145 | c3d2689d | balrog | |
1146 | c3d2689d | balrog | case 0x0c: /* ENHANCED_TIPB_CNTL */ |
1147 | c3d2689d | balrog | s->width_intr = !(value & 2);
|
1148 | c3d2689d | balrog | s->enh_control = value & 0x000f;
|
1149 | c3d2689d | balrog | break;
|
1150 | c3d2689d | balrog | |
1151 | c3d2689d | balrog | case 0x10: /* ADDRESS_DBG */ |
1152 | c3d2689d | balrog | case 0x14: /* DATA_DEBUG_LOW */ |
1153 | c3d2689d | balrog | case 0x18: /* DATA_DEBUG_HIGH */ |
1154 | c3d2689d | balrog | case 0x1c: /* DEBUG_CNTR_SIG */ |
1155 | c3d2689d | balrog | OMAP_RO_REG(addr); |
1156 | c3d2689d | balrog | break;
|
1157 | c3d2689d | balrog | |
1158 | c3d2689d | balrog | default:
|
1159 | c3d2689d | balrog | OMAP_BAD_REG(addr); |
1160 | c3d2689d | balrog | } |
1161 | c3d2689d | balrog | } |
1162 | c3d2689d | balrog | |
1163 | d60efc6b | Blue Swirl | static CPUReadMemoryFunc * const omap_tipb_bridge_readfn[] = { |
1164 | c3d2689d | balrog | omap_badwidth_read16, |
1165 | c3d2689d | balrog | omap_tipb_bridge_read, |
1166 | c3d2689d | balrog | omap_tipb_bridge_read, |
1167 | c3d2689d | balrog | }; |
1168 | c3d2689d | balrog | |
1169 | d60efc6b | Blue Swirl | static CPUWriteMemoryFunc * const omap_tipb_bridge_writefn[] = { |
1170 | c3d2689d | balrog | omap_badwidth_write16, |
1171 | c3d2689d | balrog | omap_tipb_bridge_write, |
1172 | c3d2689d | balrog | omap_tipb_bridge_write, |
1173 | c3d2689d | balrog | }; |
1174 | c3d2689d | balrog | |
1175 | c3d2689d | balrog | static void omap_tipb_bridge_reset(struct omap_tipb_bridge_s *s) |
1176 | c3d2689d | balrog | { |
1177 | c3d2689d | balrog | s->control = 0xffff;
|
1178 | c3d2689d | balrog | s->alloc = 0x0009;
|
1179 | c3d2689d | balrog | s->buffer = 0x0000;
|
1180 | c3d2689d | balrog | s->enh_control = 0x000f;
|
1181 | c3d2689d | balrog | } |
1182 | c3d2689d | balrog | |
1183 | c1ff227b | cmchao | static struct omap_tipb_bridge_s *omap_tipb_bridge_init(target_phys_addr_t base, |
1184 | c3d2689d | balrog | qemu_irq abort_irq, omap_clk clk) |
1185 | c3d2689d | balrog | { |
1186 | c3d2689d | balrog | int iomemtype;
|
1187 | c3d2689d | balrog | struct omap_tipb_bridge_s *s = (struct omap_tipb_bridge_s *) |
1188 | c3d2689d | balrog | qemu_mallocz(sizeof(struct omap_tipb_bridge_s)); |
1189 | c3d2689d | balrog | |
1190 | c3d2689d | balrog | s->abort = abort_irq; |
1191 | c3d2689d | balrog | omap_tipb_bridge_reset(s); |
1192 | c3d2689d | balrog | |
1193 | 1eed09cb | Avi Kivity | iomemtype = cpu_register_io_memory(omap_tipb_bridge_readfn, |
1194 | c3d2689d | balrog | omap_tipb_bridge_writefn, s); |
1195 | 8da3ff18 | pbrook | cpu_register_physical_memory(base, 0x100, iomemtype);
|
1196 | c3d2689d | balrog | |
1197 | c3d2689d | balrog | return s;
|
1198 | c3d2689d | balrog | } |
1199 | c3d2689d | balrog | |
1200 | c3d2689d | balrog | /* Dummy Traffic Controller's Memory Interface */
|
1201 | c227f099 | Anthony Liguori | static uint32_t omap_tcmi_read(void *opaque, target_phys_addr_t addr) |
1202 | c3d2689d | balrog | { |
1203 | c3d2689d | balrog | struct omap_mpu_state_s *s = (struct omap_mpu_state_s *) opaque; |
1204 | c3d2689d | balrog | uint32_t ret; |
1205 | c3d2689d | balrog | |
1206 | 8da3ff18 | pbrook | switch (addr) {
|
1207 | d8f699cb | balrog | case 0x00: /* IMIF_PRIO */ |
1208 | d8f699cb | balrog | case 0x04: /* EMIFS_PRIO */ |
1209 | d8f699cb | balrog | case 0x08: /* EMIFF_PRIO */ |
1210 | d8f699cb | balrog | case 0x0c: /* EMIFS_CONFIG */ |
1211 | d8f699cb | balrog | case 0x10: /* EMIFS_CS0_CONFIG */ |
1212 | d8f699cb | balrog | case 0x14: /* EMIFS_CS1_CONFIG */ |
1213 | d8f699cb | balrog | case 0x18: /* EMIFS_CS2_CONFIG */ |
1214 | d8f699cb | balrog | case 0x1c: /* EMIFS_CS3_CONFIG */ |
1215 | d8f699cb | balrog | case 0x24: /* EMIFF_MRS */ |
1216 | d8f699cb | balrog | case 0x28: /* TIMEOUT1 */ |
1217 | d8f699cb | balrog | case 0x2c: /* TIMEOUT2 */ |
1218 | d8f699cb | balrog | case 0x30: /* TIMEOUT3 */ |
1219 | d8f699cb | balrog | case 0x3c: /* EMIFF_SDRAM_CONFIG_2 */ |
1220 | d8f699cb | balrog | case 0x40: /* EMIFS_CFG_DYN_WAIT */ |
1221 | 8da3ff18 | pbrook | return s->tcmi_regs[addr >> 2]; |
1222 | c3d2689d | balrog | |
1223 | d8f699cb | balrog | case 0x20: /* EMIFF_SDRAM_CONFIG */ |
1224 | 8da3ff18 | pbrook | ret = s->tcmi_regs[addr >> 2];
|
1225 | 8da3ff18 | pbrook | s->tcmi_regs[addr >> 2] &= ~1; /* XXX: Clear SLRF on SDRAM access */ |
1226 | c3d2689d | balrog | /* XXX: We can try using the VGA_DIRTY flag for this */
|
1227 | c3d2689d | balrog | return ret;
|
1228 | c3d2689d | balrog | } |
1229 | c3d2689d | balrog | |
1230 | c3d2689d | balrog | OMAP_BAD_REG(addr); |
1231 | c3d2689d | balrog | return 0; |
1232 | c3d2689d | balrog | } |
1233 | c3d2689d | balrog | |
1234 | c227f099 | Anthony Liguori | static void omap_tcmi_write(void *opaque, target_phys_addr_t addr, |
1235 | c3d2689d | balrog | uint32_t value) |
1236 | c3d2689d | balrog | { |
1237 | c3d2689d | balrog | struct omap_mpu_state_s *s = (struct omap_mpu_state_s *) opaque; |
1238 | c3d2689d | balrog | |
1239 | 8da3ff18 | pbrook | switch (addr) {
|
1240 | d8f699cb | balrog | case 0x00: /* IMIF_PRIO */ |
1241 | d8f699cb | balrog | case 0x04: /* EMIFS_PRIO */ |
1242 | d8f699cb | balrog | case 0x08: /* EMIFF_PRIO */ |
1243 | d8f699cb | balrog | case 0x10: /* EMIFS_CS0_CONFIG */ |
1244 | d8f699cb | balrog | case 0x14: /* EMIFS_CS1_CONFIG */ |
1245 | d8f699cb | balrog | case 0x18: /* EMIFS_CS2_CONFIG */ |
1246 | d8f699cb | balrog | case 0x1c: /* EMIFS_CS3_CONFIG */ |
1247 | d8f699cb | balrog | case 0x20: /* EMIFF_SDRAM_CONFIG */ |
1248 | d8f699cb | balrog | case 0x24: /* EMIFF_MRS */ |
1249 | d8f699cb | balrog | case 0x28: /* TIMEOUT1 */ |
1250 | d8f699cb | balrog | case 0x2c: /* TIMEOUT2 */ |
1251 | d8f699cb | balrog | case 0x30: /* TIMEOUT3 */ |
1252 | d8f699cb | balrog | case 0x3c: /* EMIFF_SDRAM_CONFIG_2 */ |
1253 | d8f699cb | balrog | case 0x40: /* EMIFS_CFG_DYN_WAIT */ |
1254 | 8da3ff18 | pbrook | s->tcmi_regs[addr >> 2] = value;
|
1255 | c3d2689d | balrog | break;
|
1256 | d8f699cb | balrog | case 0x0c: /* EMIFS_CONFIG */ |
1257 | 8da3ff18 | pbrook | s->tcmi_regs[addr >> 2] = (value & 0xf) | (1 << 4); |
1258 | c3d2689d | balrog | break;
|
1259 | c3d2689d | balrog | |
1260 | c3d2689d | balrog | default:
|
1261 | c3d2689d | balrog | OMAP_BAD_REG(addr); |
1262 | c3d2689d | balrog | } |
1263 | c3d2689d | balrog | } |
1264 | c3d2689d | balrog | |
1265 | d60efc6b | Blue Swirl | static CPUReadMemoryFunc * const omap_tcmi_readfn[] = { |
1266 | c3d2689d | balrog | omap_badwidth_read32, |
1267 | c3d2689d | balrog | omap_badwidth_read32, |
1268 | c3d2689d | balrog | omap_tcmi_read, |
1269 | c3d2689d | balrog | }; |
1270 | c3d2689d | balrog | |
1271 | d60efc6b | Blue Swirl | static CPUWriteMemoryFunc * const omap_tcmi_writefn[] = { |
1272 | c3d2689d | balrog | omap_badwidth_write32, |
1273 | c3d2689d | balrog | omap_badwidth_write32, |
1274 | c3d2689d | balrog | omap_tcmi_write, |
1275 | c3d2689d | balrog | }; |
1276 | c3d2689d | balrog | |
1277 | c3d2689d | balrog | static void omap_tcmi_reset(struct omap_mpu_state_s *mpu) |
1278 | c3d2689d | balrog | { |
1279 | c3d2689d | balrog | mpu->tcmi_regs[0x00 >> 2] = 0x00000000; |
1280 | c3d2689d | balrog | mpu->tcmi_regs[0x04 >> 2] = 0x00000000; |
1281 | c3d2689d | balrog | mpu->tcmi_regs[0x08 >> 2] = 0x00000000; |
1282 | c3d2689d | balrog | mpu->tcmi_regs[0x0c >> 2] = 0x00000010; |
1283 | c3d2689d | balrog | mpu->tcmi_regs[0x10 >> 2] = 0x0010fffb; |
1284 | c3d2689d | balrog | mpu->tcmi_regs[0x14 >> 2] = 0x0010fffb; |
1285 | c3d2689d | balrog | mpu->tcmi_regs[0x18 >> 2] = 0x0010fffb; |
1286 | c3d2689d | balrog | mpu->tcmi_regs[0x1c >> 2] = 0x0010fffb; |
1287 | c3d2689d | balrog | mpu->tcmi_regs[0x20 >> 2] = 0x00618800; |
1288 | c3d2689d | balrog | mpu->tcmi_regs[0x24 >> 2] = 0x00000037; |
1289 | c3d2689d | balrog | mpu->tcmi_regs[0x28 >> 2] = 0x00000000; |
1290 | c3d2689d | balrog | mpu->tcmi_regs[0x2c >> 2] = 0x00000000; |
1291 | c3d2689d | balrog | mpu->tcmi_regs[0x30 >> 2] = 0x00000000; |
1292 | c3d2689d | balrog | mpu->tcmi_regs[0x3c >> 2] = 0x00000003; |
1293 | c3d2689d | balrog | mpu->tcmi_regs[0x40 >> 2] = 0x00000000; |
1294 | c3d2689d | balrog | } |
1295 | c3d2689d | balrog | |
1296 | c227f099 | Anthony Liguori | static void omap_tcmi_init(target_phys_addr_t base, |
1297 | c3d2689d | balrog | struct omap_mpu_state_s *mpu)
|
1298 | c3d2689d | balrog | { |
1299 | 1eed09cb | Avi Kivity | int iomemtype = cpu_register_io_memory(omap_tcmi_readfn,
|
1300 | c3d2689d | balrog | omap_tcmi_writefn, mpu); |
1301 | c3d2689d | balrog | |
1302 | 8da3ff18 | pbrook | cpu_register_physical_memory(base, 0x100, iomemtype);
|
1303 | c3d2689d | balrog | omap_tcmi_reset(mpu); |
1304 | c3d2689d | balrog | } |
1305 | c3d2689d | balrog | |
1306 | c3d2689d | balrog | /* Digital phase-locked loops control */
|
1307 | c227f099 | Anthony Liguori | static uint32_t omap_dpll_read(void *opaque, target_phys_addr_t addr) |
1308 | c3d2689d | balrog | { |
1309 | c3d2689d | balrog | struct dpll_ctl_s *s = (struct dpll_ctl_s *) opaque; |
1310 | c3d2689d | balrog | |
1311 | 8da3ff18 | pbrook | if (addr == 0x00) /* CTL_REG */ |
1312 | c3d2689d | balrog | return s->mode;
|
1313 | c3d2689d | balrog | |
1314 | c3d2689d | balrog | OMAP_BAD_REG(addr); |
1315 | c3d2689d | balrog | return 0; |
1316 | c3d2689d | balrog | } |
1317 | c3d2689d | balrog | |
1318 | c227f099 | Anthony Liguori | static void omap_dpll_write(void *opaque, target_phys_addr_t addr, |
1319 | c3d2689d | balrog | uint32_t value) |
1320 | c3d2689d | balrog | { |
1321 | c3d2689d | balrog | struct dpll_ctl_s *s = (struct dpll_ctl_s *) opaque; |
1322 | c3d2689d | balrog | uint16_t diff; |
1323 | c3d2689d | balrog | static const int bypass_div[4] = { 1, 2, 4, 4 }; |
1324 | c3d2689d | balrog | int div, mult;
|
1325 | c3d2689d | balrog | |
1326 | 8da3ff18 | pbrook | if (addr == 0x00) { /* CTL_REG */ |
1327 | c3d2689d | balrog | /* See omap_ulpd_pm_write() too */
|
1328 | c3d2689d | balrog | diff = s->mode & value; |
1329 | c3d2689d | balrog | s->mode = value & 0x2fff;
|
1330 | c3d2689d | balrog | if (diff & (0x3ff << 2)) { |
1331 | c3d2689d | balrog | if (value & (1 << 4)) { /* PLL_ENABLE */ |
1332 | c3d2689d | balrog | div = ((value >> 5) & 3) + 1; /* PLL_DIV */ |
1333 | c3d2689d | balrog | mult = MIN((value >> 7) & 0x1f, 1); /* PLL_MULT */ |
1334 | c3d2689d | balrog | } else {
|
1335 | c3d2689d | balrog | div = bypass_div[((value >> 2) & 3)]; /* BYPASS_DIV */ |
1336 | c3d2689d | balrog | mult = 1;
|
1337 | c3d2689d | balrog | } |
1338 | c3d2689d | balrog | omap_clk_setrate(s->dpll, div, mult); |
1339 | c3d2689d | balrog | } |
1340 | c3d2689d | balrog | |
1341 | c3d2689d | balrog | /* Enter the desired mode. */
|
1342 | c3d2689d | balrog | s->mode = (s->mode & 0xfffe) | ((s->mode >> 4) & 1); |
1343 | c3d2689d | balrog | |
1344 | c3d2689d | balrog | /* Act as if the lock is restored. */
|
1345 | c3d2689d | balrog | s->mode |= 2;
|
1346 | c3d2689d | balrog | } else {
|
1347 | c3d2689d | balrog | OMAP_BAD_REG(addr); |
1348 | c3d2689d | balrog | } |
1349 | c3d2689d | balrog | } |
1350 | c3d2689d | balrog | |
1351 | d60efc6b | Blue Swirl | static CPUReadMemoryFunc * const omap_dpll_readfn[] = { |
1352 | c3d2689d | balrog | omap_badwidth_read16, |
1353 | c3d2689d | balrog | omap_dpll_read, |
1354 | c3d2689d | balrog | omap_badwidth_read16, |
1355 | c3d2689d | balrog | }; |
1356 | c3d2689d | balrog | |
1357 | d60efc6b | Blue Swirl | static CPUWriteMemoryFunc * const omap_dpll_writefn[] = { |
1358 | c3d2689d | balrog | omap_badwidth_write16, |
1359 | c3d2689d | balrog | omap_dpll_write, |
1360 | c3d2689d | balrog | omap_badwidth_write16, |
1361 | c3d2689d | balrog | }; |
1362 | c3d2689d | balrog | |
1363 | c3d2689d | balrog | static void omap_dpll_reset(struct dpll_ctl_s *s) |
1364 | c3d2689d | balrog | { |
1365 | c3d2689d | balrog | s->mode = 0x2002;
|
1366 | c3d2689d | balrog | omap_clk_setrate(s->dpll, 1, 1); |
1367 | c3d2689d | balrog | } |
1368 | c3d2689d | balrog | |
1369 | c227f099 | Anthony Liguori | static void omap_dpll_init(struct dpll_ctl_s *s, target_phys_addr_t base, |
1370 | c3d2689d | balrog | omap_clk clk) |
1371 | c3d2689d | balrog | { |
1372 | 1eed09cb | Avi Kivity | int iomemtype = cpu_register_io_memory(omap_dpll_readfn,
|
1373 | c3d2689d | balrog | omap_dpll_writefn, s); |
1374 | c3d2689d | balrog | |
1375 | c3d2689d | balrog | s->dpll = clk; |
1376 | c3d2689d | balrog | omap_dpll_reset(s); |
1377 | c3d2689d | balrog | |
1378 | 8da3ff18 | pbrook | cpu_register_physical_memory(base, 0x100, iomemtype);
|
1379 | c3d2689d | balrog | } |
1380 | c3d2689d | balrog | |
1381 | c3d2689d | balrog | /* MPU Clock/Reset/Power Mode Control */
|
1382 | c227f099 | Anthony Liguori | static uint32_t omap_clkm_read(void *opaque, target_phys_addr_t addr) |
1383 | c3d2689d | balrog | { |
1384 | c3d2689d | balrog | struct omap_mpu_state_s *s = (struct omap_mpu_state_s *) opaque; |
1385 | c3d2689d | balrog | |
1386 | 8da3ff18 | pbrook | switch (addr) {
|
1387 | c3d2689d | balrog | case 0x00: /* ARM_CKCTL */ |
1388 | c3d2689d | balrog | return s->clkm.arm_ckctl;
|
1389 | c3d2689d | balrog | |
1390 | c3d2689d | balrog | case 0x04: /* ARM_IDLECT1 */ |
1391 | c3d2689d | balrog | return s->clkm.arm_idlect1;
|
1392 | c3d2689d | balrog | |
1393 | c3d2689d | balrog | case 0x08: /* ARM_IDLECT2 */ |
1394 | c3d2689d | balrog | return s->clkm.arm_idlect2;
|
1395 | c3d2689d | balrog | |
1396 | c3d2689d | balrog | case 0x0c: /* ARM_EWUPCT */ |
1397 | c3d2689d | balrog | return s->clkm.arm_ewupct;
|
1398 | c3d2689d | balrog | |
1399 | c3d2689d | balrog | case 0x10: /* ARM_RSTCT1 */ |
1400 | c3d2689d | balrog | return s->clkm.arm_rstct1;
|
1401 | c3d2689d | balrog | |
1402 | c3d2689d | balrog | case 0x14: /* ARM_RSTCT2 */ |
1403 | c3d2689d | balrog | return s->clkm.arm_rstct2;
|
1404 | c3d2689d | balrog | |
1405 | c3d2689d | balrog | case 0x18: /* ARM_SYSST */ |
1406 | d8f699cb | balrog | return (s->clkm.clocking_scheme << 11) | s->clkm.cold_start; |
1407 | c3d2689d | balrog | |
1408 | c3d2689d | balrog | case 0x1c: /* ARM_CKOUT1 */ |
1409 | c3d2689d | balrog | return s->clkm.arm_ckout1;
|
1410 | c3d2689d | balrog | |
1411 | c3d2689d | balrog | case 0x20: /* ARM_CKOUT2 */ |
1412 | c3d2689d | balrog | break;
|
1413 | c3d2689d | balrog | } |
1414 | c3d2689d | balrog | |
1415 | c3d2689d | balrog | OMAP_BAD_REG(addr); |
1416 | c3d2689d | balrog | return 0; |
1417 | c3d2689d | balrog | } |
1418 | c3d2689d | balrog | |
1419 | c3d2689d | balrog | static inline void omap_clkm_ckctl_update(struct omap_mpu_state_s *s, |
1420 | c3d2689d | balrog | uint16_t diff, uint16_t value) |
1421 | c3d2689d | balrog | { |
1422 | c3d2689d | balrog | omap_clk clk; |
1423 | c3d2689d | balrog | |
1424 | c3d2689d | balrog | if (diff & (1 << 14)) { /* ARM_INTHCK_SEL */ |
1425 | c3d2689d | balrog | if (value & (1 << 14)) |
1426 | c3d2689d | balrog | /* Reserved */;
|
1427 | c3d2689d | balrog | else {
|
1428 | c3d2689d | balrog | clk = omap_findclk(s, "arminth_ck");
|
1429 | c3d2689d | balrog | omap_clk_reparent(clk, omap_findclk(s, "tc_ck"));
|
1430 | c3d2689d | balrog | } |
1431 | c3d2689d | balrog | } |
1432 | c3d2689d | balrog | if (diff & (1 << 12)) { /* ARM_TIMXO */ |
1433 | c3d2689d | balrog | clk = omap_findclk(s, "armtim_ck");
|
1434 | c3d2689d | balrog | if (value & (1 << 12)) |
1435 | c3d2689d | balrog | omap_clk_reparent(clk, omap_findclk(s, "clkin"));
|
1436 | c3d2689d | balrog | else
|
1437 | c3d2689d | balrog | omap_clk_reparent(clk, omap_findclk(s, "ck_gen1"));
|
1438 | c3d2689d | balrog | } |
1439 | c3d2689d | balrog | /* XXX: en_dspck */
|
1440 | c3d2689d | balrog | if (diff & (3 << 10)) { /* DSPMMUDIV */ |
1441 | c3d2689d | balrog | clk = omap_findclk(s, "dspmmu_ck");
|
1442 | c3d2689d | balrog | omap_clk_setrate(clk, 1 << ((value >> 10) & 3), 1); |
1443 | c3d2689d | balrog | } |
1444 | c3d2689d | balrog | if (diff & (3 << 8)) { /* TCDIV */ |
1445 | c3d2689d | balrog | clk = omap_findclk(s, "tc_ck");
|
1446 | c3d2689d | balrog | omap_clk_setrate(clk, 1 << ((value >> 8) & 3), 1); |
1447 | c3d2689d | balrog | } |
1448 | c3d2689d | balrog | if (diff & (3 << 6)) { /* DSPDIV */ |
1449 | c3d2689d | balrog | clk = omap_findclk(s, "dsp_ck");
|
1450 | c3d2689d | balrog | omap_clk_setrate(clk, 1 << ((value >> 6) & 3), 1); |
1451 | c3d2689d | balrog | } |
1452 | c3d2689d | balrog | if (diff & (3 << 4)) { /* ARMDIV */ |
1453 | c3d2689d | balrog | clk = omap_findclk(s, "arm_ck");
|
1454 | c3d2689d | balrog | omap_clk_setrate(clk, 1 << ((value >> 4) & 3), 1); |
1455 | c3d2689d | balrog | } |
1456 | c3d2689d | balrog | if (diff & (3 << 2)) { /* LCDDIV */ |
1457 | c3d2689d | balrog | clk = omap_findclk(s, "lcd_ck");
|
1458 | c3d2689d | balrog | omap_clk_setrate(clk, 1 << ((value >> 2) & 3), 1); |
1459 | c3d2689d | balrog | } |
1460 | c3d2689d | balrog | if (diff & (3 << 0)) { /* PERDIV */ |
1461 | c3d2689d | balrog | clk = omap_findclk(s, "armper_ck");
|
1462 | c3d2689d | balrog | omap_clk_setrate(clk, 1 << ((value >> 0) & 3), 1); |
1463 | c3d2689d | balrog | } |
1464 | c3d2689d | balrog | } |
1465 | c3d2689d | balrog | |
1466 | c3d2689d | balrog | static inline void omap_clkm_idlect1_update(struct omap_mpu_state_s *s, |
1467 | c3d2689d | balrog | uint16_t diff, uint16_t value) |
1468 | c3d2689d | balrog | { |
1469 | c3d2689d | balrog | omap_clk clk; |
1470 | c3d2689d | balrog | |
1471 | c3d2689d | balrog | if (value & (1 << 11)) /* SETARM_IDLE */ |
1472 | c3d2689d | balrog | cpu_interrupt(s->env, CPU_INTERRUPT_HALT); |
1473 | c3d2689d | balrog | if (!(value & (1 << 10))) /* WKUP_MODE */ |
1474 | c3d2689d | balrog | qemu_system_shutdown_request(); /* XXX: disable wakeup from IRQ */
|
1475 | c3d2689d | balrog | |
1476 | c3d2689d | balrog | #define SET_CANIDLE(clock, bit) \
|
1477 | c3d2689d | balrog | if (diff & (1 << bit)) { \ |
1478 | c3d2689d | balrog | clk = omap_findclk(s, clock); \ |
1479 | c3d2689d | balrog | omap_clk_canidle(clk, (value >> bit) & 1); \
|
1480 | c3d2689d | balrog | } |
1481 | c3d2689d | balrog | SET_CANIDLE("mpuwd_ck", 0) /* IDLWDT_ARM */ |
1482 | c3d2689d | balrog | SET_CANIDLE("armxor_ck", 1) /* IDLXORP_ARM */ |
1483 | c3d2689d | balrog | SET_CANIDLE("mpuper_ck", 2) /* IDLPER_ARM */ |
1484 | c3d2689d | balrog | SET_CANIDLE("lcd_ck", 3) /* IDLLCD_ARM */ |
1485 | c3d2689d | balrog | SET_CANIDLE("lb_ck", 4) /* IDLLB_ARM */ |
1486 | c3d2689d | balrog | SET_CANIDLE("hsab_ck", 5) /* IDLHSAB_ARM */ |
1487 | c3d2689d | balrog | SET_CANIDLE("tipb_ck", 6) /* IDLIF_ARM */ |
1488 | c3d2689d | balrog | SET_CANIDLE("dma_ck", 6) /* IDLIF_ARM */ |
1489 | c3d2689d | balrog | SET_CANIDLE("tc_ck", 6) /* IDLIF_ARM */ |
1490 | c3d2689d | balrog | SET_CANIDLE("dpll1", 7) /* IDLDPLL_ARM */ |
1491 | c3d2689d | balrog | SET_CANIDLE("dpll2", 7) /* IDLDPLL_ARM */ |
1492 | c3d2689d | balrog | SET_CANIDLE("dpll3", 7) /* IDLDPLL_ARM */ |
1493 | c3d2689d | balrog | SET_CANIDLE("mpui_ck", 8) /* IDLAPI_ARM */ |
1494 | c3d2689d | balrog | SET_CANIDLE("armtim_ck", 9) /* IDLTIM_ARM */ |
1495 | c3d2689d | balrog | } |
1496 | c3d2689d | balrog | |
1497 | c3d2689d | balrog | static inline void omap_clkm_idlect2_update(struct omap_mpu_state_s *s, |
1498 | c3d2689d | balrog | uint16_t diff, uint16_t value) |
1499 | c3d2689d | balrog | { |
1500 | c3d2689d | balrog | omap_clk clk; |
1501 | c3d2689d | balrog | |
1502 | c3d2689d | balrog | #define SET_ONOFF(clock, bit) \
|
1503 | c3d2689d | balrog | if (diff & (1 << bit)) { \ |
1504 | c3d2689d | balrog | clk = omap_findclk(s, clock); \ |
1505 | c3d2689d | balrog | omap_clk_onoff(clk, (value >> bit) & 1); \
|
1506 | c3d2689d | balrog | } |
1507 | c3d2689d | balrog | SET_ONOFF("mpuwd_ck", 0) /* EN_WDTCK */ |
1508 | c3d2689d | balrog | SET_ONOFF("armxor_ck", 1) /* EN_XORPCK */ |
1509 | c3d2689d | balrog | SET_ONOFF("mpuper_ck", 2) /* EN_PERCK */ |
1510 | c3d2689d | balrog | SET_ONOFF("lcd_ck", 3) /* EN_LCDCK */ |
1511 | c3d2689d | balrog | SET_ONOFF("lb_ck", 4) /* EN_LBCK */ |
1512 | c3d2689d | balrog | SET_ONOFF("hsab_ck", 5) /* EN_HSABCK */ |
1513 | c3d2689d | balrog | SET_ONOFF("mpui_ck", 6) /* EN_APICK */ |
1514 | c3d2689d | balrog | SET_ONOFF("armtim_ck", 7) /* EN_TIMCK */ |
1515 | c3d2689d | balrog | SET_CANIDLE("dma_ck", 8) /* DMACK_REQ */ |
1516 | c3d2689d | balrog | SET_ONOFF("arm_gpio_ck", 9) /* EN_GPIOCK */ |
1517 | c3d2689d | balrog | SET_ONOFF("lbfree_ck", 10) /* EN_LBFREECK */ |
1518 | c3d2689d | balrog | } |
1519 | c3d2689d | balrog | |
1520 | c3d2689d | balrog | static inline void omap_clkm_ckout1_update(struct omap_mpu_state_s *s, |
1521 | c3d2689d | balrog | uint16_t diff, uint16_t value) |
1522 | c3d2689d | balrog | { |
1523 | c3d2689d | balrog | omap_clk clk; |
1524 | c3d2689d | balrog | |
1525 | c3d2689d | balrog | if (diff & (3 << 4)) { /* TCLKOUT */ |
1526 | c3d2689d | balrog | clk = omap_findclk(s, "tclk_out");
|
1527 | c3d2689d | balrog | switch ((value >> 4) & 3) { |
1528 | c3d2689d | balrog | case 1: |
1529 | c3d2689d | balrog | omap_clk_reparent(clk, omap_findclk(s, "ck_gen3"));
|
1530 | c3d2689d | balrog | omap_clk_onoff(clk, 1);
|
1531 | c3d2689d | balrog | break;
|
1532 | c3d2689d | balrog | case 2: |
1533 | c3d2689d | balrog | omap_clk_reparent(clk, omap_findclk(s, "tc_ck"));
|
1534 | c3d2689d | balrog | omap_clk_onoff(clk, 1);
|
1535 | c3d2689d | balrog | break;
|
1536 | c3d2689d | balrog | default:
|
1537 | c3d2689d | balrog | omap_clk_onoff(clk, 0);
|
1538 | c3d2689d | balrog | } |
1539 | c3d2689d | balrog | } |
1540 | c3d2689d | balrog | if (diff & (3 << 2)) { /* DCLKOUT */ |
1541 | c3d2689d | balrog | clk = omap_findclk(s, "dclk_out");
|
1542 | c3d2689d | balrog | switch ((value >> 2) & 3) { |
1543 | c3d2689d | balrog | case 0: |
1544 | c3d2689d | balrog | omap_clk_reparent(clk, omap_findclk(s, "dspmmu_ck"));
|
1545 | c3d2689d | balrog | break;
|
1546 | c3d2689d | balrog | case 1: |
1547 | c3d2689d | balrog | omap_clk_reparent(clk, omap_findclk(s, "ck_gen2"));
|
1548 | c3d2689d | balrog | break;
|
1549 | c3d2689d | balrog | case 2: |
1550 | c3d2689d | balrog | omap_clk_reparent(clk, omap_findclk(s, "dsp_ck"));
|
1551 | c3d2689d | balrog | break;
|
1552 | c3d2689d | balrog | case 3: |
1553 | c3d2689d | balrog | omap_clk_reparent(clk, omap_findclk(s, "ck_ref14"));
|
1554 | c3d2689d | balrog | break;
|
1555 | c3d2689d | balrog | } |
1556 | c3d2689d | balrog | } |
1557 | c3d2689d | balrog | if (diff & (3 << 0)) { /* ACLKOUT */ |
1558 | c3d2689d | balrog | clk = omap_findclk(s, "aclk_out");
|
1559 | c3d2689d | balrog | switch ((value >> 0) & 3) { |
1560 | c3d2689d | balrog | case 1: |
1561 | c3d2689d | balrog | omap_clk_reparent(clk, omap_findclk(s, "ck_gen1"));
|
1562 | c3d2689d | balrog | omap_clk_onoff(clk, 1);
|
1563 | c3d2689d | balrog | break;
|
1564 | c3d2689d | balrog | case 2: |
1565 | c3d2689d | balrog | omap_clk_reparent(clk, omap_findclk(s, "arm_ck"));
|
1566 | c3d2689d | balrog | omap_clk_onoff(clk, 1);
|
1567 | c3d2689d | balrog | break;
|
1568 | c3d2689d | balrog | case 3: |
1569 | c3d2689d | balrog | omap_clk_reparent(clk, omap_findclk(s, "ck_ref14"));
|
1570 | c3d2689d | balrog | omap_clk_onoff(clk, 1);
|
1571 | c3d2689d | balrog | break;
|
1572 | c3d2689d | balrog | default:
|
1573 | c3d2689d | balrog | omap_clk_onoff(clk, 0);
|
1574 | c3d2689d | balrog | } |
1575 | c3d2689d | balrog | } |
1576 | c3d2689d | balrog | } |
1577 | c3d2689d | balrog | |
1578 | c227f099 | Anthony Liguori | static void omap_clkm_write(void *opaque, target_phys_addr_t addr, |
1579 | c3d2689d | balrog | uint32_t value) |
1580 | c3d2689d | balrog | { |
1581 | c3d2689d | balrog | struct omap_mpu_state_s *s = (struct omap_mpu_state_s *) opaque; |
1582 | c3d2689d | balrog | uint16_t diff; |
1583 | c3d2689d | balrog | omap_clk clk; |
1584 | c3d2689d | balrog | static const char *clkschemename[8] = { |
1585 | c3d2689d | balrog | "fully synchronous", "fully asynchronous", "synchronous scalable", |
1586 | c3d2689d | balrog | "mix mode 1", "mix mode 2", "bypass mode", "mix mode 3", "mix mode 4", |
1587 | c3d2689d | balrog | }; |
1588 | c3d2689d | balrog | |
1589 | 8da3ff18 | pbrook | switch (addr) {
|
1590 | c3d2689d | balrog | case 0x00: /* ARM_CKCTL */ |
1591 | c3d2689d | balrog | diff = s->clkm.arm_ckctl ^ value; |
1592 | c3d2689d | balrog | s->clkm.arm_ckctl = value & 0x7fff;
|
1593 | c3d2689d | balrog | omap_clkm_ckctl_update(s, diff, value); |
1594 | c3d2689d | balrog | return;
|
1595 | c3d2689d | balrog | |
1596 | c3d2689d | balrog | case 0x04: /* ARM_IDLECT1 */ |
1597 | c3d2689d | balrog | diff = s->clkm.arm_idlect1 ^ value; |
1598 | c3d2689d | balrog | s->clkm.arm_idlect1 = value & 0x0fff;
|
1599 | c3d2689d | balrog | omap_clkm_idlect1_update(s, diff, value); |
1600 | c3d2689d | balrog | return;
|
1601 | c3d2689d | balrog | |
1602 | c3d2689d | balrog | case 0x08: /* ARM_IDLECT2 */ |
1603 | c3d2689d | balrog | diff = s->clkm.arm_idlect2 ^ value; |
1604 | c3d2689d | balrog | s->clkm.arm_idlect2 = value & 0x07ff;
|
1605 | c3d2689d | balrog | omap_clkm_idlect2_update(s, diff, value); |
1606 | c3d2689d | balrog | return;
|
1607 | c3d2689d | balrog | |
1608 | c3d2689d | balrog | case 0x0c: /* ARM_EWUPCT */ |
1609 | c3d2689d | balrog | s->clkm.arm_ewupct = value & 0x003f;
|
1610 | c3d2689d | balrog | return;
|
1611 | c3d2689d | balrog | |
1612 | c3d2689d | balrog | case 0x10: /* ARM_RSTCT1 */ |
1613 | c3d2689d | balrog | diff = s->clkm.arm_rstct1 ^ value; |
1614 | c3d2689d | balrog | s->clkm.arm_rstct1 = value & 0x0007;
|
1615 | c3d2689d | balrog | if (value & 9) { |
1616 | c3d2689d | balrog | qemu_system_reset_request(); |
1617 | c3d2689d | balrog | s->clkm.cold_start = 0xa;
|
1618 | c3d2689d | balrog | } |
1619 | c3d2689d | balrog | if (diff & ~value & 4) { /* DSP_RST */ |
1620 | c3d2689d | balrog | omap_mpui_reset(s); |
1621 | c3d2689d | balrog | omap_tipb_bridge_reset(s->private_tipb); |
1622 | c3d2689d | balrog | omap_tipb_bridge_reset(s->public_tipb); |
1623 | c3d2689d | balrog | } |
1624 | c3d2689d | balrog | if (diff & 2) { /* DSP_EN */ |
1625 | c3d2689d | balrog | clk = omap_findclk(s, "dsp_ck");
|
1626 | c3d2689d | balrog | omap_clk_canidle(clk, (~value >> 1) & 1); |
1627 | c3d2689d | balrog | } |
1628 | c3d2689d | balrog | return;
|
1629 | c3d2689d | balrog | |
1630 | c3d2689d | balrog | case 0x14: /* ARM_RSTCT2 */ |
1631 | c3d2689d | balrog | s->clkm.arm_rstct2 = value & 0x0001;
|
1632 | c3d2689d | balrog | return;
|
1633 | c3d2689d | balrog | |
1634 | c3d2689d | balrog | case 0x18: /* ARM_SYSST */ |
1635 | c3d2689d | balrog | if ((s->clkm.clocking_scheme ^ (value >> 11)) & 7) { |
1636 | c3d2689d | balrog | s->clkm.clocking_scheme = (value >> 11) & 7; |
1637 | c3d2689d | balrog | printf("%s: clocking scheme set to %s\n", __FUNCTION__,
|
1638 | c3d2689d | balrog | clkschemename[s->clkm.clocking_scheme]); |
1639 | c3d2689d | balrog | } |
1640 | c3d2689d | balrog | s->clkm.cold_start &= value & 0x3f;
|
1641 | c3d2689d | balrog | return;
|
1642 | c3d2689d | balrog | |
1643 | c3d2689d | balrog | case 0x1c: /* ARM_CKOUT1 */ |
1644 | c3d2689d | balrog | diff = s->clkm.arm_ckout1 ^ value; |
1645 | c3d2689d | balrog | s->clkm.arm_ckout1 = value & 0x003f;
|
1646 | c3d2689d | balrog | omap_clkm_ckout1_update(s, diff, value); |
1647 | c3d2689d | balrog | return;
|
1648 | c3d2689d | balrog | |
1649 | c3d2689d | balrog | case 0x20: /* ARM_CKOUT2 */ |
1650 | c3d2689d | balrog | default:
|
1651 | c3d2689d | balrog | OMAP_BAD_REG(addr); |
1652 | c3d2689d | balrog | } |
1653 | c3d2689d | balrog | } |
1654 | c3d2689d | balrog | |
1655 | d60efc6b | Blue Swirl | static CPUReadMemoryFunc * const omap_clkm_readfn[] = { |
1656 | c3d2689d | balrog | omap_badwidth_read16, |
1657 | c3d2689d | balrog | omap_clkm_read, |
1658 | c3d2689d | balrog | omap_badwidth_read16, |
1659 | c3d2689d | balrog | }; |
1660 | c3d2689d | balrog | |
1661 | d60efc6b | Blue Swirl | static CPUWriteMemoryFunc * const omap_clkm_writefn[] = { |
1662 | c3d2689d | balrog | omap_badwidth_write16, |
1663 | c3d2689d | balrog | omap_clkm_write, |
1664 | c3d2689d | balrog | omap_badwidth_write16, |
1665 | c3d2689d | balrog | }; |
1666 | c3d2689d | balrog | |
1667 | c227f099 | Anthony Liguori | static uint32_t omap_clkdsp_read(void *opaque, target_phys_addr_t addr) |
1668 | c3d2689d | balrog | { |
1669 | c3d2689d | balrog | struct omap_mpu_state_s *s = (struct omap_mpu_state_s *) opaque; |
1670 | c3d2689d | balrog | |
1671 | 8da3ff18 | pbrook | switch (addr) {
|
1672 | c3d2689d | balrog | case 0x04: /* DSP_IDLECT1 */ |
1673 | c3d2689d | balrog | return s->clkm.dsp_idlect1;
|
1674 | c3d2689d | balrog | |
1675 | c3d2689d | balrog | case 0x08: /* DSP_IDLECT2 */ |
1676 | c3d2689d | balrog | return s->clkm.dsp_idlect2;
|
1677 | c3d2689d | balrog | |
1678 | c3d2689d | balrog | case 0x14: /* DSP_RSTCT2 */ |
1679 | c3d2689d | balrog | return s->clkm.dsp_rstct2;
|
1680 | c3d2689d | balrog | |
1681 | c3d2689d | balrog | case 0x18: /* DSP_SYSST */ |
1682 | d8f699cb | balrog | return (s->clkm.clocking_scheme << 11) | s->clkm.cold_start | |
1683 | c3d2689d | balrog | (s->env->halted << 6); /* Quite useless... */ |
1684 | c3d2689d | balrog | } |
1685 | c3d2689d | balrog | |
1686 | c3d2689d | balrog | OMAP_BAD_REG(addr); |
1687 | c3d2689d | balrog | return 0; |
1688 | c3d2689d | balrog | } |
1689 | c3d2689d | balrog | |
1690 | c3d2689d | balrog | static inline void omap_clkdsp_idlect1_update(struct omap_mpu_state_s *s, |
1691 | c3d2689d | balrog | uint16_t diff, uint16_t value) |
1692 | c3d2689d | balrog | { |
1693 | c3d2689d | balrog | omap_clk clk; |
1694 | c3d2689d | balrog | |
1695 | c3d2689d | balrog | SET_CANIDLE("dspxor_ck", 1); /* IDLXORP_DSP */ |
1696 | c3d2689d | balrog | } |
1697 | c3d2689d | balrog | |
1698 | c3d2689d | balrog | static inline void omap_clkdsp_idlect2_update(struct omap_mpu_state_s *s, |
1699 | c3d2689d | balrog | uint16_t diff, uint16_t value) |
1700 | c3d2689d | balrog | { |
1701 | c3d2689d | balrog | omap_clk clk; |
1702 | c3d2689d | balrog | |
1703 | c3d2689d | balrog | SET_ONOFF("dspxor_ck", 1); /* EN_XORPCK */ |
1704 | c3d2689d | balrog | } |
1705 | c3d2689d | balrog | |
1706 | c227f099 | Anthony Liguori | static void omap_clkdsp_write(void *opaque, target_phys_addr_t addr, |
1707 | c3d2689d | balrog | uint32_t value) |
1708 | c3d2689d | balrog | { |
1709 | c3d2689d | balrog | struct omap_mpu_state_s *s = (struct omap_mpu_state_s *) opaque; |
1710 | c3d2689d | balrog | uint16_t diff; |
1711 | c3d2689d | balrog | |
1712 | 8da3ff18 | pbrook | switch (addr) {
|
1713 | c3d2689d | balrog | case 0x04: /* DSP_IDLECT1 */ |
1714 | c3d2689d | balrog | diff = s->clkm.dsp_idlect1 ^ value; |
1715 | c3d2689d | balrog | s->clkm.dsp_idlect1 = value & 0x01f7;
|
1716 | c3d2689d | balrog | omap_clkdsp_idlect1_update(s, diff, value); |
1717 | c3d2689d | balrog | break;
|
1718 | c3d2689d | balrog | |
1719 | c3d2689d | balrog | case 0x08: /* DSP_IDLECT2 */ |
1720 | c3d2689d | balrog | s->clkm.dsp_idlect2 = value & 0x0037;
|
1721 | c3d2689d | balrog | diff = s->clkm.dsp_idlect1 ^ value; |
1722 | c3d2689d | balrog | omap_clkdsp_idlect2_update(s, diff, value); |
1723 | c3d2689d | balrog | break;
|
1724 | c3d2689d | balrog | |
1725 | c3d2689d | balrog | case 0x14: /* DSP_RSTCT2 */ |
1726 | c3d2689d | balrog | s->clkm.dsp_rstct2 = value & 0x0001;
|
1727 | c3d2689d | balrog | break;
|
1728 | c3d2689d | balrog | |
1729 | c3d2689d | balrog | case 0x18: /* DSP_SYSST */ |
1730 | c3d2689d | balrog | s->clkm.cold_start &= value & 0x3f;
|
1731 | c3d2689d | balrog | break;
|
1732 | c3d2689d | balrog | |
1733 | c3d2689d | balrog | default:
|
1734 | c3d2689d | balrog | OMAP_BAD_REG(addr); |
1735 | c3d2689d | balrog | } |
1736 | c3d2689d | balrog | } |
1737 | c3d2689d | balrog | |
1738 | d60efc6b | Blue Swirl | static CPUReadMemoryFunc * const omap_clkdsp_readfn[] = { |
1739 | c3d2689d | balrog | omap_badwidth_read16, |
1740 | c3d2689d | balrog | omap_clkdsp_read, |
1741 | c3d2689d | balrog | omap_badwidth_read16, |
1742 | c3d2689d | balrog | }; |
1743 | c3d2689d | balrog | |
1744 | d60efc6b | Blue Swirl | static CPUWriteMemoryFunc * const omap_clkdsp_writefn[] = { |
1745 | c3d2689d | balrog | omap_badwidth_write16, |
1746 | c3d2689d | balrog | omap_clkdsp_write, |
1747 | c3d2689d | balrog | omap_badwidth_write16, |
1748 | c3d2689d | balrog | }; |
1749 | c3d2689d | balrog | |
1750 | c3d2689d | balrog | static void omap_clkm_reset(struct omap_mpu_state_s *s) |
1751 | c3d2689d | balrog | { |
1752 | c3d2689d | balrog | if (s->wdt && s->wdt->reset)
|
1753 | c3d2689d | balrog | s->clkm.cold_start = 0x6;
|
1754 | c3d2689d | balrog | s->clkm.clocking_scheme = 0;
|
1755 | c3d2689d | balrog | omap_clkm_ckctl_update(s, ~0, 0x3000); |
1756 | c3d2689d | balrog | s->clkm.arm_ckctl = 0x3000;
|
1757 | d8f699cb | balrog | omap_clkm_idlect1_update(s, s->clkm.arm_idlect1 ^ 0x0400, 0x0400); |
1758 | c3d2689d | balrog | s->clkm.arm_idlect1 = 0x0400;
|
1759 | d8f699cb | balrog | omap_clkm_idlect2_update(s, s->clkm.arm_idlect2 ^ 0x0100, 0x0100); |
1760 | c3d2689d | balrog | s->clkm.arm_idlect2 = 0x0100;
|
1761 | c3d2689d | balrog | s->clkm.arm_ewupct = 0x003f;
|
1762 | c3d2689d | balrog | s->clkm.arm_rstct1 = 0x0000;
|
1763 | c3d2689d | balrog | s->clkm.arm_rstct2 = 0x0000;
|
1764 | c3d2689d | balrog | s->clkm.arm_ckout1 = 0x0015;
|
1765 | c3d2689d | balrog | s->clkm.dpll1_mode = 0x2002;
|
1766 | c3d2689d | balrog | omap_clkdsp_idlect1_update(s, s->clkm.dsp_idlect1 ^ 0x0040, 0x0040); |
1767 | c3d2689d | balrog | s->clkm.dsp_idlect1 = 0x0040;
|
1768 | c3d2689d | balrog | omap_clkdsp_idlect2_update(s, ~0, 0x0000); |
1769 | c3d2689d | balrog | s->clkm.dsp_idlect2 = 0x0000;
|
1770 | c3d2689d | balrog | s->clkm.dsp_rstct2 = 0x0000;
|
1771 | c3d2689d | balrog | } |
1772 | c3d2689d | balrog | |
1773 | c227f099 | Anthony Liguori | static void omap_clkm_init(target_phys_addr_t mpu_base, |
1774 | c227f099 | Anthony Liguori | target_phys_addr_t dsp_base, struct omap_mpu_state_s *s)
|
1775 | c3d2689d | balrog | { |
1776 | c3d2689d | balrog | int iomemtype[2] = { |
1777 | 1eed09cb | Avi Kivity | cpu_register_io_memory(omap_clkm_readfn, omap_clkm_writefn, s), |
1778 | 1eed09cb | Avi Kivity | cpu_register_io_memory(omap_clkdsp_readfn, omap_clkdsp_writefn, s), |
1779 | c3d2689d | balrog | }; |
1780 | c3d2689d | balrog | |
1781 | d8f699cb | balrog | s->clkm.arm_idlect1 = 0x03ff;
|
1782 | d8f699cb | balrog | s->clkm.arm_idlect2 = 0x0100;
|
1783 | d8f699cb | balrog | s->clkm.dsp_idlect1 = 0x0002;
|
1784 | c3d2689d | balrog | omap_clkm_reset(s); |
1785 | d8f699cb | balrog | s->clkm.cold_start = 0x3a;
|
1786 | c3d2689d | balrog | |
1787 | 8da3ff18 | pbrook | cpu_register_physical_memory(mpu_base, 0x100, iomemtype[0]); |
1788 | 8da3ff18 | pbrook | cpu_register_physical_memory(dsp_base, 0x1000, iomemtype[1]); |
1789 | c3d2689d | balrog | } |
1790 | c3d2689d | balrog | |
1791 | fe71e81a | balrog | /* MPU I/O */
|
1792 | fe71e81a | balrog | struct omap_mpuio_s {
|
1793 | fe71e81a | balrog | qemu_irq irq; |
1794 | fe71e81a | balrog | qemu_irq kbd_irq; |
1795 | fe71e81a | balrog | qemu_irq *in; |
1796 | fe71e81a | balrog | qemu_irq handler[16];
|
1797 | fe71e81a | balrog | qemu_irq wakeup; |
1798 | fe71e81a | balrog | |
1799 | fe71e81a | balrog | uint16_t inputs; |
1800 | fe71e81a | balrog | uint16_t outputs; |
1801 | fe71e81a | balrog | uint16_t dir; |
1802 | fe71e81a | balrog | uint16_t edge; |
1803 | fe71e81a | balrog | uint16_t mask; |
1804 | fe71e81a | balrog | uint16_t ints; |
1805 | fe71e81a | balrog | |
1806 | fe71e81a | balrog | uint16_t debounce; |
1807 | fe71e81a | balrog | uint16_t latch; |
1808 | fe71e81a | balrog | uint8_t event; |
1809 | fe71e81a | balrog | |
1810 | fe71e81a | balrog | uint8_t buttons[5];
|
1811 | fe71e81a | balrog | uint8_t row_latch; |
1812 | fe71e81a | balrog | uint8_t cols; |
1813 | fe71e81a | balrog | int kbd_mask;
|
1814 | fe71e81a | balrog | int clk;
|
1815 | fe71e81a | balrog | }; |
1816 | fe71e81a | balrog | |
1817 | fe71e81a | balrog | static void omap_mpuio_set(void *opaque, int line, int level) |
1818 | fe71e81a | balrog | { |
1819 | fe71e81a | balrog | struct omap_mpuio_s *s = (struct omap_mpuio_s *) opaque; |
1820 | fe71e81a | balrog | uint16_t prev = s->inputs; |
1821 | fe71e81a | balrog | |
1822 | fe71e81a | balrog | if (level)
|
1823 | fe71e81a | balrog | s->inputs |= 1 << line;
|
1824 | fe71e81a | balrog | else
|
1825 | fe71e81a | balrog | s->inputs &= ~(1 << line);
|
1826 | fe71e81a | balrog | |
1827 | fe71e81a | balrog | if (((1 << line) & s->dir & ~s->mask) && s->clk) { |
1828 | fe71e81a | balrog | if ((s->edge & s->inputs & ~prev) | (~s->edge & ~s->inputs & prev)) {
|
1829 | fe71e81a | balrog | s->ints |= 1 << line;
|
1830 | fe71e81a | balrog | qemu_irq_raise(s->irq); |
1831 | fe71e81a | balrog | /* TODO: wakeup */
|
1832 | fe71e81a | balrog | } |
1833 | fe71e81a | balrog | if ((s->event & (1 << 0)) && /* SET_GPIO_EVENT_MODE */ |
1834 | fe71e81a | balrog | (s->event >> 1) == line) /* PIN_SELECT */ |
1835 | fe71e81a | balrog | s->latch = s->inputs; |
1836 | fe71e81a | balrog | } |
1837 | fe71e81a | balrog | } |
1838 | fe71e81a | balrog | |
1839 | fe71e81a | balrog | static void omap_mpuio_kbd_update(struct omap_mpuio_s *s) |
1840 | fe71e81a | balrog | { |
1841 | fe71e81a | balrog | int i;
|
1842 | fe71e81a | balrog | uint8_t *row, rows = 0, cols = ~s->cols;
|
1843 | fe71e81a | balrog | |
1844 | 38a34e1d | balrog | for (row = s->buttons + 4, i = 1 << 4; i; row --, i >>= 1) |
1845 | fe71e81a | balrog | if (*row & cols)
|
1846 | 38a34e1d | balrog | rows |= i; |
1847 | fe71e81a | balrog | |
1848 | cf6d9118 | balrog | qemu_set_irq(s->kbd_irq, rows && !s->kbd_mask && s->clk); |
1849 | cf6d9118 | balrog | s->row_latch = ~rows; |
1850 | fe71e81a | balrog | } |
1851 | fe71e81a | balrog | |
1852 | c227f099 | Anthony Liguori | static uint32_t omap_mpuio_read(void *opaque, target_phys_addr_t addr) |
1853 | fe71e81a | balrog | { |
1854 | fe71e81a | balrog | struct omap_mpuio_s *s = (struct omap_mpuio_s *) opaque; |
1855 | cf965d24 | balrog | int offset = addr & OMAP_MPUI_REG_MASK;
|
1856 | fe71e81a | balrog | uint16_t ret; |
1857 | fe71e81a | balrog | |
1858 | fe71e81a | balrog | switch (offset) {
|
1859 | fe71e81a | balrog | case 0x00: /* INPUT_LATCH */ |
1860 | fe71e81a | balrog | return s->inputs;
|
1861 | fe71e81a | balrog | |
1862 | fe71e81a | balrog | case 0x04: /* OUTPUT_REG */ |
1863 | fe71e81a | balrog | return s->outputs;
|
1864 | fe71e81a | balrog | |
1865 | fe71e81a | balrog | case 0x08: /* IO_CNTL */ |
1866 | fe71e81a | balrog | return s->dir;
|
1867 | fe71e81a | balrog | |
1868 | fe71e81a | balrog | case 0x10: /* KBR_LATCH */ |
1869 | fe71e81a | balrog | return s->row_latch;
|
1870 | fe71e81a | balrog | |
1871 | fe71e81a | balrog | case 0x14: /* KBC_REG */ |
1872 | fe71e81a | balrog | return s->cols;
|
1873 | fe71e81a | balrog | |
1874 | fe71e81a | balrog | case 0x18: /* GPIO_EVENT_MODE_REG */ |
1875 | fe71e81a | balrog | return s->event;
|
1876 | fe71e81a | balrog | |
1877 | fe71e81a | balrog | case 0x1c: /* GPIO_INT_EDGE_REG */ |
1878 | fe71e81a | balrog | return s->edge;
|
1879 | fe71e81a | balrog | |
1880 | fe71e81a | balrog | case 0x20: /* KBD_INT */ |
1881 | cf6d9118 | balrog | return (~s->row_latch & 0x1f) && !s->kbd_mask; |
1882 | fe71e81a | balrog | |
1883 | fe71e81a | balrog | case 0x24: /* GPIO_INT */ |
1884 | fe71e81a | balrog | ret = s->ints; |
1885 | 8e129e07 | balrog | s->ints &= s->mask; |
1886 | 8e129e07 | balrog | if (ret)
|
1887 | 8e129e07 | balrog | qemu_irq_lower(s->irq); |
1888 | fe71e81a | balrog | return ret;
|
1889 | fe71e81a | balrog | |
1890 | fe71e81a | balrog | case 0x28: /* KBD_MASKIT */ |
1891 | fe71e81a | balrog | return s->kbd_mask;
|
1892 | fe71e81a | balrog | |
1893 | fe71e81a | balrog | case 0x2c: /* GPIO_MASKIT */ |
1894 | fe71e81a | balrog | return s->mask;
|
1895 | fe71e81a | balrog | |
1896 | fe71e81a | balrog | case 0x30: /* GPIO_DEBOUNCING_REG */ |
1897 | fe71e81a | balrog | return s->debounce;
|
1898 | fe71e81a | balrog | |
1899 | fe71e81a | balrog | case 0x34: /* GPIO_LATCH_REG */ |
1900 | fe71e81a | balrog | return s->latch;
|
1901 | fe71e81a | balrog | } |
1902 | fe71e81a | balrog | |
1903 | fe71e81a | balrog | OMAP_BAD_REG(addr); |
1904 | fe71e81a | balrog | return 0; |
1905 | fe71e81a | balrog | } |
1906 | fe71e81a | balrog | |
1907 | c227f099 | Anthony Liguori | static void omap_mpuio_write(void *opaque, target_phys_addr_t addr, |
1908 | fe71e81a | balrog | uint32_t value) |
1909 | fe71e81a | balrog | { |
1910 | fe71e81a | balrog | struct omap_mpuio_s *s = (struct omap_mpuio_s *) opaque; |
1911 | cf965d24 | balrog | int offset = addr & OMAP_MPUI_REG_MASK;
|
1912 | fe71e81a | balrog | uint16_t diff; |
1913 | fe71e81a | balrog | int ln;
|
1914 | fe71e81a | balrog | |
1915 | fe71e81a | balrog | switch (offset) {
|
1916 | fe71e81a | balrog | case 0x04: /* OUTPUT_REG */ |
1917 | d8f699cb | balrog | diff = (s->outputs ^ value) & ~s->dir; |
1918 | fe71e81a | balrog | s->outputs = value; |
1919 | fe71e81a | balrog | while ((ln = ffs(diff))) {
|
1920 | fe71e81a | balrog | ln --; |
1921 | fe71e81a | balrog | if (s->handler[ln])
|
1922 | fe71e81a | balrog | qemu_set_irq(s->handler[ln], (value >> ln) & 1);
|
1923 | fe71e81a | balrog | diff &= ~(1 << ln);
|
1924 | fe71e81a | balrog | } |
1925 | fe71e81a | balrog | break;
|
1926 | fe71e81a | balrog | |
1927 | fe71e81a | balrog | case 0x08: /* IO_CNTL */ |
1928 | fe71e81a | balrog | diff = s->outputs & (s->dir ^ value); |
1929 | fe71e81a | balrog | s->dir = value; |
1930 | fe71e81a | balrog | |
1931 | fe71e81a | balrog | value = s->outputs & ~s->dir; |
1932 | fe71e81a | balrog | while ((ln = ffs(diff))) {
|
1933 | fe71e81a | balrog | ln --; |
1934 | fe71e81a | balrog | if (s->handler[ln])
|
1935 | fe71e81a | balrog | qemu_set_irq(s->handler[ln], (value >> ln) & 1);
|
1936 | fe71e81a | balrog | diff &= ~(1 << ln);
|
1937 | fe71e81a | balrog | } |
1938 | fe71e81a | balrog | break;
|
1939 | fe71e81a | balrog | |
1940 | fe71e81a | balrog | case 0x14: /* KBC_REG */ |
1941 | fe71e81a | balrog | s->cols = value; |
1942 | fe71e81a | balrog | omap_mpuio_kbd_update(s); |
1943 | fe71e81a | balrog | break;
|
1944 | fe71e81a | balrog | |
1945 | fe71e81a | balrog | case 0x18: /* GPIO_EVENT_MODE_REG */ |
1946 | fe71e81a | balrog | s->event = value & 0x1f;
|
1947 | fe71e81a | balrog | break;
|
1948 | fe71e81a | balrog | |
1949 | fe71e81a | balrog | case 0x1c: /* GPIO_INT_EDGE_REG */ |
1950 | fe71e81a | balrog | s->edge = value; |
1951 | fe71e81a | balrog | break;
|
1952 | fe71e81a | balrog | |
1953 | fe71e81a | balrog | case 0x28: /* KBD_MASKIT */ |
1954 | fe71e81a | balrog | s->kbd_mask = value & 1;
|
1955 | fe71e81a | balrog | omap_mpuio_kbd_update(s); |
1956 | fe71e81a | balrog | break;
|
1957 | fe71e81a | balrog | |
1958 | fe71e81a | balrog | case 0x2c: /* GPIO_MASKIT */ |
1959 | fe71e81a | balrog | s->mask = value; |
1960 | fe71e81a | balrog | break;
|
1961 | fe71e81a | balrog | |
1962 | fe71e81a | balrog | case 0x30: /* GPIO_DEBOUNCING_REG */ |
1963 | fe71e81a | balrog | s->debounce = value & 0x1ff;
|
1964 | fe71e81a | balrog | break;
|
1965 | fe71e81a | balrog | |
1966 | fe71e81a | balrog | case 0x00: /* INPUT_LATCH */ |
1967 | fe71e81a | balrog | case 0x10: /* KBR_LATCH */ |
1968 | fe71e81a | balrog | case 0x20: /* KBD_INT */ |
1969 | fe71e81a | balrog | case 0x24: /* GPIO_INT */ |
1970 | fe71e81a | balrog | case 0x34: /* GPIO_LATCH_REG */ |
1971 | fe71e81a | balrog | OMAP_RO_REG(addr); |
1972 | fe71e81a | balrog | return;
|
1973 | fe71e81a | balrog | |
1974 | fe71e81a | balrog | default:
|
1975 | fe71e81a | balrog | OMAP_BAD_REG(addr); |
1976 | fe71e81a | balrog | return;
|
1977 | fe71e81a | balrog | } |
1978 | fe71e81a | balrog | } |
1979 | fe71e81a | balrog | |
1980 | d60efc6b | Blue Swirl | static CPUReadMemoryFunc * const omap_mpuio_readfn[] = { |
1981 | fe71e81a | balrog | omap_badwidth_read16, |
1982 | fe71e81a | balrog | omap_mpuio_read, |
1983 | fe71e81a | balrog | omap_badwidth_read16, |
1984 | fe71e81a | balrog | }; |
1985 | fe71e81a | balrog | |
1986 | d60efc6b | Blue Swirl | static CPUWriteMemoryFunc * const omap_mpuio_writefn[] = { |
1987 | fe71e81a | balrog | omap_badwidth_write16, |
1988 | fe71e81a | balrog | omap_mpuio_write, |
1989 | fe71e81a | balrog | omap_badwidth_write16, |
1990 | fe71e81a | balrog | }; |
1991 | fe71e81a | balrog | |
1992 | 9596ebb7 | pbrook | static void omap_mpuio_reset(struct omap_mpuio_s *s) |
1993 | fe71e81a | balrog | { |
1994 | fe71e81a | balrog | s->inputs = 0;
|
1995 | fe71e81a | balrog | s->outputs = 0;
|
1996 | fe71e81a | balrog | s->dir = ~0;
|
1997 | fe71e81a | balrog | s->event = 0;
|
1998 | fe71e81a | balrog | s->edge = 0;
|
1999 | fe71e81a | balrog | s->kbd_mask = 0;
|
2000 | fe71e81a | balrog | s->mask = 0;
|
2001 | fe71e81a | balrog | s->debounce = 0;
|
2002 | fe71e81a | balrog | s->latch = 0;
|
2003 | fe71e81a | balrog | s->ints = 0;
|
2004 | fe71e81a | balrog | s->row_latch = 0x1f;
|
2005 | 38a34e1d | balrog | s->clk = 1;
|
2006 | fe71e81a | balrog | } |
2007 | fe71e81a | balrog | |
2008 | fe71e81a | balrog | static void omap_mpuio_onoff(void *opaque, int line, int on) |
2009 | fe71e81a | balrog | { |
2010 | fe71e81a | balrog | struct omap_mpuio_s *s = (struct omap_mpuio_s *) opaque; |
2011 | fe71e81a | balrog | |
2012 | fe71e81a | balrog | s->clk = on; |
2013 | fe71e81a | balrog | if (on)
|
2014 | fe71e81a | balrog | omap_mpuio_kbd_update(s); |
2015 | fe71e81a | balrog | } |
2016 | fe71e81a | balrog | |
2017 | c227f099 | Anthony Liguori | struct omap_mpuio_s *omap_mpuio_init(target_phys_addr_t base,
|
2018 | fe71e81a | balrog | qemu_irq kbd_int, qemu_irq gpio_int, qemu_irq wakeup, |
2019 | fe71e81a | balrog | omap_clk clk) |
2020 | fe71e81a | balrog | { |
2021 | fe71e81a | balrog | int iomemtype;
|
2022 | fe71e81a | balrog | struct omap_mpuio_s *s = (struct omap_mpuio_s *) |
2023 | fe71e81a | balrog | qemu_mallocz(sizeof(struct omap_mpuio_s)); |
2024 | fe71e81a | balrog | |
2025 | fe71e81a | balrog | s->irq = gpio_int; |
2026 | fe71e81a | balrog | s->kbd_irq = kbd_int; |
2027 | fe71e81a | balrog | s->wakeup = wakeup; |
2028 | fe71e81a | balrog | s->in = qemu_allocate_irqs(omap_mpuio_set, s, 16);
|
2029 | fe71e81a | balrog | omap_mpuio_reset(s); |
2030 | fe71e81a | balrog | |
2031 | 1eed09cb | Avi Kivity | iomemtype = cpu_register_io_memory(omap_mpuio_readfn, |
2032 | fe71e81a | balrog | omap_mpuio_writefn, s); |
2033 | 8da3ff18 | pbrook | cpu_register_physical_memory(base, 0x800, iomemtype);
|
2034 | fe71e81a | balrog | |
2035 | fe71e81a | balrog | omap_clk_adduser(clk, qemu_allocate_irqs(omap_mpuio_onoff, s, 1)[0]); |
2036 | fe71e81a | balrog | |
2037 | fe71e81a | balrog | return s;
|
2038 | fe71e81a | balrog | } |
2039 | fe71e81a | balrog | |
2040 | fe71e81a | balrog | qemu_irq *omap_mpuio_in_get(struct omap_mpuio_s *s)
|
2041 | fe71e81a | balrog | { |
2042 | fe71e81a | balrog | return s->in;
|
2043 | fe71e81a | balrog | } |
2044 | fe71e81a | balrog | |
2045 | fe71e81a | balrog | void omap_mpuio_out_set(struct omap_mpuio_s *s, int line, qemu_irq handler) |
2046 | fe71e81a | balrog | { |
2047 | fe71e81a | balrog | if (line >= 16 || line < 0) |
2048 | 2ac71179 | Paul Brook | hw_error("%s: No GPIO line %i\n", __FUNCTION__, line);
|
2049 | fe71e81a | balrog | s->handler[line] = handler; |
2050 | fe71e81a | balrog | } |
2051 | fe71e81a | balrog | |
2052 | fe71e81a | balrog | void omap_mpuio_key(struct omap_mpuio_s *s, int row, int col, int down) |
2053 | fe71e81a | balrog | { |
2054 | fe71e81a | balrog | if (row >= 5 || row < 0) |
2055 | 2ac71179 | Paul Brook | hw_error("%s: No key %i-%i\n", __FUNCTION__, col, row);
|
2056 | fe71e81a | balrog | |
2057 | fe71e81a | balrog | if (down)
|
2058 | 38a34e1d | balrog | s->buttons[row] |= 1 << col;
|
2059 | fe71e81a | balrog | else
|
2060 | 38a34e1d | balrog | s->buttons[row] &= ~(1 << col);
|
2061 | fe71e81a | balrog | |
2062 | fe71e81a | balrog | omap_mpuio_kbd_update(s); |
2063 | fe71e81a | balrog | } |
2064 | fe71e81a | balrog | |
2065 | d951f6ff | balrog | /* MicroWire Interface */
|
2066 | d951f6ff | balrog | struct omap_uwire_s {
|
2067 | d951f6ff | balrog | qemu_irq txirq; |
2068 | d951f6ff | balrog | qemu_irq rxirq; |
2069 | d951f6ff | balrog | qemu_irq txdrq; |
2070 | d951f6ff | balrog | |
2071 | d951f6ff | balrog | uint16_t txbuf; |
2072 | d951f6ff | balrog | uint16_t rxbuf; |
2073 | d951f6ff | balrog | uint16_t control; |
2074 | d951f6ff | balrog | uint16_t setup[5];
|
2075 | d951f6ff | balrog | |
2076 | bc24a225 | Paul Brook | uWireSlave *chip[4];
|
2077 | d951f6ff | balrog | }; |
2078 | d951f6ff | balrog | |
2079 | d951f6ff | balrog | static void omap_uwire_transfer_start(struct omap_uwire_s *s) |
2080 | d951f6ff | balrog | { |
2081 | d951f6ff | balrog | int chipselect = (s->control >> 10) & 3; /* INDEX */ |
2082 | bc24a225 | Paul Brook | uWireSlave *slave = s->chip[chipselect]; |
2083 | d951f6ff | balrog | |
2084 | d951f6ff | balrog | if ((s->control >> 5) & 0x1f) { /* NB_BITS_WR */ |
2085 | d951f6ff | balrog | if (s->control & (1 << 12)) /* CS_CMD */ |
2086 | d951f6ff | balrog | if (slave && slave->send)
|
2087 | d951f6ff | balrog | slave->send(slave->opaque, |
2088 | d951f6ff | balrog | s->txbuf >> (16 - ((s->control >> 5) & 0x1f))); |
2089 | d951f6ff | balrog | s->control &= ~(1 << 14); /* CSRB */ |
2090 | d951f6ff | balrog | /* TODO: depending on s->setup[4] bits [1:0] assert an IRQ or
|
2091 | d951f6ff | balrog | * a DRQ. When is the level IRQ supposed to be reset? */
|
2092 | d951f6ff | balrog | } |
2093 | d951f6ff | balrog | |
2094 | d951f6ff | balrog | if ((s->control >> 0) & 0x1f) { /* NB_BITS_RD */ |
2095 | d951f6ff | balrog | if (s->control & (1 << 12)) /* CS_CMD */ |
2096 | d951f6ff | balrog | if (slave && slave->receive)
|
2097 | d951f6ff | balrog | s->rxbuf = slave->receive(slave->opaque); |
2098 | d951f6ff | balrog | s->control |= 1 << 15; /* RDRB */ |
2099 | d951f6ff | balrog | /* TODO: depending on s->setup[4] bits [1:0] assert an IRQ or
|
2100 | d951f6ff | balrog | * a DRQ. When is the level IRQ supposed to be reset? */
|
2101 | d951f6ff | balrog | } |
2102 | d951f6ff | balrog | } |
2103 | d951f6ff | balrog | |
2104 | c227f099 | Anthony Liguori | static uint32_t omap_uwire_read(void *opaque, target_phys_addr_t addr) |
2105 | d951f6ff | balrog | { |
2106 | d951f6ff | balrog | struct omap_uwire_s *s = (struct omap_uwire_s *) opaque; |
2107 | cf965d24 | balrog | int offset = addr & OMAP_MPUI_REG_MASK;
|
2108 | d951f6ff | balrog | |
2109 | d951f6ff | balrog | switch (offset) {
|
2110 | d951f6ff | balrog | case 0x00: /* RDR */ |
2111 | d951f6ff | balrog | s->control &= ~(1 << 15); /* RDRB */ |
2112 | d951f6ff | balrog | return s->rxbuf;
|
2113 | d951f6ff | balrog | |
2114 | d951f6ff | balrog | case 0x04: /* CSR */ |
2115 | d951f6ff | balrog | return s->control;
|
2116 | d951f6ff | balrog | |
2117 | d951f6ff | balrog | case 0x08: /* SR1 */ |
2118 | d951f6ff | balrog | return s->setup[0]; |
2119 | d951f6ff | balrog | case 0x0c: /* SR2 */ |
2120 | d951f6ff | balrog | return s->setup[1]; |
2121 | d951f6ff | balrog | case 0x10: /* SR3 */ |
2122 | d951f6ff | balrog | return s->setup[2]; |
2123 | d951f6ff | balrog | case 0x14: /* SR4 */ |
2124 | d951f6ff | balrog | return s->setup[3]; |
2125 | d951f6ff | balrog | case 0x18: /* SR5 */ |
2126 | d951f6ff | balrog | return s->setup[4]; |
2127 | d951f6ff | balrog | } |
2128 | d951f6ff | balrog | |
2129 | d951f6ff | balrog | OMAP_BAD_REG(addr); |
2130 | d951f6ff | balrog | return 0; |
2131 | d951f6ff | balrog | } |
2132 | d951f6ff | balrog | |
2133 | c227f099 | Anthony Liguori | static void omap_uwire_write(void *opaque, target_phys_addr_t addr, |
2134 | d951f6ff | balrog | uint32_t value) |
2135 | d951f6ff | balrog | { |
2136 | d951f6ff | balrog | struct omap_uwire_s *s = (struct omap_uwire_s *) opaque; |
2137 | cf965d24 | balrog | int offset = addr & OMAP_MPUI_REG_MASK;
|
2138 | d951f6ff | balrog | |
2139 | d951f6ff | balrog | switch (offset) {
|
2140 | d951f6ff | balrog | case 0x00: /* TDR */ |
2141 | d951f6ff | balrog | s->txbuf = value; /* TD */
|
2142 | d951f6ff | balrog | if ((s->setup[4] & (1 << 2)) && /* AUTO_TX_EN */ |
2143 | d951f6ff | balrog | ((s->setup[4] & (1 << 3)) || /* CS_TOGGLE_TX_EN */ |
2144 | cf965d24 | balrog | (s->control & (1 << 12)))) { /* CS_CMD */ |
2145 | cf965d24 | balrog | s->control |= 1 << 14; /* CSRB */ |
2146 | d951f6ff | balrog | omap_uwire_transfer_start(s); |
2147 | cf965d24 | balrog | } |
2148 | d951f6ff | balrog | break;
|
2149 | d951f6ff | balrog | |
2150 | d951f6ff | balrog | case 0x04: /* CSR */ |
2151 | d951f6ff | balrog | s->control = value & 0x1fff;
|
2152 | d951f6ff | balrog | if (value & (1 << 13)) /* START */ |
2153 | d951f6ff | balrog | omap_uwire_transfer_start(s); |
2154 | d951f6ff | balrog | break;
|
2155 | d951f6ff | balrog | |
2156 | d951f6ff | balrog | case 0x08: /* SR1 */ |
2157 | d951f6ff | balrog | s->setup[0] = value & 0x003f; |
2158 | d951f6ff | balrog | break;
|
2159 | d951f6ff | balrog | |
2160 | d951f6ff | balrog | case 0x0c: /* SR2 */ |
2161 | d951f6ff | balrog | s->setup[1] = value & 0x0fc0; |
2162 | d951f6ff | balrog | break;
|
2163 | d951f6ff | balrog | |
2164 | d951f6ff | balrog | case 0x10: /* SR3 */ |
2165 | d951f6ff | balrog | s->setup[2] = value & 0x0003; |
2166 | d951f6ff | balrog | break;
|
2167 | d951f6ff | balrog | |
2168 | d951f6ff | balrog | case 0x14: /* SR4 */ |
2169 | d951f6ff | balrog | s->setup[3] = value & 0x0001; |
2170 | d951f6ff | balrog | break;
|
2171 | d951f6ff | balrog | |
2172 | d951f6ff | balrog | case 0x18: /* SR5 */ |
2173 | d951f6ff | balrog | s->setup[4] = value & 0x000f; |
2174 | d951f6ff | balrog | break;
|
2175 | d951f6ff | balrog | |
2176 | d951f6ff | balrog | default:
|
2177 | d951f6ff | balrog | OMAP_BAD_REG(addr); |
2178 | d951f6ff | balrog | return;
|
2179 | d951f6ff | balrog | } |
2180 | d951f6ff | balrog | } |
2181 | d951f6ff | balrog | |
2182 | d60efc6b | Blue Swirl | static CPUReadMemoryFunc * const omap_uwire_readfn[] = { |
2183 | d951f6ff | balrog | omap_badwidth_read16, |
2184 | d951f6ff | balrog | omap_uwire_read, |
2185 | d951f6ff | balrog | omap_badwidth_read16, |
2186 | d951f6ff | balrog | }; |
2187 | d951f6ff | balrog | |
2188 | d60efc6b | Blue Swirl | static CPUWriteMemoryFunc * const omap_uwire_writefn[] = { |
2189 | d951f6ff | balrog | omap_badwidth_write16, |
2190 | d951f6ff | balrog | omap_uwire_write, |
2191 | d951f6ff | balrog | omap_badwidth_write16, |
2192 | d951f6ff | balrog | }; |
2193 | d951f6ff | balrog | |
2194 | 9596ebb7 | pbrook | static void omap_uwire_reset(struct omap_uwire_s *s) |
2195 | d951f6ff | balrog | { |
2196 | 66450b15 | balrog | s->control = 0;
|
2197 | d951f6ff | balrog | s->setup[0] = 0; |
2198 | d951f6ff | balrog | s->setup[1] = 0; |
2199 | d951f6ff | balrog | s->setup[2] = 0; |
2200 | d951f6ff | balrog | s->setup[3] = 0; |
2201 | d951f6ff | balrog | s->setup[4] = 0; |
2202 | d951f6ff | balrog | } |
2203 | d951f6ff | balrog | |
2204 | c227f099 | Anthony Liguori | struct omap_uwire_s *omap_uwire_init(target_phys_addr_t base,
|
2205 | d951f6ff | balrog | qemu_irq *irq, qemu_irq dma, omap_clk clk) |
2206 | d951f6ff | balrog | { |
2207 | d951f6ff | balrog | int iomemtype;
|
2208 | d951f6ff | balrog | struct omap_uwire_s *s = (struct omap_uwire_s *) |
2209 | d951f6ff | balrog | qemu_mallocz(sizeof(struct omap_uwire_s)); |
2210 | d951f6ff | balrog | |
2211 | d951f6ff | balrog | s->txirq = irq[0];
|
2212 | d951f6ff | balrog | s->rxirq = irq[1];
|
2213 | d951f6ff | balrog | s->txdrq = dma; |
2214 | d951f6ff | balrog | omap_uwire_reset(s); |
2215 | d951f6ff | balrog | |
2216 | 1eed09cb | Avi Kivity | iomemtype = cpu_register_io_memory(omap_uwire_readfn, |
2217 | d951f6ff | balrog | omap_uwire_writefn, s); |
2218 | 8da3ff18 | pbrook | cpu_register_physical_memory(base, 0x800, iomemtype);
|
2219 | d951f6ff | balrog | |
2220 | d951f6ff | balrog | return s;
|
2221 | d951f6ff | balrog | } |
2222 | d951f6ff | balrog | |
2223 | d951f6ff | balrog | void omap_uwire_attach(struct omap_uwire_s *s, |
2224 | bc24a225 | Paul Brook | uWireSlave *slave, int chipselect)
|
2225 | d951f6ff | balrog | { |
2226 | 827df9f3 | balrog | if (chipselect < 0 || chipselect > 3) { |
2227 | 827df9f3 | balrog | fprintf(stderr, "%s: Bad chipselect %i\n", __FUNCTION__, chipselect);
|
2228 | 827df9f3 | balrog | exit(-1);
|
2229 | 827df9f3 | balrog | } |
2230 | d951f6ff | balrog | |
2231 | d951f6ff | balrog | s->chip[chipselect] = slave; |
2232 | d951f6ff | balrog | } |
2233 | d951f6ff | balrog | |
2234 | 66450b15 | balrog | /* Pseudonoise Pulse-Width Light Modulator */
|
2235 | 9596ebb7 | pbrook | static void omap_pwl_update(struct omap_mpu_state_s *s) |
2236 | 66450b15 | balrog | { |
2237 | 66450b15 | balrog | int output = (s->pwl.clk && s->pwl.enable) ? s->pwl.level : 0; |
2238 | 66450b15 | balrog | |
2239 | 66450b15 | balrog | if (output != s->pwl.output) {
|
2240 | 66450b15 | balrog | s->pwl.output = output; |
2241 | 66450b15 | balrog | printf("%s: Backlight now at %i/256\n", __FUNCTION__, output);
|
2242 | 66450b15 | balrog | } |
2243 | 66450b15 | balrog | } |
2244 | 66450b15 | balrog | |
2245 | c227f099 | Anthony Liguori | static uint32_t omap_pwl_read(void *opaque, target_phys_addr_t addr) |
2246 | 66450b15 | balrog | { |
2247 | 66450b15 | balrog | struct omap_mpu_state_s *s = (struct omap_mpu_state_s *) opaque; |
2248 | cf965d24 | balrog | int offset = addr & OMAP_MPUI_REG_MASK;
|
2249 | 66450b15 | balrog | |
2250 | 66450b15 | balrog | switch (offset) {
|
2251 | 66450b15 | balrog | case 0x00: /* PWL_LEVEL */ |
2252 | 66450b15 | balrog | return s->pwl.level;
|
2253 | 66450b15 | balrog | case 0x04: /* PWL_CTRL */ |
2254 | 66450b15 | balrog | return s->pwl.enable;
|
2255 | 66450b15 | balrog | } |
2256 | 66450b15 | balrog | OMAP_BAD_REG(addr); |
2257 | 66450b15 | balrog | return 0; |
2258 | 66450b15 | balrog | } |
2259 | 66450b15 | balrog | |
2260 | c227f099 | Anthony Liguori | static void omap_pwl_write(void *opaque, target_phys_addr_t addr, |
2261 | 66450b15 | balrog | uint32_t value) |
2262 | 66450b15 | balrog | { |
2263 | 66450b15 | balrog | struct omap_mpu_state_s *s = (struct omap_mpu_state_s *) opaque; |
2264 | cf965d24 | balrog | int offset = addr & OMAP_MPUI_REG_MASK;
|
2265 | 66450b15 | balrog | |
2266 | 66450b15 | balrog | switch (offset) {
|
2267 | 66450b15 | balrog | case 0x00: /* PWL_LEVEL */ |
2268 | 66450b15 | balrog | s->pwl.level = value; |
2269 | 66450b15 | balrog | omap_pwl_update(s); |
2270 | 66450b15 | balrog | break;
|
2271 | 66450b15 | balrog | case 0x04: /* PWL_CTRL */ |
2272 | 66450b15 | balrog | s->pwl.enable = value & 1;
|
2273 | 66450b15 | balrog | omap_pwl_update(s); |
2274 | 66450b15 | balrog | break;
|
2275 | 66450b15 | balrog | default:
|
2276 | 66450b15 | balrog | OMAP_BAD_REG(addr); |
2277 | 66450b15 | balrog | return;
|
2278 | 66450b15 | balrog | } |
2279 | 66450b15 | balrog | } |
2280 | 66450b15 | balrog | |
2281 | d60efc6b | Blue Swirl | static CPUReadMemoryFunc * const omap_pwl_readfn[] = { |
2282 | 02645926 | balrog | omap_pwl_read, |
2283 | 66450b15 | balrog | omap_badwidth_read8, |
2284 | 66450b15 | balrog | omap_badwidth_read8, |
2285 | 66450b15 | balrog | }; |
2286 | 66450b15 | balrog | |
2287 | d60efc6b | Blue Swirl | static CPUWriteMemoryFunc * const omap_pwl_writefn[] = { |
2288 | 02645926 | balrog | omap_pwl_write, |
2289 | 66450b15 | balrog | omap_badwidth_write8, |
2290 | 66450b15 | balrog | omap_badwidth_write8, |
2291 | 66450b15 | balrog | }; |
2292 | 66450b15 | balrog | |
2293 | 9596ebb7 | pbrook | static void omap_pwl_reset(struct omap_mpu_state_s *s) |
2294 | 66450b15 | balrog | { |
2295 | 66450b15 | balrog | s->pwl.output = 0;
|
2296 | 66450b15 | balrog | s->pwl.level = 0;
|
2297 | 66450b15 | balrog | s->pwl.enable = 0;
|
2298 | 66450b15 | balrog | s->pwl.clk = 1;
|
2299 | 66450b15 | balrog | omap_pwl_update(s); |
2300 | 66450b15 | balrog | } |
2301 | 66450b15 | balrog | |
2302 | 66450b15 | balrog | static void omap_pwl_clk_update(void *opaque, int line, int on) |
2303 | 66450b15 | balrog | { |
2304 | 66450b15 | balrog | struct omap_mpu_state_s *s = (struct omap_mpu_state_s *) opaque; |
2305 | 66450b15 | balrog | |
2306 | 66450b15 | balrog | s->pwl.clk = on; |
2307 | 66450b15 | balrog | omap_pwl_update(s); |
2308 | 66450b15 | balrog | } |
2309 | 66450b15 | balrog | |
2310 | c227f099 | Anthony Liguori | static void omap_pwl_init(target_phys_addr_t base, struct omap_mpu_state_s *s, |
2311 | 66450b15 | balrog | omap_clk clk) |
2312 | 66450b15 | balrog | { |
2313 | 66450b15 | balrog | int iomemtype;
|
2314 | 66450b15 | balrog | |
2315 | 66450b15 | balrog | omap_pwl_reset(s); |
2316 | 66450b15 | balrog | |
2317 | 1eed09cb | Avi Kivity | iomemtype = cpu_register_io_memory(omap_pwl_readfn, |
2318 | 66450b15 | balrog | omap_pwl_writefn, s); |
2319 | b854bc19 | balrog | cpu_register_physical_memory(base, 0x800, iomemtype);
|
2320 | 66450b15 | balrog | |
2321 | 66450b15 | balrog | omap_clk_adduser(clk, qemu_allocate_irqs(omap_pwl_clk_update, s, 1)[0]); |
2322 | 66450b15 | balrog | } |
2323 | 66450b15 | balrog | |
2324 | f34c417b | balrog | /* Pulse-Width Tone module */
|
2325 | c227f099 | Anthony Liguori | static uint32_t omap_pwt_read(void *opaque, target_phys_addr_t addr) |
2326 | f34c417b | balrog | { |
2327 | f34c417b | balrog | struct omap_mpu_state_s *s = (struct omap_mpu_state_s *) opaque; |
2328 | cf965d24 | balrog | int offset = addr & OMAP_MPUI_REG_MASK;
|
2329 | f34c417b | balrog | |
2330 | f34c417b | balrog | switch (offset) {
|
2331 | f34c417b | balrog | case 0x00: /* FRC */ |
2332 | f34c417b | balrog | return s->pwt.frc;
|
2333 | f34c417b | balrog | case 0x04: /* VCR */ |
2334 | f34c417b | balrog | return s->pwt.vrc;
|
2335 | f34c417b | balrog | case 0x08: /* GCR */ |
2336 | f34c417b | balrog | return s->pwt.gcr;
|
2337 | f34c417b | balrog | } |
2338 | f34c417b | balrog | OMAP_BAD_REG(addr); |
2339 | f34c417b | balrog | return 0; |
2340 | f34c417b | balrog | } |
2341 | f34c417b | balrog | |
2342 | c227f099 | Anthony Liguori | static void omap_pwt_write(void *opaque, target_phys_addr_t addr, |
2343 | f34c417b | balrog | uint32_t value) |
2344 | f34c417b | balrog | { |
2345 | f34c417b | balrog | struct omap_mpu_state_s *s = (struct omap_mpu_state_s *) opaque; |
2346 | cf965d24 | balrog | int offset = addr & OMAP_MPUI_REG_MASK;
|
2347 | f34c417b | balrog | |
2348 | f34c417b | balrog | switch (offset) {
|
2349 | f34c417b | balrog | case 0x00: /* FRC */ |
2350 | f34c417b | balrog | s->pwt.frc = value & 0x3f;
|
2351 | f34c417b | balrog | break;
|
2352 | f34c417b | balrog | case 0x04: /* VRC */ |
2353 | f34c417b | balrog | if ((value ^ s->pwt.vrc) & 1) { |
2354 | f34c417b | balrog | if (value & 1) |
2355 | f34c417b | balrog | printf("%s: %iHz buzz on\n", __FUNCTION__, (int) |
2356 | f34c417b | balrog | /* 1.5 MHz from a 12-MHz or 13-MHz PWT_CLK */
|
2357 | f34c417b | balrog | ((omap_clk_getrate(s->pwt.clk) >> 3) /
|
2358 | f34c417b | balrog | /* Pre-multiplexer divider */
|
2359 | f34c417b | balrog | ((s->pwt.gcr & 2) ? 1 : 154) / |
2360 | f34c417b | balrog | /* Octave multiplexer */
|
2361 | f34c417b | balrog | (2 << (value & 3)) * |
2362 | f34c417b | balrog | /* 101/107 divider */
|
2363 | f34c417b | balrog | ((value & (1 << 2)) ? 101 : 107) * |
2364 | f34c417b | balrog | /* 49/55 divider */
|
2365 | f34c417b | balrog | ((value & (1 << 3)) ? 49 : 55) * |
2366 | f34c417b | balrog | /* 50/63 divider */
|
2367 | f34c417b | balrog | ((value & (1 << 4)) ? 50 : 63) * |
2368 | f34c417b | balrog | /* 80/127 divider */
|
2369 | f34c417b | balrog | ((value & (1 << 5)) ? 80 : 127) / |
2370 | f34c417b | balrog | (107 * 55 * 63 * 127))); |
2371 | f34c417b | balrog | else
|
2372 | f34c417b | balrog | printf("%s: silence!\n", __FUNCTION__);
|
2373 | f34c417b | balrog | } |
2374 | f34c417b | balrog | s->pwt.vrc = value & 0x7f;
|
2375 | f34c417b | balrog | break;
|
2376 | f34c417b | balrog | case 0x08: /* GCR */ |
2377 | f34c417b | balrog | s->pwt.gcr = value & 3;
|
2378 | f34c417b | balrog | break;
|
2379 | f34c417b | balrog | default:
|
2380 | f34c417b | balrog | OMAP_BAD_REG(addr); |
2381 | f34c417b | balrog | return;
|
2382 | f34c417b | balrog | } |
2383 | f34c417b | balrog | } |
2384 | f34c417b | balrog | |
2385 | d60efc6b | Blue Swirl | static CPUReadMemoryFunc * const omap_pwt_readfn[] = { |
2386 | 02645926 | balrog | omap_pwt_read, |
2387 | f34c417b | balrog | omap_badwidth_read8, |
2388 | f34c417b | balrog | omap_badwidth_read8, |
2389 | f34c417b | balrog | }; |
2390 | f34c417b | balrog | |
2391 | d60efc6b | Blue Swirl | static CPUWriteMemoryFunc * const omap_pwt_writefn[] = { |
2392 | 02645926 | balrog | omap_pwt_write, |
2393 | f34c417b | balrog | omap_badwidth_write8, |
2394 | f34c417b | balrog | omap_badwidth_write8, |
2395 | f34c417b | balrog | }; |
2396 | f34c417b | balrog | |
2397 | 9596ebb7 | pbrook | static void omap_pwt_reset(struct omap_mpu_state_s *s) |
2398 | f34c417b | balrog | { |
2399 | f34c417b | balrog | s->pwt.frc = 0;
|
2400 | f34c417b | balrog | s->pwt.vrc = 0;
|
2401 | f34c417b | balrog | s->pwt.gcr = 0;
|
2402 | f34c417b | balrog | } |
2403 | f34c417b | balrog | |
2404 | c227f099 | Anthony Liguori | static void omap_pwt_init(target_phys_addr_t base, struct omap_mpu_state_s *s, |
2405 | f34c417b | balrog | omap_clk clk) |
2406 | f34c417b | balrog | { |
2407 | f34c417b | balrog | int iomemtype;
|
2408 | f34c417b | balrog | |
2409 | f34c417b | balrog | s->pwt.clk = clk; |
2410 | f34c417b | balrog | omap_pwt_reset(s); |
2411 | f34c417b | balrog | |
2412 | 1eed09cb | Avi Kivity | iomemtype = cpu_register_io_memory(omap_pwt_readfn, |
2413 | f34c417b | balrog | omap_pwt_writefn, s); |
2414 | b854bc19 | balrog | cpu_register_physical_memory(base, 0x800, iomemtype);
|
2415 | f34c417b | balrog | } |
2416 | f34c417b | balrog | |
2417 | 5c1c390f | balrog | /* Real-time Clock module */
|
2418 | 5c1c390f | balrog | struct omap_rtc_s {
|
2419 | 5c1c390f | balrog | qemu_irq irq; |
2420 | 5c1c390f | balrog | qemu_irq alarm; |
2421 | 5c1c390f | balrog | QEMUTimer *clk; |
2422 | 5c1c390f | balrog | |
2423 | 5c1c390f | balrog | uint8_t interrupts; |
2424 | 5c1c390f | balrog | uint8_t status; |
2425 | 5c1c390f | balrog | int16_t comp_reg; |
2426 | 5c1c390f | balrog | int running;
|
2427 | 5c1c390f | balrog | int pm_am;
|
2428 | 5c1c390f | balrog | int auto_comp;
|
2429 | 5c1c390f | balrog | int round;
|
2430 | 5c1c390f | balrog | struct tm alarm_tm;
|
2431 | 5c1c390f | balrog | time_t alarm_ti; |
2432 | 5c1c390f | balrog | |
2433 | 5c1c390f | balrog | struct tm current_tm;
|
2434 | 5c1c390f | balrog | time_t ti; |
2435 | 5c1c390f | balrog | uint64_t tick; |
2436 | 5c1c390f | balrog | }; |
2437 | 5c1c390f | balrog | |
2438 | 5c1c390f | balrog | static void omap_rtc_interrupts_update(struct omap_rtc_s *s) |
2439 | 5c1c390f | balrog | { |
2440 | 106627d0 | balrog | /* s->alarm is level-triggered */
|
2441 | 5c1c390f | balrog | qemu_set_irq(s->alarm, (s->status >> 6) & 1); |
2442 | 5c1c390f | balrog | } |
2443 | 5c1c390f | balrog | |
2444 | 5c1c390f | balrog | static void omap_rtc_alarm_update(struct omap_rtc_s *s) |
2445 | 5c1c390f | balrog | { |
2446 | 0cd2df75 | aurel32 | s->alarm_ti = mktimegm(&s->alarm_tm); |
2447 | 5c1c390f | balrog | if (s->alarm_ti == -1) |
2448 | 5c1c390f | balrog | printf("%s: conversion failed\n", __FUNCTION__);
|
2449 | 5c1c390f | balrog | } |
2450 | 5c1c390f | balrog | |
2451 | c227f099 | Anthony Liguori | static uint32_t omap_rtc_read(void *opaque, target_phys_addr_t addr) |
2452 | 5c1c390f | balrog | { |
2453 | 5c1c390f | balrog | struct omap_rtc_s *s = (struct omap_rtc_s *) opaque; |
2454 | cf965d24 | balrog | int offset = addr & OMAP_MPUI_REG_MASK;
|
2455 | 5c1c390f | balrog | uint8_t i; |
2456 | 5c1c390f | balrog | |
2457 | 5c1c390f | balrog | switch (offset) {
|
2458 | 5c1c390f | balrog | case 0x00: /* SECONDS_REG */ |
2459 | abd0c6bd | Paul Brook | return to_bcd(s->current_tm.tm_sec);
|
2460 | 5c1c390f | balrog | |
2461 | 5c1c390f | balrog | case 0x04: /* MINUTES_REG */ |
2462 | abd0c6bd | Paul Brook | return to_bcd(s->current_tm.tm_min);
|
2463 | 5c1c390f | balrog | |
2464 | 5c1c390f | balrog | case 0x08: /* HOURS_REG */ |
2465 | 5c1c390f | balrog | if (s->pm_am)
|
2466 | 5c1c390f | balrog | return ((s->current_tm.tm_hour > 11) << 7) | |
2467 | abd0c6bd | Paul Brook | to_bcd(((s->current_tm.tm_hour - 1) % 12) + 1); |
2468 | 5c1c390f | balrog | else
|
2469 | abd0c6bd | Paul Brook | return to_bcd(s->current_tm.tm_hour);
|
2470 | 5c1c390f | balrog | |
2471 | 5c1c390f | balrog | case 0x0c: /* DAYS_REG */ |
2472 | abd0c6bd | Paul Brook | return to_bcd(s->current_tm.tm_mday);
|
2473 | 5c1c390f | balrog | |
2474 | 5c1c390f | balrog | case 0x10: /* MONTHS_REG */ |
2475 | abd0c6bd | Paul Brook | return to_bcd(s->current_tm.tm_mon + 1); |
2476 | 5c1c390f | balrog | |
2477 | 5c1c390f | balrog | case 0x14: /* YEARS_REG */ |
2478 | abd0c6bd | Paul Brook | return to_bcd(s->current_tm.tm_year % 100); |
2479 | 5c1c390f | balrog | |
2480 | 5c1c390f | balrog | case 0x18: /* WEEK_REG */ |
2481 | 5c1c390f | balrog | return s->current_tm.tm_wday;
|
2482 | 5c1c390f | balrog | |
2483 | 5c1c390f | balrog | case 0x20: /* ALARM_SECONDS_REG */ |
2484 | abd0c6bd | Paul Brook | return to_bcd(s->alarm_tm.tm_sec);
|
2485 | 5c1c390f | balrog | |
2486 | 5c1c390f | balrog | case 0x24: /* ALARM_MINUTES_REG */ |
2487 | abd0c6bd | Paul Brook | return to_bcd(s->alarm_tm.tm_min);
|
2488 | 5c1c390f | balrog | |
2489 | 5c1c390f | balrog | case 0x28: /* ALARM_HOURS_REG */ |
2490 | 5c1c390f | balrog | if (s->pm_am)
|
2491 | 5c1c390f | balrog | return ((s->alarm_tm.tm_hour > 11) << 7) | |
2492 | abd0c6bd | Paul Brook | to_bcd(((s->alarm_tm.tm_hour - 1) % 12) + 1); |
2493 | 5c1c390f | balrog | else
|
2494 | abd0c6bd | Paul Brook | return to_bcd(s->alarm_tm.tm_hour);
|
2495 | 5c1c390f | balrog | |
2496 | 5c1c390f | balrog | case 0x2c: /* ALARM_DAYS_REG */ |
2497 | abd0c6bd | Paul Brook | return to_bcd(s->alarm_tm.tm_mday);
|
2498 | 5c1c390f | balrog | |
2499 | 5c1c390f | balrog | case 0x30: /* ALARM_MONTHS_REG */ |
2500 | abd0c6bd | Paul Brook | return to_bcd(s->alarm_tm.tm_mon + 1); |
2501 | 5c1c390f | balrog | |
2502 | 5c1c390f | balrog | case 0x34: /* ALARM_YEARS_REG */ |
2503 | abd0c6bd | Paul Brook | return to_bcd(s->alarm_tm.tm_year % 100); |
2504 | 5c1c390f | balrog | |
2505 | 5c1c390f | balrog | case 0x40: /* RTC_CTRL_REG */ |
2506 | 5c1c390f | balrog | return (s->pm_am << 3) | (s->auto_comp << 2) | |
2507 | 5c1c390f | balrog | (s->round << 1) | s->running;
|
2508 | 5c1c390f | balrog | |
2509 | 5c1c390f | balrog | case 0x44: /* RTC_STATUS_REG */ |
2510 | 5c1c390f | balrog | i = s->status; |
2511 | 5c1c390f | balrog | s->status &= ~0x3d;
|
2512 | 5c1c390f | balrog | return i;
|
2513 | 5c1c390f | balrog | |
2514 | 5c1c390f | balrog | case 0x48: /* RTC_INTERRUPTS_REG */ |
2515 | 5c1c390f | balrog | return s->interrupts;
|
2516 | 5c1c390f | balrog | |
2517 | 5c1c390f | balrog | case 0x4c: /* RTC_COMP_LSB_REG */ |
2518 | 5c1c390f | balrog | return ((uint16_t) s->comp_reg) & 0xff; |
2519 | 5c1c390f | balrog | |
2520 | 5c1c390f | balrog | case 0x50: /* RTC_COMP_MSB_REG */ |
2521 | 5c1c390f | balrog | return ((uint16_t) s->comp_reg) >> 8; |
2522 | 5c1c390f | balrog | } |
2523 | 5c1c390f | balrog | |
2524 | 5c1c390f | balrog | OMAP_BAD_REG(addr); |
2525 | 5c1c390f | balrog | return 0; |
2526 | 5c1c390f | balrog | } |
2527 | 5c1c390f | balrog | |
2528 | c227f099 | Anthony Liguori | static void omap_rtc_write(void *opaque, target_phys_addr_t addr, |
2529 | 5c1c390f | balrog | uint32_t value) |
2530 | 5c1c390f | balrog | { |
2531 | 5c1c390f | balrog | struct omap_rtc_s *s = (struct omap_rtc_s *) opaque; |
2532 | cf965d24 | balrog | int offset = addr & OMAP_MPUI_REG_MASK;
|
2533 | 5c1c390f | balrog | struct tm new_tm;
|
2534 | 5c1c390f | balrog | time_t ti[2];
|
2535 | 5c1c390f | balrog | |
2536 | 5c1c390f | balrog | switch (offset) {
|
2537 | 5c1c390f | balrog | case 0x00: /* SECONDS_REG */ |
2538 | eb38c52c | blueswir1 | #ifdef ALMDEBUG
|
2539 | 5c1c390f | balrog | printf("RTC SEC_REG <-- %02x\n", value);
|
2540 | 5c1c390f | balrog | #endif
|
2541 | 5c1c390f | balrog | s->ti -= s->current_tm.tm_sec; |
2542 | abd0c6bd | Paul Brook | s->ti += from_bcd(value); |
2543 | 5c1c390f | balrog | return;
|
2544 | 5c1c390f | balrog | |
2545 | 5c1c390f | balrog | case 0x04: /* MINUTES_REG */ |
2546 | eb38c52c | blueswir1 | #ifdef ALMDEBUG
|
2547 | 5c1c390f | balrog | printf("RTC MIN_REG <-- %02x\n", value);
|
2548 | 5c1c390f | balrog | #endif
|
2549 | 5c1c390f | balrog | s->ti -= s->current_tm.tm_min * 60;
|
2550 | abd0c6bd | Paul Brook | s->ti += from_bcd(value) * 60;
|
2551 | 5c1c390f | balrog | return;
|
2552 | 5c1c390f | balrog | |
2553 | 5c1c390f | balrog | case 0x08: /* HOURS_REG */ |
2554 | eb38c52c | blueswir1 | #ifdef ALMDEBUG
|
2555 | 5c1c390f | balrog | printf("RTC HRS_REG <-- %02x\n", value);
|
2556 | 5c1c390f | balrog | #endif
|
2557 | 5c1c390f | balrog | s->ti -= s->current_tm.tm_hour * 3600;
|
2558 | 5c1c390f | balrog | if (s->pm_am) {
|
2559 | abd0c6bd | Paul Brook | s->ti += (from_bcd(value & 0x3f) & 12) * 3600; |
2560 | 5c1c390f | balrog | s->ti += ((value >> 7) & 1) * 43200; |
2561 | 5c1c390f | balrog | } else
|
2562 | abd0c6bd | Paul Brook | s->ti += from_bcd(value & 0x3f) * 3600; |
2563 | 5c1c390f | balrog | return;
|
2564 | 5c1c390f | balrog | |
2565 | 5c1c390f | balrog | case 0x0c: /* DAYS_REG */ |
2566 | eb38c52c | blueswir1 | #ifdef ALMDEBUG
|
2567 | 5c1c390f | balrog | printf("RTC DAY_REG <-- %02x\n", value);
|
2568 | 5c1c390f | balrog | #endif
|
2569 | 5c1c390f | balrog | s->ti -= s->current_tm.tm_mday * 86400;
|
2570 | abd0c6bd | Paul Brook | s->ti += from_bcd(value) * 86400;
|
2571 | 5c1c390f | balrog | return;
|
2572 | 5c1c390f | balrog | |
2573 | 5c1c390f | balrog | case 0x10: /* MONTHS_REG */ |
2574 | eb38c52c | blueswir1 | #ifdef ALMDEBUG
|
2575 | 5c1c390f | balrog | printf("RTC MTH_REG <-- %02x\n", value);
|
2576 | 5c1c390f | balrog | #endif
|
2577 | 5c1c390f | balrog | memcpy(&new_tm, &s->current_tm, sizeof(new_tm));
|
2578 | abd0c6bd | Paul Brook | new_tm.tm_mon = from_bcd(value); |
2579 | 0cd2df75 | aurel32 | ti[0] = mktimegm(&s->current_tm);
|
2580 | 0cd2df75 | aurel32 | ti[1] = mktimegm(&new_tm);
|
2581 | 5c1c390f | balrog | |
2582 | 5c1c390f | balrog | if (ti[0] != -1 && ti[1] != -1) { |
2583 | 5c1c390f | balrog | s->ti -= ti[0];
|
2584 | 5c1c390f | balrog | s->ti += ti[1];
|
2585 | 5c1c390f | balrog | } else {
|
2586 | 5c1c390f | balrog | /* A less accurate version */
|
2587 | 5c1c390f | balrog | s->ti -= s->current_tm.tm_mon * 2592000;
|
2588 | abd0c6bd | Paul Brook | s->ti += from_bcd(value) * 2592000;
|
2589 | 5c1c390f | balrog | } |
2590 | 5c1c390f | balrog | return;
|
2591 | 5c1c390f | balrog | |
2592 | 5c1c390f | balrog | case 0x14: /* YEARS_REG */ |
2593 | eb38c52c | blueswir1 | #ifdef ALMDEBUG
|
2594 | 5c1c390f | balrog | printf("RTC YRS_REG <-- %02x\n", value);
|
2595 | 5c1c390f | balrog | #endif
|
2596 | 5c1c390f | balrog | memcpy(&new_tm, &s->current_tm, sizeof(new_tm));
|
2597 | abd0c6bd | Paul Brook | new_tm.tm_year += from_bcd(value) - (new_tm.tm_year % 100);
|
2598 | 0cd2df75 | aurel32 | ti[0] = mktimegm(&s->current_tm);
|
2599 | 0cd2df75 | aurel32 | ti[1] = mktimegm(&new_tm);
|
2600 | 5c1c390f | balrog | |
2601 | 5c1c390f | balrog | if (ti[0] != -1 && ti[1] != -1) { |
2602 | 5c1c390f | balrog | s->ti -= ti[0];
|
2603 | 5c1c390f | balrog | s->ti += ti[1];
|
2604 | 5c1c390f | balrog | } else {
|
2605 | 5c1c390f | balrog | /* A less accurate version */
|
2606 | 5c1c390f | balrog | s->ti -= (s->current_tm.tm_year % 100) * 31536000; |
2607 | abd0c6bd | Paul Brook | s->ti += from_bcd(value) * 31536000;
|
2608 | 5c1c390f | balrog | } |
2609 | 5c1c390f | balrog | return;
|
2610 | 5c1c390f | balrog | |
2611 | 5c1c390f | balrog | case 0x18: /* WEEK_REG */ |
2612 | 5c1c390f | balrog | return; /* Ignored */ |
2613 | 5c1c390f | balrog | |
2614 | 5c1c390f | balrog | case 0x20: /* ALARM_SECONDS_REG */ |
2615 | eb38c52c | blueswir1 | #ifdef ALMDEBUG
|
2616 | 5c1c390f | balrog | printf("ALM SEC_REG <-- %02x\n", value);
|
2617 | 5c1c390f | balrog | #endif
|
2618 | abd0c6bd | Paul Brook | s->alarm_tm.tm_sec = from_bcd(value); |
2619 | 5c1c390f | balrog | omap_rtc_alarm_update(s); |
2620 | 5c1c390f | balrog | return;
|
2621 | 5c1c390f | balrog | |
2622 | 5c1c390f | balrog | case 0x24: /* ALARM_MINUTES_REG */ |
2623 | eb38c52c | blueswir1 | #ifdef ALMDEBUG
|
2624 | 5c1c390f | balrog | printf("ALM MIN_REG <-- %02x\n", value);
|
2625 | 5c1c390f | balrog | #endif
|
2626 | abd0c6bd | Paul Brook | s->alarm_tm.tm_min = from_bcd(value); |
2627 | 5c1c390f | balrog | omap_rtc_alarm_update(s); |
2628 | 5c1c390f | balrog | return;
|
2629 | 5c1c390f | balrog | |
2630 | 5c1c390f | balrog | case 0x28: /* ALARM_HOURS_REG */ |
2631 | eb38c52c | blueswir1 | #ifdef ALMDEBUG
|
2632 | 5c1c390f | balrog | printf("ALM HRS_REG <-- %02x\n", value);
|
2633 | 5c1c390f | balrog | #endif
|
2634 | 5c1c390f | balrog | if (s->pm_am)
|
2635 | 5c1c390f | balrog | s->alarm_tm.tm_hour = |
2636 | abd0c6bd | Paul Brook | ((from_bcd(value & 0x3f)) % 12) + |
2637 | 5c1c390f | balrog | ((value >> 7) & 1) * 12; |
2638 | 5c1c390f | balrog | else
|
2639 | abd0c6bd | Paul Brook | s->alarm_tm.tm_hour = from_bcd(value); |
2640 | 5c1c390f | balrog | omap_rtc_alarm_update(s); |
2641 | 5c1c390f | balrog | return;
|
2642 | 5c1c390f | balrog | |
2643 | 5c1c390f | balrog | case 0x2c: /* ALARM_DAYS_REG */ |
2644 | eb38c52c | blueswir1 | #ifdef ALMDEBUG
|
2645 | 5c1c390f | balrog | printf("ALM DAY_REG <-- %02x\n", value);
|
2646 | 5c1c390f | balrog | #endif
|
2647 | abd0c6bd | Paul Brook | s->alarm_tm.tm_mday = from_bcd(value); |
2648 | 5c1c390f | balrog | omap_rtc_alarm_update(s); |
2649 | 5c1c390f | balrog | return;
|
2650 | 5c1c390f | balrog | |
2651 | 5c1c390f | balrog | case 0x30: /* ALARM_MONTHS_REG */ |
2652 | eb38c52c | blueswir1 | #ifdef ALMDEBUG
|
2653 | 5c1c390f | balrog | printf("ALM MON_REG <-- %02x\n", value);
|
2654 | 5c1c390f | balrog | #endif
|
2655 | abd0c6bd | Paul Brook | s->alarm_tm.tm_mon = from_bcd(value); |
2656 | 5c1c390f | balrog | omap_rtc_alarm_update(s); |
2657 | 5c1c390f | balrog | return;
|
2658 | 5c1c390f | balrog | |
2659 | 5c1c390f | balrog | case 0x34: /* ALARM_YEARS_REG */ |
2660 | eb38c52c | blueswir1 | #ifdef ALMDEBUG
|
2661 | 5c1c390f | balrog | printf("ALM YRS_REG <-- %02x\n", value);
|
2662 | 5c1c390f | balrog | #endif
|
2663 | abd0c6bd | Paul Brook | s->alarm_tm.tm_year = from_bcd(value); |
2664 | 5c1c390f | balrog | omap_rtc_alarm_update(s); |
2665 | 5c1c390f | balrog | return;
|
2666 | 5c1c390f | balrog | |
2667 | 5c1c390f | balrog | case 0x40: /* RTC_CTRL_REG */ |
2668 | eb38c52c | blueswir1 | #ifdef ALMDEBUG
|
2669 | 5c1c390f | balrog | printf("RTC CONTROL <-- %02x\n", value);
|
2670 | 5c1c390f | balrog | #endif
|
2671 | 5c1c390f | balrog | s->pm_am = (value >> 3) & 1; |
2672 | 5c1c390f | balrog | s->auto_comp = (value >> 2) & 1; |
2673 | 5c1c390f | balrog | s->round = (value >> 1) & 1; |
2674 | 5c1c390f | balrog | s->running = value & 1;
|
2675 | 5c1c390f | balrog | s->status &= 0xfd;
|
2676 | 5c1c390f | balrog | s->status |= s->running << 1;
|
2677 | 5c1c390f | balrog | return;
|
2678 | 5c1c390f | balrog | |
2679 | 5c1c390f | balrog | case 0x44: /* RTC_STATUS_REG */ |
2680 | eb38c52c | blueswir1 | #ifdef ALMDEBUG
|
2681 | 5c1c390f | balrog | printf("RTC STATUSL <-- %02x\n", value);
|
2682 | 5c1c390f | balrog | #endif
|
2683 | 5c1c390f | balrog | s->status &= ~((value & 0xc0) ^ 0x80); |
2684 | 5c1c390f | balrog | omap_rtc_interrupts_update(s); |
2685 | 5c1c390f | balrog | return;
|
2686 | 5c1c390f | balrog | |
2687 | 5c1c390f | balrog | case 0x48: /* RTC_INTERRUPTS_REG */ |
2688 | eb38c52c | blueswir1 | #ifdef ALMDEBUG
|
2689 | 5c1c390f | balrog | printf("RTC INTRS <-- %02x\n", value);
|
2690 | 5c1c390f | balrog | #endif
|
2691 | 5c1c390f | balrog | s->interrupts = value; |
2692 | 5c1c390f | balrog | return;
|
2693 | 5c1c390f | balrog | |
2694 | 5c1c390f | balrog | case 0x4c: /* RTC_COMP_LSB_REG */ |
2695 | eb38c52c | blueswir1 | #ifdef ALMDEBUG
|
2696 | 5c1c390f | balrog | printf("RTC COMPLSB <-- %02x\n", value);
|
2697 | 5c1c390f | balrog | #endif
|
2698 | 5c1c390f | balrog | s->comp_reg &= 0xff00;
|
2699 | 5c1c390f | balrog | s->comp_reg |= 0x00ff & value;
|
2700 | 5c1c390f | balrog | return;
|
2701 | 5c1c390f | balrog | |
2702 | 5c1c390f | balrog | case 0x50: /* RTC_COMP_MSB_REG */ |
2703 | eb38c52c | blueswir1 | #ifdef ALMDEBUG
|
2704 | 5c1c390f | balrog | printf("RTC COMPMSB <-- %02x\n", value);
|
2705 | 5c1c390f | balrog | #endif
|
2706 | 5c1c390f | balrog | s->comp_reg &= 0x00ff;
|
2707 | 5c1c390f | balrog | s->comp_reg |= 0xff00 & (value << 8); |
2708 | 5c1c390f | balrog | return;
|
2709 | 5c1c390f | balrog | |
2710 | 5c1c390f | balrog | default:
|
2711 | 5c1c390f | balrog | OMAP_BAD_REG(addr); |
2712 | 5c1c390f | balrog | return;
|
2713 | 5c1c390f | balrog | } |
2714 | 5c1c390f | balrog | } |
2715 | 5c1c390f | balrog | |
2716 | d60efc6b | Blue Swirl | static CPUReadMemoryFunc * const omap_rtc_readfn[] = { |
2717 | 5c1c390f | balrog | omap_rtc_read, |
2718 | 5c1c390f | balrog | omap_badwidth_read8, |
2719 | 5c1c390f | balrog | omap_badwidth_read8, |
2720 | 5c1c390f | balrog | }; |
2721 | 5c1c390f | balrog | |
2722 | d60efc6b | Blue Swirl | static CPUWriteMemoryFunc * const omap_rtc_writefn[] = { |
2723 | 5c1c390f | balrog | omap_rtc_write, |
2724 | 5c1c390f | balrog | omap_badwidth_write8, |
2725 | 5c1c390f | balrog | omap_badwidth_write8, |
2726 | 5c1c390f | balrog | }; |
2727 | 5c1c390f | balrog | |
2728 | 5c1c390f | balrog | static void omap_rtc_tick(void *opaque) |
2729 | 5c1c390f | balrog | { |
2730 | 5c1c390f | balrog | struct omap_rtc_s *s = opaque;
|
2731 | 5c1c390f | balrog | |
2732 | 5c1c390f | balrog | if (s->round) {
|
2733 | 5c1c390f | balrog | /* Round to nearest full minute. */
|
2734 | 5c1c390f | balrog | if (s->current_tm.tm_sec < 30) |
2735 | 5c1c390f | balrog | s->ti -= s->current_tm.tm_sec; |
2736 | 5c1c390f | balrog | else
|
2737 | 5c1c390f | balrog | s->ti += 60 - s->current_tm.tm_sec;
|
2738 | 5c1c390f | balrog | |
2739 | 5c1c390f | balrog | s->round = 0;
|
2740 | 5c1c390f | balrog | } |
2741 | 5c1c390f | balrog | |
2742 | f6503059 | balrog | memcpy(&s->current_tm, localtime(&s->ti), sizeof(s->current_tm));
|
2743 | 5c1c390f | balrog | |
2744 | 5c1c390f | balrog | if ((s->interrupts & 0x08) && s->ti == s->alarm_ti) { |
2745 | 5c1c390f | balrog | s->status |= 0x40;
|
2746 | 5c1c390f | balrog | omap_rtc_interrupts_update(s); |
2747 | 5c1c390f | balrog | } |
2748 | 5c1c390f | balrog | |
2749 | 5c1c390f | balrog | if (s->interrupts & 0x04) |
2750 | 5c1c390f | balrog | switch (s->interrupts & 3) { |
2751 | 5c1c390f | balrog | case 0: |
2752 | 5c1c390f | balrog | s->status |= 0x04;
|
2753 | 106627d0 | balrog | qemu_irq_pulse(s->irq); |
2754 | 5c1c390f | balrog | break;
|
2755 | 5c1c390f | balrog | case 1: |
2756 | 5c1c390f | balrog | if (s->current_tm.tm_sec)
|
2757 | 5c1c390f | balrog | break;
|
2758 | 5c1c390f | balrog | s->status |= 0x08;
|
2759 | 106627d0 | balrog | qemu_irq_pulse(s->irq); |
2760 | 5c1c390f | balrog | break;
|
2761 | 5c1c390f | balrog | case 2: |
2762 | 5c1c390f | balrog | if (s->current_tm.tm_sec || s->current_tm.tm_min)
|
2763 | 5c1c390f | balrog | break;
|
2764 | 5c1c390f | balrog | s->status |= 0x10;
|
2765 | 106627d0 | balrog | qemu_irq_pulse(s->irq); |
2766 | 5c1c390f | balrog | break;
|
2767 | 5c1c390f | balrog | case 3: |
2768 | 5c1c390f | balrog | if (s->current_tm.tm_sec ||
|
2769 | 5c1c390f | balrog | s->current_tm.tm_min || s->current_tm.tm_hour) |
2770 | 5c1c390f | balrog | break;
|
2771 | 5c1c390f | balrog | s->status |= 0x20;
|
2772 | 106627d0 | balrog | qemu_irq_pulse(s->irq); |
2773 | 5c1c390f | balrog | break;
|
2774 | 5c1c390f | balrog | } |
2775 | 5c1c390f | balrog | |
2776 | 5c1c390f | balrog | /* Move on */
|
2777 | 5c1c390f | balrog | if (s->running)
|
2778 | 5c1c390f | balrog | s->ti ++; |
2779 | 5c1c390f | balrog | s->tick += 1000;
|
2780 | 5c1c390f | balrog | |
2781 | 5c1c390f | balrog | /*
|
2782 | 5c1c390f | balrog | * Every full hour add a rough approximation of the compensation
|
2783 | 5c1c390f | balrog | * register to the 32kHz Timer (which drives the RTC) value.
|
2784 | 5c1c390f | balrog | */
|
2785 | 5c1c390f | balrog | if (s->auto_comp && !s->current_tm.tm_sec && !s->current_tm.tm_min)
|
2786 | 5c1c390f | balrog | s->tick += s->comp_reg * 1000 / 32768; |
2787 | 5c1c390f | balrog | |
2788 | 5c1c390f | balrog | qemu_mod_timer(s->clk, s->tick); |
2789 | 5c1c390f | balrog | } |
2790 | 5c1c390f | balrog | |
2791 | 9596ebb7 | pbrook | static void omap_rtc_reset(struct omap_rtc_s *s) |
2792 | 5c1c390f | balrog | { |
2793 | f6503059 | balrog | struct tm tm;
|
2794 | f6503059 | balrog | |
2795 | 5c1c390f | balrog | s->interrupts = 0;
|
2796 | 5c1c390f | balrog | s->comp_reg = 0;
|
2797 | 5c1c390f | balrog | s->running = 0;
|
2798 | 5c1c390f | balrog | s->pm_am = 0;
|
2799 | 5c1c390f | balrog | s->auto_comp = 0;
|
2800 | 5c1c390f | balrog | s->round = 0;
|
2801 | 5c1c390f | balrog | s->tick = qemu_get_clock(rt_clock); |
2802 | 5c1c390f | balrog | memset(&s->alarm_tm, 0, sizeof(s->alarm_tm)); |
2803 | 5c1c390f | balrog | s->alarm_tm.tm_mday = 0x01;
|
2804 | 5c1c390f | balrog | s->status = 1 << 7; |
2805 | f6503059 | balrog | qemu_get_timedate(&tm, 0);
|
2806 | 0cd2df75 | aurel32 | s->ti = mktimegm(&tm); |
2807 | 5c1c390f | balrog | |
2808 | 5c1c390f | balrog | omap_rtc_alarm_update(s); |
2809 | 5c1c390f | balrog | omap_rtc_tick(s); |
2810 | 5c1c390f | balrog | } |
2811 | 5c1c390f | balrog | |
2812 | c1ff227b | cmchao | static struct omap_rtc_s *omap_rtc_init(target_phys_addr_t base, |
2813 | 5c1c390f | balrog | qemu_irq *irq, omap_clk clk) |
2814 | 5c1c390f | balrog | { |
2815 | 5c1c390f | balrog | int iomemtype;
|
2816 | 5c1c390f | balrog | struct omap_rtc_s *s = (struct omap_rtc_s *) |
2817 | 5c1c390f | balrog | qemu_mallocz(sizeof(struct omap_rtc_s)); |
2818 | 5c1c390f | balrog | |
2819 | 5c1c390f | balrog | s->irq = irq[0];
|
2820 | 5c1c390f | balrog | s->alarm = irq[1];
|
2821 | 5c1c390f | balrog | s->clk = qemu_new_timer(rt_clock, omap_rtc_tick, s); |
2822 | 5c1c390f | balrog | |
2823 | 5c1c390f | balrog | omap_rtc_reset(s); |
2824 | 5c1c390f | balrog | |
2825 | 1eed09cb | Avi Kivity | iomemtype = cpu_register_io_memory(omap_rtc_readfn, |
2826 | 5c1c390f | balrog | omap_rtc_writefn, s); |
2827 | 8da3ff18 | pbrook | cpu_register_physical_memory(base, 0x800, iomemtype);
|
2828 | 5c1c390f | balrog | |
2829 | 5c1c390f | balrog | return s;
|
2830 | 5c1c390f | balrog | } |
2831 | 5c1c390f | balrog | |
2832 | d8f699cb | balrog | /* Multi-channel Buffered Serial Port interfaces */
|
2833 | d8f699cb | balrog | struct omap_mcbsp_s {
|
2834 | d8f699cb | balrog | qemu_irq txirq; |
2835 | d8f699cb | balrog | qemu_irq rxirq; |
2836 | d8f699cb | balrog | qemu_irq txdrq; |
2837 | d8f699cb | balrog | qemu_irq rxdrq; |
2838 | d8f699cb | balrog | |
2839 | d8f699cb | balrog | uint16_t spcr[2];
|
2840 | d8f699cb | balrog | uint16_t rcr[2];
|
2841 | d8f699cb | balrog | uint16_t xcr[2];
|
2842 | d8f699cb | balrog | uint16_t srgr[2];
|
2843 | d8f699cb | balrog | uint16_t mcr[2];
|
2844 | d8f699cb | balrog | uint16_t pcr; |
2845 | d8f699cb | balrog | uint16_t rcer[8];
|
2846 | d8f699cb | balrog | uint16_t xcer[8];
|
2847 | d8f699cb | balrog | int tx_rate;
|
2848 | d8f699cb | balrog | int rx_rate;
|
2849 | d8f699cb | balrog | int tx_req;
|
2850 | 73560bc8 | balrog | int rx_req;
|
2851 | d8f699cb | balrog | |
2852 | bc24a225 | Paul Brook | I2SCodec *codec; |
2853 | 73560bc8 | balrog | QEMUTimer *source_timer; |
2854 | 73560bc8 | balrog | QEMUTimer *sink_timer; |
2855 | d8f699cb | balrog | }; |
2856 | d8f699cb | balrog | |
2857 | d8f699cb | balrog | static void omap_mcbsp_intr_update(struct omap_mcbsp_s *s) |
2858 | d8f699cb | balrog | { |
2859 | d8f699cb | balrog | int irq;
|
2860 | d8f699cb | balrog | |
2861 | d8f699cb | balrog | switch ((s->spcr[0] >> 4) & 3) { /* RINTM */ |
2862 | d8f699cb | balrog | case 0: |
2863 | d8f699cb | balrog | irq = (s->spcr[0] >> 1) & 1; /* RRDY */ |
2864 | d8f699cb | balrog | break;
|
2865 | d8f699cb | balrog | case 3: |
2866 | d8f699cb | balrog | irq = (s->spcr[0] >> 3) & 1; /* RSYNCERR */ |
2867 | d8f699cb | balrog | break;
|
2868 | d8f699cb | balrog | default:
|
2869 | d8f699cb | balrog | irq = 0;
|
2870 | d8f699cb | balrog | break;
|
2871 | d8f699cb | balrog | } |
2872 | d8f699cb | balrog | |
2873 | 106627d0 | balrog | if (irq)
|
2874 | 106627d0 | balrog | qemu_irq_pulse(s->rxirq); |
2875 | d8f699cb | balrog | |
2876 | d8f699cb | balrog | switch ((s->spcr[1] >> 4) & 3) { /* XINTM */ |
2877 | d8f699cb | balrog | case 0: |
2878 | d8f699cb | balrog | irq = (s->spcr[1] >> 1) & 1; /* XRDY */ |
2879 | d8f699cb | balrog | break;
|
2880 | d8f699cb | balrog | case 3: |
2881 | d8f699cb | balrog | irq = (s->spcr[1] >> 3) & 1; /* XSYNCERR */ |
2882 | d8f699cb | balrog | break;
|
2883 | d8f699cb | balrog | default:
|
2884 | d8f699cb | balrog | irq = 0;
|
2885 | d8f699cb | balrog | break;
|
2886 | d8f699cb | balrog | } |
2887 | d8f699cb | balrog | |
2888 | 106627d0 | balrog | if (irq)
|
2889 | 106627d0 | balrog | qemu_irq_pulse(s->txirq); |
2890 | d8f699cb | balrog | } |
2891 | d8f699cb | balrog | |
2892 | 73560bc8 | balrog | static void omap_mcbsp_rx_newdata(struct omap_mcbsp_s *s) |
2893 | d8f699cb | balrog | { |
2894 | 73560bc8 | balrog | if ((s->spcr[0] >> 1) & 1) /* RRDY */ |
2895 | 73560bc8 | balrog | s->spcr[0] |= 1 << 2; /* RFULL */ |
2896 | 73560bc8 | balrog | s->spcr[0] |= 1 << 1; /* RRDY */ |
2897 | 73560bc8 | balrog | qemu_irq_raise(s->rxdrq); |
2898 | 73560bc8 | balrog | omap_mcbsp_intr_update(s); |
2899 | d8f699cb | balrog | } |
2900 | d8f699cb | balrog | |
2901 | 73560bc8 | balrog | static void omap_mcbsp_source_tick(void *opaque) |
2902 | d8f699cb | balrog | { |
2903 | 73560bc8 | balrog | struct omap_mcbsp_s *s = (struct omap_mcbsp_s *) opaque; |
2904 | 73560bc8 | balrog | static const int bps[8] = { 0, 1, 1, 2, 2, 2, -255, -255 }; |
2905 | 73560bc8 | balrog | |
2906 | 73560bc8 | balrog | if (!s->rx_rate)
|
2907 | d8f699cb | balrog | return;
|
2908 | 73560bc8 | balrog | if (s->rx_req)
|
2909 | 73560bc8 | balrog | printf("%s: Rx FIFO overrun\n", __FUNCTION__);
|
2910 | d8f699cb | balrog | |
2911 | 73560bc8 | balrog | s->rx_req = s->rx_rate << bps[(s->rcr[0] >> 5) & 7]; |
2912 | d8f699cb | balrog | |
2913 | 73560bc8 | balrog | omap_mcbsp_rx_newdata(s); |
2914 | 6ee093c9 | Juan Quintela | qemu_mod_timer(s->source_timer, qemu_get_clock(vm_clock) + |
2915 | 6ee093c9 | Juan Quintela | get_ticks_per_sec()); |
2916 | d8f699cb | balrog | } |
2917 | d8f699cb | balrog | |
2918 | d8f699cb | balrog | static void omap_mcbsp_rx_start(struct omap_mcbsp_s *s) |
2919 | d8f699cb | balrog | { |
2920 | 73560bc8 | balrog | if (!s->codec || !s->codec->rts)
|
2921 | 73560bc8 | balrog | omap_mcbsp_source_tick(s); |
2922 | 73560bc8 | balrog | else if (s->codec->in.len) { |
2923 | 73560bc8 | balrog | s->rx_req = s->codec->in.len; |
2924 | 73560bc8 | balrog | omap_mcbsp_rx_newdata(s); |
2925 | d8f699cb | balrog | } |
2926 | d8f699cb | balrog | } |
2927 | d8f699cb | balrog | |
2928 | d8f699cb | balrog | static void omap_mcbsp_rx_stop(struct omap_mcbsp_s *s) |
2929 | d8f699cb | balrog | { |
2930 | 73560bc8 | balrog | qemu_del_timer(s->source_timer); |
2931 | 73560bc8 | balrog | } |
2932 | 73560bc8 | balrog | |
2933 | 73560bc8 | balrog | static void omap_mcbsp_rx_done(struct omap_mcbsp_s *s) |
2934 | 73560bc8 | balrog | { |
2935 | d8f699cb | balrog | s->spcr[0] &= ~(1 << 1); /* RRDY */ |
2936 | d8f699cb | balrog | qemu_irq_lower(s->rxdrq); |
2937 | d8f699cb | balrog | omap_mcbsp_intr_update(s); |
2938 | d8f699cb | balrog | } |
2939 | d8f699cb | balrog | |
2940 | 73560bc8 | balrog | static void omap_mcbsp_tx_newdata(struct omap_mcbsp_s *s) |
2941 | 73560bc8 | balrog | { |
2942 | 73560bc8 | balrog | s->spcr[1] |= 1 << 1; /* XRDY */ |
2943 | 73560bc8 | balrog | qemu_irq_raise(s->txdrq); |
2944 | 73560bc8 | balrog | omap_mcbsp_intr_update(s); |
2945 | 73560bc8 | balrog | } |
2946 | 73560bc8 | balrog | |
2947 | 73560bc8 | balrog | static void omap_mcbsp_sink_tick(void *opaque) |
2948 | d8f699cb | balrog | { |
2949 | 73560bc8 | balrog | struct omap_mcbsp_s *s = (struct omap_mcbsp_s *) opaque; |
2950 | 73560bc8 | balrog | static const int bps[8] = { 0, 1, 1, 2, 2, 2, -255, -255 }; |
2951 | 73560bc8 | balrog | |
2952 | 73560bc8 | balrog | if (!s->tx_rate)
|
2953 | d8f699cb | balrog | return;
|
2954 | 73560bc8 | balrog | if (s->tx_req)
|
2955 | 73560bc8 | balrog | printf("%s: Tx FIFO underrun\n", __FUNCTION__);
|
2956 | 73560bc8 | balrog | |
2957 | 73560bc8 | balrog | s->tx_req = s->tx_rate << bps[(s->xcr[0] >> 5) & 7]; |
2958 | 73560bc8 | balrog | |
2959 | 73560bc8 | balrog | omap_mcbsp_tx_newdata(s); |
2960 | 6ee093c9 | Juan Quintela | qemu_mod_timer(s->sink_timer, qemu_get_clock(vm_clock) + |
2961 | 6ee093c9 | Juan Quintela | get_ticks_per_sec()); |
2962 | 73560bc8 | balrog | } |
2963 | 73560bc8 | balrog | |
2964 | 73560bc8 | balrog | static void omap_mcbsp_tx_start(struct omap_mcbsp_s *s) |
2965 | 73560bc8 | balrog | { |
2966 | 73560bc8 | balrog | if (!s->codec || !s->codec->cts)
|
2967 | 73560bc8 | balrog | omap_mcbsp_sink_tick(s); |
2968 | 73560bc8 | balrog | else if (s->codec->out.size) { |
2969 | 73560bc8 | balrog | s->tx_req = s->codec->out.size; |
2970 | 73560bc8 | balrog | omap_mcbsp_tx_newdata(s); |
2971 | 73560bc8 | balrog | } |
2972 | 73560bc8 | balrog | } |
2973 | 73560bc8 | balrog | |
2974 | 73560bc8 | balrog | static void omap_mcbsp_tx_done(struct omap_mcbsp_s *s) |
2975 | 73560bc8 | balrog | { |
2976 | 73560bc8 | balrog | s->spcr[1] &= ~(1 << 1); /* XRDY */ |
2977 | 73560bc8 | balrog | qemu_irq_lower(s->txdrq); |
2978 | 73560bc8 | balrog | omap_mcbsp_intr_update(s); |
2979 | 73560bc8 | balrog | if (s->codec && s->codec->cts)
|
2980 | 73560bc8 | balrog | s->codec->tx_swallow(s->codec->opaque); |
2981 | d8f699cb | balrog | } |
2982 | d8f699cb | balrog | |
2983 | d8f699cb | balrog | static void omap_mcbsp_tx_stop(struct omap_mcbsp_s *s) |
2984 | d8f699cb | balrog | { |
2985 | 73560bc8 | balrog | s->tx_req = 0;
|
2986 | 73560bc8 | balrog | omap_mcbsp_tx_done(s); |
2987 | 73560bc8 | balrog | qemu_del_timer(s->sink_timer); |
2988 | 73560bc8 | balrog | } |
2989 | 73560bc8 | balrog | |
2990 | 73560bc8 | balrog | static void omap_mcbsp_req_update(struct omap_mcbsp_s *s) |
2991 | 73560bc8 | balrog | { |
2992 | 73560bc8 | balrog | int prev_rx_rate, prev_tx_rate;
|
2993 | 73560bc8 | balrog | int rx_rate = 0, tx_rate = 0; |
2994 | 73560bc8 | balrog | int cpu_rate = 1500000; /* XXX */ |
2995 | 73560bc8 | balrog | |
2996 | 73560bc8 | balrog | /* TODO: check CLKSTP bit */
|
2997 | 73560bc8 | balrog | if (s->spcr[1] & (1 << 6)) { /* GRST */ |
2998 | 73560bc8 | balrog | if (s->spcr[0] & (1 << 0)) { /* RRST */ |
2999 | 73560bc8 | balrog | if ((s->srgr[1] & (1 << 13)) && /* CLKSM */ |
3000 | 73560bc8 | balrog | (s->pcr & (1 << 8))) { /* CLKRM */ |
3001 | 73560bc8 | balrog | if (~s->pcr & (1 << 7)) /* SCLKME */ |
3002 | 73560bc8 | balrog | rx_rate = cpu_rate / |
3003 | 73560bc8 | balrog | ((s->srgr[0] & 0xff) + 1); /* CLKGDV */ |
3004 | 73560bc8 | balrog | } else
|
3005 | 73560bc8 | balrog | if (s->codec)
|
3006 | 73560bc8 | balrog | rx_rate = s->codec->rx_rate; |
3007 | 73560bc8 | balrog | } |
3008 | 73560bc8 | balrog | |
3009 | 73560bc8 | balrog | if (s->spcr[1] & (1 << 0)) { /* XRST */ |
3010 | 73560bc8 | balrog | if ((s->srgr[1] & (1 << 13)) && /* CLKSM */ |
3011 | 73560bc8 | balrog | (s->pcr & (1 << 9))) { /* CLKXM */ |
3012 | 73560bc8 | balrog | if (~s->pcr & (1 << 7)) /* SCLKME */ |
3013 | 73560bc8 | balrog | tx_rate = cpu_rate / |
3014 | 73560bc8 | balrog | ((s->srgr[0] & 0xff) + 1); /* CLKGDV */ |
3015 | 73560bc8 | balrog | } else
|
3016 | 73560bc8 | balrog | if (s->codec)
|
3017 | 73560bc8 | balrog | tx_rate = s->codec->tx_rate; |
3018 | 73560bc8 | balrog | } |
3019 | 73560bc8 | balrog | } |
3020 | 73560bc8 | balrog | prev_tx_rate = s->tx_rate; |
3021 | 73560bc8 | balrog | prev_rx_rate = s->rx_rate; |
3022 | 73560bc8 | balrog | s->tx_rate = tx_rate; |
3023 | 73560bc8 | balrog | s->rx_rate = rx_rate; |
3024 | 73560bc8 | balrog | |
3025 | 73560bc8 | balrog | if (s->codec)
|
3026 | 73560bc8 | balrog | s->codec->set_rate(s->codec->opaque, rx_rate, tx_rate); |
3027 | 73560bc8 | balrog | |
3028 | 73560bc8 | balrog | if (!prev_tx_rate && tx_rate)
|
3029 | 73560bc8 | balrog | omap_mcbsp_tx_start(s); |
3030 | 73560bc8 | balrog | else if (s->tx_rate && !tx_rate) |
3031 | 73560bc8 | balrog | omap_mcbsp_tx_stop(s); |
3032 | 73560bc8 | balrog | |
3033 | 73560bc8 | balrog | if (!prev_rx_rate && rx_rate)
|
3034 | 73560bc8 | balrog | omap_mcbsp_rx_start(s); |
3035 | 73560bc8 | balrog | else if (prev_tx_rate && !tx_rate) |
3036 | 73560bc8 | balrog | omap_mcbsp_rx_stop(s); |
3037 | d8f699cb | balrog | } |
3038 | d8f699cb | balrog | |
3039 | c227f099 | Anthony Liguori | static uint32_t omap_mcbsp_read(void *opaque, target_phys_addr_t addr) |
3040 | d8f699cb | balrog | { |
3041 | d8f699cb | balrog | struct omap_mcbsp_s *s = (struct omap_mcbsp_s *) opaque; |
3042 | d8f699cb | balrog | int offset = addr & OMAP_MPUI_REG_MASK;
|
3043 | d8f699cb | balrog | uint16_t ret; |
3044 | d8f699cb | balrog | |
3045 | d8f699cb | balrog | switch (offset) {
|
3046 | d8f699cb | balrog | case 0x00: /* DRR2 */ |
3047 | d8f699cb | balrog | if (((s->rcr[0] >> 5) & 7) < 3) /* RWDLEN1 */ |
3048 | d8f699cb | balrog | return 0x0000; |
3049 | d8f699cb | balrog | /* Fall through. */
|
3050 | d8f699cb | balrog | case 0x02: /* DRR1 */ |
3051 | 73560bc8 | balrog | if (s->rx_req < 2) { |
3052 | d8f699cb | balrog | printf("%s: Rx FIFO underrun\n", __FUNCTION__);
|
3053 | 73560bc8 | balrog | omap_mcbsp_rx_done(s); |
3054 | d8f699cb | balrog | } else {
|
3055 | 73560bc8 | balrog | s->tx_req -= 2;
|
3056 | 73560bc8 | balrog | if (s->codec && s->codec->in.len >= 2) { |
3057 | 73560bc8 | balrog | ret = s->codec->in.fifo[s->codec->in.start ++] << 8;
|
3058 | 73560bc8 | balrog | ret |= s->codec->in.fifo[s->codec->in.start ++]; |
3059 | 73560bc8 | balrog | s->codec->in.len -= 2;
|
3060 | 73560bc8 | balrog | } else
|
3061 | 73560bc8 | balrog | ret = 0x0000;
|
3062 | 73560bc8 | balrog | if (!s->tx_req)
|
3063 | 73560bc8 | balrog | omap_mcbsp_rx_done(s); |
3064 | d8f699cb | balrog | return ret;
|
3065 | d8f699cb | balrog | } |
3066 | d8f699cb | balrog | return 0x0000; |
3067 | d8f699cb | balrog | |
3068 | d8f699cb | balrog | case 0x04: /* DXR2 */ |
3069 | d8f699cb | balrog | case 0x06: /* DXR1 */ |
3070 | d8f699cb | balrog | return 0x0000; |
3071 | d8f699cb | balrog | |
3072 | d8f699cb | balrog | case 0x08: /* SPCR2 */ |
3073 | d8f699cb | balrog | return s->spcr[1]; |
3074 | d8f699cb | balrog | case 0x0a: /* SPCR1 */ |
3075 | d8f699cb | balrog | return s->spcr[0]; |
3076 | d8f699cb | balrog | case 0x0c: /* RCR2 */ |
3077 | d8f699cb | balrog | return s->rcr[1]; |
3078 | d8f699cb | balrog | case 0x0e: /* RCR1 */ |
3079 | d8f699cb | balrog | return s->rcr[0]; |
3080 | d8f699cb | balrog | case 0x10: /* XCR2 */ |
3081 | d8f699cb | balrog | return s->xcr[1]; |
3082 | d8f699cb | balrog | case 0x12: /* XCR1 */ |
3083 | d8f699cb | balrog | return s->xcr[0]; |
3084 | d8f699cb | balrog | case 0x14: /* SRGR2 */ |
3085 | d8f699cb | balrog | return s->srgr[1]; |
3086 | d8f699cb | balrog | case 0x16: /* SRGR1 */ |
3087 | d8f699cb | balrog | return s->srgr[0]; |
3088 | d8f699cb | balrog | case 0x18: /* MCR2 */ |
3089 | d8f699cb | balrog | return s->mcr[1]; |
3090 | d8f699cb | balrog | case 0x1a: /* MCR1 */ |
3091 | d8f699cb | balrog | return s->mcr[0]; |
3092 | d8f699cb | balrog | case 0x1c: /* RCERA */ |
3093 | d8f699cb | balrog | return s->rcer[0]; |
3094 | d8f699cb | balrog | case 0x1e: /* RCERB */ |
3095 | d8f699cb | balrog | return s->rcer[1]; |
3096 | d8f699cb | balrog | case 0x20: /* XCERA */ |
3097 | d8f699cb | balrog | return s->xcer[0]; |
3098 | d8f699cb | balrog | case 0x22: /* XCERB */ |
3099 | d8f699cb | balrog | return s->xcer[1]; |
3100 | d8f699cb | balrog | case 0x24: /* PCR0 */ |
3101 | d8f699cb | balrog | return s->pcr;
|
3102 | d8f699cb | balrog | case 0x26: /* RCERC */ |
3103 | d8f699cb | balrog | return s->rcer[2]; |
3104 | d8f699cb | balrog | case 0x28: /* RCERD */ |
3105 | d8f699cb | balrog | return s->rcer[3]; |
3106 | d8f699cb | balrog | case 0x2a: /* XCERC */ |
3107 | d8f699cb | balrog | return s->xcer[2]; |
3108 | d8f699cb | balrog | case 0x2c: /* XCERD */ |
3109 | d8f699cb | balrog | return s->xcer[3]; |
3110 | d8f699cb | balrog | case 0x2e: /* RCERE */ |
3111 | d8f699cb | balrog | return s->rcer[4]; |
3112 | d8f699cb | balrog | case 0x30: /* RCERF */ |
3113 | d8f699cb | balrog | return s->rcer[5]; |
3114 | d8f699cb | balrog | case 0x32: /* XCERE */ |
3115 | d8f699cb | balrog | return s->xcer[4]; |
3116 | d8f699cb | balrog | case 0x34: /* XCERF */ |
3117 | d8f699cb | balrog | return s->xcer[5]; |
3118 | d8f699cb | balrog | case 0x36: /* RCERG */ |
3119 | d8f699cb | balrog | return s->rcer[6]; |
3120 | d8f699cb | balrog | case 0x38: /* RCERH */ |
3121 | d8f699cb | balrog | return s->rcer[7]; |
3122 | d8f699cb | balrog | case 0x3a: /* XCERG */ |
3123 | d8f699cb | balrog | return s->xcer[6]; |
3124 | d8f699cb | balrog | case 0x3c: /* XCERH */ |
3125 | d8f699cb | balrog | return s->xcer[7]; |
3126 | d8f699cb | balrog | } |
3127 | d8f699cb | balrog | |
3128 | d8f699cb | balrog | OMAP_BAD_REG(addr); |
3129 | d8f699cb | balrog | return 0; |
3130 | d8f699cb | balrog | } |
3131 | d8f699cb | balrog | |
3132 | c227f099 | Anthony Liguori | static void omap_mcbsp_writeh(void *opaque, target_phys_addr_t addr, |
3133 | d8f699cb | balrog | uint32_t value) |
3134 | d8f699cb | balrog | { |
3135 | d8f699cb | balrog | struct omap_mcbsp_s *s = (struct omap_mcbsp_s *) opaque; |
3136 | d8f699cb | balrog | int offset = addr & OMAP_MPUI_REG_MASK;
|
3137 | d8f699cb | balrog | |
3138 | d8f699cb | balrog | switch (offset) {
|
3139 | d8f699cb | balrog | case 0x00: /* DRR2 */ |
3140 | d8f699cb | balrog | case 0x02: /* DRR1 */ |
3141 | d8f699cb | balrog | OMAP_RO_REG(addr); |
3142 | d8f699cb | balrog | return;
|
3143 | d8f699cb | balrog | |
3144 | d8f699cb | balrog | case 0x04: /* DXR2 */ |
3145 | d8f699cb | balrog | if (((s->xcr[0] >> 5) & 7) < 3) /* XWDLEN1 */ |
3146 | d8f699cb | balrog | return;
|
3147 | d8f699cb | balrog | /* Fall through. */
|
3148 | d8f699cb | balrog | case 0x06: /* DXR1 */ |
3149 | 73560bc8 | balrog | if (s->tx_req > 1) { |
3150 | 73560bc8 | balrog | s->tx_req -= 2;
|
3151 | 73560bc8 | balrog | if (s->codec && s->codec->cts) {
|
3152 | d8f699cb | balrog | s->codec->out.fifo[s->codec->out.len ++] = (value >> 8) & 0xff; |
3153 | d8f699cb | balrog | s->codec->out.fifo[s->codec->out.len ++] = (value >> 0) & 0xff; |
3154 | d8f699cb | balrog | } |
3155 | 73560bc8 | balrog | if (s->tx_req < 2) |
3156 | 73560bc8 | balrog | omap_mcbsp_tx_done(s); |
3157 | d8f699cb | balrog | } else
|
3158 | d8f699cb | balrog | printf("%s: Tx FIFO overrun\n", __FUNCTION__);
|
3159 | d8f699cb | balrog | return;
|
3160 | d8f699cb | balrog | |
3161 | d8f699cb | balrog | case 0x08: /* SPCR2 */ |
3162 | d8f699cb | balrog | s->spcr[1] &= 0x0002; |
3163 | d8f699cb | balrog | s->spcr[1] |= 0x03f9 & value; |
3164 | d8f699cb | balrog | s->spcr[1] |= 0x0004 & (value << 2); /* XEMPTY := XRST */ |
3165 | 73560bc8 | balrog | if (~value & 1) /* XRST */ |
3166 | d8f699cb | balrog | s->spcr[1] &= ~6; |
3167 | d8f699cb | balrog | omap_mcbsp_req_update(s); |
3168 | d8f699cb | balrog | return;
|
3169 | d8f699cb | balrog | case 0x0a: /* SPCR1 */ |
3170 | d8f699cb | balrog | s->spcr[0] &= 0x0006; |
3171 | d8f699cb | balrog | s->spcr[0] |= 0xf8f9 & value; |
3172 | d8f699cb | balrog | if (value & (1 << 15)) /* DLB */ |
3173 | d8f699cb | balrog | printf("%s: Digital Loopback mode enable attempt\n", __FUNCTION__);
|
3174 | d8f699cb | balrog | if (~value & 1) { /* RRST */ |
3175 | d8f699cb | balrog | s->spcr[0] &= ~6; |
3176 | 73560bc8 | balrog | s->rx_req = 0;
|
3177 | 73560bc8 | balrog | omap_mcbsp_rx_done(s); |
3178 | d8f699cb | balrog | } |
3179 | d8f699cb | balrog | omap_mcbsp_req_update(s); |
3180 | d8f699cb | balrog | return;
|
3181 | d8f699cb | balrog | |
3182 | d8f699cb | balrog | case 0x0c: /* RCR2 */ |
3183 | d8f699cb | balrog | s->rcr[1] = value & 0xffff; |
3184 | d8f699cb | balrog | return;
|
3185 | d8f699cb | balrog | case 0x0e: /* RCR1 */ |
3186 | d8f699cb | balrog | s->rcr[0] = value & 0x7fe0; |
3187 | d8f699cb | balrog | return;
|
3188 | d8f699cb | balrog | case 0x10: /* XCR2 */ |
3189 | d8f699cb | balrog | s->xcr[1] = value & 0xffff; |
3190 | d8f699cb | balrog | return;
|
3191 | d8f699cb | balrog | case 0x12: /* XCR1 */ |
3192 | d8f699cb | balrog | s->xcr[0] = value & 0x7fe0; |
3193 | d8f699cb | balrog | return;
|
3194 | d8f699cb | balrog | case 0x14: /* SRGR2 */ |
3195 | d8f699cb | balrog | s->srgr[1] = value & 0xffff; |
3196 | 73560bc8 | balrog | omap_mcbsp_req_update(s); |
3197 | d8f699cb | balrog | return;
|
3198 | d8f699cb | balrog | case 0x16: /* SRGR1 */ |
3199 | d8f699cb | balrog | s->srgr[0] = value & 0xffff; |
3200 | 73560bc8 | balrog | omap_mcbsp_req_update(s); |
3201 | d8f699cb | balrog | return;
|
3202 | d8f699cb | balrog | case 0x18: /* MCR2 */ |
3203 | d8f699cb | balrog | s->mcr[1] = value & 0x03e3; |
3204 | d8f699cb | balrog | if (value & 3) /* XMCM */ |
3205 | d8f699cb | balrog | printf("%s: Tx channel selection mode enable attempt\n",
|
3206 | d8f699cb | balrog | __FUNCTION__); |
3207 | d8f699cb | balrog | return;
|
3208 | d8f699cb | balrog | case 0x1a: /* MCR1 */ |
3209 | d8f699cb | balrog | s->mcr[0] = value & 0x03e1; |
3210 | d8f699cb | balrog | if (value & 1) /* RMCM */ |
3211 | d8f699cb | balrog | printf("%s: Rx channel selection mode enable attempt\n",
|
3212 | d8f699cb | balrog | __FUNCTION__); |
3213 | d8f699cb | balrog | return;
|
3214 | d8f699cb | balrog | case 0x1c: /* RCERA */ |
3215 | d8f699cb | balrog | s->rcer[0] = value & 0xffff; |
3216 | d8f699cb | balrog | return;
|
3217 | d8f699cb | balrog | case 0x1e: /* RCERB */ |
3218 | d8f699cb | balrog | s->rcer[1] = value & 0xffff; |
3219 | d8f699cb | balrog | return;
|
3220 | d8f699cb | balrog | case 0x20: /* XCERA */ |
3221 | d8f699cb | balrog | s->xcer[0] = value & 0xffff; |
3222 | d8f699cb | balrog | return;
|
3223 | d8f699cb | balrog | case 0x22: /* XCERB */ |
3224 | d8f699cb | balrog | s->xcer[1] = value & 0xffff; |
3225 | d8f699cb | balrog | return;
|
3226 | d8f699cb | balrog | case 0x24: /* PCR0 */ |
3227 | d8f699cb | balrog | s->pcr = value & 0x7faf;
|
3228 | d8f699cb | balrog | return;
|
3229 | d8f699cb | balrog | case 0x26: /* RCERC */ |
3230 | d8f699cb | balrog | s->rcer[2] = value & 0xffff; |
3231 | d8f699cb | balrog | return;
|
3232 | d8f699cb | balrog | case 0x28: /* RCERD */ |
3233 | d8f699cb | balrog | s->rcer[3] = value & 0xffff; |
3234 | d8f699cb | balrog | return;
|
3235 | d8f699cb | balrog | case 0x2a: /* XCERC */ |
3236 | d8f699cb | balrog | s->xcer[2] = value & 0xffff; |
3237 | d8f699cb | balrog | return;
|
3238 | d8f699cb | balrog | case 0x2c: /* XCERD */ |
3239 | d8f699cb | balrog | s->xcer[3] = value & 0xffff; |
3240 | d8f699cb | balrog | return;
|
3241 | d8f699cb | balrog | case 0x2e: /* RCERE */ |
3242 | d8f699cb | balrog | s->rcer[4] = value & 0xffff; |
3243 | d8f699cb | balrog | return;
|
3244 | d8f699cb | balrog | case 0x30: /* RCERF */ |
3245 | d8f699cb | balrog | s->rcer[5] = value & 0xffff; |
3246 | d8f699cb | balrog | return;
|
3247 | d8f699cb | balrog | case 0x32: /* XCERE */ |
3248 | d8f699cb | balrog | s->xcer[4] = value & 0xffff; |
3249 | d8f699cb | balrog | return;
|
3250 | d8f699cb | balrog | case 0x34: /* XCERF */ |
3251 | d8f699cb | balrog | s->xcer[5] = value & 0xffff; |
3252 | d8f699cb | balrog | return;
|
3253 | d8f699cb | balrog | case 0x36: /* RCERG */ |
3254 | d8f699cb | balrog | s->rcer[6] = value & 0xffff; |
3255 | d8f699cb | balrog | return;
|
3256 | d8f699cb | balrog | case 0x38: /* RCERH */ |
3257 | d8f699cb | balrog | s->rcer[7] = value & 0xffff; |
3258 | d8f699cb | balrog | return;
|
3259 | d8f699cb | balrog | case 0x3a: /* XCERG */ |
3260 | d8f699cb | balrog | s->xcer[6] = value & 0xffff; |
3261 | d8f699cb | balrog | return;
|
3262 | d8f699cb | balrog | case 0x3c: /* XCERH */ |
3263 | d8f699cb | balrog | s->xcer[7] = value & 0xffff; |
3264 | d8f699cb | balrog | return;
|
3265 | d8f699cb | balrog | } |
3266 | d8f699cb | balrog | |
3267 | d8f699cb | balrog | OMAP_BAD_REG(addr); |
3268 | d8f699cb | balrog | } |
3269 | d8f699cb | balrog | |
3270 | c227f099 | Anthony Liguori | static void omap_mcbsp_writew(void *opaque, target_phys_addr_t addr, |
3271 | 73560bc8 | balrog | uint32_t value) |
3272 | 73560bc8 | balrog | { |
3273 | 73560bc8 | balrog | struct omap_mcbsp_s *s = (struct omap_mcbsp_s *) opaque; |
3274 | 73560bc8 | balrog | int offset = addr & OMAP_MPUI_REG_MASK;
|
3275 | 73560bc8 | balrog | |
3276 | 73560bc8 | balrog | if (offset == 0x04) { /* DXR */ |
3277 | 73560bc8 | balrog | if (((s->xcr[0] >> 5) & 7) < 3) /* XWDLEN1 */ |
3278 | 73560bc8 | balrog | return;
|
3279 | 73560bc8 | balrog | if (s->tx_req > 3) { |
3280 | 73560bc8 | balrog | s->tx_req -= 4;
|
3281 | 73560bc8 | balrog | if (s->codec && s->codec->cts) {
|
3282 | 73560bc8 | balrog | s->codec->out.fifo[s->codec->out.len ++] = |
3283 | 73560bc8 | balrog | (value >> 24) & 0xff; |
3284 | 73560bc8 | balrog | s->codec->out.fifo[s->codec->out.len ++] = |
3285 | 73560bc8 | balrog | (value >> 16) & 0xff; |
3286 | 73560bc8 | balrog | s->codec->out.fifo[s->codec->out.len ++] = |
3287 | 73560bc8 | balrog | (value >> 8) & 0xff; |
3288 | 73560bc8 | balrog | s->codec->out.fifo[s->codec->out.len ++] = |
3289 | 73560bc8 | balrog | (value >> 0) & 0xff; |
3290 | 73560bc8 | balrog | } |
3291 | 73560bc8 | balrog | if (s->tx_req < 4) |
3292 | 73560bc8 | balrog | omap_mcbsp_tx_done(s); |
3293 | 73560bc8 | balrog | } else
|
3294 | 73560bc8 | balrog | printf("%s: Tx FIFO overrun\n", __FUNCTION__);
|
3295 | 73560bc8 | balrog | return;
|
3296 | 73560bc8 | balrog | } |
3297 | 73560bc8 | balrog | |
3298 | 73560bc8 | balrog | omap_badwidth_write16(opaque, addr, value); |
3299 | 73560bc8 | balrog | } |
3300 | 73560bc8 | balrog | |
3301 | d60efc6b | Blue Swirl | static CPUReadMemoryFunc * const omap_mcbsp_readfn[] = { |
3302 | d8f699cb | balrog | omap_badwidth_read16, |
3303 | d8f699cb | balrog | omap_mcbsp_read, |
3304 | d8f699cb | balrog | omap_badwidth_read16, |
3305 | d8f699cb | balrog | }; |
3306 | d8f699cb | balrog | |
3307 | d60efc6b | Blue Swirl | static CPUWriteMemoryFunc * const omap_mcbsp_writefn[] = { |
3308 | d8f699cb | balrog | omap_badwidth_write16, |
3309 | 73560bc8 | balrog | omap_mcbsp_writeh, |
3310 | 73560bc8 | balrog | omap_mcbsp_writew, |
3311 | d8f699cb | balrog | }; |
3312 | d8f699cb | balrog | |
3313 | d8f699cb | balrog | static void omap_mcbsp_reset(struct omap_mcbsp_s *s) |
3314 | d8f699cb | balrog | { |
3315 | d8f699cb | balrog | memset(&s->spcr, 0, sizeof(s->spcr)); |
3316 | d8f699cb | balrog | memset(&s->rcr, 0, sizeof(s->rcr)); |
3317 | d8f699cb | balrog | memset(&s->xcr, 0, sizeof(s->xcr)); |
3318 | d8f699cb | balrog | s->srgr[0] = 0x0001; |
3319 | d8f699cb | balrog | s->srgr[1] = 0x2000; |
3320 | d8f699cb | balrog | memset(&s->mcr, 0, sizeof(s->mcr)); |
3321 | d8f699cb | balrog | memset(&s->pcr, 0, sizeof(s->pcr)); |
3322 | d8f699cb | balrog | memset(&s->rcer, 0, sizeof(s->rcer)); |
3323 | d8f699cb | balrog | memset(&s->xcer, 0, sizeof(s->xcer)); |
3324 | d8f699cb | balrog | s->tx_req = 0;
|
3325 | 73560bc8 | balrog | s->rx_req = 0;
|
3326 | d8f699cb | balrog | s->tx_rate = 0;
|
3327 | d8f699cb | balrog | s->rx_rate = 0;
|
3328 | 73560bc8 | balrog | qemu_del_timer(s->source_timer); |
3329 | 73560bc8 | balrog | qemu_del_timer(s->sink_timer); |
3330 | d8f699cb | balrog | } |
3331 | d8f699cb | balrog | |
3332 | c227f099 | Anthony Liguori | struct omap_mcbsp_s *omap_mcbsp_init(target_phys_addr_t base,
|
3333 | d8f699cb | balrog | qemu_irq *irq, qemu_irq *dma, omap_clk clk) |
3334 | d8f699cb | balrog | { |
3335 | d8f699cb | balrog | int iomemtype;
|
3336 | d8f699cb | balrog | struct omap_mcbsp_s *s = (struct omap_mcbsp_s *) |
3337 | d8f699cb | balrog | qemu_mallocz(sizeof(struct omap_mcbsp_s)); |
3338 | d8f699cb | balrog | |
3339 | d8f699cb | balrog | s->txirq = irq[0];
|
3340 | d8f699cb | balrog | s->rxirq = irq[1];
|
3341 | d8f699cb | balrog | s->txdrq = dma[0];
|
3342 | d8f699cb | balrog | s->rxdrq = dma[1];
|
3343 | 73560bc8 | balrog | s->sink_timer = qemu_new_timer(vm_clock, omap_mcbsp_sink_tick, s); |
3344 | 73560bc8 | balrog | s->source_timer = qemu_new_timer(vm_clock, omap_mcbsp_source_tick, s); |
3345 | d8f699cb | balrog | omap_mcbsp_reset(s); |
3346 | d8f699cb | balrog | |
3347 | 1eed09cb | Avi Kivity | iomemtype = cpu_register_io_memory(omap_mcbsp_readfn, |
3348 | d8f699cb | balrog | omap_mcbsp_writefn, s); |
3349 | 8da3ff18 | pbrook | cpu_register_physical_memory(base, 0x800, iomemtype);
|
3350 | d8f699cb | balrog | |
3351 | d8f699cb | balrog | return s;
|
3352 | d8f699cb | balrog | } |
3353 | d8f699cb | balrog | |
3354 | 9596ebb7 | pbrook | static void omap_mcbsp_i2s_swallow(void *opaque, int line, int level) |
3355 | d8f699cb | balrog | { |
3356 | d8f699cb | balrog | struct omap_mcbsp_s *s = (struct omap_mcbsp_s *) opaque; |
3357 | d8f699cb | balrog | |
3358 | 73560bc8 | balrog | if (s->rx_rate) {
|
3359 | 73560bc8 | balrog | s->rx_req = s->codec->in.len; |
3360 | 73560bc8 | balrog | omap_mcbsp_rx_newdata(s); |
3361 | 73560bc8 | balrog | } |
3362 | d8f699cb | balrog | } |
3363 | d8f699cb | balrog | |
3364 | 9596ebb7 | pbrook | static void omap_mcbsp_i2s_start(void *opaque, int line, int level) |
3365 | d8f699cb | balrog | { |
3366 | d8f699cb | balrog | struct omap_mcbsp_s *s = (struct omap_mcbsp_s *) opaque; |
3367 | d8f699cb | balrog | |
3368 | 73560bc8 | balrog | if (s->tx_rate) {
|
3369 | 73560bc8 | balrog | s->tx_req = s->codec->out.size; |
3370 | 73560bc8 | balrog | omap_mcbsp_tx_newdata(s); |
3371 | 73560bc8 | balrog | } |
3372 | d8f699cb | balrog | } |
3373 | d8f699cb | balrog | |
3374 | bc24a225 | Paul Brook | void omap_mcbsp_i2s_attach(struct omap_mcbsp_s *s, I2SCodec *slave) |
3375 | d8f699cb | balrog | { |
3376 | d8f699cb | balrog | s->codec = slave; |
3377 | d8f699cb | balrog | slave->rx_swallow = qemu_allocate_irqs(omap_mcbsp_i2s_swallow, s, 1)[0]; |
3378 | d8f699cb | balrog | slave->tx_start = qemu_allocate_irqs(omap_mcbsp_i2s_start, s, 1)[0]; |
3379 | d8f699cb | balrog | } |
3380 | d8f699cb | balrog | |
3381 | f9d43072 | balrog | /* LED Pulse Generators */
|
3382 | f9d43072 | balrog | struct omap_lpg_s {
|
3383 | f9d43072 | balrog | QEMUTimer *tm; |
3384 | f9d43072 | balrog | |
3385 | f9d43072 | balrog | uint8_t control; |
3386 | f9d43072 | balrog | uint8_t power; |
3387 | f9d43072 | balrog | int64_t on; |
3388 | f9d43072 | balrog | int64_t period; |
3389 | f9d43072 | balrog | int clk;
|
3390 | f9d43072 | balrog | int cycle;
|
3391 | f9d43072 | balrog | }; |
3392 | f9d43072 | balrog | |
3393 | f9d43072 | balrog | static void omap_lpg_tick(void *opaque) |
3394 | f9d43072 | balrog | { |
3395 | f9d43072 | balrog | struct omap_lpg_s *s = opaque;
|
3396 | f9d43072 | balrog | |
3397 | f9d43072 | balrog | if (s->cycle)
|
3398 | f9d43072 | balrog | qemu_mod_timer(s->tm, qemu_get_clock(rt_clock) + s->period - s->on); |
3399 | f9d43072 | balrog | else
|
3400 | f9d43072 | balrog | qemu_mod_timer(s->tm, qemu_get_clock(rt_clock) + s->on); |
3401 | f9d43072 | balrog | |
3402 | f9d43072 | balrog | s->cycle = !s->cycle; |
3403 | f9d43072 | balrog | printf("%s: LED is %s\n", __FUNCTION__, s->cycle ? "on" : "off"); |
3404 | f9d43072 | balrog | } |
3405 | f9d43072 | balrog | |
3406 | f9d43072 | balrog | static void omap_lpg_update(struct omap_lpg_s *s) |
3407 | f9d43072 | balrog | { |
3408 | f9d43072 | balrog | int64_t on, period = 1, ticks = 1000; |
3409 | f9d43072 | balrog | static const int per[8] = { 1, 2, 4, 8, 12, 16, 20, 24 }; |
3410 | f9d43072 | balrog | |
3411 | f9d43072 | balrog | if (~s->control & (1 << 6)) /* LPGRES */ |
3412 | f9d43072 | balrog | on = 0;
|
3413 | f9d43072 | balrog | else if (s->control & (1 << 7)) /* PERM_ON */ |
3414 | f9d43072 | balrog | on = period; |
3415 | f9d43072 | balrog | else {
|
3416 | f9d43072 | balrog | period = muldiv64(ticks, per[s->control & 7], /* PERCTRL */ |
3417 | f9d43072 | balrog | 256 / 32); |
3418 | f9d43072 | balrog | on = (s->clk && s->power) ? muldiv64(ticks, |
3419 | f9d43072 | balrog | per[(s->control >> 3) & 7], 256) : 0; /* ONCTRL */ |
3420 | f9d43072 | balrog | } |
3421 | f9d43072 | balrog | |
3422 | f9d43072 | balrog | qemu_del_timer(s->tm); |
3423 | f9d43072 | balrog | if (on == period && s->on < s->period)
|
3424 | f9d43072 | balrog | printf("%s: LED is on\n", __FUNCTION__);
|
3425 | f9d43072 | balrog | else if (on == 0 && s->on) |
3426 | f9d43072 | balrog | printf("%s: LED is off\n", __FUNCTION__);
|
3427 | f9d43072 | balrog | else if (on && (on != s->on || period != s->period)) { |
3428 | f9d43072 | balrog | s->cycle = 0;
|
3429 | f9d43072 | balrog | s->on = on; |
3430 | f9d43072 | balrog | s->period = period; |
3431 | f9d43072 | balrog | omap_lpg_tick(s); |
3432 | f9d43072 | balrog | return;
|
3433 | f9d43072 | balrog | } |
3434 | f9d43072 | balrog | |
3435 | f9d43072 | balrog | s->on = on; |
3436 | f9d43072 | balrog | s->period = period; |
3437 | f9d43072 | balrog | } |
3438 | f9d43072 | balrog | |
3439 | f9d43072 | balrog | static void omap_lpg_reset(struct omap_lpg_s *s) |
3440 | f9d43072 | balrog | { |
3441 | f9d43072 | balrog | s->control = 0x00;
|
3442 | f9d43072 | balrog | s->power = 0x00;
|
3443 | f9d43072 | balrog | s->clk = 1;
|
3444 | f9d43072 | balrog | omap_lpg_update(s); |
3445 | f9d43072 | balrog | } |
3446 | f9d43072 | balrog | |
3447 | c227f099 | Anthony Liguori | static uint32_t omap_lpg_read(void *opaque, target_phys_addr_t addr) |
3448 | f9d43072 | balrog | { |
3449 | f9d43072 | balrog | struct omap_lpg_s *s = (struct omap_lpg_s *) opaque; |
3450 | f9d43072 | balrog | int offset = addr & OMAP_MPUI_REG_MASK;
|
3451 | f9d43072 | balrog | |
3452 | f9d43072 | balrog | switch (offset) {
|
3453 | f9d43072 | balrog | case 0x00: /* LCR */ |
3454 | f9d43072 | balrog | return s->control;
|
3455 | f9d43072 | balrog | |
3456 | f9d43072 | balrog | case 0x04: /* PMR */ |
3457 | f9d43072 | balrog | return s->power;
|
3458 | f9d43072 | balrog | } |
3459 | f9d43072 | balrog | |
3460 | f9d43072 | balrog | OMAP_BAD_REG(addr); |
3461 | f9d43072 | balrog | return 0; |
3462 | f9d43072 | balrog | } |
3463 | f9d43072 | balrog | |
3464 | c227f099 | Anthony Liguori | static void omap_lpg_write(void *opaque, target_phys_addr_t addr, |
3465 | f9d43072 | balrog | uint32_t value) |
3466 | f9d43072 | balrog | { |
3467 | f9d43072 | balrog | struct omap_lpg_s *s = (struct omap_lpg_s *) opaque; |
3468 | f9d43072 | balrog | int offset = addr & OMAP_MPUI_REG_MASK;
|
3469 | f9d43072 | balrog | |
3470 | f9d43072 | balrog | switch (offset) {
|
3471 | f9d43072 | balrog | case 0x00: /* LCR */ |
3472 | f9d43072 | balrog | if (~value & (1 << 6)) /* LPGRES */ |
3473 | f9d43072 | balrog | omap_lpg_reset(s); |
3474 | f9d43072 | balrog | s->control = value & 0xff;
|
3475 | f9d43072 | balrog | omap_lpg_update(s); |
3476 | f9d43072 | balrog | return;
|
3477 | f9d43072 | balrog | |
3478 | f9d43072 | balrog | case 0x04: /* PMR */ |
3479 | f9d43072 | balrog | s->power = value & 0x01;
|
3480 | f9d43072 | balrog | omap_lpg_update(s); |
3481 | f9d43072 | balrog | return;
|
3482 | f9d43072 | balrog | |
3483 | f9d43072 | balrog | default:
|
3484 | f9d43072 | balrog | OMAP_BAD_REG(addr); |
3485 | f9d43072 | balrog | return;
|
3486 | f9d43072 | balrog | } |
3487 | f9d43072 | balrog | } |
3488 | f9d43072 | balrog | |
3489 | d60efc6b | Blue Swirl | static CPUReadMemoryFunc * const omap_lpg_readfn[] = { |
3490 | f9d43072 | balrog | omap_lpg_read, |
3491 | f9d43072 | balrog | omap_badwidth_read8, |
3492 | f9d43072 | balrog | omap_badwidth_read8, |
3493 | f9d43072 | balrog | }; |
3494 | f9d43072 | balrog | |
3495 | d60efc6b | Blue Swirl | static CPUWriteMemoryFunc * const omap_lpg_writefn[] = { |
3496 | f9d43072 | balrog | omap_lpg_write, |
3497 | f9d43072 | balrog | omap_badwidth_write8, |
3498 | f9d43072 | balrog | omap_badwidth_write8, |
3499 | f9d43072 | balrog | }; |
3500 | f9d43072 | balrog | |
3501 | f9d43072 | balrog | static void omap_lpg_clk_update(void *opaque, int line, int on) |
3502 | f9d43072 | balrog | { |
3503 | f9d43072 | balrog | struct omap_lpg_s *s = (struct omap_lpg_s *) opaque; |
3504 | f9d43072 | balrog | |
3505 | f9d43072 | balrog | s->clk = on; |
3506 | f9d43072 | balrog | omap_lpg_update(s); |
3507 | f9d43072 | balrog | } |
3508 | f9d43072 | balrog | |
3509 | c1ff227b | cmchao | static struct omap_lpg_s *omap_lpg_init(target_phys_addr_t base, omap_clk clk) |
3510 | f9d43072 | balrog | { |
3511 | f9d43072 | balrog | int iomemtype;
|
3512 | f9d43072 | balrog | struct omap_lpg_s *s = (struct omap_lpg_s *) |
3513 | f9d43072 | balrog | qemu_mallocz(sizeof(struct omap_lpg_s)); |
3514 | f9d43072 | balrog | |
3515 | f9d43072 | balrog | s->tm = qemu_new_timer(rt_clock, omap_lpg_tick, s); |
3516 | f9d43072 | balrog | |
3517 | f9d43072 | balrog | omap_lpg_reset(s); |
3518 | f9d43072 | balrog | |
3519 | 1eed09cb | Avi Kivity | iomemtype = cpu_register_io_memory(omap_lpg_readfn, |
3520 | f9d43072 | balrog | omap_lpg_writefn, s); |
3521 | 8da3ff18 | pbrook | cpu_register_physical_memory(base, 0x800, iomemtype);
|
3522 | f9d43072 | balrog | |
3523 | f9d43072 | balrog | omap_clk_adduser(clk, qemu_allocate_irqs(omap_lpg_clk_update, s, 1)[0]); |
3524 | f9d43072 | balrog | |
3525 | f9d43072 | balrog | return s;
|
3526 | f9d43072 | balrog | } |
3527 | f9d43072 | balrog | |
3528 | f9d43072 | balrog | /* MPUI Peripheral Bridge configuration */
|
3529 | c227f099 | Anthony Liguori | static uint32_t omap_mpui_io_read(void *opaque, target_phys_addr_t addr) |
3530 | f9d43072 | balrog | { |
3531 | f9d43072 | balrog | if (addr == OMAP_MPUI_BASE) /* CMR */ |
3532 | f9d43072 | balrog | return 0xfe4d; |
3533 | f9d43072 | balrog | |
3534 | f9d43072 | balrog | OMAP_BAD_REG(addr); |
3535 | f9d43072 | balrog | return 0; |
3536 | f9d43072 | balrog | } |
3537 | f9d43072 | balrog | |
3538 | d60efc6b | Blue Swirl | static CPUReadMemoryFunc * const omap_mpui_io_readfn[] = { |
3539 | f9d43072 | balrog | omap_badwidth_read16, |
3540 | f9d43072 | balrog | omap_mpui_io_read, |
3541 | f9d43072 | balrog | omap_badwidth_read16, |
3542 | f9d43072 | balrog | }; |
3543 | f9d43072 | balrog | |
3544 | d60efc6b | Blue Swirl | static CPUWriteMemoryFunc * const omap_mpui_io_writefn[] = { |
3545 | f9d43072 | balrog | omap_badwidth_write16, |
3546 | f9d43072 | balrog | omap_badwidth_write16, |
3547 | f9d43072 | balrog | omap_badwidth_write16, |
3548 | f9d43072 | balrog | }; |
3549 | f9d43072 | balrog | |
3550 | f9d43072 | balrog | static void omap_setup_mpui_io(struct omap_mpu_state_s *mpu) |
3551 | f9d43072 | balrog | { |
3552 | 1eed09cb | Avi Kivity | int iomemtype = cpu_register_io_memory(omap_mpui_io_readfn,
|
3553 | f9d43072 | balrog | omap_mpui_io_writefn, mpu); |
3554 | f9d43072 | balrog | cpu_register_physical_memory(OMAP_MPUI_BASE, 0x7fff, iomemtype);
|
3555 | f9d43072 | balrog | } |
3556 | f9d43072 | balrog | |
3557 | c3d2689d | balrog | /* General chip reset */
|
3558 | 827df9f3 | balrog | static void omap1_mpu_reset(void *opaque) |
3559 | c3d2689d | balrog | { |
3560 | c3d2689d | balrog | struct omap_mpu_state_s *mpu = (struct omap_mpu_state_s *) opaque; |
3561 | c3d2689d | balrog | |
3562 | c3d2689d | balrog | omap_inth_reset(mpu->ih[0]);
|
3563 | c3d2689d | balrog | omap_inth_reset(mpu->ih[1]);
|
3564 | c3d2689d | balrog | omap_dma_reset(mpu->dma); |
3565 | c3d2689d | balrog | omap_mpu_timer_reset(mpu->timer[0]);
|
3566 | c3d2689d | balrog | omap_mpu_timer_reset(mpu->timer[1]);
|
3567 | c3d2689d | balrog | omap_mpu_timer_reset(mpu->timer[2]);
|
3568 | c3d2689d | balrog | omap_wd_timer_reset(mpu->wdt); |
3569 | c3d2689d | balrog | omap_os_timer_reset(mpu->os_timer); |
3570 | c3d2689d | balrog | omap_lcdc_reset(mpu->lcd); |
3571 | c3d2689d | balrog | omap_ulpd_pm_reset(mpu); |
3572 | c3d2689d | balrog | omap_pin_cfg_reset(mpu); |
3573 | c3d2689d | balrog | omap_mpui_reset(mpu); |
3574 | c3d2689d | balrog | omap_tipb_bridge_reset(mpu->private_tipb); |
3575 | c3d2689d | balrog | omap_tipb_bridge_reset(mpu->public_tipb); |
3576 | c3d2689d | balrog | omap_dpll_reset(&mpu->dpll[0]);
|
3577 | c3d2689d | balrog | omap_dpll_reset(&mpu->dpll[1]);
|
3578 | c3d2689d | balrog | omap_dpll_reset(&mpu->dpll[2]);
|
3579 | d951f6ff | balrog | omap_uart_reset(mpu->uart[0]);
|
3580 | d951f6ff | balrog | omap_uart_reset(mpu->uart[1]);
|
3581 | d951f6ff | balrog | omap_uart_reset(mpu->uart[2]);
|
3582 | b30bb3a2 | balrog | omap_mmc_reset(mpu->mmc); |
3583 | fe71e81a | balrog | omap_mpuio_reset(mpu->mpuio); |
3584 | 64330148 | balrog | omap_gpio_reset(mpu->gpio); |
3585 | d951f6ff | balrog | omap_uwire_reset(mpu->microwire); |
3586 | 66450b15 | balrog | omap_pwl_reset(mpu); |
3587 | 4a2c8ac2 | balrog | omap_pwt_reset(mpu); |
3588 | 827df9f3 | balrog | omap_i2c_reset(mpu->i2c[0]);
|
3589 | 5c1c390f | balrog | omap_rtc_reset(mpu->rtc); |
3590 | d8f699cb | balrog | omap_mcbsp_reset(mpu->mcbsp1); |
3591 | d8f699cb | balrog | omap_mcbsp_reset(mpu->mcbsp2); |
3592 | d8f699cb | balrog | omap_mcbsp_reset(mpu->mcbsp3); |
3593 | f9d43072 | balrog | omap_lpg_reset(mpu->led[0]);
|
3594 | f9d43072 | balrog | omap_lpg_reset(mpu->led[1]);
|
3595 | 8ef6367e | balrog | omap_clkm_reset(mpu); |
3596 | c3d2689d | balrog | cpu_reset(mpu->env); |
3597 | c3d2689d | balrog | } |
3598 | c3d2689d | balrog | |
3599 | cf965d24 | balrog | static const struct omap_map_s { |
3600 | c227f099 | Anthony Liguori | target_phys_addr_t phys_dsp; |
3601 | c227f099 | Anthony Liguori | target_phys_addr_t phys_mpu; |
3602 | cf965d24 | balrog | uint32_t size; |
3603 | cf965d24 | balrog | const char *name; |
3604 | cf965d24 | balrog | } omap15xx_dsp_mm[] = { |
3605 | cf965d24 | balrog | /* Strobe 0 */
|
3606 | cf965d24 | balrog | { 0xe1010000, 0xfffb0000, 0x800, "UART1 BT" }, /* CS0 */ |
3607 | cf965d24 | balrog | { 0xe1010800, 0xfffb0800, 0x800, "UART2 COM" }, /* CS1 */ |
3608 | cf965d24 | balrog | { 0xe1011800, 0xfffb1800, 0x800, "McBSP1 audio" }, /* CS3 */ |
3609 | cf965d24 | balrog | { 0xe1012000, 0xfffb2000, 0x800, "MCSI2 communication" }, /* CS4 */ |
3610 | cf965d24 | balrog | { 0xe1012800, 0xfffb2800, 0x800, "MCSI1 BT u-Law" }, /* CS5 */ |
3611 | cf965d24 | balrog | { 0xe1013000, 0xfffb3000, 0x800, "uWire" }, /* CS6 */ |
3612 | cf965d24 | balrog | { 0xe1013800, 0xfffb3800, 0x800, "I^2C" }, /* CS7 */ |
3613 | cf965d24 | balrog | { 0xe1014000, 0xfffb4000, 0x800, "USB W2FC" }, /* CS8 */ |
3614 | cf965d24 | balrog | { 0xe1014800, 0xfffb4800, 0x800, "RTC" }, /* CS9 */ |
3615 | cf965d24 | balrog | { 0xe1015000, 0xfffb5000, 0x800, "MPUIO" }, /* CS10 */ |
3616 | cf965d24 | balrog | { 0xe1015800, 0xfffb5800, 0x800, "PWL" }, /* CS11 */ |
3617 | cf965d24 | balrog | { 0xe1016000, 0xfffb6000, 0x800, "PWT" }, /* CS12 */ |
3618 | cf965d24 | balrog | { 0xe1017000, 0xfffb7000, 0x800, "McBSP3" }, /* CS14 */ |
3619 | cf965d24 | balrog | { 0xe1017800, 0xfffb7800, 0x800, "MMC" }, /* CS15 */ |
3620 | cf965d24 | balrog | { 0xe1019000, 0xfffb9000, 0x800, "32-kHz timer" }, /* CS18 */ |
3621 | cf965d24 | balrog | { 0xe1019800, 0xfffb9800, 0x800, "UART3" }, /* CS19 */ |
3622 | cf965d24 | balrog | { 0xe101c800, 0xfffbc800, 0x800, "TIPB switches" }, /* CS25 */ |
3623 | cf965d24 | balrog | /* Strobe 1 */
|
3624 | cf965d24 | balrog | { 0xe101e000, 0xfffce000, 0x800, "GPIOs" }, /* CS28 */ |
3625 | cf965d24 | balrog | |
3626 | cf965d24 | balrog | { 0 }
|
3627 | cf965d24 | balrog | }; |
3628 | cf965d24 | balrog | |
3629 | cf965d24 | balrog | static void omap_setup_dsp_mapping(const struct omap_map_s *map) |
3630 | cf965d24 | balrog | { |
3631 | cf965d24 | balrog | int io;
|
3632 | cf965d24 | balrog | |
3633 | cf965d24 | balrog | for (; map->phys_dsp; map ++) {
|
3634 | cf965d24 | balrog | io = cpu_get_physical_page_desc(map->phys_mpu); |
3635 | cf965d24 | balrog | |
3636 | cf965d24 | balrog | cpu_register_physical_memory(map->phys_dsp, map->size, io); |
3637 | cf965d24 | balrog | } |
3638 | cf965d24 | balrog | } |
3639 | cf965d24 | balrog | |
3640 | 827df9f3 | balrog | void omap_mpu_wakeup(void *opaque, int irq, int req) |
3641 | c3d2689d | balrog | { |
3642 | c3d2689d | balrog | struct omap_mpu_state_s *mpu = (struct omap_mpu_state_s *) opaque; |
3643 | c3d2689d | balrog | |
3644 | fe71e81a | balrog | if (mpu->env->halted)
|
3645 | fe71e81a | balrog | cpu_interrupt(mpu->env, CPU_INTERRUPT_EXITTB); |
3646 | c3d2689d | balrog | } |
3647 | c3d2689d | balrog | |
3648 | 827df9f3 | balrog | static const struct dma_irq_map omap1_dma_irq_map[] = { |
3649 | 089b7c0a | balrog | { 0, OMAP_INT_DMA_CH0_6 },
|
3650 | 089b7c0a | balrog | { 0, OMAP_INT_DMA_CH1_7 },
|
3651 | 089b7c0a | balrog | { 0, OMAP_INT_DMA_CH2_8 },
|
3652 | 089b7c0a | balrog | { 0, OMAP_INT_DMA_CH3 },
|
3653 | 089b7c0a | balrog | { 0, OMAP_INT_DMA_CH4 },
|
3654 | 089b7c0a | balrog | { 0, OMAP_INT_DMA_CH5 },
|
3655 | 089b7c0a | balrog | { 1, OMAP_INT_1610_DMA_CH6 },
|
3656 | 089b7c0a | balrog | { 1, OMAP_INT_1610_DMA_CH7 },
|
3657 | 089b7c0a | balrog | { 1, OMAP_INT_1610_DMA_CH8 },
|
3658 | 089b7c0a | balrog | { 1, OMAP_INT_1610_DMA_CH9 },
|
3659 | 089b7c0a | balrog | { 1, OMAP_INT_1610_DMA_CH10 },
|
3660 | 089b7c0a | balrog | { 1, OMAP_INT_1610_DMA_CH11 },
|
3661 | 089b7c0a | balrog | { 1, OMAP_INT_1610_DMA_CH12 },
|
3662 | 089b7c0a | balrog | { 1, OMAP_INT_1610_DMA_CH13 },
|
3663 | 089b7c0a | balrog | { 1, OMAP_INT_1610_DMA_CH14 },
|
3664 | 089b7c0a | balrog | { 1, OMAP_INT_1610_DMA_CH15 }
|
3665 | 089b7c0a | balrog | }; |
3666 | 089b7c0a | balrog | |
3667 | b4e3104b | balrog | /* DMA ports for OMAP1 */
|
3668 | b4e3104b | balrog | static int omap_validate_emiff_addr(struct omap_mpu_state_s *s, |
3669 | c227f099 | Anthony Liguori | target_phys_addr_t addr) |
3670 | b4e3104b | balrog | { |
3671 | b4e3104b | balrog | return addr >= OMAP_EMIFF_BASE && addr < OMAP_EMIFF_BASE + s->sdram_size;
|
3672 | b4e3104b | balrog | } |
3673 | b4e3104b | balrog | |
3674 | b4e3104b | balrog | static int omap_validate_emifs_addr(struct omap_mpu_state_s *s, |
3675 | c227f099 | Anthony Liguori | target_phys_addr_t addr) |
3676 | b4e3104b | balrog | { |
3677 | b4e3104b | balrog | return addr >= OMAP_EMIFS_BASE && addr < OMAP_EMIFF_BASE;
|
3678 | b4e3104b | balrog | } |
3679 | b4e3104b | balrog | |
3680 | b4e3104b | balrog | static int omap_validate_imif_addr(struct omap_mpu_state_s *s, |
3681 | c227f099 | Anthony Liguori | target_phys_addr_t addr) |
3682 | b4e3104b | balrog | { |
3683 | b4e3104b | balrog | return addr >= OMAP_IMIF_BASE && addr < OMAP_IMIF_BASE + s->sram_size;
|
3684 | b4e3104b | balrog | } |
3685 | b4e3104b | balrog | |
3686 | b4e3104b | balrog | static int omap_validate_tipb_addr(struct omap_mpu_state_s *s, |
3687 | c227f099 | Anthony Liguori | target_phys_addr_t addr) |
3688 | b4e3104b | balrog | { |
3689 | b4e3104b | balrog | return addr >= 0xfffb0000 && addr < 0xffff0000; |
3690 | b4e3104b | balrog | } |
3691 | b4e3104b | balrog | |
3692 | b4e3104b | balrog | static int omap_validate_local_addr(struct omap_mpu_state_s *s, |
3693 | c227f099 | Anthony Liguori | target_phys_addr_t addr) |
3694 | b4e3104b | balrog | { |
3695 | b4e3104b | balrog | return addr >= OMAP_LOCALBUS_BASE && addr < OMAP_LOCALBUS_BASE + 0x1000000; |
3696 | b4e3104b | balrog | } |
3697 | b4e3104b | balrog | |
3698 | b4e3104b | balrog | static int omap_validate_tipb_mpui_addr(struct omap_mpu_state_s *s, |
3699 | c227f099 | Anthony Liguori | target_phys_addr_t addr) |
3700 | b4e3104b | balrog | { |
3701 | b4e3104b | balrog | return addr >= 0xe1010000 && addr < 0xe1020004; |
3702 | b4e3104b | balrog | } |
3703 | b4e3104b | balrog | |
3704 | c3d2689d | balrog | struct omap_mpu_state_s *omap310_mpu_init(unsigned long sdram_size, |
3705 | 3023f332 | aliguori | const char *core) |
3706 | c3d2689d | balrog | { |
3707 | 089b7c0a | balrog | int i;
|
3708 | c3d2689d | balrog | struct omap_mpu_state_s *s = (struct omap_mpu_state_s *) |
3709 | c3d2689d | balrog | qemu_mallocz(sizeof(struct omap_mpu_state_s)); |
3710 | c227f099 | Anthony Liguori | ram_addr_t imif_base, emiff_base; |
3711 | 106627d0 | balrog | qemu_irq *cpu_irq; |
3712 | 089b7c0a | balrog | qemu_irq dma_irqs[6];
|
3713 | 751c6a17 | Gerd Hoffmann | DriveInfo *dinfo; |
3714 | 106627d0 | balrog | |
3715 | aaed909a | bellard | if (!core)
|
3716 | aaed909a | bellard | core = "ti925t";
|
3717 | c3d2689d | balrog | |
3718 | c3d2689d | balrog | /* Core */
|
3719 | c3d2689d | balrog | s->mpu_model = omap310; |
3720 | aaed909a | bellard | s->env = cpu_init(core); |
3721 | aaed909a | bellard | if (!s->env) {
|
3722 | aaed909a | bellard | fprintf(stderr, "Unable to find CPU definition\n");
|
3723 | aaed909a | bellard | exit(1);
|
3724 | aaed909a | bellard | } |
3725 | c3d2689d | balrog | s->sdram_size = sdram_size; |
3726 | c3d2689d | balrog | s->sram_size = OMAP15XX_SRAM_SIZE; |
3727 | c3d2689d | balrog | |
3728 | fe71e81a | balrog | s->wakeup = qemu_allocate_irqs(omap_mpu_wakeup, s, 1)[0]; |
3729 | fe71e81a | balrog | |
3730 | c3d2689d | balrog | /* Clocks */
|
3731 | c3d2689d | balrog | omap_clk_init(s); |
3732 | c3d2689d | balrog | |
3733 | c3d2689d | balrog | /* Memory-mapped stuff */
|
3734 | c3d2689d | balrog | cpu_register_physical_memory(OMAP_EMIFF_BASE, s->sdram_size, |
3735 | 1724f049 | Alex Williamson | (emiff_base = qemu_ram_alloc(NULL, "omap1.dram", |
3736 | 1724f049 | Alex Williamson | s->sdram_size)) | IO_MEM_RAM); |
3737 | c3d2689d | balrog | cpu_register_physical_memory(OMAP_IMIF_BASE, s->sram_size, |
3738 | 1724f049 | Alex Williamson | (imif_base = qemu_ram_alloc(NULL, "omap1.sram", |
3739 | 1724f049 | Alex Williamson | s->sram_size)) | IO_MEM_RAM); |
3740 | c3d2689d | balrog | |
3741 | c3d2689d | balrog | omap_clkm_init(0xfffece00, 0xe1008000, s); |
3742 | c3d2689d | balrog | |
3743 | 106627d0 | balrog | cpu_irq = arm_pic_init_cpu(s->env); |
3744 | 827df9f3 | balrog | s->ih[0] = omap_inth_init(0xfffecb00, 0x100, 1, &s->irq[0], |
3745 | 106627d0 | balrog | cpu_irq[ARM_PIC_CPU_IRQ], cpu_irq[ARM_PIC_CPU_FIQ], |
3746 | c3d2689d | balrog | omap_findclk(s, "arminth_ck"));
|
3747 | 827df9f3 | balrog | s->ih[1] = omap_inth_init(0xfffe0000, 0x800, 1, &s->irq[1], |
3748 | 7f132a21 | cmchao | omap_inth_get_pin(s->ih[0], OMAP_INT_15XX_IH2_IRQ),
|
3749 | 7f132a21 | cmchao | NULL, omap_findclk(s, "arminth_ck")); |
3750 | c3d2689d | balrog | |
3751 | 089b7c0a | balrog | for (i = 0; i < 6; i ++) |
3752 | 827df9f3 | balrog | dma_irqs[i] = |
3753 | 827df9f3 | balrog | s->irq[omap1_dma_irq_map[i].ih][omap1_dma_irq_map[i].intr]; |
3754 | 089b7c0a | balrog | s->dma = omap_dma_init(0xfffed800, dma_irqs, s->irq[0][OMAP_INT_DMA_LCD], |
3755 | 089b7c0a | balrog | s, omap_findclk(s, "dma_ck"), omap_dma_3_1);
|
3756 | 089b7c0a | balrog | |
3757 | c3d2689d | balrog | s->port[emiff ].addr_valid = omap_validate_emiff_addr; |
3758 | c3d2689d | balrog | s->port[emifs ].addr_valid = omap_validate_emifs_addr; |
3759 | c3d2689d | balrog | s->port[imif ].addr_valid = omap_validate_imif_addr; |
3760 | c3d2689d | balrog | s->port[tipb ].addr_valid = omap_validate_tipb_addr; |
3761 | c3d2689d | balrog | s->port[local ].addr_valid = omap_validate_local_addr; |
3762 | c3d2689d | balrog | s->port[tipb_mpui].addr_valid = omap_validate_tipb_mpui_addr; |
3763 | c3d2689d | balrog | |
3764 | afbb5194 | balrog | /* Register SDRAM and SRAM DMA ports for fast transfers. */
|
3765 | afbb5194 | balrog | soc_dma_port_add_mem_ram(s->dma, |
3766 | afbb5194 | balrog | emiff_base, OMAP_EMIFF_BASE, s->sdram_size); |
3767 | afbb5194 | balrog | soc_dma_port_add_mem_ram(s->dma, |
3768 | afbb5194 | balrog | imif_base, OMAP_IMIF_BASE, s->sram_size); |
3769 | afbb5194 | balrog | |
3770 | c3d2689d | balrog | s->timer[0] = omap_mpu_timer_init(0xfffec500, |
3771 | c3d2689d | balrog | s->irq[0][OMAP_INT_TIMER1],
|
3772 | c3d2689d | balrog | omap_findclk(s, "mputim_ck"));
|
3773 | c3d2689d | balrog | s->timer[1] = omap_mpu_timer_init(0xfffec600, |
3774 | c3d2689d | balrog | s->irq[0][OMAP_INT_TIMER2],
|
3775 | c3d2689d | balrog | omap_findclk(s, "mputim_ck"));
|
3776 | c3d2689d | balrog | s->timer[2] = omap_mpu_timer_init(0xfffec700, |
3777 | c3d2689d | balrog | s->irq[0][OMAP_INT_TIMER3],
|
3778 | c3d2689d | balrog | omap_findclk(s, "mputim_ck"));
|
3779 | c3d2689d | balrog | |
3780 | c3d2689d | balrog | s->wdt = omap_wd_timer_init(0xfffec800,
|
3781 | c3d2689d | balrog | s->irq[0][OMAP_INT_WD_TIMER],
|
3782 | c3d2689d | balrog | omap_findclk(s, "armwdt_ck"));
|
3783 | c3d2689d | balrog | |
3784 | c3d2689d | balrog | s->os_timer = omap_os_timer_init(0xfffb9000,
|
3785 | c3d2689d | balrog | s->irq[1][OMAP_INT_OS_TIMER],
|
3786 | c3d2689d | balrog | omap_findclk(s, "clk32-kHz"));
|
3787 | c3d2689d | balrog | |
3788 | c3d2689d | balrog | s->lcd = omap_lcdc_init(0xfffec000, s->irq[0][OMAP_INT_LCD_CTRL], |
3789 | 3023f332 | aliguori | omap_dma_get_lcdch(s->dma), imif_base, emiff_base, |
3790 | c3d2689d | balrog | omap_findclk(s, "lcd_ck"));
|
3791 | c3d2689d | balrog | |
3792 | c3d2689d | balrog | omap_ulpd_pm_init(0xfffe0800, s);
|
3793 | c3d2689d | balrog | omap_pin_cfg_init(0xfffe1000, s);
|
3794 | c3d2689d | balrog | omap_id_init(s); |
3795 | c3d2689d | balrog | |
3796 | c3d2689d | balrog | omap_mpui_init(0xfffec900, s);
|
3797 | c3d2689d | balrog | |
3798 | c3d2689d | balrog | s->private_tipb = omap_tipb_bridge_init(0xfffeca00,
|
3799 | c3d2689d | balrog | s->irq[0][OMAP_INT_BRIDGE_PRIV],
|
3800 | c3d2689d | balrog | omap_findclk(s, "tipb_ck"));
|
3801 | c3d2689d | balrog | s->public_tipb = omap_tipb_bridge_init(0xfffed300,
|
3802 | c3d2689d | balrog | s->irq[0][OMAP_INT_BRIDGE_PUB],
|
3803 | c3d2689d | balrog | omap_findclk(s, "tipb_ck"));
|
3804 | c3d2689d | balrog | |
3805 | c3d2689d | balrog | omap_tcmi_init(0xfffecc00, s);
|
3806 | c3d2689d | balrog | |
3807 | d951f6ff | balrog | s->uart[0] = omap_uart_init(0xfffb0000, s->irq[1][OMAP_INT_UART1], |
3808 | c3d2689d | balrog | omap_findclk(s, "uart1_ck"),
|
3809 | 827df9f3 | balrog | omap_findclk(s, "uart1_ck"),
|
3810 | 827df9f3 | balrog | s->drq[OMAP_DMA_UART1_TX], s->drq[OMAP_DMA_UART1_RX], |
3811 | c3d2689d | balrog | serial_hds[0]);
|
3812 | d951f6ff | balrog | s->uart[1] = omap_uart_init(0xfffb0800, s->irq[1][OMAP_INT_UART2], |
3813 | c3d2689d | balrog | omap_findclk(s, "uart2_ck"),
|
3814 | 827df9f3 | balrog | omap_findclk(s, "uart2_ck"),
|
3815 | 827df9f3 | balrog | s->drq[OMAP_DMA_UART2_TX], s->drq[OMAP_DMA_UART2_RX], |
3816 | b9d38e95 | Blue Swirl | serial_hds[0] ? serial_hds[1] : NULL); |
3817 | 13643323 | balrog | s->uart[2] = omap_uart_init(0xfffb9800, s->irq[0][OMAP_INT_UART3], |
3818 | c3d2689d | balrog | omap_findclk(s, "uart3_ck"),
|
3819 | 827df9f3 | balrog | omap_findclk(s, "uart3_ck"),
|
3820 | 827df9f3 | balrog | s->drq[OMAP_DMA_UART3_TX], s->drq[OMAP_DMA_UART3_RX], |
3821 | b9d38e95 | Blue Swirl | serial_hds[0] && serial_hds[1] ? serial_hds[2] : NULL); |
3822 | c3d2689d | balrog | |
3823 | c3d2689d | balrog | omap_dpll_init(&s->dpll[0], 0xfffecf00, omap_findclk(s, "dpll1")); |
3824 | c3d2689d | balrog | omap_dpll_init(&s->dpll[1], 0xfffed000, omap_findclk(s, "dpll2")); |
3825 | c3d2689d | balrog | omap_dpll_init(&s->dpll[2], 0xfffed100, omap_findclk(s, "dpll3")); |
3826 | c3d2689d | balrog | |
3827 | 751c6a17 | Gerd Hoffmann | dinfo = drive_get(IF_SD, 0, 0); |
3828 | 751c6a17 | Gerd Hoffmann | if (!dinfo) {
|
3829 | e4bcb14c | ths | fprintf(stderr, "qemu: missing SecureDigital device\n");
|
3830 | e4bcb14c | ths | exit(1);
|
3831 | e4bcb14c | ths | } |
3832 | 751c6a17 | Gerd Hoffmann | s->mmc = omap_mmc_init(0xfffb7800, dinfo->bdrv,
|
3833 | 9d413d1d | balrog | s->irq[1][OMAP_INT_OQN], &s->drq[OMAP_DMA_MMC_TX],
|
3834 | 9d413d1d | balrog | omap_findclk(s, "mmc_ck"));
|
3835 | b30bb3a2 | balrog | |
3836 | fe71e81a | balrog | s->mpuio = omap_mpuio_init(0xfffb5000,
|
3837 | fe71e81a | balrog | s->irq[1][OMAP_INT_KEYBOARD], s->irq[1][OMAP_INT_MPUIO], |
3838 | fe71e81a | balrog | s->wakeup, omap_findclk(s, "clk32-kHz"));
|
3839 | fe71e81a | balrog | |
3840 | 3efda49d | balrog | s->gpio = omap_gpio_init(0xfffce000, s->irq[0][OMAP_INT_GPIO_BANK1], |
3841 | 66450b15 | balrog | omap_findclk(s, "arm_gpio_ck"));
|
3842 | 64330148 | balrog | |
3843 | d951f6ff | balrog | s->microwire = omap_uwire_init(0xfffb3000, &s->irq[1][OMAP_INT_uWireTX], |
3844 | d951f6ff | balrog | s->drq[OMAP_DMA_UWIRE_TX], omap_findclk(s, "mpuper_ck"));
|
3845 | d951f6ff | balrog | |
3846 | d8f699cb | balrog | omap_pwl_init(0xfffb5800, s, omap_findclk(s, "armxor_ck")); |
3847 | d8f699cb | balrog | omap_pwt_init(0xfffb6000, s, omap_findclk(s, "armxor_ck")); |
3848 | 66450b15 | balrog | |
3849 | 827df9f3 | balrog | s->i2c[0] = omap_i2c_init(0xfffb3800, s->irq[1][OMAP_INT_I2C], |
3850 | 4a2c8ac2 | balrog | &s->drq[OMAP_DMA_I2C_RX], omap_findclk(s, "mpuper_ck"));
|
3851 | 4a2c8ac2 | balrog | |
3852 | 5c1c390f | balrog | s->rtc = omap_rtc_init(0xfffb4800, &s->irq[1][OMAP_INT_RTC_TIMER], |
3853 | 5c1c390f | balrog | omap_findclk(s, "clk32-kHz"));
|
3854 | 02645926 | balrog | |
3855 | d8f699cb | balrog | s->mcbsp1 = omap_mcbsp_init(0xfffb1800, &s->irq[1][OMAP_INT_McBSP1TX], |
3856 | d8f699cb | balrog | &s->drq[OMAP_DMA_MCBSP1_TX], omap_findclk(s, "dspxor_ck"));
|
3857 | d8f699cb | balrog | s->mcbsp2 = omap_mcbsp_init(0xfffb1000, &s->irq[0][OMAP_INT_310_McBSP2_TX], |
3858 | d8f699cb | balrog | &s->drq[OMAP_DMA_MCBSP2_TX], omap_findclk(s, "mpuper_ck"));
|
3859 | d8f699cb | balrog | s->mcbsp3 = omap_mcbsp_init(0xfffb7000, &s->irq[1][OMAP_INT_McBSP3TX], |
3860 | d8f699cb | balrog | &s->drq[OMAP_DMA_MCBSP3_TX], omap_findclk(s, "dspxor_ck"));
|
3861 | d8f699cb | balrog | |
3862 | f9d43072 | balrog | s->led[0] = omap_lpg_init(0xfffbd000, omap_findclk(s, "clk32-kHz")); |
3863 | f9d43072 | balrog | s->led[1] = omap_lpg_init(0xfffbd800, omap_findclk(s, "clk32-kHz")); |
3864 | f9d43072 | balrog | |
3865 | 02645926 | balrog | /* Register mappings not currenlty implemented:
|
3866 | 02645926 | balrog | * MCSI2 Comm fffb2000 - fffb27ff (not mapped on OMAP310)
|
3867 | 02645926 | balrog | * MCSI1 Bluetooth fffb2800 - fffb2fff (not mapped on OMAP310)
|
3868 | 02645926 | balrog | * USB W2FC fffb4000 - fffb47ff
|
3869 | 02645926 | balrog | * Camera Interface fffb6800 - fffb6fff
|
3870 | 02645926 | balrog | * USB Host fffba000 - fffba7ff
|
3871 | 02645926 | balrog | * FAC fffba800 - fffbafff
|
3872 | 02645926 | balrog | * HDQ/1-Wire fffbc000 - fffbc7ff
|
3873 | b854bc19 | balrog | * TIPB switches fffbc800 - fffbcfff
|
3874 | 02645926 | balrog | * Mailbox fffcf000 - fffcf7ff
|
3875 | 02645926 | balrog | * Local bus IF fffec100 - fffec1ff
|
3876 | 02645926 | balrog | * Local bus MMU fffec200 - fffec2ff
|
3877 | 02645926 | balrog | * DSP MMU fffed200 - fffed2ff
|
3878 | 02645926 | balrog | */
|
3879 | 02645926 | balrog | |
3880 | cf965d24 | balrog | omap_setup_dsp_mapping(omap15xx_dsp_mm); |
3881 | f9d43072 | balrog | omap_setup_mpui_io(s); |
3882 | cf965d24 | balrog | |
3883 | a08d4367 | Jan Kiszka | qemu_register_reset(omap1_mpu_reset, s); |
3884 | c3d2689d | balrog | |
3885 | c3d2689d | balrog | return s;
|
3886 | c3d2689d | balrog | } |