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/*
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 * Tiny Code Generator for QEMU
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 *
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 * Copyright (c) 2008 Fabrice Bellard
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 *
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 * Permission is hereby granted, free of charge, to any person obtaining a copy
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 * of this software and associated documentation files (the "Software"), to deal
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 * in the Software without restriction, including without limitation the rights
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 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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 * copies of the Software, and to permit persons to whom the Software is
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 * furnished to do so, subject to the following conditions:
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 *
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 * The above copyright notice and this permission notice shall be included in
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 * all copies or substantial portions of the Software.
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 *
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 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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 * THE SOFTWARE.
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 */
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#include "tcg.h"
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int gen_new_label(void);
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static inline void tcg_gen_op1_i32(int opc, TCGv_i32 arg1)
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{
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    *gen_opc_ptr++ = opc;
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    *gen_opparam_ptr++ = GET_TCGV_I32(arg1);
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}
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static inline void tcg_gen_op1_i64(int opc, TCGv_i64 arg1)
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{
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    *gen_opc_ptr++ = opc;
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    *gen_opparam_ptr++ = GET_TCGV_I64(arg1);
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}
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static inline void tcg_gen_op1i(int opc, TCGArg arg1)
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{
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    *gen_opc_ptr++ = opc;
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    *gen_opparam_ptr++ = arg1;
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}
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static inline void tcg_gen_op2_i32(int opc, TCGv_i32 arg1, TCGv_i32 arg2)
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{
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    *gen_opc_ptr++ = opc;
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    *gen_opparam_ptr++ = GET_TCGV_I32(arg1);
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    *gen_opparam_ptr++ = GET_TCGV_I32(arg2);
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}
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static inline void tcg_gen_op2_i64(int opc, TCGv_i64 arg1, TCGv_i64 arg2)
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{
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    *gen_opc_ptr++ = opc;
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    *gen_opparam_ptr++ = GET_TCGV_I64(arg1);
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    *gen_opparam_ptr++ = GET_TCGV_I64(arg2);
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}
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static inline void tcg_gen_op2i_i32(int opc, TCGv_i32 arg1, TCGArg arg2)
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{
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    *gen_opc_ptr++ = opc;
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    *gen_opparam_ptr++ = GET_TCGV_I32(arg1);
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    *gen_opparam_ptr++ = arg2;
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}
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static inline void tcg_gen_op2i_i64(int opc, TCGv_i64 arg1, TCGArg arg2)
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{
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    *gen_opc_ptr++ = opc;
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    *gen_opparam_ptr++ = GET_TCGV_I64(arg1);
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    *gen_opparam_ptr++ = arg2;
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}
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static inline void tcg_gen_op2ii(int opc, TCGArg arg1, TCGArg arg2)
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{
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    *gen_opc_ptr++ = opc;
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    *gen_opparam_ptr++ = arg1;
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    *gen_opparam_ptr++ = arg2;
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}
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static inline void tcg_gen_op3_i32(int opc, TCGv_i32 arg1, TCGv_i32 arg2,
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                                   TCGv_i32 arg3)
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{
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    *gen_opc_ptr++ = opc;
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    *gen_opparam_ptr++ = GET_TCGV_I32(arg1);
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    *gen_opparam_ptr++ = GET_TCGV_I32(arg2);
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    *gen_opparam_ptr++ = GET_TCGV_I32(arg3);
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}
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static inline void tcg_gen_op3_i64(int opc, TCGv_i64 arg1, TCGv_i64 arg2,
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                                   TCGv_i64 arg3)
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{
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    *gen_opc_ptr++ = opc;
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    *gen_opparam_ptr++ = GET_TCGV_I64(arg1);
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    *gen_opparam_ptr++ = GET_TCGV_I64(arg2);
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    *gen_opparam_ptr++ = GET_TCGV_I64(arg3);
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}
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static inline void tcg_gen_op3i_i32(int opc, TCGv_i32 arg1, TCGv_i32 arg2,
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                                    TCGArg arg3)
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{
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    *gen_opc_ptr++ = opc;
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    *gen_opparam_ptr++ = GET_TCGV_I32(arg1);
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    *gen_opparam_ptr++ = GET_TCGV_I32(arg2);
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    *gen_opparam_ptr++ = arg3;
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}
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static inline void tcg_gen_op3i_i64(int opc, TCGv_i64 arg1, TCGv_i64 arg2,
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                                    TCGArg arg3)
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{
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    *gen_opc_ptr++ = opc;
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    *gen_opparam_ptr++ = GET_TCGV_I64(arg1);
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    *gen_opparam_ptr++ = GET_TCGV_I64(arg2);
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    *gen_opparam_ptr++ = arg3;
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}
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static inline void tcg_gen_ldst_op_i32(int opc, TCGv_i32 val, TCGv_ptr base,
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                                       TCGArg offset)
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{
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    *gen_opc_ptr++ = opc;
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    *gen_opparam_ptr++ = GET_TCGV_I32(val);
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    *gen_opparam_ptr++ = GET_TCGV_PTR(base);
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    *gen_opparam_ptr++ = offset;
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}
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static inline void tcg_gen_ldst_op_i64(int opc, TCGv_i64 val, TCGv_ptr base,
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                                       TCGArg offset)
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{
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    *gen_opc_ptr++ = opc;
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    *gen_opparam_ptr++ = GET_TCGV_I64(val);
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    *gen_opparam_ptr++ = GET_TCGV_PTR(base);
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    *gen_opparam_ptr++ = offset;
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}
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static inline void tcg_gen_qemu_ldst_op_i64_i32(int opc, TCGv_i64 val, TCGv_i32 addr,
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                                                TCGArg mem_index)
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{
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    *gen_opc_ptr++ = opc;
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    *gen_opparam_ptr++ = GET_TCGV_I64(val);
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    *gen_opparam_ptr++ = GET_TCGV_I32(addr);
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    *gen_opparam_ptr++ = mem_index;
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}
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static inline void tcg_gen_qemu_ldst_op_i64_i64(int opc, TCGv_i64 val, TCGv_i64 addr,
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                                                TCGArg mem_index)
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{
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    *gen_opc_ptr++ = opc;
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    *gen_opparam_ptr++ = GET_TCGV_I64(val);
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    *gen_opparam_ptr++ = GET_TCGV_I64(addr);
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    *gen_opparam_ptr++ = mem_index;
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}
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static inline void tcg_gen_op4_i32(int opc, TCGv_i32 arg1, TCGv_i32 arg2,
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                                   TCGv_i32 arg3, TCGv_i32 arg4)
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{
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    *gen_opc_ptr++ = opc;
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    *gen_opparam_ptr++ = GET_TCGV_I32(arg1);
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    *gen_opparam_ptr++ = GET_TCGV_I32(arg2);
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    *gen_opparam_ptr++ = GET_TCGV_I32(arg3);
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    *gen_opparam_ptr++ = GET_TCGV_I32(arg4);
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}
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static inline void tcg_gen_op4_i64(int opc, TCGv_i64 arg1, TCGv_i64 arg2,
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                                   TCGv_i64 arg3, TCGv_i64 arg4)
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{
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    *gen_opc_ptr++ = opc;
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    *gen_opparam_ptr++ = GET_TCGV_I64(arg1);
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    *gen_opparam_ptr++ = GET_TCGV_I64(arg2);
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    *gen_opparam_ptr++ = GET_TCGV_I64(arg3);
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    *gen_opparam_ptr++ = GET_TCGV_I64(arg4);
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}
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static inline void tcg_gen_op4i_i32(int opc, TCGv_i32 arg1, TCGv_i32 arg2,
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                                    TCGv_i32 arg3, TCGArg arg4)
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{
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    *gen_opc_ptr++ = opc;
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    *gen_opparam_ptr++ = GET_TCGV_I32(arg1);
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    *gen_opparam_ptr++ = GET_TCGV_I32(arg2);
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    *gen_opparam_ptr++ = GET_TCGV_I32(arg3);
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    *gen_opparam_ptr++ = arg4;
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}
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static inline void tcg_gen_op4i_i64(int opc, TCGv_i64 arg1, TCGv_i64 arg2,
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                                    TCGv_i64 arg3, TCGArg arg4)
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{
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    *gen_opc_ptr++ = opc;
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    *gen_opparam_ptr++ = GET_TCGV_I64(arg1);
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    *gen_opparam_ptr++ = GET_TCGV_I64(arg2);
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    *gen_opparam_ptr++ = GET_TCGV_I64(arg3);
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    *gen_opparam_ptr++ = arg4;
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}
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static inline void tcg_gen_op4ii_i32(int opc, TCGv_i32 arg1, TCGv_i32 arg2,
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                                     TCGArg arg3, TCGArg arg4)
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{
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    *gen_opc_ptr++ = opc;
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    *gen_opparam_ptr++ = GET_TCGV_I32(arg1);
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    *gen_opparam_ptr++ = GET_TCGV_I32(arg2);
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    *gen_opparam_ptr++ = arg3;
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    *gen_opparam_ptr++ = arg4;
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}
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static inline void tcg_gen_op4ii_i64(int opc, TCGv_i64 arg1, TCGv_i64 arg2,
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                                     TCGArg arg3, TCGArg arg4)
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{
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    *gen_opc_ptr++ = opc;
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    *gen_opparam_ptr++ = GET_TCGV_I64(arg1);
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    *gen_opparam_ptr++ = GET_TCGV_I64(arg2);
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    *gen_opparam_ptr++ = arg3;
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    *gen_opparam_ptr++ = arg4;
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}
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static inline void tcg_gen_op5_i32(int opc, TCGv_i32 arg1, TCGv_i32 arg2,
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                                   TCGv_i32 arg3, TCGv_i32 arg4, TCGv_i32 arg5)
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{
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    *gen_opc_ptr++ = opc;
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    *gen_opparam_ptr++ = GET_TCGV_I32(arg1);
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    *gen_opparam_ptr++ = GET_TCGV_I32(arg2);
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    *gen_opparam_ptr++ = GET_TCGV_I32(arg3);
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    *gen_opparam_ptr++ = GET_TCGV_I32(arg4);
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    *gen_opparam_ptr++ = GET_TCGV_I32(arg5);
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}
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static inline void tcg_gen_op5_i64(int opc, TCGv_i64 arg1, TCGv_i64 arg2,
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                                   TCGv_i64 arg3, TCGv_i64 arg4, TCGv_i64 arg5)
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{
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    *gen_opc_ptr++ = opc;
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    *gen_opparam_ptr++ = GET_TCGV_I64(arg1);
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    *gen_opparam_ptr++ = GET_TCGV_I64(arg2);
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    *gen_opparam_ptr++ = GET_TCGV_I64(arg3);
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    *gen_opparam_ptr++ = GET_TCGV_I64(arg4);
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    *gen_opparam_ptr++ = GET_TCGV_I64(arg5);
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}
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static inline void tcg_gen_op5i_i32(int opc, TCGv_i32 arg1, TCGv_i32 arg2,
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                                    TCGv_i32 arg3, TCGv_i32 arg4, TCGArg arg5)
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{
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    *gen_opc_ptr++ = opc;
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    *gen_opparam_ptr++ = GET_TCGV_I32(arg1);
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    *gen_opparam_ptr++ = GET_TCGV_I32(arg2);
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    *gen_opparam_ptr++ = GET_TCGV_I32(arg3);
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    *gen_opparam_ptr++ = GET_TCGV_I32(arg4);
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    *gen_opparam_ptr++ = arg5;
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}
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static inline void tcg_gen_op5i_i64(int opc, TCGv_i64 arg1, TCGv_i64 arg2,
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                                    TCGv_i64 arg3, TCGv_i64 arg4, TCGArg arg5)
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{
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    *gen_opc_ptr++ = opc;
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    *gen_opparam_ptr++ = GET_TCGV_I64(arg1);
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    *gen_opparam_ptr++ = GET_TCGV_I64(arg2);
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    *gen_opparam_ptr++ = GET_TCGV_I64(arg3);
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    *gen_opparam_ptr++ = GET_TCGV_I64(arg4);
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    *gen_opparam_ptr++ = arg5;
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}
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static inline void tcg_gen_op6_i32(int opc, TCGv_i32 arg1, TCGv_i32 arg2,
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                                   TCGv_i32 arg3, TCGv_i32 arg4, TCGv_i32 arg5,
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                                   TCGv_i32 arg6)
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{
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    *gen_opc_ptr++ = opc;
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    *gen_opparam_ptr++ = GET_TCGV_I32(arg1);
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    *gen_opparam_ptr++ = GET_TCGV_I32(arg2);
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    *gen_opparam_ptr++ = GET_TCGV_I32(arg3);
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    *gen_opparam_ptr++ = GET_TCGV_I32(arg4);
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    *gen_opparam_ptr++ = GET_TCGV_I32(arg5);
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    *gen_opparam_ptr++ = GET_TCGV_I32(arg6);
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}
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static inline void tcg_gen_op6_i64(int opc, TCGv_i64 arg1, TCGv_i64 arg2,
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                                   TCGv_i64 arg3, TCGv_i64 arg4, TCGv_i64 arg5,
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                                   TCGv_i64 arg6)
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{
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    *gen_opc_ptr++ = opc;
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    *gen_opparam_ptr++ = GET_TCGV_I64(arg1);
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    *gen_opparam_ptr++ = GET_TCGV_I64(arg2);
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    *gen_opparam_ptr++ = GET_TCGV_I64(arg3);
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    *gen_opparam_ptr++ = GET_TCGV_I64(arg4);
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    *gen_opparam_ptr++ = GET_TCGV_I64(arg5);
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    *gen_opparam_ptr++ = GET_TCGV_I64(arg6);
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}
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static inline void tcg_gen_op6ii_i32(int opc, TCGv_i32 arg1, TCGv_i32 arg2,
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                                     TCGv_i32 arg3, TCGv_i32 arg4, TCGArg arg5,
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                                     TCGArg arg6)
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{
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    *gen_opc_ptr++ = opc;
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    *gen_opparam_ptr++ = GET_TCGV_I32(arg1);
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    *gen_opparam_ptr++ = GET_TCGV_I32(arg2);
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    *gen_opparam_ptr++ = GET_TCGV_I32(arg3);
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    *gen_opparam_ptr++ = GET_TCGV_I32(arg4);
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    *gen_opparam_ptr++ = arg5;
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    *gen_opparam_ptr++ = arg6;
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}
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static inline void tcg_gen_op6ii_i64(int opc, TCGv_i64 arg1, TCGv_i64 arg2,
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                                     TCGv_i64 arg3, TCGv_i64 arg4, TCGArg arg5,
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                                     TCGArg arg6)
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{
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    *gen_opc_ptr++ = opc;
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    *gen_opparam_ptr++ = GET_TCGV_I64(arg1);
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    *gen_opparam_ptr++ = GET_TCGV_I64(arg2);
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    *gen_opparam_ptr++ = GET_TCGV_I64(arg3);
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    *gen_opparam_ptr++ = GET_TCGV_I64(arg4);
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    *gen_opparam_ptr++ = arg5;
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    *gen_opparam_ptr++ = arg6;
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}
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static inline void gen_set_label(int n)
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{
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    tcg_gen_op1i(INDEX_op_set_label, n);
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}
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static inline void tcg_gen_br(int label)
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{
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    tcg_gen_op1i(INDEX_op_br, label);
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}
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static inline void tcg_gen_mov_i32(TCGv_i32 ret, TCGv_i32 arg)
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{
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    if (!TCGV_EQUAL_I32(ret, arg))
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        tcg_gen_op2_i32(INDEX_op_mov_i32, ret, arg);
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}
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static inline void tcg_gen_movi_i32(TCGv_i32 ret, int32_t arg)
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{
327 a7812ae4 pbrook
    tcg_gen_op2i_i32(INDEX_op_movi_i32, ret, arg);
328 c896fe29 bellard
}
329 c896fe29 bellard
330 c896fe29 bellard
/* helper calls */
331 a7812ae4 pbrook
static inline void tcg_gen_helperN(void *func, int flags, int sizemask,
332 a7812ae4 pbrook
                                   TCGArg ret, int nargs, TCGArg *args)
333 a7812ae4 pbrook
{
334 a7812ae4 pbrook
    TCGv_ptr fn;
335 a7812ae4 pbrook
    fn = tcg_const_ptr((tcg_target_long)func);
336 a7812ae4 pbrook
    tcg_gen_callN(&tcg_ctx, fn, flags, sizemask, ret,
337 a7812ae4 pbrook
                  nargs, args);
338 a7812ae4 pbrook
    tcg_temp_free_ptr(fn);
339 a7812ae4 pbrook
}
340 c896fe29 bellard
341 a7812ae4 pbrook
/* FIXME: Should this be pure?  */
342 a7812ae4 pbrook
static inline void tcg_gen_helper64(void *func, TCGv_i64 ret,
343 a7812ae4 pbrook
                                    TCGv_i64 a, TCGv_i64 b)
344 c896fe29 bellard
{
345 a7812ae4 pbrook
    TCGv_ptr fn;
346 a7812ae4 pbrook
    TCGArg args[2];
347 a7812ae4 pbrook
    fn = tcg_const_ptr((tcg_target_long)func);
348 a7812ae4 pbrook
    args[0] = GET_TCGV_I64(a);
349 a7812ae4 pbrook
    args[1] = GET_TCGV_I64(b);
350 a7812ae4 pbrook
    tcg_gen_callN(&tcg_ctx, fn, 0, 7, GET_TCGV_I64(ret), 2, args);
351 a7812ae4 pbrook
    tcg_temp_free_ptr(fn);
352 f8422f52 blueswir1
}
353 f8422f52 blueswir1
354 c896fe29 bellard
/* 32 bit ops */
355 c896fe29 bellard
356 a7812ae4 pbrook
static inline void tcg_gen_ld8u_i32(TCGv_i32 ret, TCGv_ptr arg2, tcg_target_long offset)
357 c896fe29 bellard
{
358 a7812ae4 pbrook
    tcg_gen_ldst_op_i32(INDEX_op_ld8u_i32, ret, arg2, offset);
359 c896fe29 bellard
}
360 c896fe29 bellard
361 a7812ae4 pbrook
static inline void tcg_gen_ld8s_i32(TCGv_i32 ret, TCGv_ptr arg2, tcg_target_long offset)
362 c896fe29 bellard
{
363 a7812ae4 pbrook
    tcg_gen_ldst_op_i32(INDEX_op_ld8s_i32, ret, arg2, offset);
364 c896fe29 bellard
}
365 c896fe29 bellard
366 a7812ae4 pbrook
static inline void tcg_gen_ld16u_i32(TCGv_i32 ret, TCGv_ptr arg2, tcg_target_long offset)
367 c896fe29 bellard
{
368 a7812ae4 pbrook
    tcg_gen_ldst_op_i32(INDEX_op_ld16u_i32, ret, arg2, offset);
369 c896fe29 bellard
}
370 c896fe29 bellard
371 a7812ae4 pbrook
static inline void tcg_gen_ld16s_i32(TCGv_i32 ret, TCGv_ptr arg2, tcg_target_long offset)
372 c896fe29 bellard
{
373 a7812ae4 pbrook
    tcg_gen_ldst_op_i32(INDEX_op_ld16s_i32, ret, arg2, offset);
374 c896fe29 bellard
}
375 c896fe29 bellard
376 a7812ae4 pbrook
static inline void tcg_gen_ld_i32(TCGv_i32 ret, TCGv_ptr arg2, tcg_target_long offset)
377 c896fe29 bellard
{
378 a7812ae4 pbrook
    tcg_gen_ldst_op_i32(INDEX_op_ld_i32, ret, arg2, offset);
379 c896fe29 bellard
}
380 c896fe29 bellard
381 a7812ae4 pbrook
static inline void tcg_gen_st8_i32(TCGv_i32 arg1, TCGv_ptr arg2, tcg_target_long offset)
382 c896fe29 bellard
{
383 a7812ae4 pbrook
    tcg_gen_ldst_op_i32(INDEX_op_st8_i32, arg1, arg2, offset);
384 c896fe29 bellard
}
385 c896fe29 bellard
386 a7812ae4 pbrook
static inline void tcg_gen_st16_i32(TCGv_i32 arg1, TCGv_ptr arg2, tcg_target_long offset)
387 c896fe29 bellard
{
388 a7812ae4 pbrook
    tcg_gen_ldst_op_i32(INDEX_op_st16_i32, arg1, arg2, offset);
389 c896fe29 bellard
}
390 c896fe29 bellard
391 a7812ae4 pbrook
static inline void tcg_gen_st_i32(TCGv_i32 arg1, TCGv_ptr arg2, tcg_target_long offset)
392 c896fe29 bellard
{
393 a7812ae4 pbrook
    tcg_gen_ldst_op_i32(INDEX_op_st_i32, arg1, arg2, offset);
394 c896fe29 bellard
}
395 c896fe29 bellard
396 a7812ae4 pbrook
static inline void tcg_gen_add_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2)
397 c896fe29 bellard
{
398 a7812ae4 pbrook
    tcg_gen_op3_i32(INDEX_op_add_i32, ret, arg1, arg2);
399 c896fe29 bellard
}
400 c896fe29 bellard
401 a7812ae4 pbrook
static inline void tcg_gen_addi_i32(TCGv_i32 ret, TCGv_i32 arg1, int32_t arg2)
402 c896fe29 bellard
{
403 7089442c blueswir1
    /* some cases can be optimized here */
404 7089442c blueswir1
    if (arg2 == 0) {
405 7089442c blueswir1
        tcg_gen_mov_i32(ret, arg1);
406 7089442c blueswir1
    } else {
407 a7812ae4 pbrook
        TCGv_i32 t0 = tcg_const_i32(arg2);
408 e8996ee0 bellard
        tcg_gen_add_i32(ret, arg1, t0);
409 a7812ae4 pbrook
        tcg_temp_free_i32(t0);
410 7089442c blueswir1
    }
411 c896fe29 bellard
}
412 c896fe29 bellard
413 a7812ae4 pbrook
static inline void tcg_gen_sub_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2)
414 c896fe29 bellard
{
415 a7812ae4 pbrook
    tcg_gen_op3_i32(INDEX_op_sub_i32, ret, arg1, arg2);
416 c896fe29 bellard
}
417 c896fe29 bellard
418 a7812ae4 pbrook
static inline void tcg_gen_subfi_i32(TCGv_i32 ret, int32_t arg1, TCGv_i32 arg2)
419 0045734a aurel32
{
420 a7812ae4 pbrook
    TCGv_i32 t0 = tcg_const_i32(arg1);
421 0045734a aurel32
    tcg_gen_sub_i32(ret, t0, arg2);
422 a7812ae4 pbrook
    tcg_temp_free_i32(t0);
423 0045734a aurel32
}
424 0045734a aurel32
425 a7812ae4 pbrook
static inline void tcg_gen_subi_i32(TCGv_i32 ret, TCGv_i32 arg1, int32_t arg2)
426 c896fe29 bellard
{
427 7089442c blueswir1
    /* some cases can be optimized here */
428 7089442c blueswir1
    if (arg2 == 0) {
429 7089442c blueswir1
        tcg_gen_mov_i32(ret, arg1);
430 7089442c blueswir1
    } else {
431 a7812ae4 pbrook
        TCGv_i32 t0 = tcg_const_i32(arg2);
432 e8996ee0 bellard
        tcg_gen_sub_i32(ret, arg1, t0);
433 a7812ae4 pbrook
        tcg_temp_free_i32(t0);
434 7089442c blueswir1
    }
435 c896fe29 bellard
}
436 c896fe29 bellard
437 a7812ae4 pbrook
static inline void tcg_gen_and_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2)
438 c896fe29 bellard
{
439 7fc81051 aurel32
    if (TCGV_EQUAL_I32(arg1, arg2)) {
440 7fc81051 aurel32
        tcg_gen_mov_i32(ret, arg1);
441 7fc81051 aurel32
    } else {
442 7fc81051 aurel32
        tcg_gen_op3_i32(INDEX_op_and_i32, ret, arg1, arg2);
443 7fc81051 aurel32
    }
444 c896fe29 bellard
}
445 c896fe29 bellard
446 a7812ae4 pbrook
static inline void tcg_gen_andi_i32(TCGv_i32 ret, TCGv_i32 arg1, int32_t arg2)
447 c896fe29 bellard
{
448 c896fe29 bellard
    /* some cases can be optimized here */
449 c896fe29 bellard
    if (arg2 == 0) {
450 c896fe29 bellard
        tcg_gen_movi_i32(ret, 0);
451 c896fe29 bellard
    } else if (arg2 == 0xffffffff) {
452 c896fe29 bellard
        tcg_gen_mov_i32(ret, arg1);
453 c896fe29 bellard
    } else {
454 a7812ae4 pbrook
        TCGv_i32 t0 = tcg_const_i32(arg2);
455 e8996ee0 bellard
        tcg_gen_and_i32(ret, arg1, t0);
456 a7812ae4 pbrook
        tcg_temp_free_i32(t0);
457 c896fe29 bellard
    }
458 c896fe29 bellard
}
459 c896fe29 bellard
460 a7812ae4 pbrook
static inline void tcg_gen_or_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2)
461 c896fe29 bellard
{
462 7fc81051 aurel32
    if (TCGV_EQUAL_I32(arg1, arg2)) {
463 7fc81051 aurel32
        tcg_gen_mov_i32(ret, arg1);
464 7fc81051 aurel32
    } else {
465 7fc81051 aurel32
        tcg_gen_op3_i32(INDEX_op_or_i32, ret, arg1, arg2);
466 7fc81051 aurel32
    }
467 c896fe29 bellard
}
468 c896fe29 bellard
469 a7812ae4 pbrook
static inline void tcg_gen_ori_i32(TCGv_i32 ret, TCGv_i32 arg1, int32_t arg2)
470 c896fe29 bellard
{
471 c896fe29 bellard
    /* some cases can be optimized here */
472 c896fe29 bellard
    if (arg2 == 0xffffffff) {
473 7089442c blueswir1
        tcg_gen_movi_i32(ret, 0xffffffff);
474 c896fe29 bellard
    } else if (arg2 == 0) {
475 c896fe29 bellard
        tcg_gen_mov_i32(ret, arg1);
476 c896fe29 bellard
    } else {
477 a7812ae4 pbrook
        TCGv_i32 t0 = tcg_const_i32(arg2);
478 e8996ee0 bellard
        tcg_gen_or_i32(ret, arg1, t0);
479 a7812ae4 pbrook
        tcg_temp_free_i32(t0);
480 c896fe29 bellard
    }
481 c896fe29 bellard
}
482 c896fe29 bellard
483 a7812ae4 pbrook
static inline void tcg_gen_xor_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2)
484 c896fe29 bellard
{
485 7fc81051 aurel32
    if (TCGV_EQUAL_I32(arg1, arg2)) {
486 7fc81051 aurel32
        tcg_gen_movi_i32(ret, 0);
487 7fc81051 aurel32
    } else {
488 7fc81051 aurel32
        tcg_gen_op3_i32(INDEX_op_xor_i32, ret, arg1, arg2);
489 7fc81051 aurel32
    }
490 c896fe29 bellard
}
491 c896fe29 bellard
492 a7812ae4 pbrook
static inline void tcg_gen_xori_i32(TCGv_i32 ret, TCGv_i32 arg1, int32_t arg2)
493 c896fe29 bellard
{
494 c896fe29 bellard
    /* some cases can be optimized here */
495 c896fe29 bellard
    if (arg2 == 0) {
496 c896fe29 bellard
        tcg_gen_mov_i32(ret, arg1);
497 c896fe29 bellard
    } else {
498 a7812ae4 pbrook
        TCGv_i32 t0 = tcg_const_i32(arg2);
499 e8996ee0 bellard
        tcg_gen_xor_i32(ret, arg1, t0);
500 a7812ae4 pbrook
        tcg_temp_free_i32(t0);
501 c896fe29 bellard
    }
502 c896fe29 bellard
}
503 c896fe29 bellard
504 a7812ae4 pbrook
static inline void tcg_gen_shl_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2)
505 c896fe29 bellard
{
506 a7812ae4 pbrook
    tcg_gen_op3_i32(INDEX_op_shl_i32, ret, arg1, arg2);
507 c896fe29 bellard
}
508 c896fe29 bellard
509 a7812ae4 pbrook
static inline void tcg_gen_shli_i32(TCGv_i32 ret, TCGv_i32 arg1, int32_t arg2)
510 c896fe29 bellard
{
511 34151a20 bellard
    if (arg2 == 0) {
512 34151a20 bellard
        tcg_gen_mov_i32(ret, arg1);
513 34151a20 bellard
    } else {
514 a7812ae4 pbrook
        TCGv_i32 t0 = tcg_const_i32(arg2);
515 e8996ee0 bellard
        tcg_gen_shl_i32(ret, arg1, t0);
516 a7812ae4 pbrook
        tcg_temp_free_i32(t0);
517 34151a20 bellard
    }
518 c896fe29 bellard
}
519 c896fe29 bellard
520 a7812ae4 pbrook
static inline void tcg_gen_shr_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2)
521 c896fe29 bellard
{
522 a7812ae4 pbrook
    tcg_gen_op3_i32(INDEX_op_shr_i32, ret, arg1, arg2);
523 c896fe29 bellard
}
524 c896fe29 bellard
525 a7812ae4 pbrook
static inline void tcg_gen_shri_i32(TCGv_i32 ret, TCGv_i32 arg1, int32_t arg2)
526 c896fe29 bellard
{
527 34151a20 bellard
    if (arg2 == 0) {
528 34151a20 bellard
        tcg_gen_mov_i32(ret, arg1);
529 34151a20 bellard
    } else {
530 a7812ae4 pbrook
        TCGv_i32 t0 = tcg_const_i32(arg2);
531 e8996ee0 bellard
        tcg_gen_shr_i32(ret, arg1, t0);
532 a7812ae4 pbrook
        tcg_temp_free_i32(t0);
533 34151a20 bellard
    }
534 c896fe29 bellard
}
535 c896fe29 bellard
536 a7812ae4 pbrook
static inline void tcg_gen_sar_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2)
537 c896fe29 bellard
{
538 a7812ae4 pbrook
    tcg_gen_op3_i32(INDEX_op_sar_i32, ret, arg1, arg2);
539 c896fe29 bellard
}
540 c896fe29 bellard
541 a7812ae4 pbrook
static inline void tcg_gen_sari_i32(TCGv_i32 ret, TCGv_i32 arg1, int32_t arg2)
542 c896fe29 bellard
{
543 34151a20 bellard
    if (arg2 == 0) {
544 34151a20 bellard
        tcg_gen_mov_i32(ret, arg1);
545 34151a20 bellard
    } else {
546 a7812ae4 pbrook
        TCGv_i32 t0 = tcg_const_i32(arg2);
547 e8996ee0 bellard
        tcg_gen_sar_i32(ret, arg1, t0);
548 a7812ae4 pbrook
        tcg_temp_free_i32(t0);
549 34151a20 bellard
    }
550 c896fe29 bellard
}
551 c896fe29 bellard
552 a7812ae4 pbrook
static inline void tcg_gen_brcond_i32(int cond, TCGv_i32 arg1, TCGv_i32 arg2,
553 c896fe29 bellard
                                      int label_index)
554 c896fe29 bellard
{
555 a7812ae4 pbrook
    tcg_gen_op4ii_i32(INDEX_op_brcond_i32, arg1, arg2, cond, label_index);
556 c896fe29 bellard
}
557 c896fe29 bellard
558 a7812ae4 pbrook
static inline void tcg_gen_brcondi_i32(int cond, TCGv_i32 arg1, int32_t arg2,
559 cb63669a pbrook
                                       int label_index)
560 cb63669a pbrook
{
561 a7812ae4 pbrook
    TCGv_i32 t0 = tcg_const_i32(arg2);
562 cb63669a pbrook
    tcg_gen_brcond_i32(cond, arg1, t0, label_index);
563 a7812ae4 pbrook
    tcg_temp_free_i32(t0);
564 cb63669a pbrook
}
565 cb63669a pbrook
566 a7812ae4 pbrook
static inline void tcg_gen_mul_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2)
567 c896fe29 bellard
{
568 a7812ae4 pbrook
    tcg_gen_op3_i32(INDEX_op_mul_i32, ret, arg1, arg2);
569 c896fe29 bellard
}
570 c896fe29 bellard
571 a7812ae4 pbrook
static inline void tcg_gen_muli_i32(TCGv_i32 ret, TCGv_i32 arg1, int32_t arg2)
572 f730fd27 ths
{
573 a7812ae4 pbrook
    TCGv_i32 t0 = tcg_const_i32(arg2);
574 e8996ee0 bellard
    tcg_gen_mul_i32(ret, arg1, t0);
575 a7812ae4 pbrook
    tcg_temp_free_i32(t0);
576 f730fd27 ths
}
577 f730fd27 ths
578 c896fe29 bellard
#ifdef TCG_TARGET_HAS_div_i32
579 a7812ae4 pbrook
static inline void tcg_gen_div_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2)
580 c896fe29 bellard
{
581 a7812ae4 pbrook
    tcg_gen_op3_i32(INDEX_op_div_i32, ret, arg1, arg2);
582 c896fe29 bellard
}
583 c896fe29 bellard
584 a7812ae4 pbrook
static inline void tcg_gen_rem_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2)
585 c896fe29 bellard
{
586 a7812ae4 pbrook
    tcg_gen_op3_i32(INDEX_op_rem_i32, ret, arg1, arg2);
587 c896fe29 bellard
}
588 c896fe29 bellard
589 a7812ae4 pbrook
static inline void tcg_gen_divu_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2)
590 c896fe29 bellard
{
591 a7812ae4 pbrook
    tcg_gen_op3_i32(INDEX_op_divu_i32, ret, arg1, arg2);
592 c896fe29 bellard
}
593 c896fe29 bellard
594 a7812ae4 pbrook
static inline void tcg_gen_remu_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2)
595 c896fe29 bellard
{
596 a7812ae4 pbrook
    tcg_gen_op3_i32(INDEX_op_remu_i32, ret, arg1, arg2);
597 c896fe29 bellard
}
598 c896fe29 bellard
#else
599 a7812ae4 pbrook
static inline void tcg_gen_div_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2)
600 c896fe29 bellard
{
601 a7812ae4 pbrook
    TCGv_i32 t0;
602 a7812ae4 pbrook
    t0 = tcg_temp_new_i32();
603 c896fe29 bellard
    tcg_gen_sari_i32(t0, arg1, 31);
604 a7812ae4 pbrook
    tcg_gen_op5_i32(INDEX_op_div2_i32, ret, t0, arg1, t0, arg2);
605 a7812ae4 pbrook
    tcg_temp_free_i32(t0);
606 c896fe29 bellard
}
607 c896fe29 bellard
608 a7812ae4 pbrook
static inline void tcg_gen_rem_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2)
609 c896fe29 bellard
{
610 a7812ae4 pbrook
    TCGv_i32 t0;
611 a7812ae4 pbrook
    t0 = tcg_temp_new_i32();
612 c896fe29 bellard
    tcg_gen_sari_i32(t0, arg1, 31);
613 a7812ae4 pbrook
    tcg_gen_op5_i32(INDEX_op_div2_i32, t0, ret, arg1, t0, arg2);
614 a7812ae4 pbrook
    tcg_temp_free_i32(t0);
615 c896fe29 bellard
}
616 c896fe29 bellard
617 a7812ae4 pbrook
static inline void tcg_gen_divu_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2)
618 c896fe29 bellard
{
619 a7812ae4 pbrook
    TCGv_i32 t0;
620 a7812ae4 pbrook
    t0 = tcg_temp_new_i32();
621 c896fe29 bellard
    tcg_gen_movi_i32(t0, 0);
622 a7812ae4 pbrook
    tcg_gen_op5_i32(INDEX_op_divu2_i32, ret, t0, arg1, t0, arg2);
623 a7812ae4 pbrook
    tcg_temp_free_i32(t0);
624 c896fe29 bellard
}
625 c896fe29 bellard
626 a7812ae4 pbrook
static inline void tcg_gen_remu_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2)
627 c896fe29 bellard
{
628 a7812ae4 pbrook
    TCGv_i32 t0;
629 a7812ae4 pbrook
    t0 = tcg_temp_new_i32();
630 c896fe29 bellard
    tcg_gen_movi_i32(t0, 0);
631 a7812ae4 pbrook
    tcg_gen_op5_i32(INDEX_op_divu2_i32, t0, ret, arg1, t0, arg2);
632 a7812ae4 pbrook
    tcg_temp_free_i32(t0);
633 c896fe29 bellard
}
634 c896fe29 bellard
#endif
635 c896fe29 bellard
636 c896fe29 bellard
#if TCG_TARGET_REG_BITS == 32
637 c896fe29 bellard
638 a7812ae4 pbrook
static inline void tcg_gen_mov_i64(TCGv_i64 ret, TCGv_i64 arg)
639 c896fe29 bellard
{
640 fe75bcf7 aurel32
    if (!TCGV_EQUAL_I64(ret, arg)) {
641 a7812ae4 pbrook
        tcg_gen_mov_i32(TCGV_LOW(ret), TCGV_LOW(arg));
642 4d07272d blueswir1
        tcg_gen_mov_i32(TCGV_HIGH(ret), TCGV_HIGH(arg));
643 4d07272d blueswir1
    }
644 c896fe29 bellard
}
645 c896fe29 bellard
646 a7812ae4 pbrook
static inline void tcg_gen_movi_i64(TCGv_i64 ret, int64_t arg)
647 c896fe29 bellard
{
648 a7812ae4 pbrook
    tcg_gen_movi_i32(TCGV_LOW(ret), arg);
649 ac56dd48 pbrook
    tcg_gen_movi_i32(TCGV_HIGH(ret), arg >> 32);
650 c896fe29 bellard
}
651 c896fe29 bellard
652 a7812ae4 pbrook
static inline void tcg_gen_ld8u_i64(TCGv_i64 ret, TCGv_ptr arg2,
653 a7812ae4 pbrook
                                    tcg_target_long offset)
654 c896fe29 bellard
{
655 a7812ae4 pbrook
    tcg_gen_ld8u_i32(TCGV_LOW(ret), arg2, offset);
656 ac56dd48 pbrook
    tcg_gen_movi_i32(TCGV_HIGH(ret), 0);
657 c896fe29 bellard
}
658 c896fe29 bellard
659 a7812ae4 pbrook
static inline void tcg_gen_ld8s_i64(TCGv_i64 ret, TCGv_ptr arg2,
660 a7812ae4 pbrook
                                    tcg_target_long offset)
661 c896fe29 bellard
{
662 a7812ae4 pbrook
    tcg_gen_ld8s_i32(TCGV_LOW(ret), arg2, offset);
663 a7812ae4 pbrook
    tcg_gen_sari_i32(TCGV_HIGH(ret), TCGV_HIGH(ret), 31);
664 c896fe29 bellard
}
665 c896fe29 bellard
666 a7812ae4 pbrook
static inline void tcg_gen_ld16u_i64(TCGv_i64 ret, TCGv_ptr arg2,
667 a7812ae4 pbrook
                                     tcg_target_long offset)
668 c896fe29 bellard
{
669 a747723b aurel32
    tcg_gen_ld16u_i32(TCGV_LOW(ret), arg2, offset);
670 ac56dd48 pbrook
    tcg_gen_movi_i32(TCGV_HIGH(ret), 0);
671 c896fe29 bellard
}
672 c896fe29 bellard
673 a7812ae4 pbrook
static inline void tcg_gen_ld16s_i64(TCGv_i64 ret, TCGv_ptr arg2,
674 a7812ae4 pbrook
                                     tcg_target_long offset)
675 c896fe29 bellard
{
676 a7812ae4 pbrook
    tcg_gen_ld16s_i32(TCGV_LOW(ret), arg2, offset);
677 a7812ae4 pbrook
    tcg_gen_sari_i32(TCGV_HIGH(ret), TCGV_LOW(ret), 31);
678 c896fe29 bellard
}
679 c896fe29 bellard
680 a7812ae4 pbrook
static inline void tcg_gen_ld32u_i64(TCGv_i64 ret, TCGv_ptr arg2,
681 a7812ae4 pbrook
                                     tcg_target_long offset)
682 c896fe29 bellard
{
683 a7812ae4 pbrook
    tcg_gen_ld_i32(TCGV_LOW(ret), arg2, offset);
684 ac56dd48 pbrook
    tcg_gen_movi_i32(TCGV_HIGH(ret), 0);
685 c896fe29 bellard
}
686 c896fe29 bellard
687 a7812ae4 pbrook
static inline void tcg_gen_ld32s_i64(TCGv_i64 ret, TCGv_ptr arg2,
688 a7812ae4 pbrook
                                     tcg_target_long offset)
689 c896fe29 bellard
{
690 a7812ae4 pbrook
    tcg_gen_ld_i32(TCGV_LOW(ret), arg2, offset);
691 a7812ae4 pbrook
    tcg_gen_sari_i32(TCGV_HIGH(ret), TCGV_LOW(ret), 31);
692 c896fe29 bellard
}
693 c896fe29 bellard
694 a7812ae4 pbrook
static inline void tcg_gen_ld_i64(TCGv_i64 ret, TCGv_ptr arg2,
695 a7812ae4 pbrook
                                  tcg_target_long offset)
696 c896fe29 bellard
{
697 c896fe29 bellard
    /* since arg2 and ret have different types, they cannot be the
698 c896fe29 bellard
       same temporary */
699 c896fe29 bellard
#ifdef TCG_TARGET_WORDS_BIGENDIAN
700 ac56dd48 pbrook
    tcg_gen_ld_i32(TCGV_HIGH(ret), arg2, offset);
701 a7812ae4 pbrook
    tcg_gen_ld_i32(TCGV_LOW(ret), arg2, offset + 4);
702 c896fe29 bellard
#else
703 a7812ae4 pbrook
    tcg_gen_ld_i32(TCGV_LOW(ret), arg2, offset);
704 ac56dd48 pbrook
    tcg_gen_ld_i32(TCGV_HIGH(ret), arg2, offset + 4);
705 c896fe29 bellard
#endif
706 c896fe29 bellard
}
707 c896fe29 bellard
708 a7812ae4 pbrook
static inline void tcg_gen_st8_i64(TCGv_i64 arg1, TCGv_ptr arg2,
709 a7812ae4 pbrook
                                   tcg_target_long offset)
710 c896fe29 bellard
{
711 a7812ae4 pbrook
    tcg_gen_st8_i32(TCGV_LOW(arg1), arg2, offset);
712 c896fe29 bellard
}
713 c896fe29 bellard
714 a7812ae4 pbrook
static inline void tcg_gen_st16_i64(TCGv_i64 arg1, TCGv_ptr arg2,
715 a7812ae4 pbrook
                                    tcg_target_long offset)
716 c896fe29 bellard
{
717 a7812ae4 pbrook
    tcg_gen_st16_i32(TCGV_LOW(arg1), arg2, offset);
718 c896fe29 bellard
}
719 c896fe29 bellard
720 a7812ae4 pbrook
static inline void tcg_gen_st32_i64(TCGv_i64 arg1, TCGv_ptr arg2,
721 a7812ae4 pbrook
                                    tcg_target_long offset)
722 c896fe29 bellard
{
723 a7812ae4 pbrook
    tcg_gen_st_i32(TCGV_LOW(arg1), arg2, offset);
724 c896fe29 bellard
}
725 c896fe29 bellard
726 a7812ae4 pbrook
static inline void tcg_gen_st_i64(TCGv_i64 arg1, TCGv_ptr arg2,
727 a7812ae4 pbrook
                                  tcg_target_long offset)
728 c896fe29 bellard
{
729 c896fe29 bellard
#ifdef TCG_TARGET_WORDS_BIGENDIAN
730 ac56dd48 pbrook
    tcg_gen_st_i32(TCGV_HIGH(arg1), arg2, offset);
731 a7812ae4 pbrook
    tcg_gen_st_i32(TCGV_LOW(arg1), arg2, offset + 4);
732 c896fe29 bellard
#else
733 a7812ae4 pbrook
    tcg_gen_st_i32(TCGV_LOW(arg1), arg2, offset);
734 ac56dd48 pbrook
    tcg_gen_st_i32(TCGV_HIGH(arg1), arg2, offset + 4);
735 c896fe29 bellard
#endif
736 c896fe29 bellard
}
737 c896fe29 bellard
738 a7812ae4 pbrook
static inline void tcg_gen_add_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2)
739 c896fe29 bellard
{
740 a7812ae4 pbrook
    tcg_gen_op6_i32(INDEX_op_add2_i32, TCGV_LOW(ret), TCGV_HIGH(ret),
741 a7812ae4 pbrook
                    TCGV_LOW(arg1), TCGV_HIGH(arg1), TCGV_LOW(arg2),
742 a7812ae4 pbrook
                    TCGV_HIGH(arg2));
743 c896fe29 bellard
}
744 c896fe29 bellard
745 a7812ae4 pbrook
static inline void tcg_gen_sub_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2)
746 c896fe29 bellard
{
747 a7812ae4 pbrook
    tcg_gen_op6_i32(INDEX_op_sub2_i32, TCGV_LOW(ret), TCGV_HIGH(ret),
748 a7812ae4 pbrook
                    TCGV_LOW(arg1), TCGV_HIGH(arg1), TCGV_LOW(arg2),
749 a7812ae4 pbrook
                    TCGV_HIGH(arg2));
750 c896fe29 bellard
}
751 c896fe29 bellard
752 a7812ae4 pbrook
static inline void tcg_gen_and_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2)
753 c896fe29 bellard
{
754 a7812ae4 pbrook
    tcg_gen_and_i32(TCGV_LOW(ret), TCGV_LOW(arg1), TCGV_LOW(arg2));
755 ac56dd48 pbrook
    tcg_gen_and_i32(TCGV_HIGH(ret), TCGV_HIGH(arg1), TCGV_HIGH(arg2));
756 c896fe29 bellard
}
757 c896fe29 bellard
758 a7812ae4 pbrook
static inline void tcg_gen_andi_i64(TCGv_i64 ret, TCGv_i64 arg1, int64_t arg2)
759 c896fe29 bellard
{
760 e5105083 aurel32
    tcg_gen_andi_i32(TCGV_LOW(ret), TCGV_LOW(arg1), arg2);
761 e5105083 aurel32
    tcg_gen_andi_i32(TCGV_HIGH(ret), TCGV_HIGH(arg1), arg2 >> 32);
762 c896fe29 bellard
}
763 c896fe29 bellard
764 a7812ae4 pbrook
static inline void tcg_gen_or_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2)
765 c896fe29 bellard
{
766 e5105083 aurel32
    tcg_gen_or_i32(TCGV_LOW(ret), TCGV_LOW(arg1), TCGV_LOW(arg2));
767 e5105083 aurel32
    tcg_gen_or_i32(TCGV_HIGH(ret), TCGV_HIGH(arg1), TCGV_HIGH(arg2));
768 c896fe29 bellard
}
769 c896fe29 bellard
770 a7812ae4 pbrook
static inline void tcg_gen_ori_i64(TCGv_i64 ret, TCGv_i64 arg1, int64_t arg2)
771 c896fe29 bellard
{
772 a7812ae4 pbrook
    tcg_gen_ori_i32(TCGV_LOW(ret), TCGV_LOW(arg1), arg2);
773 ac56dd48 pbrook
    tcg_gen_ori_i32(TCGV_HIGH(ret), TCGV_HIGH(arg1), arg2 >> 32);
774 c896fe29 bellard
}
775 c896fe29 bellard
776 a7812ae4 pbrook
static inline void tcg_gen_xor_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2)
777 c896fe29 bellard
{
778 e5105083 aurel32
    tcg_gen_xor_i32(TCGV_LOW(ret), TCGV_LOW(arg1), TCGV_LOW(arg2));
779 e5105083 aurel32
    tcg_gen_xor_i32(TCGV_HIGH(ret), TCGV_HIGH(arg1), TCGV_HIGH(arg2));
780 c896fe29 bellard
}
781 c896fe29 bellard
782 a7812ae4 pbrook
static inline void tcg_gen_xori_i64(TCGv_i64 ret, TCGv_i64 arg1, int64_t arg2)
783 c896fe29 bellard
{
784 a7812ae4 pbrook
    tcg_gen_xori_i32(TCGV_LOW(ret), TCGV_LOW(arg1), arg2);
785 ac56dd48 pbrook
    tcg_gen_xori_i32(TCGV_HIGH(ret), TCGV_HIGH(arg1), arg2 >> 32);
786 c896fe29 bellard
}
787 c896fe29 bellard
788 c896fe29 bellard
/* XXX: use generic code when basic block handling is OK or CPU
789 c896fe29 bellard
   specific code (x86) */
790 a7812ae4 pbrook
static inline void tcg_gen_shl_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2)
791 c896fe29 bellard
{
792 a7812ae4 pbrook
    tcg_gen_helper64(tcg_helper_shl_i64, ret, arg1, arg2);
793 c896fe29 bellard
}
794 c896fe29 bellard
795 a7812ae4 pbrook
static inline void tcg_gen_shli_i64(TCGv_i64 ret, TCGv_i64 arg1, int64_t arg2)
796 c896fe29 bellard
{
797 c896fe29 bellard
    tcg_gen_shifti_i64(ret, arg1, arg2, 0, 0);
798 c896fe29 bellard
}
799 c896fe29 bellard
800 a7812ae4 pbrook
static inline void tcg_gen_shr_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2)
801 c896fe29 bellard
{
802 a7812ae4 pbrook
    tcg_gen_helper64(tcg_helper_shr_i64, ret, arg1, arg2);
803 c896fe29 bellard
}
804 c896fe29 bellard
805 a7812ae4 pbrook
static inline void tcg_gen_shri_i64(TCGv_i64 ret, TCGv_i64 arg1, int64_t arg2)
806 c896fe29 bellard
{
807 c896fe29 bellard
    tcg_gen_shifti_i64(ret, arg1, arg2, 1, 0);
808 c896fe29 bellard
}
809 c896fe29 bellard
810 a7812ae4 pbrook
static inline void tcg_gen_sar_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2)
811 c896fe29 bellard
{
812 a7812ae4 pbrook
    tcg_gen_helper64(tcg_helper_sar_i64, ret, arg1, arg2);
813 c896fe29 bellard
}
814 c896fe29 bellard
815 a7812ae4 pbrook
static inline void tcg_gen_sari_i64(TCGv_i64 ret, TCGv_i64 arg1, int64_t arg2)
816 c896fe29 bellard
{
817 c896fe29 bellard
    tcg_gen_shifti_i64(ret, arg1, arg2, 1, 1);
818 c896fe29 bellard
}
819 c896fe29 bellard
820 a7812ae4 pbrook
static inline void tcg_gen_brcond_i64(int cond, TCGv_i64 arg1, TCGv_i64 arg2,
821 c896fe29 bellard
                                      int label_index)
822 c896fe29 bellard
{
823 a7812ae4 pbrook
    tcg_gen_op6ii_i32(INDEX_op_brcond2_i32,
824 a7812ae4 pbrook
                      TCGV_LOW(arg1), TCGV_HIGH(arg1), TCGV_LOW(arg2),
825 a7812ae4 pbrook
                      TCGV_HIGH(arg2), cond, label_index);
826 c896fe29 bellard
}
827 c896fe29 bellard
828 a7812ae4 pbrook
static inline void tcg_gen_mul_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2)
829 c896fe29 bellard
{
830 a7812ae4 pbrook
    TCGv_i64 t0;
831 a7812ae4 pbrook
    TCGv_i32 t1;
832 c896fe29 bellard
833 a7812ae4 pbrook
    t0 = tcg_temp_new_i64();
834 a7812ae4 pbrook
    t1 = tcg_temp_new_i32();
835 a7812ae4 pbrook
836 a7812ae4 pbrook
    tcg_gen_op4_i32(INDEX_op_mulu2_i32, TCGV_LOW(t0), TCGV_HIGH(t0),
837 a7812ae4 pbrook
                    TCGV_LOW(arg1), TCGV_LOW(arg2));
838 a7812ae4 pbrook
839 a7812ae4 pbrook
    tcg_gen_mul_i32(t1, TCGV_LOW(arg1), TCGV_HIGH(arg2));
840 ac56dd48 pbrook
    tcg_gen_add_i32(TCGV_HIGH(t0), TCGV_HIGH(t0), t1);
841 a7812ae4 pbrook
    tcg_gen_mul_i32(t1, TCGV_HIGH(arg1), TCGV_LOW(arg2));
842 ac56dd48 pbrook
    tcg_gen_add_i32(TCGV_HIGH(t0), TCGV_HIGH(t0), t1);
843 a7812ae4 pbrook
844 c896fe29 bellard
    tcg_gen_mov_i64(ret, t0);
845 a7812ae4 pbrook
    tcg_temp_free_i64(t0);
846 a7812ae4 pbrook
    tcg_temp_free_i32(t1);
847 c896fe29 bellard
}
848 c896fe29 bellard
849 a7812ae4 pbrook
static inline void tcg_gen_div_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2)
850 c896fe29 bellard
{
851 a7812ae4 pbrook
    tcg_gen_helper64(tcg_helper_div_i64, ret, arg1, arg2);
852 c896fe29 bellard
}
853 c896fe29 bellard
854 a7812ae4 pbrook
static inline void tcg_gen_rem_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2)
855 c896fe29 bellard
{
856 a7812ae4 pbrook
    tcg_gen_helper64(tcg_helper_rem_i64, ret, arg1, arg2);
857 c896fe29 bellard
}
858 c896fe29 bellard
859 a7812ae4 pbrook
static inline void tcg_gen_divu_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2)
860 c896fe29 bellard
{
861 a7812ae4 pbrook
    tcg_gen_helper64(tcg_helper_divu_i64, ret, arg1, arg2);
862 c896fe29 bellard
}
863 c896fe29 bellard
864 a7812ae4 pbrook
static inline void tcg_gen_remu_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2)
865 c896fe29 bellard
{
866 a7812ae4 pbrook
    tcg_gen_helper64(tcg_helper_remu_i64, ret, arg1, arg2);
867 c896fe29 bellard
}
868 c896fe29 bellard
869 c896fe29 bellard
#else
870 c896fe29 bellard
871 a7812ae4 pbrook
static inline void tcg_gen_mov_i64(TCGv_i64 ret, TCGv_i64 arg)
872 c896fe29 bellard
{
873 fe75bcf7 aurel32
    if (!TCGV_EQUAL_I64(ret, arg))
874 a7812ae4 pbrook
        tcg_gen_op2_i64(INDEX_op_mov_i64, ret, arg);
875 c896fe29 bellard
}
876 c896fe29 bellard
877 a7812ae4 pbrook
static inline void tcg_gen_movi_i64(TCGv_i64 ret, int64_t arg)
878 c896fe29 bellard
{
879 a7812ae4 pbrook
    tcg_gen_op2i_i64(INDEX_op_movi_i64, ret, arg);
880 c896fe29 bellard
}
881 c896fe29 bellard
882 a7812ae4 pbrook
static inline void tcg_gen_ld8u_i64(TCGv_i64 ret, TCGv_i64 arg2,
883 ac56dd48 pbrook
                                    tcg_target_long offset)
884 c896fe29 bellard
{
885 a7812ae4 pbrook
    tcg_gen_ldst_op_i64(INDEX_op_ld8u_i64, ret, arg2, offset);
886 c896fe29 bellard
}
887 c896fe29 bellard
888 a7812ae4 pbrook
static inline void tcg_gen_ld8s_i64(TCGv_i64 ret, TCGv_i64 arg2,
889 ac56dd48 pbrook
                                    tcg_target_long offset)
890 c896fe29 bellard
{
891 a7812ae4 pbrook
    tcg_gen_ldst_op_i64(INDEX_op_ld8s_i64, ret, arg2, offset);
892 c896fe29 bellard
}
893 c896fe29 bellard
894 a7812ae4 pbrook
static inline void tcg_gen_ld16u_i64(TCGv_i64 ret, TCGv_i64 arg2,
895 ac56dd48 pbrook
                                     tcg_target_long offset)
896 c896fe29 bellard
{
897 a7812ae4 pbrook
    tcg_gen_ldst_op_i64(INDEX_op_ld16u_i64, ret, arg2, offset);
898 c896fe29 bellard
}
899 c896fe29 bellard
900 a7812ae4 pbrook
static inline void tcg_gen_ld16s_i64(TCGv_i64 ret, TCGv_i64 arg2,
901 ac56dd48 pbrook
                                     tcg_target_long offset)
902 c896fe29 bellard
{
903 a7812ae4 pbrook
    tcg_gen_ldst_op_i64(INDEX_op_ld16s_i64, ret, arg2, offset);
904 c896fe29 bellard
}
905 c896fe29 bellard
906 a7812ae4 pbrook
static inline void tcg_gen_ld32u_i64(TCGv_i64 ret, TCGv_i64 arg2,
907 ac56dd48 pbrook
                                     tcg_target_long offset)
908 c896fe29 bellard
{
909 a7812ae4 pbrook
    tcg_gen_ldst_op_i64(INDEX_op_ld32u_i64, ret, arg2, offset);
910 c896fe29 bellard
}
911 c896fe29 bellard
912 a7812ae4 pbrook
static inline void tcg_gen_ld32s_i64(TCGv_i64 ret, TCGv_i64 arg2,
913 ac56dd48 pbrook
                                     tcg_target_long offset)
914 c896fe29 bellard
{
915 a7812ae4 pbrook
    tcg_gen_ldst_op_i64(INDEX_op_ld32s_i64, ret, arg2, offset);
916 c896fe29 bellard
}
917 c896fe29 bellard
918 a7812ae4 pbrook
static inline void tcg_gen_ld_i64(TCGv_i64 ret, TCGv_i64 arg2, tcg_target_long offset)
919 c896fe29 bellard
{
920 a7812ae4 pbrook
    tcg_gen_ldst_op_i64(INDEX_op_ld_i64, ret, arg2, offset);
921 c896fe29 bellard
}
922 c896fe29 bellard
923 a7812ae4 pbrook
static inline void tcg_gen_st8_i64(TCGv_i64 arg1, TCGv_i64 arg2,
924 ac56dd48 pbrook
                                   tcg_target_long offset)
925 c896fe29 bellard
{
926 a7812ae4 pbrook
    tcg_gen_ldst_op_i64(INDEX_op_st8_i64, arg1, arg2, offset);
927 c896fe29 bellard
}
928 c896fe29 bellard
929 a7812ae4 pbrook
static inline void tcg_gen_st16_i64(TCGv_i64 arg1, TCGv_i64 arg2,
930 ac56dd48 pbrook
                                    tcg_target_long offset)
931 c896fe29 bellard
{
932 a7812ae4 pbrook
    tcg_gen_ldst_op_i64(INDEX_op_st16_i64, arg1, arg2, offset);
933 c896fe29 bellard
}
934 c896fe29 bellard
935 a7812ae4 pbrook
static inline void tcg_gen_st32_i64(TCGv_i64 arg1, TCGv_i64 arg2,
936 ac56dd48 pbrook
                                    tcg_target_long offset)
937 c896fe29 bellard
{
938 a7812ae4 pbrook
    tcg_gen_ldst_op_i64(INDEX_op_st32_i64, arg1, arg2, offset);
939 c896fe29 bellard
}
940 c896fe29 bellard
941 a7812ae4 pbrook
static inline void tcg_gen_st_i64(TCGv_i64 arg1, TCGv_i64 arg2, tcg_target_long offset)
942 c896fe29 bellard
{
943 a7812ae4 pbrook
    tcg_gen_ldst_op_i64(INDEX_op_st_i64, arg1, arg2, offset);
944 c896fe29 bellard
}
945 c896fe29 bellard
946 a7812ae4 pbrook
static inline void tcg_gen_add_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2)
947 c896fe29 bellard
{
948 a7812ae4 pbrook
    tcg_gen_op3_i64(INDEX_op_add_i64, ret, arg1, arg2);
949 c896fe29 bellard
}
950 c896fe29 bellard
951 a7812ae4 pbrook
static inline void tcg_gen_sub_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2)
952 c896fe29 bellard
{
953 a7812ae4 pbrook
    tcg_gen_op3_i64(INDEX_op_sub_i64, ret, arg1, arg2);
954 c896fe29 bellard
}
955 c896fe29 bellard
956 a7812ae4 pbrook
static inline void tcg_gen_and_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2)
957 c896fe29 bellard
{
958 7fc81051 aurel32
    if (TCGV_EQUAL_I64(arg1, arg2)) {
959 7fc81051 aurel32
        tcg_gen_mov_i64(ret, arg1);
960 7fc81051 aurel32
    } else {
961 7fc81051 aurel32
        tcg_gen_op3_i64(INDEX_op_and_i64, ret, arg1, arg2);
962 7fc81051 aurel32
    }
963 c896fe29 bellard
}
964 c896fe29 bellard
965 a7812ae4 pbrook
static inline void tcg_gen_andi_i64(TCGv_i64 ret, TCGv_i64 arg1, int64_t arg2)
966 c896fe29 bellard
{
967 a7812ae4 pbrook
    TCGv_i64 t0 = tcg_const_i64(arg2);
968 e8996ee0 bellard
    tcg_gen_and_i64(ret, arg1, t0);
969 a7812ae4 pbrook
    tcg_temp_free_i64(t0);
970 c896fe29 bellard
}
971 c896fe29 bellard
972 a7812ae4 pbrook
static inline void tcg_gen_or_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2)
973 c896fe29 bellard
{
974 7fc81051 aurel32
    if (TCGV_EQUAL_I64(arg1, arg2)) {
975 7fc81051 aurel32
        tcg_gen_mov_i64(ret, arg1);
976 7fc81051 aurel32
    } else {
977 7fc81051 aurel32
        tcg_gen_op3_i64(INDEX_op_or_i64, ret, arg1, arg2);
978 7fc81051 aurel32
    }
979 c896fe29 bellard
}
980 c896fe29 bellard
981 a7812ae4 pbrook
static inline void tcg_gen_ori_i64(TCGv_i64 ret, TCGv_i64 arg1, int64_t arg2)
982 c896fe29 bellard
{
983 a7812ae4 pbrook
    TCGv_i64 t0 = tcg_const_i64(arg2);
984 e8996ee0 bellard
    tcg_gen_or_i64(ret, arg1, t0);
985 a7812ae4 pbrook
    tcg_temp_free_i64(t0);
986 c896fe29 bellard
}
987 c896fe29 bellard
988 a7812ae4 pbrook
static inline void tcg_gen_xor_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2)
989 c896fe29 bellard
{
990 7fc81051 aurel32
    if (TCGV_EQUAL_I64(arg1, arg2)) {
991 7fc81051 aurel32
        tcg_gen_movi_i64(ret, 0);
992 7fc81051 aurel32
    } else {
993 7fc81051 aurel32
        tcg_gen_op3_i64(INDEX_op_xor_i64, ret, arg1, arg2);
994 7fc81051 aurel32
    }
995 c896fe29 bellard
}
996 c896fe29 bellard
997 a7812ae4 pbrook
static inline void tcg_gen_xori_i64(TCGv_i64 ret, TCGv_i64 arg1, int64_t arg2)
998 c896fe29 bellard
{
999 a7812ae4 pbrook
    TCGv_i64 t0 = tcg_const_i64(arg2);
1000 e8996ee0 bellard
    tcg_gen_xor_i64(ret, arg1, t0);
1001 a7812ae4 pbrook
    tcg_temp_free_i64(t0);
1002 c896fe29 bellard
}
1003 c896fe29 bellard
1004 a7812ae4 pbrook
static inline void tcg_gen_shl_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2)
1005 c896fe29 bellard
{
1006 a7812ae4 pbrook
    tcg_gen_op3_i64(INDEX_op_shl_i64, ret, arg1, arg2);
1007 c896fe29 bellard
}
1008 c896fe29 bellard
1009 a7812ae4 pbrook
static inline void tcg_gen_shli_i64(TCGv_i64 ret, TCGv_i64 arg1, int64_t arg2)
1010 c896fe29 bellard
{
1011 34151a20 bellard
    if (arg2 == 0) {
1012 34151a20 bellard
        tcg_gen_mov_i64(ret, arg1);
1013 34151a20 bellard
    } else {
1014 a7812ae4 pbrook
        TCGv_i64 t0 = tcg_const_i64(arg2);
1015 e8996ee0 bellard
        tcg_gen_shl_i64(ret, arg1, t0);
1016 a7812ae4 pbrook
        tcg_temp_free_i64(t0);
1017 34151a20 bellard
    }
1018 c896fe29 bellard
}
1019 c896fe29 bellard
1020 a7812ae4 pbrook
static inline void tcg_gen_shr_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2)
1021 c896fe29 bellard
{
1022 a7812ae4 pbrook
    tcg_gen_op3_i64(INDEX_op_shr_i64, ret, arg1, arg2);
1023 c896fe29 bellard
}
1024 c896fe29 bellard
1025 a7812ae4 pbrook
static inline void tcg_gen_shri_i64(TCGv_i64 ret, TCGv_i64 arg1, int64_t arg2)
1026 c896fe29 bellard
{
1027 34151a20 bellard
    if (arg2 == 0) {
1028 34151a20 bellard
        tcg_gen_mov_i64(ret, arg1);
1029 34151a20 bellard
    } else {
1030 a7812ae4 pbrook
        TCGv_i64 t0 = tcg_const_i64(arg2);
1031 e8996ee0 bellard
        tcg_gen_shr_i64(ret, arg1, t0);
1032 a7812ae4 pbrook
        tcg_temp_free_i64(t0);
1033 34151a20 bellard
    }
1034 c896fe29 bellard
}
1035 c896fe29 bellard
1036 a7812ae4 pbrook
static inline void tcg_gen_sar_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2)
1037 c896fe29 bellard
{
1038 a7812ae4 pbrook
    tcg_gen_op3_i64(INDEX_op_sar_i64, ret, arg1, arg2);
1039 c896fe29 bellard
}
1040 c896fe29 bellard
1041 a7812ae4 pbrook
static inline void tcg_gen_sari_i64(TCGv_i64 ret, TCGv_i64 arg1, int64_t arg2)
1042 c896fe29 bellard
{
1043 34151a20 bellard
    if (arg2 == 0) {
1044 34151a20 bellard
        tcg_gen_mov_i64(ret, arg1);
1045 34151a20 bellard
    } else {
1046 a7812ae4 pbrook
        TCGv_i64 t0 = tcg_const_i64(arg2);
1047 e8996ee0 bellard
        tcg_gen_sar_i64(ret, arg1, t0);
1048 a7812ae4 pbrook
        tcg_temp_free_i64(t0);
1049 34151a20 bellard
    }
1050 c896fe29 bellard
}
1051 c896fe29 bellard
1052 a7812ae4 pbrook
static inline void tcg_gen_brcond_i64(int cond, TCGv_i64 arg1, TCGv_i64 arg2,
1053 c896fe29 bellard
                                      int label_index)
1054 c896fe29 bellard
{
1055 a7812ae4 pbrook
    tcg_gen_op4ii_i64(INDEX_op_brcond_i64, arg1, arg2, cond, label_index);
1056 c896fe29 bellard
}
1057 c896fe29 bellard
1058 a7812ae4 pbrook
static inline void tcg_gen_mul_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2)
1059 c896fe29 bellard
{
1060 a7812ae4 pbrook
    tcg_gen_op3_i64(INDEX_op_mul_i64, ret, arg1, arg2);
1061 c896fe29 bellard
}
1062 c896fe29 bellard
1063 c896fe29 bellard
#ifdef TCG_TARGET_HAS_div_i64
1064 a7812ae4 pbrook
static inline void tcg_gen_div_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2)
1065 c896fe29 bellard
{
1066 a7812ae4 pbrook
    tcg_gen_op3_i64(INDEX_op_div_i64, ret, arg1, arg2);
1067 c896fe29 bellard
}
1068 c896fe29 bellard
1069 a7812ae4 pbrook
static inline void tcg_gen_rem_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2)
1070 c896fe29 bellard
{
1071 a7812ae4 pbrook
    tcg_gen_op3_i64(INDEX_op_rem_i64, ret, arg1, arg2);
1072 c896fe29 bellard
}
1073 c896fe29 bellard
1074 a7812ae4 pbrook
static inline void tcg_gen_divu_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2)
1075 c896fe29 bellard
{
1076 a7812ae4 pbrook
    tcg_gen_op3_i64(INDEX_op_divu_i64, ret, arg1, arg2);
1077 c896fe29 bellard
}
1078 c896fe29 bellard
1079 a7812ae4 pbrook
static inline void tcg_gen_remu_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2)
1080 c896fe29 bellard
{
1081 a7812ae4 pbrook
    tcg_gen_op3_i64(INDEX_op_remu_i64, ret, arg1, arg2);
1082 c896fe29 bellard
}
1083 c896fe29 bellard
#else
1084 a7812ae4 pbrook
static inline void tcg_gen_div_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2)
1085 c896fe29 bellard
{
1086 a7812ae4 pbrook
    TCGv_i64 t0;
1087 a7812ae4 pbrook
    t0 = tcg_temp_new_i64();
1088 c896fe29 bellard
    tcg_gen_sari_i64(t0, arg1, 63);
1089 a7812ae4 pbrook
    tcg_gen_op5_i64(INDEX_op_div2_i64, ret, t0, arg1, t0, arg2);
1090 a7812ae4 pbrook
    tcg_temp_free_i64(t0);
1091 c896fe29 bellard
}
1092 c896fe29 bellard
1093 a7812ae4 pbrook
static inline void tcg_gen_rem_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2)
1094 c896fe29 bellard
{
1095 a7812ae4 pbrook
    TCGv_i64 t0;
1096 a7812ae4 pbrook
    t0 = tcg_temp_new_i64();
1097 c896fe29 bellard
    tcg_gen_sari_i64(t0, arg1, 63);
1098 a7812ae4 pbrook
    tcg_gen_op5_i64(INDEX_op_div2_i64, t0, ret, arg1, t0, arg2);
1099 a7812ae4 pbrook
    tcg_temp_free_i64(t0);
1100 c896fe29 bellard
}
1101 c896fe29 bellard
1102 a7812ae4 pbrook
static inline void tcg_gen_divu_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2)
1103 c896fe29 bellard
{
1104 a7812ae4 pbrook
    TCGv_i64 t0;
1105 a7812ae4 pbrook
    t0 = tcg_temp_new_i64();
1106 c896fe29 bellard
    tcg_gen_movi_i64(t0, 0);
1107 a7812ae4 pbrook
    tcg_gen_op5_i64(INDEX_op_divu2_i64, ret, t0, arg1, t0, arg2);
1108 a7812ae4 pbrook
    tcg_temp_free_i64(t0);
1109 c896fe29 bellard
}
1110 c896fe29 bellard
1111 a7812ae4 pbrook
static inline void tcg_gen_remu_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2)
1112 c896fe29 bellard
{
1113 a7812ae4 pbrook
    TCGv_i64 t0;
1114 a7812ae4 pbrook
    t0 = tcg_temp_new_i64();
1115 c896fe29 bellard
    tcg_gen_movi_i64(t0, 0);
1116 a7812ae4 pbrook
    tcg_gen_op5_i64(INDEX_op_divu2_i64, t0, ret, arg1, t0, arg2);
1117 a7812ae4 pbrook
    tcg_temp_free_i64(t0);
1118 c896fe29 bellard
}
1119 c896fe29 bellard
#endif
1120 c896fe29 bellard
1121 c896fe29 bellard
#endif
1122 c896fe29 bellard
1123 a7812ae4 pbrook
static inline void tcg_gen_addi_i64(TCGv_i64 ret, TCGv_i64 arg1, int64_t arg2)
1124 6359706f aurel32
{
1125 6359706f aurel32
    /* some cases can be optimized here */
1126 6359706f aurel32
    if (arg2 == 0) {
1127 6359706f aurel32
        tcg_gen_mov_i64(ret, arg1);
1128 6359706f aurel32
    } else {
1129 a7812ae4 pbrook
        TCGv_i64 t0 = tcg_const_i64(arg2);
1130 6359706f aurel32
        tcg_gen_add_i64(ret, arg1, t0);
1131 a7812ae4 pbrook
        tcg_temp_free_i64(t0);
1132 6359706f aurel32
    }
1133 6359706f aurel32
}
1134 6359706f aurel32
1135 a7812ae4 pbrook
static inline void tcg_gen_subfi_i64(TCGv_i64 ret, int64_t arg1, TCGv_i64 arg2)
1136 0045734a aurel32
{
1137 a7812ae4 pbrook
    TCGv_i64 t0 = tcg_const_i64(arg1);
1138 0045734a aurel32
    tcg_gen_sub_i64(ret, t0, arg2);
1139 a7812ae4 pbrook
    tcg_temp_free_i64(t0);
1140 0045734a aurel32
}
1141 0045734a aurel32
1142 a7812ae4 pbrook
static inline void tcg_gen_subi_i64(TCGv_i64 ret, TCGv_i64 arg1, int64_t arg2)
1143 6359706f aurel32
{
1144 6359706f aurel32
    /* some cases can be optimized here */
1145 6359706f aurel32
    if (arg2 == 0) {
1146 6359706f aurel32
        tcg_gen_mov_i64(ret, arg1);
1147 6359706f aurel32
    } else {
1148 a7812ae4 pbrook
        TCGv_i64 t0 = tcg_const_i64(arg2);
1149 6359706f aurel32
        tcg_gen_sub_i64(ret, arg1, t0);
1150 a7812ae4 pbrook
        tcg_temp_free_i64(t0);
1151 6359706f aurel32
    }
1152 6359706f aurel32
}
1153 a7812ae4 pbrook
static inline void tcg_gen_brcondi_i64(int cond, TCGv_i64 arg1, int64_t arg2,
1154 f02bb954 aurel32
                                       int label_index)
1155 f02bb954 aurel32
{
1156 a7812ae4 pbrook
    TCGv_i64 t0 = tcg_const_i64(arg2);
1157 f02bb954 aurel32
    tcg_gen_brcond_i64(cond, arg1, t0, label_index);
1158 a7812ae4 pbrook
    tcg_temp_free_i64(t0);
1159 f02bb954 aurel32
}
1160 f02bb954 aurel32
1161 a7812ae4 pbrook
static inline void tcg_gen_muli_i64(TCGv_i64 ret, TCGv_i64 arg1, int64_t arg2)
1162 f02bb954 aurel32
{
1163 a7812ae4 pbrook
    TCGv_i64 t0 = tcg_const_i64(arg2);
1164 f02bb954 aurel32
    tcg_gen_mul_i64(ret, arg1, t0);
1165 a7812ae4 pbrook
    tcg_temp_free_i64(t0);
1166 f02bb954 aurel32
}
1167 f02bb954 aurel32
1168 6359706f aurel32
1169 c896fe29 bellard
/***************************************/
1170 c896fe29 bellard
/* optional operations */
1171 c896fe29 bellard
1172 a7812ae4 pbrook
static inline void tcg_gen_ext8s_i32(TCGv_i32 ret, TCGv_i32 arg)
1173 c896fe29 bellard
{
1174 c896fe29 bellard
#ifdef TCG_TARGET_HAS_ext8s_i32
1175 a7812ae4 pbrook
    tcg_gen_op2_i32(INDEX_op_ext8s_i32, ret, arg);
1176 c896fe29 bellard
#else
1177 c896fe29 bellard
    tcg_gen_shli_i32(ret, arg, 24);
1178 5ff9d6a4 bellard
    tcg_gen_sari_i32(ret, ret, 24);
1179 c896fe29 bellard
#endif
1180 c896fe29 bellard
}
1181 c896fe29 bellard
1182 a7812ae4 pbrook
static inline void tcg_gen_ext16s_i32(TCGv_i32 ret, TCGv_i32 arg)
1183 c896fe29 bellard
{
1184 c896fe29 bellard
#ifdef TCG_TARGET_HAS_ext16s_i32
1185 a7812ae4 pbrook
    tcg_gen_op2_i32(INDEX_op_ext16s_i32, ret, arg);
1186 c896fe29 bellard
#else
1187 c896fe29 bellard
    tcg_gen_shli_i32(ret, arg, 16);
1188 5ff9d6a4 bellard
    tcg_gen_sari_i32(ret, ret, 16);
1189 c896fe29 bellard
#endif
1190 c896fe29 bellard
}
1191 c896fe29 bellard
1192 a7812ae4 pbrook
static inline void tcg_gen_ext8u_i32(TCGv_i32 ret, TCGv_i32 arg)
1193 86831435 pbrook
{
1194 cfc86988 Aurelien Jarno
#ifdef TCG_TARGET_HAS_ext8u_i32
1195 cfc86988 Aurelien Jarno
    tcg_gen_op2_i32(INDEX_op_ext8u_i32, ret, arg);
1196 cfc86988 Aurelien Jarno
#else
1197 86831435 pbrook
    tcg_gen_andi_i32(ret, arg, 0xffu);
1198 cfc86988 Aurelien Jarno
#endif
1199 86831435 pbrook
}
1200 86831435 pbrook
1201 a7812ae4 pbrook
static inline void tcg_gen_ext16u_i32(TCGv_i32 ret, TCGv_i32 arg)
1202 86831435 pbrook
{
1203 cfc86988 Aurelien Jarno
#ifdef TCG_TARGET_HAS_ext16u_i32
1204 cfc86988 Aurelien Jarno
    tcg_gen_op2_i32(INDEX_op_ext16u_i32, ret, arg);
1205 cfc86988 Aurelien Jarno
#else
1206 86831435 pbrook
    tcg_gen_andi_i32(ret, arg, 0xffffu);
1207 cfc86988 Aurelien Jarno
#endif
1208 86831435 pbrook
}
1209 86831435 pbrook
1210 c896fe29 bellard
/* Note: we assume the two high bytes are set to zero */
1211 a7812ae4 pbrook
static inline void tcg_gen_bswap16_i32(TCGv_i32 ret, TCGv_i32 arg)
1212 c896fe29 bellard
{
1213 c896fe29 bellard
#ifdef TCG_TARGET_HAS_bswap16_i32
1214 a7812ae4 pbrook
    tcg_gen_op2_i32(INDEX_op_bswap16_i32, ret, arg);
1215 c896fe29 bellard
#else
1216 dfa1a3f1 aurel32
    TCGv_i32 t0 = tcg_temp_new_i32();
1217 c896fe29 bellard
    
1218 dfa1a3f1 aurel32
    tcg_gen_ext8u_i32(t0, arg);
1219 dfa1a3f1 aurel32
    tcg_gen_shli_i32(t0, t0, 8);
1220 dfa1a3f1 aurel32
    tcg_gen_shri_i32(ret, arg, 8);
1221 dfa1a3f1 aurel32
    tcg_gen_or_i32(ret, ret, t0);
1222 a7812ae4 pbrook
    tcg_temp_free_i32(t0);
1223 c896fe29 bellard
#endif
1224 c896fe29 bellard
}
1225 c896fe29 bellard
1226 66896cb8 aurel32
static inline void tcg_gen_bswap32_i32(TCGv_i32 ret, TCGv_i32 arg)
1227 c896fe29 bellard
{
1228 66896cb8 aurel32
#ifdef TCG_TARGET_HAS_bswap32_i32
1229 66896cb8 aurel32
    tcg_gen_op2_i32(INDEX_op_bswap32_i32, ret, arg);
1230 c896fe29 bellard
#else
1231 a7812ae4 pbrook
    TCGv_i32 t0, t1;
1232 a7812ae4 pbrook
    t0 = tcg_temp_new_i32();
1233 a7812ae4 pbrook
    t1 = tcg_temp_new_i32();
1234 c896fe29 bellard
    
1235 c896fe29 bellard
    tcg_gen_shli_i32(t0, arg, 24);
1236 c896fe29 bellard
    
1237 c896fe29 bellard
    tcg_gen_andi_i32(t1, arg, 0x0000ff00);
1238 c896fe29 bellard
    tcg_gen_shli_i32(t1, t1, 8);
1239 c896fe29 bellard
    tcg_gen_or_i32(t0, t0, t1);
1240 c896fe29 bellard
    
1241 c896fe29 bellard
    tcg_gen_shri_i32(t1, arg, 8);
1242 c896fe29 bellard
    tcg_gen_andi_i32(t1, t1, 0x0000ff00);
1243 c896fe29 bellard
    tcg_gen_or_i32(t0, t0, t1);
1244 c896fe29 bellard
    
1245 c896fe29 bellard
    tcg_gen_shri_i32(t1, arg, 24);
1246 c896fe29 bellard
    tcg_gen_or_i32(ret, t0, t1);
1247 a7812ae4 pbrook
    tcg_temp_free_i32(t0);
1248 a7812ae4 pbrook
    tcg_temp_free_i32(t1);
1249 c896fe29 bellard
#endif
1250 c896fe29 bellard
}
1251 c896fe29 bellard
1252 c896fe29 bellard
#if TCG_TARGET_REG_BITS == 32
1253 a7812ae4 pbrook
static inline void tcg_gen_ext8s_i64(TCGv_i64 ret, TCGv_i64 arg)
1254 c896fe29 bellard
{
1255 a7812ae4 pbrook
    tcg_gen_ext8s_i32(TCGV_LOW(ret), TCGV_LOW(arg));
1256 a7812ae4 pbrook
    tcg_gen_sari_i32(TCGV_HIGH(ret), TCGV_LOW(ret), 31);
1257 c896fe29 bellard
}
1258 c896fe29 bellard
1259 a7812ae4 pbrook
static inline void tcg_gen_ext16s_i64(TCGv_i64 ret, TCGv_i64 arg)
1260 c896fe29 bellard
{
1261 a7812ae4 pbrook
    tcg_gen_ext16s_i32(TCGV_LOW(ret), TCGV_LOW(arg));
1262 a7812ae4 pbrook
    tcg_gen_sari_i32(TCGV_HIGH(ret), TCGV_LOW(ret), 31);
1263 c896fe29 bellard
}
1264 c896fe29 bellard
1265 a7812ae4 pbrook
static inline void tcg_gen_ext32s_i64(TCGv_i64 ret, TCGv_i64 arg)
1266 c896fe29 bellard
{
1267 a7812ae4 pbrook
    tcg_gen_mov_i32(TCGV_LOW(ret), TCGV_LOW(arg));
1268 a7812ae4 pbrook
    tcg_gen_sari_i32(TCGV_HIGH(ret), TCGV_LOW(ret), 31);
1269 c896fe29 bellard
}
1270 c896fe29 bellard
1271 a7812ae4 pbrook
static inline void tcg_gen_ext8u_i64(TCGv_i64 ret, TCGv_i64 arg)
1272 86831435 pbrook
{
1273 a7812ae4 pbrook
    tcg_gen_ext8u_i32(TCGV_LOW(ret), TCGV_LOW(arg));
1274 86831435 pbrook
    tcg_gen_movi_i32(TCGV_HIGH(ret), 0);
1275 86831435 pbrook
}
1276 86831435 pbrook
1277 a7812ae4 pbrook
static inline void tcg_gen_ext16u_i64(TCGv_i64 ret, TCGv_i64 arg)
1278 86831435 pbrook
{
1279 a7812ae4 pbrook
    tcg_gen_ext16u_i32(TCGV_LOW(ret), TCGV_LOW(arg));
1280 86831435 pbrook
    tcg_gen_movi_i32(TCGV_HIGH(ret), 0);
1281 86831435 pbrook
}
1282 86831435 pbrook
1283 a7812ae4 pbrook
static inline void tcg_gen_ext32u_i64(TCGv_i64 ret, TCGv_i64 arg)
1284 86831435 pbrook
{
1285 a7812ae4 pbrook
    tcg_gen_mov_i32(TCGV_LOW(ret), TCGV_LOW(arg));
1286 86831435 pbrook
    tcg_gen_movi_i32(TCGV_HIGH(ret), 0);
1287 86831435 pbrook
}
1288 86831435 pbrook
1289 a7812ae4 pbrook
static inline void tcg_gen_trunc_i64_i32(TCGv_i32 ret, TCGv_i64 arg)
1290 c896fe29 bellard
{
1291 a7812ae4 pbrook
    tcg_gen_mov_i32(ret, TCGV_LOW(arg));
1292 c896fe29 bellard
}
1293 c896fe29 bellard
1294 a7812ae4 pbrook
static inline void tcg_gen_extu_i32_i64(TCGv_i64 ret, TCGv_i32 arg)
1295 c896fe29 bellard
{
1296 a7812ae4 pbrook
    tcg_gen_mov_i32(TCGV_LOW(ret), arg);
1297 ac56dd48 pbrook
    tcg_gen_movi_i32(TCGV_HIGH(ret), 0);
1298 c896fe29 bellard
}
1299 c896fe29 bellard
1300 a7812ae4 pbrook
static inline void tcg_gen_ext_i32_i64(TCGv_i64 ret, TCGv_i32 arg)
1301 c896fe29 bellard
{
1302 a7812ae4 pbrook
    tcg_gen_mov_i32(TCGV_LOW(ret), arg);
1303 a7812ae4 pbrook
    tcg_gen_sari_i32(TCGV_HIGH(ret), TCGV_LOW(ret), 31);
1304 c896fe29 bellard
}
1305 c896fe29 bellard
1306 9a5c57fd aurel32
/* Note: we assume the six high bytes are set to zero */
1307 9a5c57fd aurel32
static inline void tcg_gen_bswap16_i64(TCGv_i64 ret, TCGv_i64 arg)
1308 9a5c57fd aurel32
{
1309 9a5c57fd aurel32
    tcg_gen_mov_i32(TCGV_HIGH(ret), TCGV_HIGH(arg));
1310 9a5c57fd aurel32
    tcg_gen_bswap16_i32(TCGV_LOW(ret), TCGV_LOW(arg));
1311 9a5c57fd aurel32
}
1312 9a5c57fd aurel32
1313 9a5c57fd aurel32
/* Note: we assume the four high bytes are set to zero */
1314 9a5c57fd aurel32
static inline void tcg_gen_bswap32_i64(TCGv_i64 ret, TCGv_i64 arg)
1315 9a5c57fd aurel32
{
1316 9a5c57fd aurel32
    tcg_gen_mov_i32(TCGV_HIGH(ret), TCGV_HIGH(arg));
1317 9a5c57fd aurel32
    tcg_gen_bswap32_i32(TCGV_LOW(ret), TCGV_LOW(arg));
1318 9a5c57fd aurel32
}
1319 9a5c57fd aurel32
1320 66896cb8 aurel32
static inline void tcg_gen_bswap64_i64(TCGv_i64 ret, TCGv_i64 arg)
1321 c896fe29 bellard
{
1322 a7812ae4 pbrook
    TCGv_i32 t0, t1;
1323 a7812ae4 pbrook
    t0 = tcg_temp_new_i32();
1324 a7812ae4 pbrook
    t1 = tcg_temp_new_i32();
1325 c896fe29 bellard
1326 66896cb8 aurel32
    tcg_gen_bswap32_i32(t0, TCGV_LOW(arg));
1327 66896cb8 aurel32
    tcg_gen_bswap32_i32(t1, TCGV_HIGH(arg));
1328 a7812ae4 pbrook
    tcg_gen_mov_i32(TCGV_LOW(ret), t1);
1329 ac56dd48 pbrook
    tcg_gen_mov_i32(TCGV_HIGH(ret), t0);
1330 a7812ae4 pbrook
    tcg_temp_free_i32(t0);
1331 a7812ae4 pbrook
    tcg_temp_free_i32(t1);
1332 c896fe29 bellard
}
1333 c896fe29 bellard
#else
1334 c896fe29 bellard
1335 a7812ae4 pbrook
static inline void tcg_gen_ext8s_i64(TCGv_i64 ret, TCGv_i64 arg)
1336 c896fe29 bellard
{
1337 c896fe29 bellard
#ifdef TCG_TARGET_HAS_ext8s_i64
1338 a7812ae4 pbrook
    tcg_gen_op2_i64(INDEX_op_ext8s_i64, ret, arg);
1339 c896fe29 bellard
#else
1340 c896fe29 bellard
    tcg_gen_shli_i64(ret, arg, 56);
1341 5ff9d6a4 bellard
    tcg_gen_sari_i64(ret, ret, 56);
1342 c896fe29 bellard
#endif
1343 c896fe29 bellard
}
1344 c896fe29 bellard
1345 a7812ae4 pbrook
static inline void tcg_gen_ext16s_i64(TCGv_i64 ret, TCGv_i64 arg)
1346 c896fe29 bellard
{
1347 c896fe29 bellard
#ifdef TCG_TARGET_HAS_ext16s_i64
1348 a7812ae4 pbrook
    tcg_gen_op2_i64(INDEX_op_ext16s_i64, ret, arg);
1349 c896fe29 bellard
#else
1350 c896fe29 bellard
    tcg_gen_shli_i64(ret, arg, 48);
1351 5ff9d6a4 bellard
    tcg_gen_sari_i64(ret, ret, 48);
1352 c896fe29 bellard
#endif
1353 c896fe29 bellard
}
1354 c896fe29 bellard
1355 a7812ae4 pbrook
static inline void tcg_gen_ext32s_i64(TCGv_i64 ret, TCGv_i64 arg)
1356 c896fe29 bellard
{
1357 c896fe29 bellard
#ifdef TCG_TARGET_HAS_ext32s_i64
1358 a7812ae4 pbrook
    tcg_gen_op2_i64(INDEX_op_ext32s_i64, ret, arg);
1359 c896fe29 bellard
#else
1360 c896fe29 bellard
    tcg_gen_shli_i64(ret, arg, 32);
1361 5ff9d6a4 bellard
    tcg_gen_sari_i64(ret, ret, 32);
1362 c896fe29 bellard
#endif
1363 c896fe29 bellard
}
1364 c896fe29 bellard
1365 a7812ae4 pbrook
static inline void tcg_gen_ext8u_i64(TCGv_i64 ret, TCGv_i64 arg)
1366 86831435 pbrook
{
1367 cfc86988 Aurelien Jarno
#ifdef TCG_TARGET_HAS_ext8u_i64
1368 cfc86988 Aurelien Jarno
    tcg_gen_op2_i64(INDEX_op_ext8u_i64, ret, arg);
1369 cfc86988 Aurelien Jarno
#else
1370 86831435 pbrook
    tcg_gen_andi_i64(ret, arg, 0xffu);
1371 cfc86988 Aurelien Jarno
#endif
1372 86831435 pbrook
}
1373 86831435 pbrook
1374 a7812ae4 pbrook
static inline void tcg_gen_ext16u_i64(TCGv_i64 ret, TCGv_i64 arg)
1375 86831435 pbrook
{
1376 cfc86988 Aurelien Jarno
#ifdef TCG_TARGET_HAS_ext16u_i64
1377 cfc86988 Aurelien Jarno
    tcg_gen_op2_i64(INDEX_op_ext16u_i64, ret, arg);
1378 cfc86988 Aurelien Jarno
#else
1379 86831435 pbrook
    tcg_gen_andi_i64(ret, arg, 0xffffu);
1380 cfc86988 Aurelien Jarno
#endif
1381 86831435 pbrook
}
1382 86831435 pbrook
1383 a7812ae4 pbrook
static inline void tcg_gen_ext32u_i64(TCGv_i64 ret, TCGv_i64 arg)
1384 86831435 pbrook
{
1385 cfc86988 Aurelien Jarno
#ifdef TCG_TARGET_HAS_ext32u_i64
1386 cfc86988 Aurelien Jarno
    tcg_gen_op2_i64(INDEX_op_ext32u_i64, ret, arg);
1387 cfc86988 Aurelien Jarno
#else
1388 86831435 pbrook
    tcg_gen_andi_i64(ret, arg, 0xffffffffu);
1389 cfc86988 Aurelien Jarno
#endif
1390 86831435 pbrook
}
1391 86831435 pbrook
1392 c896fe29 bellard
/* Note: we assume the target supports move between 32 and 64 bit
1393 ac56dd48 pbrook
   registers.  This will probably break MIPS64 targets.  */
1394 a7812ae4 pbrook
static inline void tcg_gen_trunc_i64_i32(TCGv_i32 ret, TCGv_i64 arg)
1395 c896fe29 bellard
{
1396 a7812ae4 pbrook
    tcg_gen_mov_i32(ret, MAKE_TCGV_I32(GET_TCGV_I64(arg)));
1397 c896fe29 bellard
}
1398 c896fe29 bellard
1399 c896fe29 bellard
/* Note: we assume the target supports move between 32 and 64 bit
1400 c896fe29 bellard
   registers */
1401 a7812ae4 pbrook
static inline void tcg_gen_extu_i32_i64(TCGv_i64 ret, TCGv_i32 arg)
1402 c896fe29 bellard
{
1403 cfc86988 Aurelien Jarno
    tcg_gen_ext32u_i64(ret, MAKE_TCGV_I64(GET_TCGV_I32(arg)));
1404 c896fe29 bellard
}
1405 c896fe29 bellard
1406 c896fe29 bellard
/* Note: we assume the target supports move between 32 and 64 bit
1407 c896fe29 bellard
   registers */
1408 a7812ae4 pbrook
static inline void tcg_gen_ext_i32_i64(TCGv_i64 ret, TCGv_i32 arg)
1409 c896fe29 bellard
{
1410 a7812ae4 pbrook
    tcg_gen_ext32s_i64(ret, MAKE_TCGV_I64(GET_TCGV_I32(arg)));
1411 c896fe29 bellard
}
1412 c896fe29 bellard
1413 9a5c57fd aurel32
/* Note: we assume the six high bytes are set to zero */
1414 9a5c57fd aurel32
static inline void tcg_gen_bswap16_i64(TCGv_i64 ret, TCGv_i64 arg)
1415 9a5c57fd aurel32
{
1416 9a5c57fd aurel32
#ifdef TCG_TARGET_HAS_bswap16_i64
1417 9a5c57fd aurel32
    tcg_gen_op2_i64(INDEX_op_bswap16_i64, ret, arg);
1418 9a5c57fd aurel32
#else
1419 9a5c57fd aurel32
    TCGv_i64 t0 = tcg_temp_new_i64();
1420 9a5c57fd aurel32
1421 9a5c57fd aurel32
    tcg_gen_ext8u_i64(t0, arg);
1422 9a5c57fd aurel32
    tcg_gen_shli_i64(t0, t0, 8);
1423 9a5c57fd aurel32
    tcg_gen_shri_i64(ret, arg, 8);
1424 9a5c57fd aurel32
    tcg_gen_or_i64(ret, ret, t0);
1425 9a5c57fd aurel32
    tcg_temp_free_i64(t0);
1426 9a5c57fd aurel32
#endif
1427 9a5c57fd aurel32
}
1428 9a5c57fd aurel32
1429 9a5c57fd aurel32
/* Note: we assume the four high bytes are set to zero */
1430 9a5c57fd aurel32
static inline void tcg_gen_bswap32_i64(TCGv_i64 ret, TCGv_i64 arg)
1431 9a5c57fd aurel32
{
1432 9a5c57fd aurel32
#ifdef TCG_TARGET_HAS_bswap32_i64
1433 9a5c57fd aurel32
    tcg_gen_op2_i64(INDEX_op_bswap32_i64, ret, arg);
1434 9a5c57fd aurel32
#else
1435 9a5c57fd aurel32
    TCGv_i64 t0, t1;
1436 9a5c57fd aurel32
    t0 = tcg_temp_new_i64();
1437 9a5c57fd aurel32
    t1 = tcg_temp_new_i64();
1438 9a5c57fd aurel32
1439 9a5c57fd aurel32
    tcg_gen_shli_i64(t0, arg, 24);
1440 9a5c57fd aurel32
    tcg_gen_ext32u_i64(t0, t0);
1441 9a5c57fd aurel32
1442 9a5c57fd aurel32
    tcg_gen_andi_i64(t1, arg, 0x0000ff00);
1443 9a5c57fd aurel32
    tcg_gen_shli_i64(t1, t1, 8);
1444 9a5c57fd aurel32
    tcg_gen_or_i64(t0, t0, t1);
1445 9a5c57fd aurel32
1446 9a5c57fd aurel32
    tcg_gen_shri_i64(t1, arg, 8);
1447 9a5c57fd aurel32
    tcg_gen_andi_i64(t1, t1, 0x0000ff00);
1448 9a5c57fd aurel32
    tcg_gen_or_i64(t0, t0, t1);
1449 9a5c57fd aurel32
1450 9a5c57fd aurel32
    tcg_gen_shri_i64(t1, arg, 24);
1451 9a5c57fd aurel32
    tcg_gen_or_i64(ret, t0, t1);
1452 9a5c57fd aurel32
    tcg_temp_free_i64(t0);
1453 9a5c57fd aurel32
    tcg_temp_free_i64(t1);
1454 9a5c57fd aurel32
#endif
1455 9a5c57fd aurel32
}
1456 9a5c57fd aurel32
1457 66896cb8 aurel32
static inline void tcg_gen_bswap64_i64(TCGv_i64 ret, TCGv_i64 arg)
1458 c896fe29 bellard
{
1459 66896cb8 aurel32
#ifdef TCG_TARGET_HAS_bswap64_i64
1460 66896cb8 aurel32
    tcg_gen_op2_i64(INDEX_op_bswap64_i64, ret, arg);
1461 c896fe29 bellard
#else
1462 b348113d Stefan Weil
    TCGv_i64 t0 = tcg_temp_new_i64();
1463 b348113d Stefan Weil
    TCGv_i64 t1 = tcg_temp_new_i64();
1464 c896fe29 bellard
    
1465 c896fe29 bellard
    tcg_gen_shli_i64(t0, arg, 56);
1466 c896fe29 bellard
    
1467 c896fe29 bellard
    tcg_gen_andi_i64(t1, arg, 0x0000ff00);
1468 c896fe29 bellard
    tcg_gen_shli_i64(t1, t1, 40);
1469 c896fe29 bellard
    tcg_gen_or_i64(t0, t0, t1);
1470 c896fe29 bellard
    
1471 c896fe29 bellard
    tcg_gen_andi_i64(t1, arg, 0x00ff0000);
1472 c896fe29 bellard
    tcg_gen_shli_i64(t1, t1, 24);
1473 c896fe29 bellard
    tcg_gen_or_i64(t0, t0, t1);
1474 c896fe29 bellard
1475 c896fe29 bellard
    tcg_gen_andi_i64(t1, arg, 0xff000000);
1476 c896fe29 bellard
    tcg_gen_shli_i64(t1, t1, 8);
1477 c896fe29 bellard
    tcg_gen_or_i64(t0, t0, t1);
1478 c896fe29 bellard
1479 c896fe29 bellard
    tcg_gen_shri_i64(t1, arg, 8);
1480 c896fe29 bellard
    tcg_gen_andi_i64(t1, t1, 0xff000000);
1481 c896fe29 bellard
    tcg_gen_or_i64(t0, t0, t1);
1482 c896fe29 bellard
    
1483 c896fe29 bellard
    tcg_gen_shri_i64(t1, arg, 24);
1484 c896fe29 bellard
    tcg_gen_andi_i64(t1, t1, 0x00ff0000);
1485 c896fe29 bellard
    tcg_gen_or_i64(t0, t0, t1);
1486 c896fe29 bellard
1487 c896fe29 bellard
    tcg_gen_shri_i64(t1, arg, 40);
1488 c896fe29 bellard
    tcg_gen_andi_i64(t1, t1, 0x0000ff00);
1489 c896fe29 bellard
    tcg_gen_or_i64(t0, t0, t1);
1490 c896fe29 bellard
1491 c896fe29 bellard
    tcg_gen_shri_i64(t1, arg, 56);
1492 c896fe29 bellard
    tcg_gen_or_i64(ret, t0, t1);
1493 b348113d Stefan Weil
    tcg_temp_free_i64(t0);
1494 b348113d Stefan Weil
    tcg_temp_free_i64(t1);
1495 c896fe29 bellard
#endif
1496 c896fe29 bellard
}
1497 c896fe29 bellard
1498 c896fe29 bellard
#endif
1499 c896fe29 bellard
1500 a7812ae4 pbrook
static inline void tcg_gen_neg_i32(TCGv_i32 ret, TCGv_i32 arg)
1501 390efc54 pbrook
{
1502 390efc54 pbrook
#ifdef TCG_TARGET_HAS_neg_i32
1503 a7812ae4 pbrook
    tcg_gen_op2_i32(INDEX_op_neg_i32, ret, arg);
1504 390efc54 pbrook
#else
1505 a7812ae4 pbrook
    TCGv_i32 t0 = tcg_const_i32(0);
1506 e8996ee0 bellard
    tcg_gen_sub_i32(ret, t0, arg);
1507 a7812ae4 pbrook
    tcg_temp_free_i32(t0);
1508 390efc54 pbrook
#endif
1509 390efc54 pbrook
}
1510 390efc54 pbrook
1511 a7812ae4 pbrook
static inline void tcg_gen_neg_i64(TCGv_i64 ret, TCGv_i64 arg)
1512 390efc54 pbrook
{
1513 390efc54 pbrook
#ifdef TCG_TARGET_HAS_neg_i64
1514 a7812ae4 pbrook
    tcg_gen_op2_i64(INDEX_op_neg_i64, ret, arg);
1515 390efc54 pbrook
#else
1516 a7812ae4 pbrook
    TCGv_i64 t0 = tcg_const_i64(0);
1517 e8996ee0 bellard
    tcg_gen_sub_i64(ret, t0, arg);
1518 a7812ae4 pbrook
    tcg_temp_free_i64(t0);
1519 390efc54 pbrook
#endif
1520 390efc54 pbrook
}
1521 390efc54 pbrook
1522 a7812ae4 pbrook
static inline void tcg_gen_not_i32(TCGv_i32 ret, TCGv_i32 arg)
1523 0b6ce4cf bellard
{
1524 d2604285 aurel32
#ifdef TCG_TARGET_HAS_not_i32
1525 d2604285 aurel32
    tcg_gen_op2_i32(INDEX_op_not_i32, ret, arg);
1526 d2604285 aurel32
#else
1527 e8996ee0 bellard
    tcg_gen_xori_i32(ret, arg, -1);
1528 d2604285 aurel32
#endif
1529 0b6ce4cf bellard
}
1530 0b6ce4cf bellard
1531 a7812ae4 pbrook
static inline void tcg_gen_not_i64(TCGv_i64 ret, TCGv_i64 arg)
1532 0b6ce4cf bellard
{
1533 d2604285 aurel32
#ifdef TCG_TARGET_HAS_not_i64
1534 43e860ef aurel32
    tcg_gen_op2_i64(INDEX_op_not_i64, ret, arg);
1535 d2604285 aurel32
#else
1536 e8996ee0 bellard
    tcg_gen_xori_i64(ret, arg, -1);
1537 d2604285 aurel32
#endif
1538 0b6ce4cf bellard
}
1539 5ff9d6a4 bellard
1540 a7812ae4 pbrook
static inline void tcg_gen_discard_i32(TCGv_i32 arg)
1541 5ff9d6a4 bellard
{
1542 a7812ae4 pbrook
    tcg_gen_op1_i32(INDEX_op_discard, arg);
1543 5ff9d6a4 bellard
}
1544 5ff9d6a4 bellard
1545 5ff9d6a4 bellard
#if TCG_TARGET_REG_BITS == 32
1546 a7812ae4 pbrook
static inline void tcg_gen_discard_i64(TCGv_i64 arg)
1547 5ff9d6a4 bellard
{
1548 a7812ae4 pbrook
    tcg_gen_discard_i32(TCGV_LOW(arg));
1549 5ff9d6a4 bellard
    tcg_gen_discard_i32(TCGV_HIGH(arg));
1550 5ff9d6a4 bellard
}
1551 5ff9d6a4 bellard
#else
1552 a7812ae4 pbrook
static inline void tcg_gen_discard_i64(TCGv_i64 arg)
1553 5ff9d6a4 bellard
{
1554 a7812ae4 pbrook
    tcg_gen_op1_i64(INDEX_op_discard, arg);
1555 5ff9d6a4 bellard
}
1556 5ff9d6a4 bellard
#endif
1557 5ff9d6a4 bellard
1558 a7812ae4 pbrook
static inline void tcg_gen_concat_i32_i64(TCGv_i64 dest, TCGv_i32 low, TCGv_i32 high)
1559 36aa55dc pbrook
{
1560 36aa55dc pbrook
#if TCG_TARGET_REG_BITS == 32
1561 a7812ae4 pbrook
    tcg_gen_mov_i32(TCGV_LOW(dest), low);
1562 36aa55dc pbrook
    tcg_gen_mov_i32(TCGV_HIGH(dest), high);
1563 36aa55dc pbrook
#else
1564 a7812ae4 pbrook
    TCGv_i64 tmp = tcg_temp_new_i64();
1565 36aa55dc pbrook
    /* This extension is only needed for type correctness.
1566 36aa55dc pbrook
       We may be able to do better given target specific information.  */
1567 36aa55dc pbrook
    tcg_gen_extu_i32_i64(tmp, high);
1568 36aa55dc pbrook
    tcg_gen_shli_i64(tmp, tmp, 32);
1569 36aa55dc pbrook
    tcg_gen_extu_i32_i64(dest, low);
1570 36aa55dc pbrook
    tcg_gen_or_i64(dest, dest, tmp);
1571 a7812ae4 pbrook
    tcg_temp_free_i64(tmp);
1572 36aa55dc pbrook
#endif
1573 36aa55dc pbrook
}
1574 36aa55dc pbrook
1575 a7812ae4 pbrook
static inline void tcg_gen_concat32_i64(TCGv_i64 dest, TCGv_i64 low, TCGv_i64 high)
1576 945ca823 blueswir1
{
1577 945ca823 blueswir1
#if TCG_TARGET_REG_BITS == 32
1578 a7812ae4 pbrook
    tcg_gen_concat_i32_i64(dest, TCGV_LOW(low), TCGV_LOW(high));
1579 945ca823 blueswir1
#else
1580 a7812ae4 pbrook
    TCGv_i64 tmp = tcg_temp_new_i64();
1581 88422e2e pbrook
    tcg_gen_ext32u_i64(dest, low);
1582 945ca823 blueswir1
    tcg_gen_shli_i64(tmp, high, 32);
1583 88422e2e pbrook
    tcg_gen_or_i64(dest, dest, tmp);
1584 a7812ae4 pbrook
    tcg_temp_free_i64(tmp);
1585 945ca823 blueswir1
#endif
1586 945ca823 blueswir1
}
1587 945ca823 blueswir1
1588 a7812ae4 pbrook
static inline void tcg_gen_andc_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2)
1589 f24cb33e aurel32
{
1590 a7812ae4 pbrook
    TCGv_i32 t0;
1591 a7812ae4 pbrook
    t0 = tcg_temp_new_i32();
1592 f24cb33e aurel32
    tcg_gen_not_i32(t0, arg2);
1593 f24cb33e aurel32
    tcg_gen_and_i32(ret, arg1, t0);
1594 a7812ae4 pbrook
    tcg_temp_free_i32(t0);
1595 f24cb33e aurel32
}
1596 f24cb33e aurel32
1597 a7812ae4 pbrook
static inline void tcg_gen_andc_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2)
1598 f24cb33e aurel32
{
1599 a7812ae4 pbrook
    TCGv_i64 t0;
1600 a7812ae4 pbrook
    t0 = tcg_temp_new_i64();
1601 f24cb33e aurel32
    tcg_gen_not_i64(t0, arg2);
1602 f24cb33e aurel32
    tcg_gen_and_i64(ret, arg1, t0);
1603 a7812ae4 pbrook
    tcg_temp_free_i64(t0);
1604 f24cb33e aurel32
}
1605 f24cb33e aurel32
1606 a7812ae4 pbrook
static inline void tcg_gen_eqv_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2)
1607 f24cb33e aurel32
{
1608 7fc81051 aurel32
    tcg_gen_xor_i32(ret, arg1, arg2);
1609 7fc81051 aurel32
    tcg_gen_not_i32(ret, ret);
1610 f24cb33e aurel32
}
1611 f24cb33e aurel32
1612 a7812ae4 pbrook
static inline void tcg_gen_eqv_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2)
1613 f24cb33e aurel32
{
1614 7fc81051 aurel32
    tcg_gen_xor_i64(ret, arg1, arg2);
1615 7fc81051 aurel32
    tcg_gen_not_i64(ret, ret);
1616 f24cb33e aurel32
}
1617 f24cb33e aurel32
1618 a7812ae4 pbrook
static inline void tcg_gen_nand_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2)
1619 f24cb33e aurel32
{
1620 7fc81051 aurel32
    tcg_gen_and_i32(ret, arg1, arg2);
1621 7fc81051 aurel32
    tcg_gen_not_i32(ret, ret);
1622 f24cb33e aurel32
}
1623 f24cb33e aurel32
1624 a7812ae4 pbrook
static inline void tcg_gen_nand_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2)
1625 f24cb33e aurel32
{
1626 7fc81051 aurel32
    tcg_gen_and_i64(ret, arg1, arg2);
1627 7fc81051 aurel32
    tcg_gen_not_i64(ret, ret);
1628 f24cb33e aurel32
}
1629 f24cb33e aurel32
1630 a7812ae4 pbrook
static inline void tcg_gen_nor_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2)
1631 f24cb33e aurel32
{
1632 7fc81051 aurel32
    tcg_gen_or_i32(ret, arg1, arg2);
1633 7fc81051 aurel32
    tcg_gen_not_i32(ret, ret);
1634 f24cb33e aurel32
}
1635 f24cb33e aurel32
1636 a7812ae4 pbrook
static inline void tcg_gen_nor_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2)
1637 f24cb33e aurel32
{
1638 7fc81051 aurel32
    tcg_gen_or_i64(ret, arg1, arg2);
1639 7fc81051 aurel32
    tcg_gen_not_i64(ret, ret);
1640 f24cb33e aurel32
}
1641 f24cb33e aurel32
1642 a7812ae4 pbrook
static inline void tcg_gen_orc_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2)
1643 f24cb33e aurel32
{
1644 a7812ae4 pbrook
    TCGv_i32 t0;
1645 a7812ae4 pbrook
    t0 = tcg_temp_new_i32();
1646 f24cb33e aurel32
    tcg_gen_not_i32(t0, arg2);
1647 f24cb33e aurel32
    tcg_gen_or_i32(ret, arg1, t0);
1648 a7812ae4 pbrook
    tcg_temp_free_i32(t0);
1649 f24cb33e aurel32
}
1650 f24cb33e aurel32
1651 a7812ae4 pbrook
static inline void tcg_gen_orc_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2)
1652 f24cb33e aurel32
{
1653 a7812ae4 pbrook
    TCGv_i64 t0;
1654 a7812ae4 pbrook
    t0 = tcg_temp_new_i64();
1655 f24cb33e aurel32
    tcg_gen_not_i64(t0, arg2);
1656 f24cb33e aurel32
    tcg_gen_or_i64(ret, arg1, t0);
1657 a7812ae4 pbrook
    tcg_temp_free_i64(t0);
1658 f24cb33e aurel32
}
1659 f24cb33e aurel32
1660 a7812ae4 pbrook
static inline void tcg_gen_rotl_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2)
1661 15824571 aurel32
{
1662 d42f183c aurel32
#ifdef TCG_TARGET_HAS_rot_i32
1663 d42f183c aurel32
    tcg_gen_op3_i32(INDEX_op_rotl_i32, ret, arg1, arg2);
1664 d42f183c aurel32
#else
1665 a7812ae4 pbrook
    TCGv_i32 t0, t1;
1666 15824571 aurel32
1667 a7812ae4 pbrook
    t0 = tcg_temp_new_i32();
1668 a7812ae4 pbrook
    t1 = tcg_temp_new_i32();
1669 15824571 aurel32
    tcg_gen_shl_i32(t0, arg1, arg2);
1670 15824571 aurel32
    tcg_gen_subfi_i32(t1, 32, arg2);
1671 15824571 aurel32
    tcg_gen_shr_i32(t1, arg1, t1);
1672 15824571 aurel32
    tcg_gen_or_i32(ret, t0, t1);
1673 a7812ae4 pbrook
    tcg_temp_free_i32(t0);
1674 a7812ae4 pbrook
    tcg_temp_free_i32(t1);
1675 d42f183c aurel32
#endif
1676 15824571 aurel32
}
1677 15824571 aurel32
1678 a7812ae4 pbrook
static inline void tcg_gen_rotl_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2)
1679 15824571 aurel32
{
1680 d42f183c aurel32
#ifdef TCG_TARGET_HAS_rot_i64
1681 d42f183c aurel32
    tcg_gen_op3_i64(INDEX_op_rotl_i64, ret, arg1, arg2);
1682 d42f183c aurel32
#else
1683 a7812ae4 pbrook
    TCGv_i64 t0, t1;
1684 15824571 aurel32
1685 a7812ae4 pbrook
    t0 = tcg_temp_new_i64();
1686 a7812ae4 pbrook
    t1 = tcg_temp_new_i64();
1687 15824571 aurel32
    tcg_gen_shl_i64(t0, arg1, arg2);
1688 15824571 aurel32
    tcg_gen_subfi_i64(t1, 64, arg2);
1689 15824571 aurel32
    tcg_gen_shr_i64(t1, arg1, t1);
1690 15824571 aurel32
    tcg_gen_or_i64(ret, t0, t1);
1691 a7812ae4 pbrook
    tcg_temp_free_i64(t0);
1692 a7812ae4 pbrook
    tcg_temp_free_i64(t1);
1693 d42f183c aurel32
#endif
1694 15824571 aurel32
}
1695 15824571 aurel32
1696 a7812ae4 pbrook
static inline void tcg_gen_rotli_i32(TCGv_i32 ret, TCGv_i32 arg1, int32_t arg2)
1697 15824571 aurel32
{
1698 15824571 aurel32
    /* some cases can be optimized here */
1699 15824571 aurel32
    if (arg2 == 0) {
1700 15824571 aurel32
        tcg_gen_mov_i32(ret, arg1);
1701 15824571 aurel32
    } else {
1702 d42f183c aurel32
#ifdef TCG_TARGET_HAS_rot_i32
1703 d42f183c aurel32
        TCGv_i32 t0 = tcg_const_i32(arg2);
1704 d42f183c aurel32
        tcg_gen_rotl_i32(ret, arg1, t0);
1705 d42f183c aurel32
        tcg_temp_free_i32(t0);
1706 d42f183c aurel32
#else
1707 a7812ae4 pbrook
        TCGv_i32 t0, t1;
1708 a7812ae4 pbrook
        t0 = tcg_temp_new_i32();
1709 a7812ae4 pbrook
        t1 = tcg_temp_new_i32();
1710 15824571 aurel32
        tcg_gen_shli_i32(t0, arg1, arg2);
1711 15824571 aurel32
        tcg_gen_shri_i32(t1, arg1, 32 - arg2);
1712 15824571 aurel32
        tcg_gen_or_i32(ret, t0, t1);
1713 a7812ae4 pbrook
        tcg_temp_free_i32(t0);
1714 a7812ae4 pbrook
        tcg_temp_free_i32(t1);
1715 d42f183c aurel32
#endif
1716 15824571 aurel32
    }
1717 15824571 aurel32
}
1718 15824571 aurel32
1719 a7812ae4 pbrook
static inline void tcg_gen_rotli_i64(TCGv_i64 ret, TCGv_i64 arg1, int64_t arg2)
1720 15824571 aurel32
{
1721 15824571 aurel32
    /* some cases can be optimized here */
1722 15824571 aurel32
    if (arg2 == 0) {
1723 15824571 aurel32
        tcg_gen_mov_i64(ret, arg1);
1724 15824571 aurel32
    } else {
1725 d42f183c aurel32
#ifdef TCG_TARGET_HAS_rot_i64
1726 d42f183c aurel32
        TCGv_i64 t0 = tcg_const_i64(arg2);
1727 d42f183c aurel32
        tcg_gen_rotl_i64(ret, arg1, t0);
1728 d42f183c aurel32
        tcg_temp_free_i64(t0);
1729 d42f183c aurel32
#else
1730 a7812ae4 pbrook
        TCGv_i64 t0, t1;
1731 a7812ae4 pbrook
        t0 = tcg_temp_new_i64();
1732 a7812ae4 pbrook
        t1 = tcg_temp_new_i64();
1733 15824571 aurel32
        tcg_gen_shli_i64(t0, arg1, arg2);
1734 15824571 aurel32
        tcg_gen_shri_i64(t1, arg1, 64 - arg2);
1735 15824571 aurel32
        tcg_gen_or_i64(ret, t0, t1);
1736 a7812ae4 pbrook
        tcg_temp_free_i64(t0);
1737 a7812ae4 pbrook
        tcg_temp_free_i64(t1);
1738 d42f183c aurel32
#endif
1739 15824571 aurel32
    }
1740 15824571 aurel32
}
1741 15824571 aurel32
1742 a7812ae4 pbrook
static inline void tcg_gen_rotr_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2)
1743 15824571 aurel32
{
1744 d42f183c aurel32
#ifdef TCG_TARGET_HAS_rot_i32
1745 d42f183c aurel32
    tcg_gen_op3_i32(INDEX_op_rotr_i32, ret, arg1, arg2);
1746 d42f183c aurel32
#else
1747 a7812ae4 pbrook
    TCGv_i32 t0, t1;
1748 15824571 aurel32
1749 a7812ae4 pbrook
    t0 = tcg_temp_new_i32();
1750 a7812ae4 pbrook
    t1 = tcg_temp_new_i32();
1751 15824571 aurel32
    tcg_gen_shr_i32(t0, arg1, arg2);
1752 15824571 aurel32
    tcg_gen_subfi_i32(t1, 32, arg2);
1753 15824571 aurel32
    tcg_gen_shl_i32(t1, arg1, t1);
1754 15824571 aurel32
    tcg_gen_or_i32(ret, t0, t1);
1755 a7812ae4 pbrook
    tcg_temp_free_i32(t0);
1756 a7812ae4 pbrook
    tcg_temp_free_i32(t1);
1757 d42f183c aurel32
#endif
1758 15824571 aurel32
}
1759 15824571 aurel32
1760 a7812ae4 pbrook
static inline void tcg_gen_rotr_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2)
1761 15824571 aurel32
{
1762 d42f183c aurel32
#ifdef TCG_TARGET_HAS_rot_i64
1763 d42f183c aurel32
    tcg_gen_op3_i64(INDEX_op_rotr_i64, ret, arg1, arg2);
1764 d42f183c aurel32
#else
1765 a7812ae4 pbrook
    TCGv_i64 t0, t1;
1766 15824571 aurel32
1767 a7812ae4 pbrook
    t0 = tcg_temp_new_i64();
1768 a7812ae4 pbrook
    t1 = tcg_temp_new_i64();
1769 d9885a0b Aurelien Jarno
    tcg_gen_shr_i64(t0, arg1, arg2);
1770 15824571 aurel32
    tcg_gen_subfi_i64(t1, 64, arg2);
1771 15824571 aurel32
    tcg_gen_shl_i64(t1, arg1, t1);
1772 15824571 aurel32
    tcg_gen_or_i64(ret, t0, t1);
1773 a7812ae4 pbrook
    tcg_temp_free_i64(t0);
1774 a7812ae4 pbrook
    tcg_temp_free_i64(t1);
1775 d42f183c aurel32
#endif
1776 15824571 aurel32
}
1777 15824571 aurel32
1778 a7812ae4 pbrook
static inline void tcg_gen_rotri_i32(TCGv_i32 ret, TCGv_i32 arg1, int32_t arg2)
1779 15824571 aurel32
{
1780 15824571 aurel32
    /* some cases can be optimized here */
1781 15824571 aurel32
    if (arg2 == 0) {
1782 15824571 aurel32
        tcg_gen_mov_i32(ret, arg1);
1783 15824571 aurel32
    } else {
1784 15824571 aurel32
        tcg_gen_rotli_i32(ret, arg1, 32 - arg2);
1785 15824571 aurel32
    }
1786 15824571 aurel32
}
1787 15824571 aurel32
1788 a7812ae4 pbrook
static inline void tcg_gen_rotri_i64(TCGv_i64 ret, TCGv_i64 arg1, int64_t arg2)
1789 15824571 aurel32
{
1790 15824571 aurel32
    /* some cases can be optimized here */
1791 15824571 aurel32
    if (arg2 == 0) {
1792 de3526b2 pbrook
        tcg_gen_mov_i64(ret, arg1);
1793 15824571 aurel32
    } else {
1794 15824571 aurel32
        tcg_gen_rotli_i64(ret, arg1, 64 - arg2);
1795 15824571 aurel32
    }
1796 15824571 aurel32
}
1797 15824571 aurel32
1798 c896fe29 bellard
/***************************************/
1799 c896fe29 bellard
/* QEMU specific operations. Their type depend on the QEMU CPU
1800 c896fe29 bellard
   type. */
1801 c896fe29 bellard
#ifndef TARGET_LONG_BITS
1802 c896fe29 bellard
#error must include QEMU headers
1803 c896fe29 bellard
#endif
1804 c896fe29 bellard
1805 a7812ae4 pbrook
#if TARGET_LONG_BITS == 32
1806 a7812ae4 pbrook
#define TCGv TCGv_i32
1807 a7812ae4 pbrook
#define tcg_temp_new() tcg_temp_new_i32()
1808 a7812ae4 pbrook
#define tcg_global_reg_new tcg_global_reg_new_i32
1809 a7812ae4 pbrook
#define tcg_global_mem_new tcg_global_mem_new_i32
1810 df9247b2 aurel32
#define tcg_temp_local_new() tcg_temp_local_new_i32()
1811 a7812ae4 pbrook
#define tcg_temp_free tcg_temp_free_i32
1812 a7812ae4 pbrook
#define tcg_gen_qemu_ldst_op tcg_gen_op3i_i32
1813 a7812ae4 pbrook
#define tcg_gen_qemu_ldst_op_i64 tcg_gen_qemu_ldst_op_i64_i32
1814 a7812ae4 pbrook
#define TCGV_UNUSED(x) TCGV_UNUSED_I32(x)
1815 fe75bcf7 aurel32
#define TCGV_EQUAL(a, b) TCGV_EQUAL_I32(a, b)
1816 a7812ae4 pbrook
#else
1817 a7812ae4 pbrook
#define TCGv TCGv_i64
1818 a7812ae4 pbrook
#define tcg_temp_new() tcg_temp_new_i64()
1819 a7812ae4 pbrook
#define tcg_global_reg_new tcg_global_reg_new_i64
1820 a7812ae4 pbrook
#define tcg_global_mem_new tcg_global_mem_new_i64
1821 df9247b2 aurel32
#define tcg_temp_local_new() tcg_temp_local_new_i64()
1822 a7812ae4 pbrook
#define tcg_temp_free tcg_temp_free_i64
1823 a7812ae4 pbrook
#define tcg_gen_qemu_ldst_op tcg_gen_op3i_i64
1824 a7812ae4 pbrook
#define tcg_gen_qemu_ldst_op_i64 tcg_gen_qemu_ldst_op_i64_i64
1825 a7812ae4 pbrook
#define TCGV_UNUSED(x) TCGV_UNUSED_I64(x)
1826 fe75bcf7 aurel32
#define TCGV_EQUAL(a, b) TCGV_EQUAL_I64(a, b)
1827 a7812ae4 pbrook
#endif
1828 a7812ae4 pbrook
1829 7e4597d7 bellard
/* debug info: write the PC of the corresponding QEMU CPU instruction */
1830 7e4597d7 bellard
static inline void tcg_gen_debug_insn_start(uint64_t pc)
1831 7e4597d7 bellard
{
1832 7e4597d7 bellard
    /* XXX: must really use a 32 bit size for TCGArg in all cases */
1833 7e4597d7 bellard
#if TARGET_LONG_BITS > TCG_TARGET_REG_BITS
1834 bcb0126f pbrook
    tcg_gen_op2ii(INDEX_op_debug_insn_start, 
1835 bcb0126f pbrook
                  (uint32_t)(pc), (uint32_t)(pc >> 32));
1836 7e4597d7 bellard
#else
1837 7e4597d7 bellard
    tcg_gen_op1i(INDEX_op_debug_insn_start, pc);
1838 7e4597d7 bellard
#endif
1839 7e4597d7 bellard
}
1840 7e4597d7 bellard
1841 c896fe29 bellard
static inline void tcg_gen_exit_tb(tcg_target_long val)
1842 c896fe29 bellard
{
1843 ac56dd48 pbrook
    tcg_gen_op1i(INDEX_op_exit_tb, val);
1844 c896fe29 bellard
}
1845 c896fe29 bellard
1846 c896fe29 bellard
static inline void tcg_gen_goto_tb(int idx)
1847 c896fe29 bellard
{
1848 ac56dd48 pbrook
    tcg_gen_op1i(INDEX_op_goto_tb, idx);
1849 c896fe29 bellard
}
1850 c896fe29 bellard
1851 c896fe29 bellard
#if TCG_TARGET_REG_BITS == 32
1852 ac56dd48 pbrook
static inline void tcg_gen_qemu_ld8u(TCGv ret, TCGv addr, int mem_index)
1853 c896fe29 bellard
{
1854 c896fe29 bellard
#if TARGET_LONG_BITS == 32
1855 a7812ae4 pbrook
    tcg_gen_op3i_i32(INDEX_op_qemu_ld8u, ret, addr, mem_index);
1856 c896fe29 bellard
#else
1857 a7812ae4 pbrook
    tcg_gen_op4i_i32(INDEX_op_qemu_ld8u, TCGV_LOW(ret), TCGV_LOW(addr),
1858 a7812ae4 pbrook
                     TCGV_HIGH(addr), mem_index);
1859 ac56dd48 pbrook
    tcg_gen_movi_i32(TCGV_HIGH(ret), 0);
1860 c896fe29 bellard
#endif
1861 c896fe29 bellard
}
1862 c896fe29 bellard
1863 ac56dd48 pbrook
static inline void tcg_gen_qemu_ld8s(TCGv ret, TCGv addr, int mem_index)
1864 c896fe29 bellard
{
1865 c896fe29 bellard
#if TARGET_LONG_BITS == 32
1866 a7812ae4 pbrook
    tcg_gen_op3i_i32(INDEX_op_qemu_ld8s, ret, addr, mem_index);
1867 c896fe29 bellard
#else
1868 a7812ae4 pbrook
    tcg_gen_op4i_i32(INDEX_op_qemu_ld8s, TCGV_LOW(ret), TCGV_LOW(addr),
1869 a7812ae4 pbrook
                     TCGV_HIGH(addr), mem_index);
1870 a7812ae4 pbrook
    tcg_gen_sari_i32(TCGV_HIGH(ret), TCGV_LOW(ret), 31);
1871 c896fe29 bellard
#endif
1872 c896fe29 bellard
}
1873 c896fe29 bellard
1874 ac56dd48 pbrook
static inline void tcg_gen_qemu_ld16u(TCGv ret, TCGv addr, int mem_index)
1875 c896fe29 bellard
{
1876 c896fe29 bellard
#if TARGET_LONG_BITS == 32
1877 a7812ae4 pbrook
    tcg_gen_op3i_i32(INDEX_op_qemu_ld16u, ret, addr, mem_index);
1878 c896fe29 bellard
#else
1879 a7812ae4 pbrook
    tcg_gen_op4i_i32(INDEX_op_qemu_ld16u, TCGV_LOW(ret), TCGV_LOW(addr),
1880 a7812ae4 pbrook
                     TCGV_HIGH(addr), mem_index);
1881 ac56dd48 pbrook
    tcg_gen_movi_i32(TCGV_HIGH(ret), 0);
1882 c896fe29 bellard
#endif
1883 c896fe29 bellard
}
1884 c896fe29 bellard
1885 ac56dd48 pbrook
static inline void tcg_gen_qemu_ld16s(TCGv ret, TCGv addr, int mem_index)
1886 c896fe29 bellard
{
1887 c896fe29 bellard
#if TARGET_LONG_BITS == 32
1888 a7812ae4 pbrook
    tcg_gen_op3i_i32(INDEX_op_qemu_ld16s, ret, addr, mem_index);
1889 c896fe29 bellard
#else
1890 a7812ae4 pbrook
    tcg_gen_op4i_i32(INDEX_op_qemu_ld16s, TCGV_LOW(ret), TCGV_LOW(addr),
1891 a7812ae4 pbrook
                     TCGV_HIGH(addr), mem_index);
1892 a7812ae4 pbrook
    tcg_gen_sari_i32(TCGV_HIGH(ret), TCGV_LOW(ret), 31);
1893 c896fe29 bellard
#endif
1894 c896fe29 bellard
}
1895 c896fe29 bellard
1896 ac56dd48 pbrook
static inline void tcg_gen_qemu_ld32u(TCGv ret, TCGv addr, int mem_index)
1897 c896fe29 bellard
{
1898 c896fe29 bellard
#if TARGET_LONG_BITS == 32
1899 a7812ae4 pbrook
    tcg_gen_op3i_i32(INDEX_op_qemu_ld32u, ret, addr, mem_index);
1900 c896fe29 bellard
#else
1901 a7812ae4 pbrook
    tcg_gen_op4i_i32(INDEX_op_qemu_ld32u, TCGV_LOW(ret), TCGV_LOW(addr),
1902 a7812ae4 pbrook
                     TCGV_HIGH(addr), mem_index);
1903 ac56dd48 pbrook
    tcg_gen_movi_i32(TCGV_HIGH(ret), 0);
1904 c896fe29 bellard
#endif
1905 c896fe29 bellard
}
1906 c896fe29 bellard
1907 ac56dd48 pbrook
static inline void tcg_gen_qemu_ld32s(TCGv ret, TCGv addr, int mem_index)
1908 c896fe29 bellard
{
1909 c896fe29 bellard
#if TARGET_LONG_BITS == 32
1910 a7812ae4 pbrook
    tcg_gen_op3i_i32(INDEX_op_qemu_ld32u, ret, addr, mem_index);
1911 c896fe29 bellard
#else
1912 a7812ae4 pbrook
    tcg_gen_op4i_i32(INDEX_op_qemu_ld32u, TCGV_LOW(ret), TCGV_LOW(addr),
1913 a7812ae4 pbrook
                     TCGV_HIGH(addr), mem_index);
1914 a7812ae4 pbrook
    tcg_gen_sari_i32(TCGV_HIGH(ret), TCGV_LOW(ret), 31);
1915 c896fe29 bellard
#endif
1916 c896fe29 bellard
}
1917 c896fe29 bellard
1918 a7812ae4 pbrook
static inline void tcg_gen_qemu_ld64(TCGv_i64 ret, TCGv addr, int mem_index)
1919 c896fe29 bellard
{
1920 c896fe29 bellard
#if TARGET_LONG_BITS == 32
1921 a7812ae4 pbrook
    tcg_gen_op4i_i32(INDEX_op_qemu_ld64, TCGV_LOW(ret), TCGV_HIGH(ret), addr, mem_index);
1922 c896fe29 bellard
#else
1923 a7812ae4 pbrook
    tcg_gen_op5i_i32(INDEX_op_qemu_ld64, TCGV_LOW(ret), TCGV_HIGH(ret),
1924 a7812ae4 pbrook
                     TCGV_LOW(addr), TCGV_HIGH(addr), mem_index);
1925 c896fe29 bellard
#endif
1926 c896fe29 bellard
}
1927 c896fe29 bellard
1928 ac56dd48 pbrook
static inline void tcg_gen_qemu_st8(TCGv arg, TCGv addr, int mem_index)
1929 c896fe29 bellard
{
1930 c896fe29 bellard
#if TARGET_LONG_BITS == 32
1931 a7812ae4 pbrook
    tcg_gen_op3i_i32(INDEX_op_qemu_st8, arg, addr, mem_index);
1932 c896fe29 bellard
#else
1933 a7812ae4 pbrook
    tcg_gen_op4i_i32(INDEX_op_qemu_st8, TCGV_LOW(arg), TCGV_LOW(addr),
1934 a7812ae4 pbrook
                     TCGV_HIGH(addr), mem_index);
1935 c896fe29 bellard
#endif
1936 c896fe29 bellard
}
1937 c896fe29 bellard
1938 ac56dd48 pbrook
static inline void tcg_gen_qemu_st16(TCGv arg, TCGv addr, int mem_index)
1939 c896fe29 bellard
{
1940 c896fe29 bellard
#if TARGET_LONG_BITS == 32
1941 a7812ae4 pbrook
    tcg_gen_op3i_i32(INDEX_op_qemu_st16, arg, addr, mem_index);
1942 c896fe29 bellard
#else
1943 a7812ae4 pbrook
    tcg_gen_op4i_i32(INDEX_op_qemu_st16, TCGV_LOW(arg), TCGV_LOW(addr),
1944 a7812ae4 pbrook
                     TCGV_HIGH(addr), mem_index);
1945 c896fe29 bellard
#endif
1946 c896fe29 bellard
}
1947 c896fe29 bellard
1948 ac56dd48 pbrook
static inline void tcg_gen_qemu_st32(TCGv arg, TCGv addr, int mem_index)
1949 c896fe29 bellard
{
1950 c896fe29 bellard
#if TARGET_LONG_BITS == 32
1951 a7812ae4 pbrook
    tcg_gen_op3i_i32(INDEX_op_qemu_st32, arg, addr, mem_index);
1952 c896fe29 bellard
#else
1953 a7812ae4 pbrook
    tcg_gen_op4i_i32(INDEX_op_qemu_st32, TCGV_LOW(arg), TCGV_LOW(addr),
1954 a7812ae4 pbrook
                     TCGV_HIGH(addr), mem_index);
1955 c896fe29 bellard
#endif
1956 c896fe29 bellard
}
1957 c896fe29 bellard
1958 a7812ae4 pbrook
static inline void tcg_gen_qemu_st64(TCGv_i64 arg, TCGv addr, int mem_index)
1959 c896fe29 bellard
{
1960 c896fe29 bellard
#if TARGET_LONG_BITS == 32
1961 a7812ae4 pbrook
    tcg_gen_op4i_i32(INDEX_op_qemu_st64, TCGV_LOW(arg), TCGV_HIGH(arg), addr,
1962 a7812ae4 pbrook
                     mem_index);
1963 c896fe29 bellard
#else
1964 a7812ae4 pbrook
    tcg_gen_op5i_i32(INDEX_op_qemu_st64, TCGV_LOW(arg), TCGV_HIGH(arg),
1965 a7812ae4 pbrook
                     TCGV_LOW(addr), TCGV_HIGH(addr), mem_index);
1966 c896fe29 bellard
#endif
1967 c896fe29 bellard
}
1968 c896fe29 bellard
1969 56b8f567 blueswir1
#define tcg_gen_ld_ptr tcg_gen_ld_i32
1970 a768e4b2 blueswir1
#define tcg_gen_discard_ptr tcg_gen_discard_i32
1971 f8422f52 blueswir1
1972 c896fe29 bellard
#else /* TCG_TARGET_REG_BITS == 32 */
1973 c896fe29 bellard
1974 ac56dd48 pbrook
static inline void tcg_gen_qemu_ld8u(TCGv ret, TCGv addr, int mem_index)
1975 c896fe29 bellard
{
1976 a7812ae4 pbrook
    tcg_gen_qemu_ldst_op(INDEX_op_qemu_ld8u, ret, addr, mem_index);
1977 c896fe29 bellard
}
1978 c896fe29 bellard
1979 ac56dd48 pbrook
static inline void tcg_gen_qemu_ld8s(TCGv ret, TCGv addr, int mem_index)
1980 c896fe29 bellard
{
1981 a7812ae4 pbrook
    tcg_gen_qemu_ldst_op(INDEX_op_qemu_ld8s, ret, addr, mem_index);
1982 c896fe29 bellard
}
1983 c896fe29 bellard
1984 ac56dd48 pbrook
static inline void tcg_gen_qemu_ld16u(TCGv ret, TCGv addr, int mem_index)
1985 c896fe29 bellard
{
1986 a7812ae4 pbrook
    tcg_gen_qemu_ldst_op(INDEX_op_qemu_ld16u, ret, addr, mem_index);
1987 c896fe29 bellard
}
1988 c896fe29 bellard
1989 ac56dd48 pbrook
static inline void tcg_gen_qemu_ld16s(TCGv ret, TCGv addr, int mem_index)
1990 c896fe29 bellard
{
1991 a7812ae4 pbrook
    tcg_gen_qemu_ldst_op(INDEX_op_qemu_ld16s, ret, addr, mem_index);
1992 c896fe29 bellard
}
1993 c896fe29 bellard
1994 ac56dd48 pbrook
static inline void tcg_gen_qemu_ld32u(TCGv ret, TCGv addr, int mem_index)
1995 c896fe29 bellard
{
1996 a7812ae4 pbrook
    tcg_gen_qemu_ldst_op(INDEX_op_qemu_ld32u, ret, addr, mem_index);
1997 c896fe29 bellard
}
1998 c896fe29 bellard
1999 ac56dd48 pbrook
static inline void tcg_gen_qemu_ld32s(TCGv ret, TCGv addr, int mem_index)
2000 c896fe29 bellard
{
2001 a7812ae4 pbrook
    tcg_gen_qemu_ldst_op(INDEX_op_qemu_ld32s, ret, addr, mem_index);
2002 c896fe29 bellard
}
2003 c896fe29 bellard
2004 a7812ae4 pbrook
static inline void tcg_gen_qemu_ld64(TCGv_i64 ret, TCGv addr, int mem_index)
2005 c896fe29 bellard
{
2006 a7812ae4 pbrook
    tcg_gen_qemu_ldst_op_i64(INDEX_op_qemu_ld64, ret, addr, mem_index);
2007 c896fe29 bellard
}
2008 c896fe29 bellard
2009 ac56dd48 pbrook
static inline void tcg_gen_qemu_st8(TCGv arg, TCGv addr, int mem_index)
2010 c896fe29 bellard
{
2011 a7812ae4 pbrook
    tcg_gen_qemu_ldst_op(INDEX_op_qemu_st8, arg, addr, mem_index);
2012 c896fe29 bellard
}
2013 c896fe29 bellard
2014 ac56dd48 pbrook
static inline void tcg_gen_qemu_st16(TCGv arg, TCGv addr, int mem_index)
2015 c896fe29 bellard
{
2016 a7812ae4 pbrook
    tcg_gen_qemu_ldst_op(INDEX_op_qemu_st16, arg, addr, mem_index);
2017 c896fe29 bellard
}
2018 c896fe29 bellard
2019 ac56dd48 pbrook
static inline void tcg_gen_qemu_st32(TCGv arg, TCGv addr, int mem_index)
2020 c896fe29 bellard
{
2021 a7812ae4 pbrook
    tcg_gen_qemu_ldst_op(INDEX_op_qemu_st32, arg, addr, mem_index);
2022 c896fe29 bellard
}
2023 c896fe29 bellard
2024 a7812ae4 pbrook
static inline void tcg_gen_qemu_st64(TCGv_i64 arg, TCGv addr, int mem_index)
2025 c896fe29 bellard
{
2026 a7812ae4 pbrook
    tcg_gen_qemu_ldst_op_i64(INDEX_op_qemu_st64, arg, addr, mem_index);
2027 c896fe29 bellard
}
2028 c896fe29 bellard
2029 56b8f567 blueswir1
#define tcg_gen_ld_ptr tcg_gen_ld_i64
2030 a768e4b2 blueswir1
#define tcg_gen_discard_ptr tcg_gen_discard_i64
2031 f8422f52 blueswir1
2032 c896fe29 bellard
#endif /* TCG_TARGET_REG_BITS != 32 */
2033 f8422f52 blueswir1
2034 f8422f52 blueswir1
#if TARGET_LONG_BITS == 64
2035 f8422f52 blueswir1
#define TCG_TYPE_TL TCG_TYPE_I64
2036 f8422f52 blueswir1
#define tcg_gen_movi_tl tcg_gen_movi_i64
2037 f8422f52 blueswir1
#define tcg_gen_mov_tl tcg_gen_mov_i64
2038 f8422f52 blueswir1
#define tcg_gen_ld8u_tl tcg_gen_ld8u_i64
2039 f8422f52 blueswir1
#define tcg_gen_ld8s_tl tcg_gen_ld8s_i64
2040 f8422f52 blueswir1
#define tcg_gen_ld16u_tl tcg_gen_ld16u_i64
2041 f8422f52 blueswir1
#define tcg_gen_ld16s_tl tcg_gen_ld16s_i64
2042 f8422f52 blueswir1
#define tcg_gen_ld32u_tl tcg_gen_ld32u_i64
2043 f8422f52 blueswir1
#define tcg_gen_ld32s_tl tcg_gen_ld32s_i64
2044 f8422f52 blueswir1
#define tcg_gen_ld_tl tcg_gen_ld_i64
2045 f8422f52 blueswir1
#define tcg_gen_st8_tl tcg_gen_st8_i64
2046 f8422f52 blueswir1
#define tcg_gen_st16_tl tcg_gen_st16_i64
2047 f8422f52 blueswir1
#define tcg_gen_st32_tl tcg_gen_st32_i64
2048 f8422f52 blueswir1
#define tcg_gen_st_tl tcg_gen_st_i64
2049 f8422f52 blueswir1
#define tcg_gen_add_tl tcg_gen_add_i64
2050 f8422f52 blueswir1
#define tcg_gen_addi_tl tcg_gen_addi_i64
2051 f8422f52 blueswir1
#define tcg_gen_sub_tl tcg_gen_sub_i64
2052 390efc54 pbrook
#define tcg_gen_neg_tl tcg_gen_neg_i64
2053 10460c8a pbrook
#define tcg_gen_subfi_tl tcg_gen_subfi_i64
2054 f8422f52 blueswir1
#define tcg_gen_subi_tl tcg_gen_subi_i64
2055 f8422f52 blueswir1
#define tcg_gen_and_tl tcg_gen_and_i64
2056 f8422f52 blueswir1
#define tcg_gen_andi_tl tcg_gen_andi_i64
2057 f8422f52 blueswir1
#define tcg_gen_or_tl tcg_gen_or_i64
2058 f8422f52 blueswir1
#define tcg_gen_ori_tl tcg_gen_ori_i64
2059 f8422f52 blueswir1
#define tcg_gen_xor_tl tcg_gen_xor_i64
2060 f8422f52 blueswir1
#define tcg_gen_xori_tl tcg_gen_xori_i64
2061 0b6ce4cf bellard
#define tcg_gen_not_tl tcg_gen_not_i64
2062 f8422f52 blueswir1
#define tcg_gen_shl_tl tcg_gen_shl_i64
2063 f8422f52 blueswir1
#define tcg_gen_shli_tl tcg_gen_shli_i64
2064 f8422f52 blueswir1
#define tcg_gen_shr_tl tcg_gen_shr_i64
2065 f8422f52 blueswir1
#define tcg_gen_shri_tl tcg_gen_shri_i64
2066 f8422f52 blueswir1
#define tcg_gen_sar_tl tcg_gen_sar_i64
2067 f8422f52 blueswir1
#define tcg_gen_sari_tl tcg_gen_sari_i64
2068 0cf767d6 blueswir1
#define tcg_gen_brcond_tl tcg_gen_brcond_i64
2069 cb63669a pbrook
#define tcg_gen_brcondi_tl tcg_gen_brcondi_i64
2070 f730fd27 ths
#define tcg_gen_mul_tl tcg_gen_mul_i64
2071 f730fd27 ths
#define tcg_gen_muli_tl tcg_gen_muli_i64
2072 ab36421e aurel32
#define tcg_gen_div_tl tcg_gen_div_i64
2073 ab36421e aurel32
#define tcg_gen_rem_tl tcg_gen_rem_i64
2074 864951af aurel32
#define tcg_gen_divu_tl tcg_gen_divu_i64
2075 864951af aurel32
#define tcg_gen_remu_tl tcg_gen_remu_i64
2076 a768e4b2 blueswir1
#define tcg_gen_discard_tl tcg_gen_discard_i64
2077 e429073d blueswir1
#define tcg_gen_trunc_tl_i32 tcg_gen_trunc_i64_i32
2078 e429073d blueswir1
#define tcg_gen_trunc_i64_tl tcg_gen_mov_i64
2079 e429073d blueswir1
#define tcg_gen_extu_i32_tl tcg_gen_extu_i32_i64
2080 e429073d blueswir1
#define tcg_gen_ext_i32_tl tcg_gen_ext_i32_i64
2081 e429073d blueswir1
#define tcg_gen_extu_tl_i64 tcg_gen_mov_i64
2082 e429073d blueswir1
#define tcg_gen_ext_tl_i64 tcg_gen_mov_i64
2083 0b6ce4cf bellard
#define tcg_gen_ext8u_tl tcg_gen_ext8u_i64
2084 0b6ce4cf bellard
#define tcg_gen_ext8s_tl tcg_gen_ext8s_i64
2085 0b6ce4cf bellard
#define tcg_gen_ext16u_tl tcg_gen_ext16u_i64
2086 0b6ce4cf bellard
#define tcg_gen_ext16s_tl tcg_gen_ext16s_i64
2087 0b6ce4cf bellard
#define tcg_gen_ext32u_tl tcg_gen_ext32u_i64
2088 0b6ce4cf bellard
#define tcg_gen_ext32s_tl tcg_gen_ext32s_i64
2089 911d79ba aurel32
#define tcg_gen_bswap16_tl tcg_gen_bswap16_i64
2090 911d79ba aurel32
#define tcg_gen_bswap32_tl tcg_gen_bswap32_i64
2091 911d79ba aurel32
#define tcg_gen_bswap64_tl tcg_gen_bswap64_i64
2092 945ca823 blueswir1
#define tcg_gen_concat_tl_i64 tcg_gen_concat32_i64
2093 f24cb33e aurel32
#define tcg_gen_andc_tl tcg_gen_andc_i64
2094 f24cb33e aurel32
#define tcg_gen_eqv_tl tcg_gen_eqv_i64
2095 f24cb33e aurel32
#define tcg_gen_nand_tl tcg_gen_nand_i64
2096 f24cb33e aurel32
#define tcg_gen_nor_tl tcg_gen_nor_i64
2097 f24cb33e aurel32
#define tcg_gen_orc_tl tcg_gen_orc_i64
2098 15824571 aurel32
#define tcg_gen_rotl_tl tcg_gen_rotl_i64
2099 15824571 aurel32
#define tcg_gen_rotli_tl tcg_gen_rotli_i64
2100 15824571 aurel32
#define tcg_gen_rotr_tl tcg_gen_rotr_i64
2101 15824571 aurel32
#define tcg_gen_rotri_tl tcg_gen_rotri_i64
2102 a98824ac blueswir1
#define tcg_const_tl tcg_const_i64
2103 bdffd4a9 aurel32
#define tcg_const_local_tl tcg_const_local_i64
2104 f8422f52 blueswir1
#else
2105 f8422f52 blueswir1
#define TCG_TYPE_TL TCG_TYPE_I32
2106 f8422f52 blueswir1
#define tcg_gen_movi_tl tcg_gen_movi_i32
2107 f8422f52 blueswir1
#define tcg_gen_mov_tl tcg_gen_mov_i32
2108 f8422f52 blueswir1
#define tcg_gen_ld8u_tl tcg_gen_ld8u_i32
2109 f8422f52 blueswir1
#define tcg_gen_ld8s_tl tcg_gen_ld8s_i32
2110 f8422f52 blueswir1
#define tcg_gen_ld16u_tl tcg_gen_ld16u_i32
2111 f8422f52 blueswir1
#define tcg_gen_ld16s_tl tcg_gen_ld16s_i32
2112 f8422f52 blueswir1
#define tcg_gen_ld32u_tl tcg_gen_ld_i32
2113 f8422f52 blueswir1
#define tcg_gen_ld32s_tl tcg_gen_ld_i32
2114 f8422f52 blueswir1
#define tcg_gen_ld_tl tcg_gen_ld_i32
2115 f8422f52 blueswir1
#define tcg_gen_st8_tl tcg_gen_st8_i32
2116 f8422f52 blueswir1
#define tcg_gen_st16_tl tcg_gen_st16_i32
2117 f8422f52 blueswir1
#define tcg_gen_st32_tl tcg_gen_st_i32
2118 f8422f52 blueswir1
#define tcg_gen_st_tl tcg_gen_st_i32
2119 f8422f52 blueswir1
#define tcg_gen_add_tl tcg_gen_add_i32
2120 f8422f52 blueswir1
#define tcg_gen_addi_tl tcg_gen_addi_i32
2121 f8422f52 blueswir1
#define tcg_gen_sub_tl tcg_gen_sub_i32
2122 390efc54 pbrook
#define tcg_gen_neg_tl tcg_gen_neg_i32
2123 0045734a aurel32
#define tcg_gen_subfi_tl tcg_gen_subfi_i32
2124 f8422f52 blueswir1
#define tcg_gen_subi_tl tcg_gen_subi_i32
2125 f8422f52 blueswir1
#define tcg_gen_and_tl tcg_gen_and_i32
2126 f8422f52 blueswir1
#define tcg_gen_andi_tl tcg_gen_andi_i32
2127 f8422f52 blueswir1
#define tcg_gen_or_tl tcg_gen_or_i32
2128 f8422f52 blueswir1
#define tcg_gen_ori_tl tcg_gen_ori_i32
2129 f8422f52 blueswir1
#define tcg_gen_xor_tl tcg_gen_xor_i32
2130 f8422f52 blueswir1
#define tcg_gen_xori_tl tcg_gen_xori_i32
2131 0b6ce4cf bellard
#define tcg_gen_not_tl tcg_gen_not_i32
2132 f8422f52 blueswir1
#define tcg_gen_shl_tl tcg_gen_shl_i32
2133 f8422f52 blueswir1
#define tcg_gen_shli_tl tcg_gen_shli_i32
2134 f8422f52 blueswir1
#define tcg_gen_shr_tl tcg_gen_shr_i32
2135 f8422f52 blueswir1
#define tcg_gen_shri_tl tcg_gen_shri_i32
2136 f8422f52 blueswir1
#define tcg_gen_sar_tl tcg_gen_sar_i32
2137 f8422f52 blueswir1
#define tcg_gen_sari_tl tcg_gen_sari_i32
2138 0cf767d6 blueswir1
#define tcg_gen_brcond_tl tcg_gen_brcond_i32
2139 cb63669a pbrook
#define tcg_gen_brcondi_tl tcg_gen_brcondi_i32
2140 f730fd27 ths
#define tcg_gen_mul_tl tcg_gen_mul_i32
2141 f730fd27 ths
#define tcg_gen_muli_tl tcg_gen_muli_i32
2142 ab36421e aurel32
#define tcg_gen_div_tl tcg_gen_div_i32
2143 ab36421e aurel32
#define tcg_gen_rem_tl tcg_gen_rem_i32
2144 864951af aurel32
#define tcg_gen_divu_tl tcg_gen_divu_i32
2145 864951af aurel32
#define tcg_gen_remu_tl tcg_gen_remu_i32
2146 a768e4b2 blueswir1
#define tcg_gen_discard_tl tcg_gen_discard_i32
2147 e429073d blueswir1
#define tcg_gen_trunc_tl_i32 tcg_gen_mov_i32
2148 e429073d blueswir1
#define tcg_gen_trunc_i64_tl tcg_gen_trunc_i64_i32
2149 e429073d blueswir1
#define tcg_gen_extu_i32_tl tcg_gen_mov_i32
2150 e429073d blueswir1
#define tcg_gen_ext_i32_tl tcg_gen_mov_i32
2151 e429073d blueswir1
#define tcg_gen_extu_tl_i64 tcg_gen_extu_i32_i64
2152 e429073d blueswir1
#define tcg_gen_ext_tl_i64 tcg_gen_ext_i32_i64
2153 0b6ce4cf bellard
#define tcg_gen_ext8u_tl tcg_gen_ext8u_i32
2154 0b6ce4cf bellard
#define tcg_gen_ext8s_tl tcg_gen_ext8s_i32
2155 0b6ce4cf bellard
#define tcg_gen_ext16u_tl tcg_gen_ext16u_i32
2156 0b6ce4cf bellard
#define tcg_gen_ext16s_tl tcg_gen_ext16s_i32
2157 0b6ce4cf bellard
#define tcg_gen_ext32u_tl tcg_gen_mov_i32
2158 0b6ce4cf bellard
#define tcg_gen_ext32s_tl tcg_gen_mov_i32
2159 911d79ba aurel32
#define tcg_gen_bswap16_tl tcg_gen_bswap16_i32
2160 911d79ba aurel32
#define tcg_gen_bswap32_tl tcg_gen_bswap32_i32
2161 945ca823 blueswir1
#define tcg_gen_concat_tl_i64 tcg_gen_concat_i32_i64
2162 f24cb33e aurel32
#define tcg_gen_andc_tl tcg_gen_andc_i32
2163 f24cb33e aurel32
#define tcg_gen_eqv_tl tcg_gen_eqv_i32
2164 f24cb33e aurel32
#define tcg_gen_nand_tl tcg_gen_nand_i32
2165 f24cb33e aurel32
#define tcg_gen_nor_tl tcg_gen_nor_i32
2166 f24cb33e aurel32
#define tcg_gen_orc_tl tcg_gen_orc_i32
2167 15824571 aurel32
#define tcg_gen_rotl_tl tcg_gen_rotl_i32
2168 15824571 aurel32
#define tcg_gen_rotli_tl tcg_gen_rotli_i32
2169 15824571 aurel32
#define tcg_gen_rotr_tl tcg_gen_rotr_i32
2170 15824571 aurel32
#define tcg_gen_rotri_tl tcg_gen_rotri_i32
2171 a98824ac blueswir1
#define tcg_const_tl tcg_const_i32
2172 bdffd4a9 aurel32
#define tcg_const_local_tl tcg_const_local_i32
2173 f8422f52 blueswir1
#endif
2174 6ddbc6e4 pbrook
2175 6ddbc6e4 pbrook
#if TCG_TARGET_REG_BITS == 32
2176 48d38ca5 ths
#define tcg_gen_add_ptr tcg_gen_add_i32
2177 6ddbc6e4 pbrook
#define tcg_gen_addi_ptr tcg_gen_addi_i32
2178 48d38ca5 ths
#define tcg_gen_ext_i32_ptr tcg_gen_mov_i32
2179 6ddbc6e4 pbrook
#else /* TCG_TARGET_REG_BITS == 32 */
2180 48d38ca5 ths
#define tcg_gen_add_ptr tcg_gen_add_i64
2181 6ddbc6e4 pbrook
#define tcg_gen_addi_ptr tcg_gen_addi_i64
2182 48d38ca5 ths
#define tcg_gen_ext_i32_ptr tcg_gen_ext_i32_i64
2183 6ddbc6e4 pbrook
#endif /* TCG_TARGET_REG_BITS != 32 */