Revision cfe5f011
| b/hw/collie.c | ||
|---|---|---|
| 26 | 26 |
{
|
| 27 | 27 |
StrongARMState *s; |
| 28 | 28 |
DriveInfo *dinfo; |
| 29 |
ram_addr_t phys_flash; |
|
| 30 | 29 |
|
| 31 | 30 |
if (!cpu_model) {
|
| 32 | 31 |
cpu_model = "sa1110"; |
| ... | ... | |
| 34 | 33 |
|
| 35 | 34 |
s = sa1110_init(collie_binfo.ram_size, cpu_model); |
| 36 | 35 |
|
| 37 |
phys_flash = qemu_ram_alloc(NULL, "collie.fl1", 0x02000000); |
|
| 38 | 36 |
dinfo = drive_get(IF_PFLASH, 0, 0); |
| 39 |
pflash_cfi01_register(SA_CS0, phys_flash,
|
|
| 37 |
pflash_cfi01_register(SA_CS0, NULL, "collie.fl1", 0x02000000,
|
|
| 40 | 38 |
dinfo ? dinfo->bdrv : NULL, (64 * 1024), |
| 41 | 39 |
512, 4, 0x00, 0x00, 0x00, 0x00, 0); |
| 42 | 40 |
|
| 43 |
phys_flash = qemu_ram_alloc(NULL, "collie.fl2", 0x02000000); |
|
| 44 | 41 |
dinfo = drive_get(IF_PFLASH, 0, 1); |
| 45 |
pflash_cfi01_register(SA_CS1, phys_flash,
|
|
| 42 |
pflash_cfi01_register(SA_CS1, NULL, "collie.fl2", 0x02000000,
|
|
| 46 | 43 |
dinfo ? dinfo->bdrv : NULL, (64 * 1024), |
| 47 | 44 |
512, 4, 0x00, 0x00, 0x00, 0x00, 0); |
| 48 | 45 |
|
| b/hw/flash.h | ||
|---|---|---|
| 1 | 1 |
/* NOR flash devices */ |
| 2 |
|
|
| 3 |
#include "memory.h" |
|
| 4 |
|
|
| 2 | 5 |
typedef struct pflash_t pflash_t; |
| 3 | 6 |
|
| 4 | 7 |
/* pflash_cfi01.c */ |
| 5 |
pflash_t *pflash_cfi01_register(target_phys_addr_t base, ram_addr_t off, |
|
| 8 |
pflash_t *pflash_cfi01_register(target_phys_addr_t base, |
|
| 9 |
DeviceState *qdev, const char *name, |
|
| 10 |
target_phys_addr_t size, |
|
| 6 | 11 |
BlockDriverState *bs, |
| 7 | 12 |
uint32_t sector_len, int nb_blocs, int width, |
| 8 | 13 |
uint16_t id0, uint16_t id1, |
| 9 | 14 |
uint16_t id2, uint16_t id3, int be); |
| 10 | 15 |
|
| 11 | 16 |
/* pflash_cfi02.c */ |
| 12 |
pflash_t *pflash_cfi02_register(target_phys_addr_t base, ram_addr_t off, |
|
| 17 |
pflash_t *pflash_cfi02_register(target_phys_addr_t base, |
|
| 18 |
DeviceState *qdev, const char *name, |
|
| 19 |
target_phys_addr_t size, |
|
| 13 | 20 |
BlockDriverState *bs, uint32_t sector_len, |
| 14 | 21 |
int nb_blocs, int nb_mappings, int width, |
| 15 | 22 |
uint16_t id0, uint16_t id1, |
| ... | ... | |
| 17 | 24 |
uint16_t unlock_addr0, uint16_t unlock_addr1, |
| 18 | 25 |
int be); |
| 19 | 26 |
|
| 27 |
MemoryRegion *pflash_cfi01_get_memory(pflash_t *fl); |
|
| 28 |
|
|
| 20 | 29 |
/* nand.c */ |
| 21 | 30 |
DeviceState *nand_init(BlockDriverState *bdrv, int manf_id, int chip_id); |
| 22 | 31 |
void nand_setpins(DeviceState *dev, uint8_t cle, uint8_t ale, |
| b/hw/gumstix.c | ||
|---|---|---|
| 67 | 67 |
#else |
| 68 | 68 |
be = 0; |
| 69 | 69 |
#endif |
| 70 |
if (!pflash_cfi01_register(0x00000000, qemu_ram_alloc(NULL, "connext.rom", |
|
| 71 |
connex_rom), |
|
| 70 |
if (!pflash_cfi01_register(0x00000000, NULL, "connext.rom", connex_rom, |
|
| 72 | 71 |
dinfo->bdrv, sector_len, connex_rom / sector_len, |
| 73 | 72 |
2, 0, 0, 0, 0, be)) {
|
| 74 | 73 |
fprintf(stderr, "qemu: Error registering flash memory.\n"); |
| ... | ... | |
| 106 | 105 |
#else |
| 107 | 106 |
be = 0; |
| 108 | 107 |
#endif |
| 109 |
if (!pflash_cfi01_register(0x00000000, qemu_ram_alloc(NULL, "verdex.rom", |
|
| 110 |
verdex_rom), |
|
| 108 |
if (!pflash_cfi01_register(0x00000000, NULL, "verdex.rom", verdex_rom, |
|
| 111 | 109 |
dinfo->bdrv, sector_len, verdex_rom / sector_len, |
| 112 | 110 |
2, 0, 0, 0, 0, be)) {
|
| 113 | 111 |
fprintf(stderr, "qemu: Error registering flash memory.\n"); |
| b/hw/lm32_boards.c | ||
|---|---|---|
| 77 | 77 |
CPUState *env; |
| 78 | 78 |
DriveInfo *dinfo; |
| 79 | 79 |
ram_addr_t phys_ram; |
| 80 |
ram_addr_t phys_flash; |
|
| 81 | 80 |
qemu_irq *cpu_irq, irq[32]; |
| 82 | 81 |
ResetInfo *reset_info; |
| 83 | 82 |
int i; |
| ... | ... | |
| 108 | 107 |
phys_ram = qemu_ram_alloc(NULL, "lm32_evr.sdram", ram_size); |
| 109 | 108 |
cpu_register_physical_memory(ram_base, ram_size, phys_ram | IO_MEM_RAM); |
| 110 | 109 |
|
| 111 |
phys_flash = qemu_ram_alloc(NULL, "lm32_evr.flash", flash_size); |
|
| 112 | 110 |
dinfo = drive_get(IF_PFLASH, 0, 0); |
| 113 | 111 |
/* Spansion S29NS128P */ |
| 114 |
pflash_cfi02_register(flash_base, phys_flash,
|
|
| 112 |
pflash_cfi02_register(flash_base, NULL, "lm32_evr.flash", flash_size,
|
|
| 115 | 113 |
dinfo ? dinfo->bdrv : NULL, flash_sector_size, |
| 116 | 114 |
flash_size / flash_sector_size, 1, 2, |
| 117 | 115 |
0x01, 0x7e, 0x43, 0x00, 0x555, 0x2aa, 1); |
| ... | ... | |
| 165 | 163 |
CPUState *env; |
| 166 | 164 |
DriveInfo *dinfo; |
| 167 | 165 |
ram_addr_t phys_ram; |
| 168 |
ram_addr_t phys_flash; |
|
| 169 | 166 |
qemu_irq *cpu_irq, irq[32]; |
| 170 | 167 |
HWSetup *hw; |
| 171 | 168 |
ResetInfo *reset_info; |
| ... | ... | |
| 203 | 200 |
phys_ram = qemu_ram_alloc(NULL, "lm32_uclinux.sdram", ram_size); |
| 204 | 201 |
cpu_register_physical_memory(ram_base, ram_size, phys_ram | IO_MEM_RAM); |
| 205 | 202 |
|
| 206 |
phys_flash = qemu_ram_alloc(NULL, "lm32_uclinux.flash", flash_size); |
|
| 207 | 203 |
dinfo = drive_get(IF_PFLASH, 0, 0); |
| 208 | 204 |
/* Spansion S29NS128P */ |
| 209 |
pflash_cfi02_register(flash_base, phys_flash,
|
|
| 205 |
pflash_cfi02_register(flash_base, NULL, "lm32_uclinux.flash", flash_size,
|
|
| 210 | 206 |
dinfo ? dinfo->bdrv : NULL, flash_sector_size, |
| 211 | 207 |
flash_size / flash_sector_size, 1, 2, |
| 212 | 208 |
0x01, 0x7e, 0x43, 0x00, 0x555, 0x2aa, 1); |
| b/hw/mainstone.c | ||
|---|---|---|
| 126 | 126 |
exit(1); |
| 127 | 127 |
} |
| 128 | 128 |
|
| 129 |
if (!pflash_cfi01_register(mainstone_flash_base[i], |
|
| 130 |
qemu_ram_alloc(NULL, i ? "mainstone.flash1" : |
|
| 131 |
"mainstone.flash0", |
|
| 132 |
MAINSTONE_FLASH), |
|
| 129 |
if (!pflash_cfi01_register(mainstone_flash_base[i], NULL, |
|
| 130 |
i ? "mainstone.flash1" : "mainstone.flash0", |
|
| 131 |
MAINSTONE_FLASH, |
|
| 133 | 132 |
dinfo->bdrv, sector_len, |
| 134 | 133 |
MAINSTONE_FLASH / sector_len, 4, 0, 0, 0, 0, |
| 135 | 134 |
be)) {
|
| b/hw/milkymist.c | ||
|---|---|---|
| 82 | 82 |
int kernel_size; |
| 83 | 83 |
DriveInfo *dinfo; |
| 84 | 84 |
ram_addr_t phys_sdram; |
| 85 |
ram_addr_t phys_flash; |
|
| 86 | 85 |
qemu_irq irq[32], *cpu_irq; |
| 87 | 86 |
int i; |
| 88 | 87 |
char *bios_filename; |
| ... | ... | |
| 113 | 112 |
cpu_register_physical_memory(sdram_base, sdram_size, |
| 114 | 113 |
phys_sdram | IO_MEM_RAM); |
| 115 | 114 |
|
| 116 |
phys_flash = qemu_ram_alloc(NULL, "milkymist.flash", flash_size); |
|
| 117 | 115 |
dinfo = drive_get(IF_PFLASH, 0, 0); |
| 118 | 116 |
/* Numonyx JS28F256J3F105 */ |
| 119 |
pflash_cfi01_register(flash_base, phys_flash,
|
|
| 117 |
pflash_cfi01_register(flash_base, NULL, "milkymist.flash", flash_size,
|
|
| 120 | 118 |
dinfo ? dinfo->bdrv : NULL, flash_sector_size, |
| 121 | 119 |
flash_size / flash_sector_size, 2, |
| 122 | 120 |
0x00, 0x89, 0x00, 0x1d, 1); |
| b/hw/mips_malta.c | ||
|---|---|---|
| 46 | 46 |
#include "elf.h" |
| 47 | 47 |
#include "mc146818rtc.h" |
| 48 | 48 |
#include "blockdev.h" |
| 49 |
#include "exec-memory.h" |
|
| 49 | 50 |
|
| 50 | 51 |
//#define DEBUG_BOARD_INIT |
| 51 | 52 |
|
| ... | ... | |
| 761 | 762 |
const char *initrd_filename, const char *cpu_model) |
| 762 | 763 |
{
|
| 763 | 764 |
char *filename; |
| 765 |
pflash_t *fl; |
|
| 764 | 766 |
ram_addr_t ram_offset; |
| 765 |
ram_addr_t bios_offset; |
|
| 767 |
MemoryRegion *system_memory = get_system_memory(); |
|
| 768 |
MemoryRegion *bios, *bios_alias = g_new(MemoryRegion, 1); |
|
| 766 | 769 |
target_long bios_size; |
| 767 | 770 |
int64_t kernel_entry; |
| 768 | 771 |
PCIBus *pci_bus; |
| ... | ... | |
| 811 | 814 |
exit(1); |
| 812 | 815 |
} |
| 813 | 816 |
ram_offset = qemu_ram_alloc(NULL, "mips_malta.ram", ram_size); |
| 814 |
bios_offset = qemu_ram_alloc(NULL, "mips_malta.bios", BIOS_SIZE); |
|
| 815 |
|
|
| 816 | 817 |
|
| 817 | 818 |
cpu_register_physical_memory(0, ram_size, ram_offset | IO_MEM_RAM); |
| 818 | 819 |
|
| 819 |
/* Map the bios at two physical locations, as on the real board. */ |
|
| 820 |
cpu_register_physical_memory(0x1e000000LL, |
|
| 821 |
BIOS_SIZE, bios_offset | IO_MEM_ROM); |
|
| 822 |
cpu_register_physical_memory(0x1fc00000LL, |
|
| 823 |
BIOS_SIZE, bios_offset | IO_MEM_ROM); |
|
| 824 |
|
|
| 825 | 820 |
#ifdef TARGET_WORDS_BIGENDIAN |
| 826 | 821 |
be = 1; |
| 827 | 822 |
#else |
| ... | ... | |
| 833 | 828 |
/* Load firmware in flash / BIOS unless we boot directly into a kernel. */ |
| 834 | 829 |
if (kernel_filename) {
|
| 835 | 830 |
/* Write a small bootloader to the flash location. */ |
| 831 |
bios = g_new(MemoryRegion, 1); |
|
| 832 |
memory_region_init_ram(bios, NULL, "mips_malta.bios", BIOS_SIZE); |
|
| 833 |
memory_region_set_readonly(bios, true); |
|
| 834 |
memory_region_init_alias(bios_alias, "bios.1fc", bios, 0, BIOS_SIZE); |
|
| 835 |
/* Map the bios at two physical locations, as on the real board. */ |
|
| 836 |
memory_region_add_subregion(system_memory, 0x1e000000LL, bios); |
|
| 837 |
memory_region_add_subregion(system_memory, 0x1fc00000LL, bios_alias); |
|
| 836 | 838 |
loaderparams.ram_size = ram_size; |
| 837 | 839 |
loaderparams.kernel_filename = kernel_filename; |
| 838 | 840 |
loaderparams.kernel_cmdline = kernel_cmdline; |
| 839 | 841 |
loaderparams.initrd_filename = initrd_filename; |
| 840 | 842 |
kernel_entry = load_kernel(); |
| 841 |
write_bootloader(env, qemu_get_ram_ptr(bios_offset), kernel_entry);
|
|
| 843 |
write_bootloader(env, memory_region_get_ram_ptr(bios), kernel_entry);
|
|
| 842 | 844 |
} else {
|
| 843 | 845 |
dinfo = drive_get(IF_PFLASH, 0, fl_idx); |
| 844 | 846 |
if (dinfo) {
|
| ... | ... | |
| 847 | 849 |
fl_sectors = bios_size >> 16; |
| 848 | 850 |
#ifdef DEBUG_BOARD_INIT |
| 849 | 851 |
printf("Register parallel flash %d size " TARGET_FMT_lx " at "
|
| 850 |
"offset %08lx addr %08llx '%s' %x\n",
|
|
| 851 |
fl_idx, bios_size, bios_offset, 0x1e000000LL,
|
|
| 852 |
"addr %08llx '%s' %x\n", |
|
| 853 |
fl_idx, bios_size, 0x1e000000LL, |
|
| 852 | 854 |
bdrv_get_device_name(dinfo->bdrv), fl_sectors); |
| 853 | 855 |
#endif |
| 854 |
pflash_cfi01_register(0x1e000000LL, bios_offset, |
|
| 855 |
dinfo->bdrv, 65536, fl_sectors, |
|
| 856 |
4, 0x0000, 0x0000, 0x0000, 0x0000, be); |
|
| 857 |
fl_idx++; |
|
| 856 |
fl = pflash_cfi01_register(0x1e000000LL, |
|
| 857 |
NULL, "mips_malta.bios", BIOS_SIZE, |
|
| 858 |
dinfo->bdrv, 65536, fl_sectors, |
|
| 859 |
4, 0x0000, 0x0000, 0x0000, 0x0000, be); |
|
| 860 |
bios = pflash_cfi01_get_memory(fl); |
|
| 861 |
/* Map the bios at two physical locations, as on the real board. */ |
|
| 862 |
memory_region_init_alias(bios_alias, "bios.1fc", |
|
| 863 |
bios, 0, BIOS_SIZE); |
|
| 864 |
memory_region_add_subregion(system_memory, 0x1fc00000LL, |
|
| 865 |
bios_alias); |
|
| 866 |
fl_idx++; |
|
| 858 | 867 |
} else {
|
| 868 |
bios = g_new(MemoryRegion, 1); |
|
| 869 |
memory_region_init_ram(bios, NULL, "mips_malta.bios", BIOS_SIZE); |
|
| 870 |
memory_region_set_readonly(bios, true); |
|
| 871 |
memory_region_init_alias(bios_alias, "bios.1fc", |
|
| 872 |
bios, 0, BIOS_SIZE); |
|
| 873 |
/* Map the bios at two physical locations, as on the real board. */ |
|
| 874 |
memory_region_add_subregion(system_memory, 0x1e000000LL, bios); |
|
| 875 |
memory_region_add_subregion(system_memory, 0x1fc00000LL, |
|
| 876 |
bios_alias); |
|
| 859 | 877 |
/* Load a BIOS image. */ |
| 860 | 878 |
if (bios_name == NULL) |
| 861 | 879 |
bios_name = BIOS_FILENAME; |
| ... | ... | |
| 878 | 896 |
a neat trick which allows bi-endian firmware. */ |
| 879 | 897 |
#ifndef TARGET_WORDS_BIGENDIAN |
| 880 | 898 |
{
|
| 881 |
uint32_t *addr = qemu_get_ram_ptr(bios_offset);;
|
|
| 899 |
uint32_t *addr = memory_region_get_ram_ptr(bios);
|
|
| 882 | 900 |
uint32_t *end = addr + bios_size; |
| 883 | 901 |
while (addr < end) {
|
| 884 | 902 |
bswap32s(addr); |
| ... | ... | |
| 890 | 908 |
/* Board ID = 0x420 (Malta Board with CoreLV) |
| 891 | 909 |
XXX: theoretically 0x1e000010 should map to flash and 0x1fc00010 should |
| 892 | 910 |
map to the board ID. */ |
| 893 |
stl_p(qemu_get_ram_ptr(bios_offset) + 0x10, 0x00000420);
|
|
| 911 |
stl_p(memory_region_get_ram_ptr(bios) + 0x10, 0x00000420);
|
|
| 894 | 912 |
|
| 895 | 913 |
/* Init internal devices */ |
| 896 | 914 |
cpu_mips_irq_init_cpu(env); |
| b/hw/mips_r4k.c | ||
|---|---|---|
| 23 | 23 |
#include "elf.h" |
| 24 | 24 |
#include "mc146818rtc.h" |
| 25 | 25 |
#include "blockdev.h" |
| 26 |
#include "exec-memory.h" |
|
| 26 | 27 |
|
| 27 | 28 |
#define MAX_IDE_BUS 2 |
| 28 | 29 |
|
| ... | ... | |
| 163 | 164 |
{
|
| 164 | 165 |
char *filename; |
| 165 | 166 |
ram_addr_t ram_offset; |
| 166 |
ram_addr_t bios_offset;
|
|
| 167 |
MemoryRegion *bios;
|
|
| 167 | 168 |
int bios_size; |
| 168 | 169 |
CPUState *env; |
| 169 | 170 |
ResetData *reset_info; |
| ... | ... | |
| 227 | 228 |
be = 0; |
| 228 | 229 |
#endif |
| 229 | 230 |
if ((bios_size > 0) && (bios_size <= BIOS_SIZE)) {
|
| 230 |
bios_offset = qemu_ram_alloc(NULL, "mips_r4k.bios", BIOS_SIZE); |
|
| 231 |
cpu_register_physical_memory(0x1fc00000, BIOS_SIZE, |
|
| 232 |
bios_offset | IO_MEM_ROM); |
|
| 231 |
bios = g_new(MemoryRegion, 1); |
|
| 232 |
memory_region_init_ram(bios, NULL, "mips_r4k.bios", BIOS_SIZE); |
|
| 233 |
memory_region_set_readonly(bios, true); |
|
| 234 |
memory_region_add_subregion(get_system_memory(), 0x1fc00000, bios); |
|
| 233 | 235 |
|
| 234 | 236 |
load_image_targphys(filename, 0x1fc00000, BIOS_SIZE); |
| 235 | 237 |
} else if ((dinfo = drive_get(IF_PFLASH, 0, 0)) != NULL) {
|
| 236 | 238 |
uint32_t mips_rom = 0x00400000; |
| 237 |
bios_offset = qemu_ram_alloc(NULL, "mips_r4k.bios", mips_rom); |
|
| 238 |
if (!pflash_cfi01_register(0x1fc00000, bios_offset, |
|
| 239 |
if (!pflash_cfi01_register(0x1fc00000, NULL, "mips_r4k.bios", mips_rom, |
|
| 239 | 240 |
dinfo->bdrv, sector_len, |
| 240 | 241 |
mips_rom / sector_len, |
| 241 | 242 |
4, 0, 0, 0, 0, be)) {
|
| b/hw/musicpal.c | ||
|---|---|---|
| 1565 | 1565 |
* image is smaller than 32 MB. |
| 1566 | 1566 |
*/ |
| 1567 | 1567 |
#ifdef TARGET_WORDS_BIGENDIAN |
| 1568 |
pflash_cfi02_register(0-MP_FLASH_SIZE_MAX, qemu_ram_alloc(NULL,
|
|
| 1569 |
"musicpal.flash", flash_size),
|
|
| 1568 |
pflash_cfi02_register(0-MP_FLASH_SIZE_MAX, NULL, |
|
| 1569 |
"musicpal.flash", flash_size, |
|
| 1570 | 1570 |
dinfo->bdrv, 0x10000, |
| 1571 | 1571 |
(flash_size + 0xffff) >> 16, |
| 1572 | 1572 |
MP_FLASH_SIZE_MAX / flash_size, |
| 1573 | 1573 |
2, 0x00BF, 0x236D, 0x0000, 0x0000, |
| 1574 | 1574 |
0x5555, 0x2AAA, 1); |
| 1575 | 1575 |
#else |
| 1576 |
pflash_cfi02_register(0-MP_FLASH_SIZE_MAX, qemu_ram_alloc(NULL,
|
|
| 1577 |
"musicpal.flash", flash_size),
|
|
| 1576 |
pflash_cfi02_register(0-MP_FLASH_SIZE_MAX, NULL, |
|
| 1577 |
"musicpal.flash", flash_size, |
|
| 1578 | 1578 |
dinfo->bdrv, 0x10000, |
| 1579 | 1579 |
(flash_size + 0xffff) >> 16, |
| 1580 | 1580 |
MP_FLASH_SIZE_MAX / flash_size, |
| b/hw/omap_sx1.c | ||
|---|---|---|
| 161 | 161 |
#endif |
| 162 | 162 |
|
| 163 | 163 |
if ((dinfo = drive_get(IF_PFLASH, 0, fl_idx)) != NULL) {
|
| 164 |
if (!pflash_cfi01_register(OMAP_CS0_BASE, qemu_ram_alloc(NULL,
|
|
| 165 |
"omap_sx1.flash0-1", flash_size),
|
|
| 164 |
if (!pflash_cfi01_register(OMAP_CS0_BASE, NULL, |
|
| 165 |
"omap_sx1.flash0-1", flash_size, |
|
| 166 | 166 |
dinfo->bdrv, sector_size, |
| 167 | 167 |
flash_size / sector_size, |
| 168 | 168 |
4, 0, 0, 0, 0, be)) {
|
| ... | ... | |
| 182 | 182 |
cpu_register_physical_memory(OMAP_CS1_BASE + flash1_size, |
| 183 | 183 |
OMAP_CS1_SIZE - flash1_size, io); |
| 184 | 184 |
|
| 185 |
if (!pflash_cfi01_register(OMAP_CS1_BASE, qemu_ram_alloc(NULL,
|
|
| 186 |
"omap_sx1.flash1-1", flash1_size),
|
|
| 185 |
if (!pflash_cfi01_register(OMAP_CS1_BASE, NULL, |
|
| 186 |
"omap_sx1.flash1-1", flash1_size, |
|
| 187 | 187 |
dinfo->bdrv, sector_size, |
| 188 | 188 |
flash1_size / sector_size, |
| 189 | 189 |
4, 0, 0, 0, 0, be)) {
|
| b/hw/petalogix_ml605_mmu.c | ||
|---|---|---|
| 149 | 149 |
target_phys_addr_t ddr_base = MEMORY_BASEADDR; |
| 150 | 150 |
ram_addr_t phys_lmb_bram; |
| 151 | 151 |
ram_addr_t phys_ram; |
| 152 |
ram_addr_t phys_flash; |
|
| 153 | 152 |
qemu_irq irq[32], *cpu_irq; |
| 154 | 153 |
|
| 155 | 154 |
/* init CPUs */ |
| ... | ... | |
| 169 | 168 |
phys_ram = qemu_ram_alloc(NULL, "petalogix_ml605.ram", ram_size); |
| 170 | 169 |
cpu_register_physical_memory(ddr_base, ram_size, phys_ram | IO_MEM_RAM); |
| 171 | 170 |
|
| 172 |
phys_flash = qemu_ram_alloc(NULL, "petalogix_ml605.flash", FLASH_SIZE); |
|
| 173 | 171 |
dinfo = drive_get(IF_PFLASH, 0, 0); |
| 174 | 172 |
/* 5th parameter 2 means bank-width |
| 175 | 173 |
* 10th paremeter 0 means little-endian */ |
| 176 |
pflash_cfi01_register(FLASH_BASEADDR, phys_flash, |
|
| 174 |
pflash_cfi01_register(FLASH_BASEADDR, |
|
| 175 |
NULL, "petalogix_ml605.flash", FLASH_SIZE, |
|
| 177 | 176 |
dinfo ? dinfo->bdrv : NULL, (64 * 1024), |
| 178 | 177 |
FLASH_SIZE >> 16, |
| 179 | 178 |
2, 0x89, 0x18, 0x0000, 0x0, 0); |
| b/hw/petalogix_s3adsp1800_mmu.c | ||
|---|---|---|
| 127 | 127 |
target_phys_addr_t ddr_base = 0x90000000; |
| 128 | 128 |
ram_addr_t phys_lmb_bram; |
| 129 | 129 |
ram_addr_t phys_ram; |
| 130 |
ram_addr_t phys_flash; |
|
| 131 | 130 |
qemu_irq irq[32], *cpu_irq; |
| 132 | 131 |
|
| 133 | 132 |
/* init CPUs */ |
| ... | ... | |
| 148 | 147 |
phys_ram = qemu_ram_alloc(NULL, "petalogix_s3adsp1800.ram", ram_size); |
| 149 | 148 |
cpu_register_physical_memory(ddr_base, ram_size, phys_ram | IO_MEM_RAM); |
| 150 | 149 |
|
| 151 |
phys_flash = qemu_ram_alloc(NULL, "petalogix_s3adsp1800.flash", FLASH_SIZE); |
|
| 152 | 150 |
dinfo = drive_get(IF_PFLASH, 0, 0); |
| 153 |
pflash_cfi01_register(0xa0000000, phys_flash, |
|
| 151 |
pflash_cfi01_register(0xa0000000, |
|
| 152 |
NULL, "petalogix_s3adsp1800.flash", FLASH_SIZE, |
|
| 154 | 153 |
dinfo ? dinfo->bdrv : NULL, (64 * 1024), |
| 155 | 154 |
FLASH_SIZE >> 16, |
| 156 | 155 |
1, 0x89, 0x18, 0x0000, 0x0, 1); |
| b/hw/pflash_cfi01.c | ||
|---|---|---|
| 40 | 40 |
#include "flash.h" |
| 41 | 41 |
#include "block.h" |
| 42 | 42 |
#include "qemu-timer.h" |
| 43 |
#include "exec-memory.h" |
|
| 43 | 44 |
|
| 44 | 45 |
#define PFLASH_BUG(fmt, ...) \ |
| 45 | 46 |
do { \
|
| ... | ... | |
| 74 | 75 |
target_phys_addr_t counter; |
| 75 | 76 |
unsigned int writeblock_size; |
| 76 | 77 |
QEMUTimer *timer; |
| 77 |
ram_addr_t off; |
|
| 78 |
int fl_mem; |
|
| 78 |
MemoryRegion mem; |
|
| 79 | 79 |
void *storage; |
| 80 | 80 |
}; |
| 81 | 81 |
|
| ... | ... | |
| 89 | 89 |
if (pfl->bypass) {
|
| 90 | 90 |
pfl->wcycle = 2; |
| 91 | 91 |
} else {
|
| 92 |
cpu_register_physical_memory(pfl->base, pfl->total_len, |
|
| 93 |
pfl->off | IO_MEM_ROMD | pfl->fl_mem); |
|
| 92 |
memory_region_rom_device_set_readable(&pfl->mem, true); |
|
| 94 | 93 |
pfl->wcycle = 0; |
| 95 | 94 |
} |
| 96 | 95 |
pfl->cmd = 0; |
| ... | ... | |
| 263 | 262 |
|
| 264 | 263 |
if (!pfl->wcycle) {
|
| 265 | 264 |
/* Set the device in I/O access mode */ |
| 266 |
cpu_register_physical_memory(pfl->base, pfl->total_len, pfl->fl_mem);
|
|
| 265 |
memory_region_rom_device_set_readable(&pfl->mem, false);
|
|
| 267 | 266 |
} |
| 268 | 267 |
|
| 269 | 268 |
switch (pfl->wcycle) {
|
| ... | ... | |
| 422 | 421 |
__func__, offset, pfl->wcycle, pfl->cmd, value); |
| 423 | 422 |
|
| 424 | 423 |
reset_flash: |
| 425 |
cpu_register_physical_memory(pfl->base, pfl->total_len, |
|
| 426 |
pfl->off | IO_MEM_ROMD | pfl->fl_mem); |
|
| 424 |
memory_region_rom_device_set_readable(&pfl->mem, true); |
|
| 427 | 425 |
|
| 428 | 426 |
pfl->bypass = 0; |
| 429 | 427 |
pfl->wcycle = 0; |
| ... | ... | |
| 514 | 512 |
pflash_write(pfl, addr, value, 4, 0); |
| 515 | 513 |
} |
| 516 | 514 |
|
| 517 |
static CPUWriteMemoryFunc * const pflash_write_ops_be[] = {
|
|
| 518 |
&pflash_writeb_be, |
|
| 519 |
&pflash_writew_be, |
|
| 520 |
&pflash_writel_be, |
|
| 515 |
static const MemoryRegionOps pflash_cfi01_ops_be = {
|
|
| 516 |
.old_mmio = {
|
|
| 517 |
.read = { pflash_readb_be, pflash_readw_be, pflash_readl_be, },
|
|
| 518 |
.write = { pflash_writeb_be, pflash_writew_be, pflash_writel_be, },
|
|
| 519 |
}, |
|
| 520 |
.endianness = DEVICE_NATIVE_ENDIAN, |
|
| 521 | 521 |
}; |
| 522 | 522 |
|
| 523 |
static CPUReadMemoryFunc * const pflash_read_ops_be[] = {
|
|
| 524 |
&pflash_readb_be, |
|
| 525 |
&pflash_readw_be, |
|
| 526 |
&pflash_readl_be, |
|
| 527 |
}; |
|
| 528 |
|
|
| 529 |
static CPUWriteMemoryFunc * const pflash_write_ops_le[] = {
|
|
| 530 |
&pflash_writeb_le, |
|
| 531 |
&pflash_writew_le, |
|
| 532 |
&pflash_writel_le, |
|
| 533 |
}; |
|
| 534 |
|
|
| 535 |
static CPUReadMemoryFunc * const pflash_read_ops_le[] = {
|
|
| 536 |
&pflash_readb_le, |
|
| 537 |
&pflash_readw_le, |
|
| 538 |
&pflash_readl_le, |
|
| 523 |
static const MemoryRegionOps pflash_cfi01_ops_le = {
|
|
| 524 |
.old_mmio = {
|
|
| 525 |
.read = { pflash_readb_le, pflash_readw_le, pflash_readl_le, },
|
|
| 526 |
.write = { pflash_writeb_le, pflash_writew_le, pflash_writel_le, },
|
|
| 527 |
}, |
|
| 528 |
.endianness = DEVICE_NATIVE_ENDIAN, |
|
| 539 | 529 |
}; |
| 540 | 530 |
|
| 541 | 531 |
/* Count trailing zeroes of a 32 bits quantity */ |
| ... | ... | |
| 574 | 564 |
return ret; |
| 575 | 565 |
} |
| 576 | 566 |
|
| 577 |
pflash_t *pflash_cfi01_register(target_phys_addr_t base, ram_addr_t off, |
|
| 567 |
pflash_t *pflash_cfi01_register(target_phys_addr_t base, |
|
| 568 |
DeviceState *qdev, const char *name, |
|
| 569 |
target_phys_addr_t size, |
|
| 578 | 570 |
BlockDriverState *bs, uint32_t sector_len, |
| 579 | 571 |
int nb_blocs, int width, |
| 580 | 572 |
uint16_t id0, uint16_t id1, |
| 581 |
uint16_t id2, uint16_t id3, |
|
| 582 |
int be) |
|
| 573 |
uint16_t id2, uint16_t id3, int be) |
|
| 583 | 574 |
{
|
| 584 | 575 |
pflash_t *pfl; |
| 585 | 576 |
target_phys_addr_t total_len; |
| ... | ... | |
| 596 | 587 |
|
| 597 | 588 |
pfl = g_malloc0(sizeof(pflash_t)); |
| 598 | 589 |
|
| 599 |
/* FIXME: Allocate ram ourselves. */ |
|
| 600 |
pfl->storage = qemu_get_ram_ptr(off); |
|
| 601 |
if (be) {
|
|
| 602 |
pfl->fl_mem = cpu_register_io_memory(pflash_read_ops_be, |
|
| 603 |
pflash_write_ops_be, pfl, |
|
| 604 |
DEVICE_NATIVE_ENDIAN); |
|
| 605 |
} else {
|
|
| 606 |
pfl->fl_mem = cpu_register_io_memory(pflash_read_ops_le, |
|
| 607 |
pflash_write_ops_le, pfl, |
|
| 608 |
DEVICE_NATIVE_ENDIAN); |
|
| 609 |
} |
|
| 610 |
pfl->off = off; |
|
| 611 |
cpu_register_physical_memory(base, total_len, |
|
| 612 |
off | pfl->fl_mem | IO_MEM_ROMD); |
|
| 590 |
memory_region_init_rom_device( |
|
| 591 |
&pfl->mem, be ? &pflash_cfi01_ops_be : &pflash_cfi01_ops_le, pfl, |
|
| 592 |
qdev, name, size); |
|
| 593 |
pfl->storage = memory_region_get_ram_ptr(&pfl->mem); |
|
| 594 |
memory_region_add_subregion(get_system_memory(), base, &pfl->mem); |
|
| 613 | 595 |
|
| 614 | 596 |
pfl->bs = bs; |
| 615 | 597 |
if (pfl->bs) {
|
| 616 | 598 |
/* read the initial flash content */ |
| 617 | 599 |
ret = bdrv_read(pfl->bs, 0, pfl->storage, total_len >> 9); |
| 618 | 600 |
if (ret < 0) {
|
| 619 |
cpu_unregister_io_memory(pfl->fl_mem); |
|
| 601 |
memory_region_del_subregion(get_system_memory(), &pfl->mem); |
|
| 602 |
memory_region_destroy(&pfl->mem); |
|
| 620 | 603 |
g_free(pfl); |
| 621 | 604 |
return NULL; |
| 622 | 605 |
} |
| ... | ... | |
| 724 | 707 |
|
| 725 | 708 |
return pfl; |
| 726 | 709 |
} |
| 710 |
|
|
| 711 |
MemoryRegion *pflash_cfi01_get_memory(pflash_t *fl) |
|
| 712 |
{
|
|
| 713 |
return &fl->mem; |
|
| 714 |
} |
|
| b/hw/pflash_cfi02.c | ||
|---|---|---|
| 39 | 39 |
#include "flash.h" |
| 40 | 40 |
#include "qemu-timer.h" |
| 41 | 41 |
#include "block.h" |
| 42 |
#include "exec-memory.h" |
|
| 42 | 43 |
|
| 43 | 44 |
//#define PFLASH_DEBUG |
| 44 | 45 |
#ifdef PFLASH_DEBUG |
| ... | ... | |
| 69 | 70 |
uint8_t cfi_len; |
| 70 | 71 |
uint8_t cfi_table[0x52]; |
| 71 | 72 |
QEMUTimer *timer; |
| 72 |
ram_addr_t off; |
|
| 73 |
int fl_mem; |
|
| 73 |
/* The device replicates the flash memory across its memory space. Emulate |
|
| 74 |
* that by having a container (.mem) filled with an array of aliases |
|
| 75 |
* (.mem_mappings) pointing to the flash memory (.orig_mem). |
|
| 76 |
*/ |
|
| 77 |
MemoryRegion mem; |
|
| 78 |
MemoryRegion *mem_mappings; /* array; one per mapping */ |
|
| 79 |
MemoryRegion orig_mem; |
|
| 74 | 80 |
int rom_mode; |
| 75 | 81 |
int read_counter; /* used for lazy switch-back to rom mode */ |
| 76 | 82 |
void *storage; |
| 77 | 83 |
}; |
| 78 | 84 |
|
| 79 |
static void pflash_register_memory(pflash_t *pfl, int rom_mode) |
|
| 85 |
/* |
|
| 86 |
* Set up replicated mappings of the same region. |
|
| 87 |
*/ |
|
| 88 |
static void pflash_setup_mappings(pflash_t *pfl) |
|
| 80 | 89 |
{
|
| 81 |
unsigned long phys_offset = pfl->fl_mem; |
|
| 82 |
int i; |
|
| 83 |
|
|
| 84 |
if (rom_mode) |
|
| 85 |
phys_offset |= pfl->off | IO_MEM_ROMD; |
|
| 86 |
pfl->rom_mode = rom_mode; |
|
| 90 |
unsigned i; |
|
| 91 |
target_phys_addr_t size = memory_region_size(&pfl->orig_mem); |
|
| 92 |
|
|
| 93 |
memory_region_init(&pfl->mem, "pflash", pfl->mappings * size); |
|
| 94 |
pfl->mem_mappings = g_new(MemoryRegion, pfl->mappings); |
|
| 95 |
for (i = 0; i < pfl->mappings; ++i) {
|
|
| 96 |
memory_region_init_alias(&pfl->mem_mappings[i], "pflash-alias", |
|
| 97 |
&pfl->orig_mem, 0, size); |
|
| 98 |
memory_region_add_subregion(&pfl->mem, i * size, &pfl->mem_mappings[i]); |
|
| 99 |
} |
|
| 100 |
} |
|
| 87 | 101 |
|
| 88 |
for (i = 0; i < pfl->mappings; i++)
|
|
| 89 |
cpu_register_physical_memory(pfl->base + i * pfl->chip_len,
|
|
| 90 |
pfl->chip_len, phys_offset);
|
|
| 102 |
static void pflash_register_memory(pflash_t *pfl, int rom_mode)
|
|
| 103 |
{
|
|
| 104 |
memory_region_rom_device_set_readable(&pfl->orig_mem, rom_mode);
|
|
| 91 | 105 |
} |
| 92 | 106 |
|
| 93 | 107 |
static void pflash_timer (void *opaque) |
| ... | ... | |
| 538 | 552 |
pflash_write(pfl, addr, value, 4, 0); |
| 539 | 553 |
} |
| 540 | 554 |
|
| 541 |
static CPUWriteMemoryFunc * const pflash_write_ops_be[] = {
|
|
| 542 |
&pflash_writeb_be, |
|
| 543 |
&pflash_writew_be, |
|
| 544 |
&pflash_writel_be, |
|
| 545 |
}; |
|
| 546 |
|
|
| 547 |
static CPUReadMemoryFunc * const pflash_read_ops_be[] = {
|
|
| 548 |
&pflash_readb_be, |
|
| 549 |
&pflash_readw_be, |
|
| 550 |
&pflash_readl_be, |
|
| 555 |
static const MemoryRegionOps pflash_cfi02_ops_be = {
|
|
| 556 |
.old_mmio = {
|
|
| 557 |
.read = { pflash_readb_be, pflash_readw_be, pflash_readl_be, },
|
|
| 558 |
.write = { pflash_writeb_be, pflash_writew_be, pflash_writel_be, },
|
|
| 559 |
}, |
|
| 560 |
.endianness = DEVICE_NATIVE_ENDIAN, |
|
| 551 | 561 |
}; |
| 552 | 562 |
|
| 553 |
static CPUWriteMemoryFunc * const pflash_write_ops_le[] = {
|
|
| 554 |
&pflash_writeb_le, |
|
| 555 |
&pflash_writew_le, |
|
| 556 |
&pflash_writel_le, |
|
| 557 |
}; |
|
| 558 |
|
|
| 559 |
static CPUReadMemoryFunc * const pflash_read_ops_le[] = {
|
|
| 560 |
&pflash_readb_le, |
|
| 561 |
&pflash_readw_le, |
|
| 562 |
&pflash_readl_le, |
|
| 563 |
static const MemoryRegionOps pflash_cfi02_ops_le = {
|
|
| 564 |
.old_mmio = {
|
|
| 565 |
.read = { pflash_readb_le, pflash_readw_le, pflash_readl_le, },
|
|
| 566 |
.write = { pflash_writeb_le, pflash_writew_le, pflash_writel_le, },
|
|
| 567 |
}, |
|
| 568 |
.endianness = DEVICE_NATIVE_ENDIAN, |
|
| 563 | 569 |
}; |
| 564 | 570 |
|
| 565 | 571 |
/* Count trailing zeroes of a 32 bits quantity */ |
| ... | ... | |
| 598 | 604 |
return ret; |
| 599 | 605 |
} |
| 600 | 606 |
|
| 601 |
pflash_t *pflash_cfi02_register(target_phys_addr_t base, ram_addr_t off, |
|
| 607 |
pflash_t *pflash_cfi02_register(target_phys_addr_t base, |
|
| 608 |
DeviceState *qdev, const char *name, |
|
| 609 |
target_phys_addr_t size, |
|
| 602 | 610 |
BlockDriverState *bs, uint32_t sector_len, |
| 603 | 611 |
int nb_blocs, int nb_mappings, int width, |
| 604 | 612 |
uint16_t id0, uint16_t id1, |
| ... | ... | |
| 618 | 626 |
return NULL; |
| 619 | 627 |
#endif |
| 620 | 628 |
pfl = g_malloc0(sizeof(pflash_t)); |
| 621 |
/* FIXME: Allocate ram ourselves. */ |
|
| 622 |
pfl->storage = qemu_get_ram_ptr(off); |
|
| 623 |
if (be) {
|
|
| 624 |
pfl->fl_mem = cpu_register_io_memory(pflash_read_ops_be, |
|
| 625 |
pflash_write_ops_be, |
|
| 626 |
pfl, DEVICE_NATIVE_ENDIAN); |
|
| 627 |
} else {
|
|
| 628 |
pfl->fl_mem = cpu_register_io_memory(pflash_read_ops_le, |
|
| 629 |
pflash_write_ops_le, |
|
| 630 |
pfl, DEVICE_NATIVE_ENDIAN); |
|
| 631 |
} |
|
| 632 |
pfl->off = off; |
|
| 629 |
memory_region_init_rom_device( |
|
| 630 |
&pfl->orig_mem, be ? &pflash_cfi02_ops_be : &pflash_cfi02_ops_le, pfl, |
|
| 631 |
qdev, name, size); |
|
| 632 |
pfl->storage = memory_region_get_ram_ptr(&pfl->orig_mem); |
|
| 633 | 633 |
pfl->base = base; |
| 634 | 634 |
pfl->chip_len = chip_len; |
| 635 | 635 |
pfl->mappings = nb_mappings; |
| 636 |
pflash_register_memory(pfl, 1); |
|
| 637 | 636 |
pfl->bs = bs; |
| 638 | 637 |
if (pfl->bs) {
|
| 639 | 638 |
/* read the initial flash content */ |
| 640 | 639 |
ret = bdrv_read(pfl->bs, 0, pfl->storage, chip_len >> 9); |
| 641 | 640 |
if (ret < 0) {
|
| 642 |
cpu_unregister_io_memory(pfl->fl_mem); |
|
| 643 | 641 |
g_free(pfl); |
| 644 | 642 |
return NULL; |
| 645 | 643 |
} |
| 646 | 644 |
} |
| 645 |
pflash_setup_mappings(pfl); |
|
| 646 |
pfl->rom_mode = 1; |
|
| 647 |
memory_region_add_subregion(get_system_memory(), pfl->base, &pfl->mem); |
|
| 647 | 648 |
#if 0 /* XXX: there should be a bit to set up read-only, |
| 648 | 649 |
* the same way the hardware does (with WP pin). |
| 649 | 650 |
*/ |
| b/hw/ppc405_boards.c | ||
|---|---|---|
| 32 | 32 |
#include "qemu-log.h" |
| 33 | 33 |
#include "loader.h" |
| 34 | 34 |
#include "blockdev.h" |
| 35 |
#include "exec-memory.h" |
|
| 35 | 36 |
|
| 36 | 37 |
#define BIOS_FILENAME "ppc405_rom.bin" |
| 37 | 38 |
#define BIOS_SIZE (2048 * 1024) |
| ... | ... | |
| 181 | 182 |
ppc4xx_bd_info_t bd; |
| 182 | 183 |
CPUPPCState *env; |
| 183 | 184 |
qemu_irq *pic; |
| 184 |
ram_addr_t sram_offset, bios_offset, bdloc; |
|
| 185 |
MemoryRegion *bios; |
|
| 186 |
ram_addr_t sram_offset, bdloc; |
|
| 185 | 187 |
MemoryRegion *ram_memories = g_malloc(2 * sizeof(*ram_memories)); |
| 186 | 188 |
target_phys_addr_t ram_bases[2], ram_sizes[2]; |
| 187 | 189 |
target_ulong sram_size; |
| ... | ... | |
| 224 | 226 |
dinfo = drive_get(IF_PFLASH, 0, fl_idx); |
| 225 | 227 |
if (dinfo) {
|
| 226 | 228 |
bios_size = bdrv_getlength(dinfo->bdrv); |
| 227 |
bios_offset = qemu_ram_alloc(NULL, "ef405ep.bios", bios_size); |
|
| 228 | 229 |
fl_sectors = (bios_size + 65535) >> 16; |
| 229 | 230 |
#ifdef DEBUG_BOARD_INIT |
| 230 | 231 |
printf("Register parallel flash %d size %lx"
|
| 231 |
" at offset %08lx addr %lx '%s' %d\n",
|
|
| 232 |
fl_idx, bios_size, bios_offset, -bios_size,
|
|
| 232 |
" at addr %lx '%s' %d\n", |
|
| 233 |
fl_idx, bios_size, -bios_size, |
|
| 233 | 234 |
bdrv_get_device_name(dinfo->bdrv), fl_sectors); |
| 234 | 235 |
#endif |
| 235 |
pflash_cfi02_register((uint32_t)(-bios_size), bios_offset, |
|
| 236 |
pflash_cfi02_register((uint32_t)(-bios_size), |
|
| 237 |
NULL, "ef405ep.bios", bios_size, |
|
| 236 | 238 |
dinfo->bdrv, 65536, fl_sectors, 1, |
| 237 | 239 |
2, 0x0001, 0x22DA, 0x0000, 0x0000, 0x555, 0x2AA, |
| 238 | 240 |
1); |
| ... | ... | |
| 243 | 245 |
#ifdef DEBUG_BOARD_INIT |
| 244 | 246 |
printf("Load BIOS from file\n");
|
| 245 | 247 |
#endif |
| 246 |
bios_offset = qemu_ram_alloc(NULL, "ef405ep.bios", BIOS_SIZE); |
|
| 248 |
bios = g_new(MemoryRegion, 1); |
|
| 249 |
memory_region_init_ram(bios, NULL, "ef405ep.bios", BIOS_SIZE); |
|
| 247 | 250 |
if (bios_name == NULL) |
| 248 | 251 |
bios_name = BIOS_FILENAME; |
| 249 | 252 |
filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, bios_name); |
| 250 | 253 |
if (filename) {
|
| 251 |
bios_size = load_image(filename, qemu_get_ram_ptr(bios_offset));
|
|
| 254 |
bios_size = load_image(filename, memory_region_get_ram_ptr(bios));
|
|
| 252 | 255 |
g_free(filename); |
| 253 | 256 |
} else {
|
| 254 | 257 |
bios_size = -1; |
| ... | ... | |
| 259 | 262 |
exit(1); |
| 260 | 263 |
} |
| 261 | 264 |
bios_size = (bios_size + 0xfff) & ~0xfff; |
| 262 |
cpu_register_physical_memory((uint32_t)(-bios_size), |
|
| 263 |
bios_size, bios_offset | IO_MEM_ROM); |
|
| 265 |
memory_region_set_readonly(bios, true); |
|
| 266 |
memory_region_add_subregion(get_system_memory(), |
|
| 267 |
(uint32_t)(-bios_size), bios); |
|
| 264 | 268 |
} |
| 265 | 269 |
/* Register FPGA */ |
| 266 | 270 |
#ifdef DEBUG_BOARD_INIT |
| ... | ... | |
| 507 | 511 |
{
|
| 508 | 512 |
char *filename; |
| 509 | 513 |
qemu_irq *pic; |
| 510 |
ram_addr_t bios_offset;
|
|
| 514 |
MemoryRegion *bios;
|
|
| 511 | 515 |
MemoryRegion *ram_memories = g_malloc(2 * sizeof(*ram_memories)); |
| 512 | 516 |
target_phys_addr_t ram_bases[2], ram_sizes[2]; |
| 513 | 517 |
long bios_size; |
| ... | ... | |
| 544 | 548 |
/* XXX: should check that size is 2MB */ |
| 545 | 549 |
// bios_size = 2 * 1024 * 1024; |
| 546 | 550 |
fl_sectors = (bios_size + 65535) >> 16; |
| 547 |
bios_offset = qemu_ram_alloc(NULL, "taihu_405ep.bios", bios_size); |
|
| 548 | 551 |
#ifdef DEBUG_BOARD_INIT |
| 549 | 552 |
printf("Register parallel flash %d size %lx"
|
| 550 |
" at offset %08lx addr %lx '%s' %d\n",
|
|
| 551 |
fl_idx, bios_size, bios_offset, -bios_size,
|
|
| 553 |
" at addr %lx '%s' %d\n", |
|
| 554 |
fl_idx, bios_size, -bios_size, |
|
| 552 | 555 |
bdrv_get_device_name(dinfo->bdrv), fl_sectors); |
| 553 | 556 |
#endif |
| 554 |
pflash_cfi02_register((uint32_t)(-bios_size), bios_offset, |
|
| 557 |
pflash_cfi02_register((uint32_t)(-bios_size), |
|
| 558 |
NULL, "taihu_405ep.bios", bios_size, |
|
| 555 | 559 |
dinfo->bdrv, 65536, fl_sectors, 1, |
| 556 | 560 |
4, 0x0001, 0x22DA, 0x0000, 0x0000, 0x555, 0x2AA, |
| 557 | 561 |
1); |
| ... | ... | |
| 564 | 568 |
#endif |
| 565 | 569 |
if (bios_name == NULL) |
| 566 | 570 |
bios_name = BIOS_FILENAME; |
| 567 |
bios_offset = qemu_ram_alloc(NULL, "taihu_405ep.bios", BIOS_SIZE); |
|
| 571 |
bios = g_new(MemoryRegion, 1); |
|
| 572 |
memory_region_init_ram(bios, NULL, "taihu_405ep.bios", BIOS_SIZE); |
|
| 568 | 573 |
filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, bios_name); |
| 569 | 574 |
if (filename) {
|
| 570 |
bios_size = load_image(filename, qemu_get_ram_ptr(bios_offset));
|
|
| 575 |
bios_size = load_image(filename, memory_region_get_ram_ptr(bios));
|
|
| 571 | 576 |
g_free(filename); |
| 572 | 577 |
} else {
|
| 573 | 578 |
bios_size = -1; |
| ... | ... | |
| 578 | 583 |
exit(1); |
| 579 | 584 |
} |
| 580 | 585 |
bios_size = (bios_size + 0xfff) & ~0xfff; |
| 581 |
cpu_register_physical_memory((uint32_t)(-bios_size), |
|
| 582 |
bios_size, bios_offset | IO_MEM_ROM); |
|
| 586 |
memory_region_set_readonly(bios, true); |
|
| 587 |
memory_region_add_subregion(get_system_memory(), (uint32_t)(-bios_size), |
|
| 588 |
bios); |
|
| 583 | 589 |
} |
| 584 | 590 |
/* Register Linux flash */ |
| 585 | 591 |
dinfo = drive_get(IF_PFLASH, 0, fl_idx); |
| ... | ... | |
| 590 | 596 |
fl_sectors = (bios_size + 65535) >> 16; |
| 591 | 597 |
#ifdef DEBUG_BOARD_INIT |
| 592 | 598 |
printf("Register parallel flash %d size %lx"
|
| 593 |
" at offset %08lx addr " TARGET_FMT_lx " '%s'\n",
|
|
| 594 |
fl_idx, bios_size, bios_offset, (target_ulong)0xfc000000,
|
|
| 599 |
" at addr " TARGET_FMT_lx " '%s'\n", |
|
| 600 |
fl_idx, bios_size, (target_ulong)0xfc000000, |
|
| 595 | 601 |
bdrv_get_device_name(dinfo->bdrv)); |
| 596 | 602 |
#endif |
| 597 |
bios_offset = qemu_ram_alloc(NULL, "taihu_405ep.flash", bios_size); |
|
| 598 |
pflash_cfi02_register(0xfc000000, bios_offset, |
|
| 603 |
pflash_cfi02_register(0xfc000000, NULL, "taihu_405ep.flash", bios_size, |
|
| 599 | 604 |
dinfo->bdrv, 65536, fl_sectors, 1, |
| 600 | 605 |
4, 0x0001, 0x22DA, 0x0000, 0x0000, 0x555, 0x2AA, |
| 601 | 606 |
1); |
| b/hw/r2d.c | ||
|---|---|---|
| 267 | 267 |
|
| 268 | 268 |
/* onboard flash memory */ |
| 269 | 269 |
dinfo = drive_get(IF_PFLASH, 0, 0); |
| 270 |
pflash_cfi02_register(0x0, qemu_ram_alloc(NULL, "r2d.flash", FLASH_SIZE),
|
|
| 270 |
pflash_cfi02_register(0x0, NULL, "r2d.flash", FLASH_SIZE,
|
|
| 271 | 271 |
dinfo ? dinfo->bdrv : NULL, (16 * 1024), |
| 272 | 272 |
FLASH_SIZE >> 16, |
| 273 | 273 |
1, 4, 0x0000, 0x0000, 0x0000, 0x0000, |
| b/hw/virtex_ml507.c | ||
|---|---|---|
| 196 | 196 |
target_phys_addr_t ram_base = 0; |
| 197 | 197 |
DriveInfo *dinfo; |
| 198 | 198 |
ram_addr_t phys_ram; |
| 199 |
ram_addr_t phys_flash; |
|
| 200 | 199 |
qemu_irq irq[32], *cpu_irq; |
| 201 | 200 |
clk_setup_t clk_setup[7]; |
| 202 | 201 |
int kernel_size; |
| ... | ... | |
| 215 | 214 |
phys_ram = qemu_ram_alloc(NULL, "ram", ram_size); |
| 216 | 215 |
cpu_register_physical_memory(ram_base, ram_size, phys_ram | IO_MEM_RAM); |
| 217 | 216 |
|
| 218 |
phys_flash = qemu_ram_alloc(NULL, "virtex.flash", FLASH_SIZE); |
|
| 219 | 217 |
dinfo = drive_get(IF_PFLASH, 0, 0); |
| 220 |
pflash_cfi01_register(0xfc000000, phys_flash,
|
|
| 218 |
pflash_cfi01_register(0xfc000000, NULL, "virtex.flash", FLASH_SIZE,
|
|
| 221 | 219 |
dinfo ? dinfo->bdrv : NULL, (64 * 1024), |
| 222 | 220 |
FLASH_SIZE >> 16, |
| 223 | 221 |
1, 0x89, 0x18, 0x0000, 0x0, 1); |
| b/hw/z2.c | ||
|---|---|---|
| 305 | 305 |
} |
| 306 | 306 |
|
| 307 | 307 |
if (!pflash_cfi01_register(Z2_FLASH_BASE, |
| 308 |
qemu_ram_alloc(NULL, "z2.flash0", Z2_FLASH_SIZE),
|
|
| 308 |
NULL, "z2.flash0", Z2_FLASH_SIZE,
|
|
| 309 | 309 |
dinfo->bdrv, sector_len, |
| 310 | 310 |
Z2_FLASH_SIZE / sector_len, 4, 0, 0, 0, 0, |
| 311 | 311 |
be)) {
|
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