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1 | d4e8164f | bellard | /*
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2 | d4e8164f | bellard | * internal execution defines for qemu
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3 | d4e8164f | bellard | *
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4 | d4e8164f | bellard | * Copyright (c) 2003 Fabrice Bellard
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5 | d4e8164f | bellard | *
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6 | d4e8164f | bellard | * This library is free software; you can redistribute it and/or
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7 | d4e8164f | bellard | * modify it under the terms of the GNU Lesser General Public
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8 | d4e8164f | bellard | * License as published by the Free Software Foundation; either
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9 | d4e8164f | bellard | * version 2 of the License, or (at your option) any later version.
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10 | d4e8164f | bellard | *
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11 | d4e8164f | bellard | * This library is distributed in the hope that it will be useful,
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12 | d4e8164f | bellard | * but WITHOUT ANY WARRANTY; without even the implied warranty of
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13 | d4e8164f | bellard | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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14 | d4e8164f | bellard | * Lesser General Public License for more details.
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15 | d4e8164f | bellard | *
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16 | d4e8164f | bellard | * You should have received a copy of the GNU Lesser General Public
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17 | d4e8164f | bellard | * License along with this library; if not, write to the Free Software
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18 | d4e8164f | bellard | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
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19 | d4e8164f | bellard | */
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20 | d4e8164f | bellard | |
21 | b346ff46 | bellard | /* allow to see translation results - the slowdown should be negligible, so we leave it */
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22 | b346ff46 | bellard | #define DEBUG_DISAS
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23 | b346ff46 | bellard | |
24 | 33417e70 | bellard | #ifndef glue
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25 | 33417e70 | bellard | #define xglue(x, y) x ## y |
26 | 33417e70 | bellard | #define glue(x, y) xglue(x, y)
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27 | 33417e70 | bellard | #define stringify(s) tostring(s)
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28 | 33417e70 | bellard | #define tostring(s) #s |
29 | 33417e70 | bellard | #endif
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30 | 33417e70 | bellard | |
31 | 33417e70 | bellard | #if GCC_MAJOR < 3 |
32 | 33417e70 | bellard | #define __builtin_expect(x, n) (x)
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33 | 33417e70 | bellard | #endif
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34 | 33417e70 | bellard | |
35 | e2222c39 | bellard | #ifdef __i386__
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36 | e2222c39 | bellard | #define REGPARM(n) __attribute((regparm(n)))
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37 | e2222c39 | bellard | #else
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38 | e2222c39 | bellard | #define REGPARM(n)
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39 | e2222c39 | bellard | #endif
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40 | e2222c39 | bellard | |
41 | b346ff46 | bellard | /* is_jmp field values */
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42 | b346ff46 | bellard | #define DISAS_NEXT 0 /* next instruction can be analyzed */ |
43 | b346ff46 | bellard | #define DISAS_JUMP 1 /* only pc was modified dynamically */ |
44 | b346ff46 | bellard | #define DISAS_UPDATE 2 /* cpu state was modified dynamically */ |
45 | b346ff46 | bellard | #define DISAS_TB_JUMP 3 /* only pc was modified statically */ |
46 | b346ff46 | bellard | |
47 | b346ff46 | bellard | struct TranslationBlock;
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48 | b346ff46 | bellard | |
49 | b346ff46 | bellard | /* XXX: make safe guess about sizes */
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50 | b346ff46 | bellard | #define MAX_OP_PER_INSTR 32 |
51 | b346ff46 | bellard | #define OPC_BUF_SIZE 512 |
52 | b346ff46 | bellard | #define OPC_MAX_SIZE (OPC_BUF_SIZE - MAX_OP_PER_INSTR)
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53 | b346ff46 | bellard | |
54 | b346ff46 | bellard | #define OPPARAM_BUF_SIZE (OPC_BUF_SIZE * 3) |
55 | b346ff46 | bellard | |
56 | b346ff46 | bellard | extern uint16_t gen_opc_buf[OPC_BUF_SIZE];
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57 | b346ff46 | bellard | extern uint32_t gen_opparam_buf[OPPARAM_BUF_SIZE];
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58 | b346ff46 | bellard | extern uint32_t gen_opc_pc[OPC_BUF_SIZE];
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59 | 66e85a21 | bellard | extern uint8_t gen_opc_cc_op[OPC_BUF_SIZE];
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60 | b346ff46 | bellard | extern uint8_t gen_opc_instr_start[OPC_BUF_SIZE];
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61 | b346ff46 | bellard | |
62 | b346ff46 | bellard | #if defined(TARGET_I386)
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63 | b346ff46 | bellard | |
64 | 33417e70 | bellard | #define GEN_FLAG_CODE32_SHIFT 0 |
65 | 33417e70 | bellard | #define GEN_FLAG_ADDSEG_SHIFT 1 |
66 | 33417e70 | bellard | #define GEN_FLAG_SS32_SHIFT 2 |
67 | 33417e70 | bellard | #define GEN_FLAG_VM_SHIFT 3 |
68 | 33417e70 | bellard | #define GEN_FLAG_ST_SHIFT 4 |
69 | 33417e70 | bellard | #define GEN_FLAG_TF_SHIFT 8 /* same position as eflags */ |
70 | 33417e70 | bellard | #define GEN_FLAG_CPL_SHIFT 9 |
71 | 33417e70 | bellard | #define GEN_FLAG_SOFT_MMU_SHIFT 11 |
72 | 33417e70 | bellard | #define GEN_FLAG_IOPL_SHIFT 12 /* same position as eflags */ |
73 | 33417e70 | bellard | |
74 | 33417e70 | bellard | void optimize_flags_init(void); |
75 | d4e8164f | bellard | |
76 | b346ff46 | bellard | #endif
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77 | b346ff46 | bellard | |
78 | b346ff46 | bellard | extern FILE *logfile;
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79 | b346ff46 | bellard | extern int loglevel; |
80 | b346ff46 | bellard | |
81 | 4c3a88a2 | bellard | int gen_intermediate_code(CPUState *env, struct TranslationBlock *tb); |
82 | 4c3a88a2 | bellard | int gen_intermediate_code_pc(CPUState *env, struct TranslationBlock *tb); |
83 | b346ff46 | bellard | void dump_ops(const uint16_t *opc_buf, const uint32_t *opparam_buf); |
84 | 4c3a88a2 | bellard | int cpu_gen_code(CPUState *env, struct TranslationBlock *tb, |
85 | b346ff46 | bellard | int max_code_size, int *gen_code_size_ptr); |
86 | 66e85a21 | bellard | int cpu_restore_state(struct TranslationBlock *tb, |
87 | 66e85a21 | bellard | CPUState *env, unsigned long searched_pc); |
88 | b346ff46 | bellard | void cpu_exec_init(void); |
89 | d4e8164f | bellard | int page_unprotect(unsigned long address); |
90 | 66e85a21 | bellard | void page_unmap(void); |
91 | 33417e70 | bellard | void tlb_flush_page(CPUState *env, uint32_t addr);
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92 | 33417e70 | bellard | void tlb_flush(CPUState *env);
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93 | d4e8164f | bellard | |
94 | d4e8164f | bellard | #define CODE_GEN_MAX_SIZE 65536 |
95 | d4e8164f | bellard | #define CODE_GEN_ALIGN 16 /* must be >= of the size of a icache line */ |
96 | d4e8164f | bellard | |
97 | d4e8164f | bellard | #define CODE_GEN_HASH_BITS 15 |
98 | d4e8164f | bellard | #define CODE_GEN_HASH_SIZE (1 << CODE_GEN_HASH_BITS) |
99 | d4e8164f | bellard | |
100 | d4e8164f | bellard | /* maximum total translate dcode allocated */
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101 | d4e8164f | bellard | #define CODE_GEN_BUFFER_SIZE (2048 * 1024) |
102 | d4e8164f | bellard | //#define CODE_GEN_BUFFER_SIZE (128 * 1024)
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103 | d4e8164f | bellard | |
104 | d4e8164f | bellard | #if defined(__powerpc__)
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105 | d4e8164f | bellard | #define USE_DIRECT_JUMP
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106 | d4e8164f | bellard | #endif
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107 | d4e8164f | bellard | |
108 | d4e8164f | bellard | typedef struct TranslationBlock { |
109 | d4e8164f | bellard | unsigned long pc; /* simulated PC corresponding to this block (EIP + CS base) */ |
110 | d4e8164f | bellard | unsigned long cs_base; /* CS base for this block */ |
111 | d4e8164f | bellard | unsigned int flags; /* flags defining in which context the code was generated */ |
112 | d4e8164f | bellard | uint16_t size; /* size of target code for this block (1 <=
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113 | d4e8164f | bellard | size <= TARGET_PAGE_SIZE) */
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114 | d4e8164f | bellard | uint8_t *tc_ptr; /* pointer to the translated code */
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115 | d4e8164f | bellard | struct TranslationBlock *hash_next; /* next matching block */ |
116 | d4e8164f | bellard | struct TranslationBlock *page_next[2]; /* next blocks in even/odd page */ |
117 | d4e8164f | bellard | /* the following data are used to directly call another TB from
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118 | d4e8164f | bellard | the code of this one. */
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119 | d4e8164f | bellard | uint16_t tb_next_offset[2]; /* offset of original jump target */ |
120 | d4e8164f | bellard | #ifdef USE_DIRECT_JUMP
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121 | d4e8164f | bellard | uint16_t tb_jmp_offset[2]; /* offset of jump instruction */ |
122 | d4e8164f | bellard | #else
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123 | 95f7652d | bellard | uint32_t tb_next[2]; /* address of jump generated code */ |
124 | d4e8164f | bellard | #endif
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125 | d4e8164f | bellard | /* list of TBs jumping to this one. This is a circular list using
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126 | d4e8164f | bellard | the two least significant bits of the pointers to tell what is
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127 | d4e8164f | bellard | the next pointer: 0 = jmp_next[0], 1 = jmp_next[1], 2 =
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128 | d4e8164f | bellard | jmp_first */
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129 | d4e8164f | bellard | struct TranslationBlock *jmp_next[2]; |
130 | d4e8164f | bellard | struct TranslationBlock *jmp_first;
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131 | d4e8164f | bellard | } TranslationBlock; |
132 | d4e8164f | bellard | |
133 | d4e8164f | bellard | static inline unsigned int tb_hash_func(unsigned long pc) |
134 | d4e8164f | bellard | { |
135 | d4e8164f | bellard | return pc & (CODE_GEN_HASH_SIZE - 1); |
136 | d4e8164f | bellard | } |
137 | d4e8164f | bellard | |
138 | d4e8164f | bellard | TranslationBlock *tb_alloc(unsigned long pc); |
139 | d4e8164f | bellard | void tb_flush(void); |
140 | d4e8164f | bellard | void tb_link(TranslationBlock *tb);
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141 | d4e8164f | bellard | |
142 | d4e8164f | bellard | extern TranslationBlock *tb_hash[CODE_GEN_HASH_SIZE];
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143 | d4e8164f | bellard | |
144 | d4e8164f | bellard | extern uint8_t code_gen_buffer[CODE_GEN_BUFFER_SIZE];
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145 | d4e8164f | bellard | extern uint8_t *code_gen_ptr;
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146 | d4e8164f | bellard | |
147 | d4e8164f | bellard | /* find a translation block in the translation cache. If not found,
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148 | d4e8164f | bellard | return NULL and the pointer to the last element of the list in pptb */
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149 | d4e8164f | bellard | static inline TranslationBlock *tb_find(TranslationBlock ***pptb, |
150 | d4e8164f | bellard | unsigned long pc, |
151 | d4e8164f | bellard | unsigned long cs_base, |
152 | d4e8164f | bellard | unsigned int flags) |
153 | d4e8164f | bellard | { |
154 | d4e8164f | bellard | TranslationBlock **ptb, *tb; |
155 | d4e8164f | bellard | unsigned int h; |
156 | d4e8164f | bellard | |
157 | d4e8164f | bellard | h = tb_hash_func(pc); |
158 | d4e8164f | bellard | ptb = &tb_hash[h]; |
159 | d4e8164f | bellard | for(;;) {
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160 | d4e8164f | bellard | tb = *ptb; |
161 | d4e8164f | bellard | if (!tb)
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162 | d4e8164f | bellard | break;
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163 | d4e8164f | bellard | if (tb->pc == pc && tb->cs_base == cs_base && tb->flags == flags)
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164 | d4e8164f | bellard | return tb;
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165 | d4e8164f | bellard | ptb = &tb->hash_next; |
166 | d4e8164f | bellard | } |
167 | d4e8164f | bellard | *pptb = ptb; |
168 | d4e8164f | bellard | return NULL; |
169 | d4e8164f | bellard | } |
170 | d4e8164f | bellard | |
171 | d4e8164f | bellard | #if defined(__powerpc__)
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172 | d4e8164f | bellard | |
173 | d4e8164f | bellard | static inline void tb_set_jmp_target(TranslationBlock *tb, |
174 | d4e8164f | bellard | int n, unsigned long addr) |
175 | d4e8164f | bellard | { |
176 | d4e8164f | bellard | uint32_t val, *ptr; |
177 | d4e8164f | bellard | unsigned long offset; |
178 | d4e8164f | bellard | |
179 | d4e8164f | bellard | offset = (unsigned long)(tb->tc_ptr + tb->tb_jmp_offset[n]); |
180 | d4e8164f | bellard | |
181 | d4e8164f | bellard | /* patch the branch destination */
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182 | d4e8164f | bellard | ptr = (uint32_t *)offset; |
183 | d4e8164f | bellard | val = *ptr; |
184 | d4e8164f | bellard | val = (val & ~0x03fffffc) | ((addr - offset) & 0x03fffffc); |
185 | d4e8164f | bellard | *ptr = val; |
186 | d4e8164f | bellard | /* flush icache */
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187 | d4e8164f | bellard | asm volatile ("dcbst 0,%0" : : "r"(ptr) : "memory"); |
188 | d4e8164f | bellard | asm volatile ("sync" : : : "memory"); |
189 | d4e8164f | bellard | asm volatile ("icbi 0,%0" : : "r"(ptr) : "memory"); |
190 | d4e8164f | bellard | asm volatile ("sync" : : : "memory"); |
191 | d4e8164f | bellard | asm volatile ("isync" : : : "memory"); |
192 | d4e8164f | bellard | } |
193 | d4e8164f | bellard | |
194 | d4e8164f | bellard | #else
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195 | d4e8164f | bellard | |
196 | d4e8164f | bellard | /* set the jump target */
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197 | d4e8164f | bellard | static inline void tb_set_jmp_target(TranslationBlock *tb, |
198 | d4e8164f | bellard | int n, unsigned long addr) |
199 | d4e8164f | bellard | { |
200 | 95f7652d | bellard | tb->tb_next[n] = addr; |
201 | d4e8164f | bellard | } |
202 | d4e8164f | bellard | |
203 | d4e8164f | bellard | #endif
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204 | d4e8164f | bellard | |
205 | d4e8164f | bellard | static inline void tb_add_jump(TranslationBlock *tb, int n, |
206 | d4e8164f | bellard | TranslationBlock *tb_next) |
207 | d4e8164f | bellard | { |
208 | cf25629d | bellard | /* NOTE: this test is only needed for thread safety */
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209 | cf25629d | bellard | if (!tb->jmp_next[n]) {
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210 | cf25629d | bellard | /* patch the native jump address */
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211 | cf25629d | bellard | tb_set_jmp_target(tb, n, (unsigned long)tb_next->tc_ptr); |
212 | cf25629d | bellard | |
213 | cf25629d | bellard | /* add in TB jmp circular list */
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214 | cf25629d | bellard | tb->jmp_next[n] = tb_next->jmp_first; |
215 | cf25629d | bellard | tb_next->jmp_first = (TranslationBlock *)((long)(tb) | (n));
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216 | cf25629d | bellard | } |
217 | d4e8164f | bellard | } |
218 | d4e8164f | bellard | |
219 | a513fe19 | bellard | TranslationBlock *tb_find_pc(unsigned long pc_ptr); |
220 | a513fe19 | bellard | |
221 | d4e8164f | bellard | #ifndef offsetof
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222 | d4e8164f | bellard | #define offsetof(type, field) ((size_t) &((type *)0)->field) |
223 | d4e8164f | bellard | #endif
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224 | d4e8164f | bellard | |
225 | b346ff46 | bellard | #if defined(__powerpc__)
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226 | b346ff46 | bellard | |
227 | b346ff46 | bellard | /* on PowerPC we patch the jump instruction directly */
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228 | 9257a9e4 | bellard | #define JUMP_TB(opname, tbparam, n, eip)\
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229 | b346ff46 | bellard | do {\
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230 | 9257a9e4 | bellard | asm volatile (".section \".data\"\n"\ |
231 | 9257a9e4 | bellard | "__op_label" #n "." stringify(opname) ":\n"\ |
232 | 9257a9e4 | bellard | ".long 1f\n"\
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233 | 9257a9e4 | bellard | ".previous\n"\
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234 | 9257a9e4 | bellard | "b __op_jmp" #n "\n"\ |
235 | 9257a9e4 | bellard | "1:\n");\
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236 | b346ff46 | bellard | T0 = (long)(tbparam) + (n);\
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237 | b346ff46 | bellard | EIP = eip;\ |
238 | 31e8f3c8 | bellard | EXIT_TB();\ |
239 | b346ff46 | bellard | } while (0) |
240 | b346ff46 | bellard | |
241 | b346ff46 | bellard | #else
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242 | b346ff46 | bellard | |
243 | b346ff46 | bellard | /* jump to next block operations (more portable code, does not need
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244 | b346ff46 | bellard | cache flushing, but slower because of indirect jump) */
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245 | 9257a9e4 | bellard | #define JUMP_TB(opname, tbparam, n, eip)\
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246 | b346ff46 | bellard | do {\
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247 | b346ff46 | bellard | static void __attribute__((unused)) *__op_label ## n = &&label ## n;\ |
248 | 2f62b397 | bellard | static void __attribute__((unused)) *dummy ## n = &&dummy_label ## n;\ |
249 | b346ff46 | bellard | goto *(void *)(((TranslationBlock *)tbparam)->tb_next[n]);\ |
250 | b346ff46 | bellard | label ## n:\ |
251 | b346ff46 | bellard | T0 = (long)(tbparam) + (n);\
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252 | b346ff46 | bellard | EIP = eip;\ |
253 | 2f62b397 | bellard | dummy_label ## n:\ |
254 | 9621339d | bellard | EXIT_TB();\ |
255 | b346ff46 | bellard | } while (0) |
256 | b346ff46 | bellard | |
257 | b346ff46 | bellard | #endif
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258 | b346ff46 | bellard | |
259 | 33417e70 | bellard | /* physical memory access */
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260 | 33417e70 | bellard | #define IO_MEM_NB_ENTRIES 256 |
261 | 33417e70 | bellard | #define TLB_INVALID_MASK (1 << 3) |
262 | 33417e70 | bellard | #define IO_MEM_SHIFT 4 |
263 | 33417e70 | bellard | #define IO_MEM_UNASSIGNED (1 << IO_MEM_SHIFT) |
264 | 33417e70 | bellard | |
265 | 33417e70 | bellard | unsigned long physpage_find(unsigned long page); |
266 | 33417e70 | bellard | |
267 | 33417e70 | bellard | extern CPUWriteMemoryFunc *io_mem_write[IO_MEM_NB_ENTRIES][4]; |
268 | 33417e70 | bellard | extern CPUReadMemoryFunc *io_mem_read[IO_MEM_NB_ENTRIES][4]; |
269 | 33417e70 | bellard | |
270 | d4e8164f | bellard | #ifdef __powerpc__
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271 | d4e8164f | bellard | static inline int testandset (int *p) |
272 | d4e8164f | bellard | { |
273 | d4e8164f | bellard | int ret;
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274 | d4e8164f | bellard | __asm__ __volatile__ ( |
275 | d4e8164f | bellard | "0: lwarx %0,0,%1 ;"
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276 | d4e8164f | bellard | " xor. %0,%3,%0;"
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277 | d4e8164f | bellard | " bne 1f;"
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278 | d4e8164f | bellard | " stwcx. %2,0,%1;"
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279 | d4e8164f | bellard | " bne- 0b;"
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280 | d4e8164f | bellard | "1: "
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281 | d4e8164f | bellard | : "=&r" (ret)
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282 | d4e8164f | bellard | : "r" (p), "r" (1), "r" (0) |
283 | d4e8164f | bellard | : "cr0", "memory"); |
284 | d4e8164f | bellard | return ret;
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285 | d4e8164f | bellard | } |
286 | d4e8164f | bellard | #endif
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287 | d4e8164f | bellard | |
288 | d4e8164f | bellard | #ifdef __i386__
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289 | d4e8164f | bellard | static inline int testandset (int *p) |
290 | d4e8164f | bellard | { |
291 | d4e8164f | bellard | char ret;
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292 | d4e8164f | bellard | long int readval; |
293 | d4e8164f | bellard | |
294 | d4e8164f | bellard | __asm__ __volatile__ ("lock; cmpxchgl %3, %1; sete %0"
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295 | d4e8164f | bellard | : "=q" (ret), "=m" (*p), "=a" (readval) |
296 | d4e8164f | bellard | : "r" (1), "m" (*p), "a" (0) |
297 | d4e8164f | bellard | : "memory");
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298 | d4e8164f | bellard | return ret;
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299 | d4e8164f | bellard | } |
300 | d4e8164f | bellard | #endif
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301 | d4e8164f | bellard | |
302 | d4e8164f | bellard | #ifdef __s390__
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303 | d4e8164f | bellard | static inline int testandset (int *p) |
304 | d4e8164f | bellard | { |
305 | d4e8164f | bellard | int ret;
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306 | d4e8164f | bellard | |
307 | d4e8164f | bellard | __asm__ __volatile__ ("0: cs %0,%1,0(%2)\n"
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308 | d4e8164f | bellard | " jl 0b"
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309 | d4e8164f | bellard | : "=&d" (ret)
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310 | d4e8164f | bellard | : "r" (1), "a" (p), "0" (*p) |
311 | d4e8164f | bellard | : "cc", "memory" ); |
312 | d4e8164f | bellard | return ret;
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313 | d4e8164f | bellard | } |
314 | d4e8164f | bellard | #endif
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315 | d4e8164f | bellard | |
316 | d4e8164f | bellard | #ifdef __alpha__
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317 | 2f87c607 | bellard | static inline int testandset (int *p) |
318 | d4e8164f | bellard | { |
319 | d4e8164f | bellard | int ret;
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320 | d4e8164f | bellard | unsigned long one; |
321 | d4e8164f | bellard | |
322 | d4e8164f | bellard | __asm__ __volatile__ ("0: mov 1,%2\n"
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323 | d4e8164f | bellard | " ldl_l %0,%1\n"
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324 | d4e8164f | bellard | " stl_c %2,%1\n"
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325 | d4e8164f | bellard | " beq %2,1f\n"
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326 | d4e8164f | bellard | ".subsection 2\n"
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327 | d4e8164f | bellard | "1: br 0b\n"
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328 | d4e8164f | bellard | ".previous"
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329 | d4e8164f | bellard | : "=r" (ret), "=m" (*p), "=r" (one) |
330 | d4e8164f | bellard | : "m" (*p));
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331 | d4e8164f | bellard | return ret;
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332 | d4e8164f | bellard | } |
333 | d4e8164f | bellard | #endif
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334 | d4e8164f | bellard | |
335 | d4e8164f | bellard | #ifdef __sparc__
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336 | d4e8164f | bellard | static inline int testandset (int *p) |
337 | d4e8164f | bellard | { |
338 | d4e8164f | bellard | int ret;
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339 | d4e8164f | bellard | |
340 | d4e8164f | bellard | __asm__ __volatile__("ldstub [%1], %0"
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341 | d4e8164f | bellard | : "=r" (ret)
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342 | d4e8164f | bellard | : "r" (p)
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343 | d4e8164f | bellard | : "memory");
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344 | d4e8164f | bellard | |
345 | d4e8164f | bellard | return (ret ? 1 : 0); |
346 | d4e8164f | bellard | } |
347 | d4e8164f | bellard | #endif
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348 | d4e8164f | bellard | |
349 | a95c6790 | bellard | #ifdef __arm__
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350 | a95c6790 | bellard | static inline int testandset (int *spinlock) |
351 | a95c6790 | bellard | { |
352 | a95c6790 | bellard | register unsigned int ret; |
353 | a95c6790 | bellard | __asm__ __volatile__("swp %0, %1, [%2]"
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354 | a95c6790 | bellard | : "=r"(ret)
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355 | a95c6790 | bellard | : "0"(1), "r"(spinlock)); |
356 | a95c6790 | bellard | |
357 | a95c6790 | bellard | return ret;
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358 | a95c6790 | bellard | } |
359 | a95c6790 | bellard | #endif
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360 | a95c6790 | bellard | |
361 | 38e584a0 | bellard | #ifdef __mc68000
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362 | 38e584a0 | bellard | static inline int testandset (int *p) |
363 | 38e584a0 | bellard | { |
364 | 38e584a0 | bellard | char ret;
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365 | 38e584a0 | bellard | __asm__ __volatile__("tas %1; sne %0"
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366 | 38e584a0 | bellard | : "=r" (ret)
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367 | 38e584a0 | bellard | : "m" (p)
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368 | 38e584a0 | bellard | : "cc","memory"); |
369 | 38e584a0 | bellard | return ret == 0; |
370 | 38e584a0 | bellard | } |
371 | 38e584a0 | bellard | #endif
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372 | 38e584a0 | bellard | |
373 | d4e8164f | bellard | typedef int spinlock_t; |
374 | d4e8164f | bellard | |
375 | d4e8164f | bellard | #define SPIN_LOCK_UNLOCKED 0 |
376 | d4e8164f | bellard | |
377 | 3c1cf9fa | bellard | #if 1 |
378 | d4e8164f | bellard | static inline void spin_lock(spinlock_t *lock) |
379 | d4e8164f | bellard | { |
380 | d4e8164f | bellard | while (testandset(lock));
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381 | d4e8164f | bellard | } |
382 | d4e8164f | bellard | |
383 | d4e8164f | bellard | static inline void spin_unlock(spinlock_t *lock) |
384 | d4e8164f | bellard | { |
385 | d4e8164f | bellard | *lock = 0;
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386 | d4e8164f | bellard | } |
387 | d4e8164f | bellard | |
388 | d4e8164f | bellard | static inline int spin_trylock(spinlock_t *lock) |
389 | d4e8164f | bellard | { |
390 | d4e8164f | bellard | return !testandset(lock);
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391 | d4e8164f | bellard | } |
392 | 3c1cf9fa | bellard | #else
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393 | 3c1cf9fa | bellard | static inline void spin_lock(spinlock_t *lock) |
394 | 3c1cf9fa | bellard | { |
395 | 3c1cf9fa | bellard | } |
396 | 3c1cf9fa | bellard | |
397 | 3c1cf9fa | bellard | static inline void spin_unlock(spinlock_t *lock) |
398 | 3c1cf9fa | bellard | { |
399 | 3c1cf9fa | bellard | } |
400 | 3c1cf9fa | bellard | |
401 | 3c1cf9fa | bellard | static inline int spin_trylock(spinlock_t *lock) |
402 | 3c1cf9fa | bellard | { |
403 | 3c1cf9fa | bellard | return 1; |
404 | 3c1cf9fa | bellard | } |
405 | 3c1cf9fa | bellard | #endif
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406 | d4e8164f | bellard | |
407 | d4e8164f | bellard | extern spinlock_t tb_lock;
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