Revision d084469c
b/target-sparc/translate.c | ||
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274 | 274 |
tcg_gen_andi_tl(reg, reg, 0x1); |
275 | 275 |
} |
276 | 276 |
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277 |
static inline void gen_cc_clear_icc(void) |
|
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{ |
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tcg_gen_movi_i32(cpu_psr, 0); |
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} |
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#ifdef TARGET_SPARC64 |
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static inline void gen_cc_clear_xcc(void) |
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{ |
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tcg_gen_movi_i32(cpu_xcc, 0); |
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} |
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#endif |
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288 |
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/* old op: |
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if (!T0) |
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env->psr |= PSR_ZERO; |
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if ((int32_t) T0 < 0) |
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env->psr |= PSR_NEG; |
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*/ |
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static inline void gen_cc_NZ_icc(TCGv dst) |
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{ |
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TCGv r_temp; |
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int l1, l2; |
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l1 = gen_new_label(); |
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l2 = gen_new_label(); |
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r_temp = tcg_temp_new(); |
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tcg_gen_andi_tl(r_temp, dst, 0xffffffffULL); |
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tcg_gen_brcondi_tl(TCG_COND_NE, r_temp, 0, l1); |
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tcg_gen_ori_i32(cpu_psr, cpu_psr, PSR_ZERO); |
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gen_set_label(l1); |
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tcg_gen_ext32s_tl(r_temp, dst); |
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tcg_gen_brcondi_tl(TCG_COND_GE, r_temp, 0, l2); |
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tcg_gen_ori_i32(cpu_psr, cpu_psr, PSR_NEG); |
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gen_set_label(l2); |
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tcg_temp_free(r_temp); |
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} |
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|
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#ifdef TARGET_SPARC64 |
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static inline void gen_cc_NZ_xcc(TCGv dst) |
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{ |
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int l1, l2; |
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318 |
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l1 = gen_new_label(); |
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l2 = gen_new_label(); |
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tcg_gen_brcondi_tl(TCG_COND_NE, dst, 0, l1); |
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tcg_gen_ori_i32(cpu_xcc, cpu_xcc, PSR_ZERO); |
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gen_set_label(l1); |
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tcg_gen_brcondi_tl(TCG_COND_GE, dst, 0, l2); |
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tcg_gen_ori_i32(cpu_xcc, cpu_xcc, PSR_NEG); |
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gen_set_label(l2); |
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} |
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#endif |
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329 |
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/* old op: |
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if (T0 < src1) |
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env->psr |= PSR_CARRY; |
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*/ |
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static inline void gen_cc_C_add_icc(TCGv dst, TCGv src1) |
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{ |
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336 |
TCGv r_temp1, r_temp2; |
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int l1; |
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l1 = gen_new_label(); |
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r_temp1 = tcg_temp_new(); |
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r_temp2 = tcg_temp_new(); |
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tcg_gen_andi_tl(r_temp1, dst, 0xffffffffULL); |
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tcg_gen_andi_tl(r_temp2, src1, 0xffffffffULL); |
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tcg_gen_brcond_tl(TCG_COND_GEU, r_temp1, r_temp2, l1); |
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tcg_gen_ori_i32(cpu_psr, cpu_psr, PSR_CARRY); |
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gen_set_label(l1); |
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tcg_temp_free(r_temp1); |
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tcg_temp_free(r_temp2); |
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} |
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#ifdef TARGET_SPARC64 |
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static inline void gen_cc_C_add_xcc(TCGv dst, TCGv src1) |
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{ |
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int l1; |
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l1 = gen_new_label(); |
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tcg_gen_brcond_tl(TCG_COND_GEU, dst, src1, l1); |
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tcg_gen_ori_i32(cpu_xcc, cpu_xcc, PSR_CARRY); |
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gen_set_label(l1); |
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} |
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#endif |
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362 |
|
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/* old op: |
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if (((src1 ^ T1 ^ -1) & (src1 ^ T0)) & (1 << 31)) |
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365 |
env->psr |= PSR_OVF; |
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*/ |
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367 |
static inline void gen_cc_V_add_icc(TCGv dst, TCGv src1, TCGv src2) |
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{ |
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369 |
TCGv r_temp; |
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370 |
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r_temp = tcg_temp_new(); |
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372 |
tcg_gen_xor_tl(r_temp, src1, src2); |
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tcg_gen_not_tl(r_temp, r_temp); |
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374 |
tcg_gen_xor_tl(cpu_tmp0, src1, dst); |
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tcg_gen_and_tl(r_temp, r_temp, cpu_tmp0); |
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tcg_gen_andi_tl(r_temp, r_temp, (1ULL << 31)); |
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tcg_gen_shri_tl(r_temp, r_temp, 31 - PSR_OVF_SHIFT); |
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378 |
tcg_gen_trunc_tl_i32(cpu_tmp32, r_temp); |
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379 |
tcg_temp_free(r_temp); |
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380 |
tcg_gen_or_i32(cpu_psr, cpu_psr, cpu_tmp32); |
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} |
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382 |
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#ifdef TARGET_SPARC64 |
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384 |
static inline void gen_cc_V_add_xcc(TCGv dst, TCGv src1, TCGv src2) |
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385 |
{ |
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386 |
TCGv r_temp; |
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387 |
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r_temp = tcg_temp_new(); |
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389 |
tcg_gen_xor_tl(r_temp, src1, src2); |
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390 |
tcg_gen_not_tl(r_temp, r_temp); |
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391 |
tcg_gen_xor_tl(cpu_tmp0, src1, dst); |
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392 |
tcg_gen_and_tl(r_temp, r_temp, cpu_tmp0); |
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393 |
tcg_gen_andi_tl(r_temp, r_temp, (1ULL << 63)); |
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394 |
tcg_gen_shri_tl(r_temp, r_temp, 63 - PSR_OVF_SHIFT); |
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395 |
tcg_gen_trunc_tl_i32(cpu_tmp32, r_temp); |
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396 |
tcg_temp_free(r_temp); |
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397 |
tcg_gen_or_i32(cpu_xcc, cpu_xcc, cpu_tmp32); |
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398 |
} |
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399 |
#endif |
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400 |
|
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401 | 277 |
static inline void gen_add_tv(TCGv dst, TCGv src1, TCGv src2) |
402 | 278 |
{ |
403 | 279 |
TCGv r_temp; |
... | ... | |
612 | 488 |
tcg_gen_shri_tl(cpu_cc_src, cpu_cc_src, 1); |
613 | 489 |
tcg_gen_or_tl(cpu_cc_src, cpu_cc_src, cpu_tmp0); |
614 | 490 |
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615 |
/* do addition and update flags */ |
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616 | 491 |
tcg_gen_add_tl(cpu_cc_dst, cpu_cc_src, cpu_cc_src2); |
617 | 492 |
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618 |
gen_cc_clear_icc(); |
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619 |
gen_cc_NZ_icc(cpu_cc_dst); |
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620 |
gen_cc_V_add_icc(cpu_cc_dst, cpu_cc_src, cpu_cc_src2); |
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621 |
gen_cc_C_add_icc(cpu_cc_dst, cpu_cc_src); |
|
622 | 493 |
tcg_gen_mov_tl(dst, cpu_cc_dst); |
623 | 494 |
} |
624 | 495 |
|
... | ... | |
3190 | 3061 |
gen_helper_compute_psr(); |
3191 | 3062 |
gen_op_mulscc(cpu_dst, cpu_src1, cpu_src2); |
3192 | 3063 |
gen_movl_TN_reg(rd, cpu_dst); |
3193 |
tcg_gen_movi_i32(cpu_cc_op, CC_OP_FLAGS);
|
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3194 |
dc->cc_op = CC_OP_FLAGS;
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3064 |
tcg_gen_movi_i32(cpu_cc_op, CC_OP_ADD);
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3065 |
dc->cc_op = CC_OP_ADD;
|
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3195 | 3066 |
break; |
3196 | 3067 |
#ifndef TARGET_SPARC64 |
3197 | 3068 |
case 0x25: /* sll */ |
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