Revision d0f2c4c6 hw/hpet.c
| b/hw/hpet.c | ||
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| 32 | 32 |
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| 33 | 33 |
//#define HPET_DEBUG |
| 34 | 34 |
#ifdef HPET_DEBUG |
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#define dprintf printf
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#define DPRINTF printf
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#else |
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#define dprintf(...)
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#define DPRINTF(...)
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#endif |
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static HPETState *hpet_statep; |
| ... | ... | |
| 288 | 288 |
HPETState *s = (HPETState *)opaque; |
| 289 | 289 |
uint64_t cur_tick, index; |
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dprintf("qemu: Enter hpet_ram_readl at %" PRIx64 "\n", addr);
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DPRINTF("qemu: Enter hpet_ram_readl at %" PRIx64 "\n", addr);
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index = addr; |
| 293 | 293 |
/*address range of all TN regs*/ |
| 294 | 294 |
if (index >= 0x100 && index <= 0x3ff) {
|
| ... | ... | |
| 311 | 311 |
case HPET_TN_ROUTE: |
| 312 | 312 |
return timer->fsb >> 32; |
| 313 | 313 |
default: |
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dprintf("qemu: invalid hpet_ram_readl\n");
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DPRINTF("qemu: invalid hpet_ram_readl\n");
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break; |
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} |
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} else {
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| ... | ... | |
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case HPET_CFG: |
| 324 | 324 |
return s->config; |
| 325 | 325 |
case HPET_CFG + 4: |
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dprintf("qemu: invalid HPET_CFG + 4 hpet_ram_readl \n");
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DPRINTF("qemu: invalid HPET_CFG + 4 hpet_ram_readl \n");
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return 0; |
| 328 | 328 |
case HPET_COUNTER: |
| 329 | 329 |
if (hpet_enabled()) |
| 330 | 330 |
cur_tick = hpet_get_ticks(); |
| 331 | 331 |
else |
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cur_tick = s->hpet_counter; |
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dprintf("qemu: reading counter = %" PRIx64 "\n", cur_tick);
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DPRINTF("qemu: reading counter = %" PRIx64 "\n", cur_tick);
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return cur_tick; |
| 335 | 335 |
case HPET_COUNTER + 4: |
| 336 | 336 |
if (hpet_enabled()) |
| 337 | 337 |
cur_tick = hpet_get_ticks(); |
| 338 | 338 |
else |
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cur_tick = s->hpet_counter; |
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dprintf("qemu: reading counter + 4 = %" PRIx64 "\n", cur_tick);
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DPRINTF("qemu: reading counter + 4 = %" PRIx64 "\n", cur_tick);
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return cur_tick >> 32; |
| 342 | 342 |
case HPET_STATUS: |
| 343 | 343 |
return s->isr; |
| 344 | 344 |
default: |
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dprintf("qemu: invalid hpet_ram_readl\n");
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DPRINTF("qemu: invalid hpet_ram_readl\n");
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break; |
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} |
| 348 | 348 |
} |
| ... | ... | |
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HPETState *s = (HPETState *)opaque; |
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uint64_t old_val, new_val, val, index; |
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dprintf("qemu: Enter hpet_ram_writel at %" PRIx64 " = %#x\n", addr, value);
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DPRINTF("qemu: Enter hpet_ram_writel at %" PRIx64 " = %#x\n", addr, value);
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index = addr; |
| 377 | 377 |
old_val = hpet_ram_readl(opaque, addr); |
| 378 | 378 |
new_val = value; |
| ... | ... | |
| 380 | 380 |
/*address range of all TN regs*/ |
| 381 | 381 |
if (index >= 0x100 && index <= 0x3ff) {
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| 382 | 382 |
uint8_t timer_id = (addr - 0x100) / 0x20; |
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dprintf("qemu: hpet_ram_writel timer_id = %#x \n", timer_id);
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DPRINTF("qemu: hpet_ram_writel timer_id = %#x \n", timer_id);
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HPETTimer *timer = &s->timer[timer_id]; |
| 385 | 385 |
|
| 386 | 386 |
switch ((addr - 0x100) % 0x20) {
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| 387 | 387 |
case HPET_TN_CFG: |
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dprintf("qemu: hpet_ram_writel HPET_TN_CFG\n");
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DPRINTF("qemu: hpet_ram_writel HPET_TN_CFG\n");
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val = hpet_fixup_reg(new_val, old_val, HPET_TN_CFG_WRITE_MASK); |
| 390 | 390 |
timer->config = (timer->config & 0xffffffff00000000ULL) | val; |
| 391 | 391 |
if (new_val & HPET_TN_32BIT) {
|
| ... | ... | |
| 399 | 399 |
|
| 400 | 400 |
break; |
| 401 | 401 |
case HPET_TN_CFG + 4: // Interrupt capabilities |
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dprintf("qemu: invalid HPET_TN_CFG+4 write\n");
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DPRINTF("qemu: invalid HPET_TN_CFG+4 write\n");
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| 403 | 403 |
break; |
| 404 | 404 |
case HPET_TN_CMP: // comparator register |
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dprintf("qemu: hpet_ram_writel HPET_TN_CMP \n");
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DPRINTF("qemu: hpet_ram_writel HPET_TN_CMP \n");
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| 406 | 406 |
if (timer->config & HPET_TN_32BIT) |
| 407 | 407 |
new_val = (uint32_t)new_val; |
| 408 | 408 |
if (!timer_is_periodic(timer) || |
| ... | ... | |
| 423 | 423 |
hpet_set_timer(timer); |
| 424 | 424 |
break; |
| 425 | 425 |
case HPET_TN_CMP + 4: // comparator register high order |
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dprintf("qemu: hpet_ram_writel HPET_TN_CMP + 4\n");
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DPRINTF("qemu: hpet_ram_writel HPET_TN_CMP + 4\n");
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| 427 | 427 |
if (!timer_is_periodic(timer) || |
| 428 | 428 |
(timer->config & HPET_TN_SETVAL)) |
| 429 | 429 |
timer->cmp = (timer->cmp & 0xffffffffULL) |
| ... | ... | |
| 443 | 443 |
hpet_set_timer(timer); |
| 444 | 444 |
break; |
| 445 | 445 |
case HPET_TN_ROUTE + 4: |
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dprintf("qemu: hpet_ram_writel HPET_TN_ROUTE + 4\n");
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DPRINTF("qemu: hpet_ram_writel HPET_TN_ROUTE + 4\n");
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| 447 | 447 |
break; |
| 448 | 448 |
default: |
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dprintf("qemu: invalid hpet_ram_writel\n");
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DPRINTF("qemu: invalid hpet_ram_writel\n");
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| 450 | 450 |
break; |
| 451 | 451 |
} |
| 452 | 452 |
return; |
| ... | ... | |
| 479 | 479 |
} |
| 480 | 480 |
break; |
| 481 | 481 |
case HPET_CFG + 4: |
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dprintf("qemu: invalid HPET_CFG+4 write \n");
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DPRINTF("qemu: invalid HPET_CFG+4 write \n");
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| 483 | 483 |
break; |
| 484 | 484 |
case HPET_STATUS: |
| 485 | 485 |
/* FIXME: need to handle level-triggered interrupts */ |
| ... | ... | |
| 489 | 489 |
printf("qemu: Writing counter while HPET enabled!\n");
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| 490 | 490 |
s->hpet_counter = (s->hpet_counter & 0xffffffff00000000ULL) |
| 491 | 491 |
| value; |
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dprintf("qemu: HPET counter written. ctr = %#x -> %" PRIx64 "\n",
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DPRINTF("qemu: HPET counter written. ctr = %#x -> %" PRIx64 "\n",
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| 493 | 493 |
value, s->hpet_counter); |
| 494 | 494 |
break; |
| 495 | 495 |
case HPET_COUNTER + 4: |
| ... | ... | |
| 497 | 497 |
printf("qemu: Writing counter while HPET enabled!\n");
|
| 498 | 498 |
s->hpet_counter = (s->hpet_counter & 0xffffffffULL) |
| 499 | 499 |
| (((uint64_t)value) << 32); |
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dprintf("qemu: HPET counter + 4 written. ctr = %#x -> %" PRIx64 "\n",
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DPRINTF("qemu: HPET counter + 4 written. ctr = %#x -> %" PRIx64 "\n",
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| 501 | 501 |
value, s->hpet_counter); |
| 502 | 502 |
break; |
| 503 | 503 |
default: |
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dprintf("qemu: invalid hpet_ram_writel\n");
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DPRINTF("qemu: invalid hpet_ram_writel\n");
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| 505 | 505 |
break; |
| 506 | 506 |
} |
| 507 | 507 |
} |
| ... | ... | |
| 568 | 568 |
int i, iomemtype; |
| 569 | 569 |
HPETState *s; |
| 570 | 570 |
|
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dprintf ("hpet_init\n");
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DPRINTF ("hpet_init\n");
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| 572 | 572 |
|
| 573 | 573 |
s = qemu_mallocz(sizeof(HPETState)); |
| 574 | 574 |
hpet_statep = s; |
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