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| 1 | 4c9649a9 | j_mayer | /*
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| 2 | 4c9649a9 | j_mayer | * Alpha emulation cpu translation for qemu.
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| 3 | 5fafdf24 | ths | *
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| 4 | 4c9649a9 | j_mayer | * Copyright (c) 2007 Jocelyn Mayer
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| 5 | 4c9649a9 | j_mayer | *
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| 6 | 4c9649a9 | j_mayer | * This library is free software; you can redistribute it and/or
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| 7 | 4c9649a9 | j_mayer | * modify it under the terms of the GNU Lesser General Public
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| 8 | 4c9649a9 | j_mayer | * License as published by the Free Software Foundation; either
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| 9 | 4c9649a9 | j_mayer | * version 2 of the License, or (at your option) any later version.
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| 10 | 4c9649a9 | j_mayer | *
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| 11 | 4c9649a9 | j_mayer | * This library is distributed in the hope that it will be useful,
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| 12 | 4c9649a9 | j_mayer | * but WITHOUT ANY WARRANTY; without even the implied warranty of
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| 13 | 4c9649a9 | j_mayer | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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| 14 | 4c9649a9 | j_mayer | * Lesser General Public License for more details.
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| 15 | 4c9649a9 | j_mayer | *
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| 16 | 4c9649a9 | j_mayer | * You should have received a copy of the GNU Lesser General Public
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| 17 | 4c9649a9 | j_mayer | * License along with this library; if not, write to the Free Software
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| 18 | fad6cb1a | aurel32 | * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston MA 02110-1301 USA
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| 19 | 4c9649a9 | j_mayer | */
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| 20 | 4c9649a9 | j_mayer | |
| 21 | 4c9649a9 | j_mayer | #include <stdint.h> |
| 22 | 4c9649a9 | j_mayer | #include <stdlib.h> |
| 23 | 4c9649a9 | j_mayer | #include <stdio.h> |
| 24 | 4c9649a9 | j_mayer | |
| 25 | 4c9649a9 | j_mayer | #include "cpu.h" |
| 26 | 4c9649a9 | j_mayer | #include "exec-all.h" |
| 27 | 4c9649a9 | j_mayer | #include "disas.h" |
| 28 | ae8ecd42 | aurel32 | #include "host-utils.h" |
| 29 | 57fec1fe | bellard | #include "tcg-op.h" |
| 30 | ca10f867 | aurel32 | #include "qemu-common.h" |
| 31 | 4c9649a9 | j_mayer | |
| 32 | a7812ae4 | pbrook | #include "helper.h" |
| 33 | a7812ae4 | pbrook | #define GEN_HELPER 1 |
| 34 | a7812ae4 | pbrook | #include "helper.h" |
| 35 | a7812ae4 | pbrook | |
| 36 | 55489a17 | aurel32 | /* #define DO_SINGLE_STEP */
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| 37 | 4c9649a9 | j_mayer | #define ALPHA_DEBUG_DISAS
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| 38 | 55489a17 | aurel32 | /* #define DO_TB_FLUSH */
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| 39 | 4c9649a9 | j_mayer | |
| 40 | d12d51d5 | aliguori | |
| 41 | d12d51d5 | aliguori | #ifdef ALPHA_DEBUG_DISAS
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| 42 | d12d51d5 | aliguori | # define LOG_DISAS(...) do { \ |
| 43 | d12d51d5 | aliguori | if (logfile) \
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| 44 | d12d51d5 | aliguori | fprintf(logfile, ## __VA_ARGS__); \ |
| 45 | d12d51d5 | aliguori | } while (0) |
| 46 | d12d51d5 | aliguori | #else
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| 47 | d12d51d5 | aliguori | # define LOG_DISAS(...) do { } while (0) |
| 48 | d12d51d5 | aliguori | #endif
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| 49 | d12d51d5 | aliguori | |
| 50 | 4c9649a9 | j_mayer | typedef struct DisasContext DisasContext; |
| 51 | 4c9649a9 | j_mayer | struct DisasContext {
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| 52 | 4c9649a9 | j_mayer | uint64_t pc; |
| 53 | 4c9649a9 | j_mayer | int mem_idx;
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| 54 | 4c9649a9 | j_mayer | #if !defined (CONFIG_USER_ONLY)
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| 55 | 4c9649a9 | j_mayer | int pal_mode;
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| 56 | 4c9649a9 | j_mayer | #endif
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| 57 | 4c9649a9 | j_mayer | uint32_t amask; |
| 58 | 4c9649a9 | j_mayer | }; |
| 59 | 4c9649a9 | j_mayer | |
| 60 | 3761035f | aurel32 | /* global register indexes */
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| 61 | a7812ae4 | pbrook | static TCGv_ptr cpu_env;
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| 62 | 496cb5b9 | aurel32 | static TCGv cpu_ir[31]; |
| 63 | f18cd223 | aurel32 | static TCGv cpu_fir[31]; |
| 64 | 496cb5b9 | aurel32 | static TCGv cpu_pc;
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| 65 | f4ed8679 | aurel32 | static TCGv cpu_lock;
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| 66 | 496cb5b9 | aurel32 | |
| 67 | 3761035f | aurel32 | /* register names */
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| 68 | f18cd223 | aurel32 | static char cpu_reg_names[10*4+21*5 + 10*5+21*6]; |
| 69 | 2e70f6ef | pbrook | |
| 70 | 2e70f6ef | pbrook | #include "gen-icount.h" |
| 71 | 2e70f6ef | pbrook | |
| 72 | a5f1b965 | blueswir1 | static void alpha_translate_init(void) |
| 73 | 2e70f6ef | pbrook | {
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| 74 | 496cb5b9 | aurel32 | int i;
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| 75 | 496cb5b9 | aurel32 | char *p;
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| 76 | 2e70f6ef | pbrook | static int done_init = 0; |
| 77 | 496cb5b9 | aurel32 | |
| 78 | 2e70f6ef | pbrook | if (done_init)
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| 79 | 2e70f6ef | pbrook | return;
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| 80 | 496cb5b9 | aurel32 | |
| 81 | a7812ae4 | pbrook | cpu_env = tcg_global_reg_new_ptr(TCG_AREG0, "env");
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| 82 | 496cb5b9 | aurel32 | |
| 83 | 496cb5b9 | aurel32 | p = cpu_reg_names; |
| 84 | 496cb5b9 | aurel32 | for (i = 0; i < 31; i++) { |
| 85 | 496cb5b9 | aurel32 | sprintf(p, "ir%d", i);
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| 86 | a7812ae4 | pbrook | cpu_ir[i] = tcg_global_mem_new_i64(TCG_AREG0, |
| 87 | a7812ae4 | pbrook | offsetof(CPUState, ir[i]), p); |
| 88 | 6ba8dcd7 | aurel32 | p += (i < 10) ? 4 : 5; |
| 89 | f18cd223 | aurel32 | |
| 90 | f18cd223 | aurel32 | sprintf(p, "fir%d", i);
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| 91 | a7812ae4 | pbrook | cpu_fir[i] = tcg_global_mem_new_i64(TCG_AREG0, |
| 92 | a7812ae4 | pbrook | offsetof(CPUState, fir[i]), p); |
| 93 | f18cd223 | aurel32 | p += (i < 10) ? 5 : 6; |
| 94 | 496cb5b9 | aurel32 | } |
| 95 | 496cb5b9 | aurel32 | |
| 96 | a7812ae4 | pbrook | cpu_pc = tcg_global_mem_new_i64(TCG_AREG0, |
| 97 | a7812ae4 | pbrook | offsetof(CPUState, pc), "pc");
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| 98 | 496cb5b9 | aurel32 | |
| 99 | a7812ae4 | pbrook | cpu_lock = tcg_global_mem_new_i64(TCG_AREG0, |
| 100 | a7812ae4 | pbrook | offsetof(CPUState, lock), "lock");
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| 101 | f4ed8679 | aurel32 | |
| 102 | 496cb5b9 | aurel32 | /* register helpers */
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| 103 | a7812ae4 | pbrook | #define GEN_HELPER 2 |
| 104 | 496cb5b9 | aurel32 | #include "helper.h" |
| 105 | 496cb5b9 | aurel32 | |
| 106 | 2e70f6ef | pbrook | done_init = 1;
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| 107 | 2e70f6ef | pbrook | } |
| 108 | 2e70f6ef | pbrook | |
| 109 | f071b4d3 | j_mayer | static always_inline void gen_excp (DisasContext *ctx, |
| 110 | f071b4d3 | j_mayer | int exception, int error_code) |
| 111 | 4c9649a9 | j_mayer | {
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| 112 | a7812ae4 | pbrook | TCGv_i32 tmp1, tmp2; |
| 113 | 6ad02592 | aurel32 | |
| 114 | 496cb5b9 | aurel32 | tcg_gen_movi_i64(cpu_pc, ctx->pc); |
| 115 | 6ad02592 | aurel32 | tmp1 = tcg_const_i32(exception); |
| 116 | 6ad02592 | aurel32 | tmp2 = tcg_const_i32(error_code); |
| 117 | a7812ae4 | pbrook | gen_helper_excp(tmp1, tmp2); |
| 118 | a7812ae4 | pbrook | tcg_temp_free_i32(tmp2); |
| 119 | a7812ae4 | pbrook | tcg_temp_free_i32(tmp1); |
| 120 | 4c9649a9 | j_mayer | } |
| 121 | 4c9649a9 | j_mayer | |
| 122 | f071b4d3 | j_mayer | static always_inline void gen_invalid (DisasContext *ctx) |
| 123 | 4c9649a9 | j_mayer | {
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| 124 | 4c9649a9 | j_mayer | gen_excp(ctx, EXCP_OPCDEC, 0);
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| 125 | 4c9649a9 | j_mayer | } |
| 126 | 4c9649a9 | j_mayer | |
| 127 | f18cd223 | aurel32 | static always_inline void gen_qemu_ldf (TCGv t0, TCGv t1, int flags) |
| 128 | f18cd223 | aurel32 | {
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| 129 | a7812ae4 | pbrook | TCGv tmp = tcg_temp_new(); |
| 130 | a7812ae4 | pbrook | TCGv_i32 tmp32 = tcg_temp_new_i32(); |
| 131 | f18cd223 | aurel32 | tcg_gen_qemu_ld32u(tmp, t1, flags); |
| 132 | a7812ae4 | pbrook | tcg_gen_trunc_i64_i32(tmp32, tmp); |
| 133 | a7812ae4 | pbrook | gen_helper_memory_to_f(t0, tmp32); |
| 134 | a7812ae4 | pbrook | tcg_temp_free_i32(tmp32); |
| 135 | f18cd223 | aurel32 | tcg_temp_free(tmp); |
| 136 | f18cd223 | aurel32 | } |
| 137 | f18cd223 | aurel32 | |
| 138 | f18cd223 | aurel32 | static always_inline void gen_qemu_ldg (TCGv t0, TCGv t1, int flags) |
| 139 | f18cd223 | aurel32 | {
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| 140 | a7812ae4 | pbrook | TCGv tmp = tcg_temp_new(); |
| 141 | f18cd223 | aurel32 | tcg_gen_qemu_ld64(tmp, t1, flags); |
| 142 | a7812ae4 | pbrook | gen_helper_memory_to_g(t0, tmp); |
| 143 | f18cd223 | aurel32 | tcg_temp_free(tmp); |
| 144 | f18cd223 | aurel32 | } |
| 145 | f18cd223 | aurel32 | |
| 146 | f18cd223 | aurel32 | static always_inline void gen_qemu_lds (TCGv t0, TCGv t1, int flags) |
| 147 | f18cd223 | aurel32 | {
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| 148 | a7812ae4 | pbrook | TCGv tmp = tcg_temp_new(); |
| 149 | a7812ae4 | pbrook | TCGv_i32 tmp32 = tcg_temp_new_i32(); |
| 150 | f18cd223 | aurel32 | tcg_gen_qemu_ld32u(tmp, t1, flags); |
| 151 | a7812ae4 | pbrook | tcg_gen_trunc_i64_i32(tmp32, tmp); |
| 152 | a7812ae4 | pbrook | gen_helper_memory_to_s(t0, tmp32); |
| 153 | a7812ae4 | pbrook | tcg_temp_free_i32(tmp32); |
| 154 | f18cd223 | aurel32 | tcg_temp_free(tmp); |
| 155 | f18cd223 | aurel32 | } |
| 156 | f18cd223 | aurel32 | |
| 157 | f4ed8679 | aurel32 | static always_inline void gen_qemu_ldl_l (TCGv t0, TCGv t1, int flags) |
| 158 | f4ed8679 | aurel32 | {
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| 159 | f4ed8679 | aurel32 | tcg_gen_mov_i64(cpu_lock, t1); |
| 160 | f4ed8679 | aurel32 | tcg_gen_qemu_ld32s(t0, t1, flags); |
| 161 | f4ed8679 | aurel32 | } |
| 162 | f4ed8679 | aurel32 | |
| 163 | f4ed8679 | aurel32 | static always_inline void gen_qemu_ldq_l (TCGv t0, TCGv t1, int flags) |
| 164 | f4ed8679 | aurel32 | {
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| 165 | f4ed8679 | aurel32 | tcg_gen_mov_i64(cpu_lock, t1); |
| 166 | f4ed8679 | aurel32 | tcg_gen_qemu_ld64(t0, t1, flags); |
| 167 | f4ed8679 | aurel32 | } |
| 168 | f4ed8679 | aurel32 | |
| 169 | 023d8ca2 | aurel32 | static always_inline void gen_load_mem (DisasContext *ctx, |
| 170 | 023d8ca2 | aurel32 | void (*tcg_gen_qemu_load)(TCGv t0, TCGv t1, int flags), |
| 171 | 023d8ca2 | aurel32 | int ra, int rb, int32_t disp16, |
| 172 | f18cd223 | aurel32 | int fp, int clear) |
| 173 | 023d8ca2 | aurel32 | {
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| 174 | 023d8ca2 | aurel32 | TCGv addr; |
| 175 | 023d8ca2 | aurel32 | |
| 176 | 023d8ca2 | aurel32 | if (unlikely(ra == 31)) |
| 177 | 023d8ca2 | aurel32 | return;
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| 178 | 023d8ca2 | aurel32 | |
| 179 | a7812ae4 | pbrook | addr = tcg_temp_new(); |
| 180 | 023d8ca2 | aurel32 | if (rb != 31) { |
| 181 | 023d8ca2 | aurel32 | tcg_gen_addi_i64(addr, cpu_ir[rb], disp16); |
| 182 | 023d8ca2 | aurel32 | if (clear)
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| 183 | 023d8ca2 | aurel32 | tcg_gen_andi_i64(addr, addr, ~0x7);
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| 184 | 023d8ca2 | aurel32 | } else {
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| 185 | 023d8ca2 | aurel32 | if (clear)
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| 186 | 023d8ca2 | aurel32 | disp16 &= ~0x7;
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| 187 | 023d8ca2 | aurel32 | tcg_gen_movi_i64(addr, disp16); |
| 188 | 023d8ca2 | aurel32 | } |
| 189 | f18cd223 | aurel32 | if (fp)
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| 190 | f18cd223 | aurel32 | tcg_gen_qemu_load(cpu_fir[ra], addr, ctx->mem_idx); |
| 191 | f18cd223 | aurel32 | else
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| 192 | f18cd223 | aurel32 | tcg_gen_qemu_load(cpu_ir[ra], addr, ctx->mem_idx); |
| 193 | 023d8ca2 | aurel32 | tcg_temp_free(addr); |
| 194 | 023d8ca2 | aurel32 | } |
| 195 | 023d8ca2 | aurel32 | |
| 196 | f18cd223 | aurel32 | static always_inline void gen_qemu_stf (TCGv t0, TCGv t1, int flags) |
| 197 | f18cd223 | aurel32 | {
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| 198 | a7812ae4 | pbrook | TCGv_i32 tmp32 = tcg_temp_new_i32(); |
| 199 | a7812ae4 | pbrook | TCGv tmp = tcg_temp_new(); |
| 200 | a7812ae4 | pbrook | gen_helper_f_to_memory(tmp32, t0); |
| 201 | a7812ae4 | pbrook | tcg_gen_extu_i32_i64(tmp, tmp32); |
| 202 | f18cd223 | aurel32 | tcg_gen_qemu_st32(tmp, t1, flags); |
| 203 | f18cd223 | aurel32 | tcg_temp_free(tmp); |
| 204 | a7812ae4 | pbrook | tcg_temp_free_i32(tmp32); |
| 205 | f18cd223 | aurel32 | } |
| 206 | f18cd223 | aurel32 | |
| 207 | f18cd223 | aurel32 | static always_inline void gen_qemu_stg (TCGv t0, TCGv t1, int flags) |
| 208 | f18cd223 | aurel32 | {
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| 209 | a7812ae4 | pbrook | TCGv tmp = tcg_temp_new(); |
| 210 | a7812ae4 | pbrook | gen_helper_g_to_memory(tmp, t0); |
| 211 | f18cd223 | aurel32 | tcg_gen_qemu_st64(tmp, t1, flags); |
| 212 | f18cd223 | aurel32 | tcg_temp_free(tmp); |
| 213 | f18cd223 | aurel32 | } |
| 214 | f18cd223 | aurel32 | |
| 215 | f18cd223 | aurel32 | static always_inline void gen_qemu_sts (TCGv t0, TCGv t1, int flags) |
| 216 | f18cd223 | aurel32 | {
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| 217 | a7812ae4 | pbrook | TCGv_i32 tmp32 = tcg_temp_new_i32(); |
| 218 | a7812ae4 | pbrook | TCGv tmp = tcg_temp_new(); |
| 219 | a7812ae4 | pbrook | gen_helper_s_to_memory(tmp32, t0); |
| 220 | a7812ae4 | pbrook | tcg_gen_extu_i32_i64(tmp, tmp32); |
| 221 | f18cd223 | aurel32 | tcg_gen_qemu_st32(tmp, t1, flags); |
| 222 | f18cd223 | aurel32 | tcg_temp_free(tmp); |
| 223 | a7812ae4 | pbrook | tcg_temp_free_i32(tmp32); |
| 224 | f18cd223 | aurel32 | } |
| 225 | f18cd223 | aurel32 | |
| 226 | f4ed8679 | aurel32 | static always_inline void gen_qemu_stl_c (TCGv t0, TCGv t1, int flags) |
| 227 | f4ed8679 | aurel32 | {
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| 228 | f4ed8679 | aurel32 | int l1, l2;
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| 229 | f4ed8679 | aurel32 | |
| 230 | f4ed8679 | aurel32 | l1 = gen_new_label(); |
| 231 | f4ed8679 | aurel32 | l2 = gen_new_label(); |
| 232 | f4ed8679 | aurel32 | tcg_gen_brcond_i64(TCG_COND_NE, cpu_lock, t1, l1); |
| 233 | f4ed8679 | aurel32 | tcg_gen_qemu_st32(t0, t1, flags); |
| 234 | 6223246a | aurel32 | tcg_gen_movi_i64(t0, 1);
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| 235 | f4ed8679 | aurel32 | tcg_gen_br(l2); |
| 236 | f4ed8679 | aurel32 | gen_set_label(l1); |
| 237 | 6223246a | aurel32 | tcg_gen_movi_i64(t0, 0);
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| 238 | f4ed8679 | aurel32 | gen_set_label(l2); |
| 239 | f4ed8679 | aurel32 | tcg_gen_movi_i64(cpu_lock, -1);
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| 240 | f4ed8679 | aurel32 | } |
| 241 | f4ed8679 | aurel32 | |
| 242 | f4ed8679 | aurel32 | static always_inline void gen_qemu_stq_c (TCGv t0, TCGv t1, int flags) |
| 243 | f4ed8679 | aurel32 | {
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| 244 | f4ed8679 | aurel32 | int l1, l2;
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| 245 | f4ed8679 | aurel32 | |
| 246 | f4ed8679 | aurel32 | l1 = gen_new_label(); |
| 247 | f4ed8679 | aurel32 | l2 = gen_new_label(); |
| 248 | f4ed8679 | aurel32 | tcg_gen_brcond_i64(TCG_COND_NE, cpu_lock, t1, l1); |
| 249 | f4ed8679 | aurel32 | tcg_gen_qemu_st64(t0, t1, flags); |
| 250 | 6223246a | aurel32 | tcg_gen_movi_i64(t0, 1);
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| 251 | f4ed8679 | aurel32 | tcg_gen_br(l2); |
| 252 | f4ed8679 | aurel32 | gen_set_label(l1); |
| 253 | 6223246a | aurel32 | tcg_gen_movi_i64(t0, 0);
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| 254 | f4ed8679 | aurel32 | gen_set_label(l2); |
| 255 | f4ed8679 | aurel32 | tcg_gen_movi_i64(cpu_lock, -1);
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| 256 | f4ed8679 | aurel32 | } |
| 257 | f4ed8679 | aurel32 | |
| 258 | 023d8ca2 | aurel32 | static always_inline void gen_store_mem (DisasContext *ctx, |
| 259 | 023d8ca2 | aurel32 | void (*tcg_gen_qemu_store)(TCGv t0, TCGv t1, int flags), |
| 260 | 023d8ca2 | aurel32 | int ra, int rb, int32_t disp16, |
| 261 | 57a92c8e | aurel32 | int fp, int clear, int local) |
| 262 | 023d8ca2 | aurel32 | {
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| 263 | 9cd38c23 | aurel32 | TCGv addr; |
| 264 | 57a92c8e | aurel32 | if (local)
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| 265 | a7812ae4 | pbrook | addr = tcg_temp_local_new(); |
| 266 | 57a92c8e | aurel32 | else
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| 267 | a7812ae4 | pbrook | addr = tcg_temp_new(); |
| 268 | 023d8ca2 | aurel32 | if (rb != 31) { |
| 269 | 023d8ca2 | aurel32 | tcg_gen_addi_i64(addr, cpu_ir[rb], disp16); |
| 270 | 023d8ca2 | aurel32 | if (clear)
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| 271 | 023d8ca2 | aurel32 | tcg_gen_andi_i64(addr, addr, ~0x7);
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| 272 | 023d8ca2 | aurel32 | } else {
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| 273 | 023d8ca2 | aurel32 | if (clear)
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| 274 | 023d8ca2 | aurel32 | disp16 &= ~0x7;
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| 275 | 023d8ca2 | aurel32 | tcg_gen_movi_i64(addr, disp16); |
| 276 | 023d8ca2 | aurel32 | } |
| 277 | f18cd223 | aurel32 | if (ra != 31) { |
| 278 | f18cd223 | aurel32 | if (fp)
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| 279 | f18cd223 | aurel32 | tcg_gen_qemu_store(cpu_fir[ra], addr, ctx->mem_idx); |
| 280 | f18cd223 | aurel32 | else
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| 281 | f18cd223 | aurel32 | tcg_gen_qemu_store(cpu_ir[ra], addr, ctx->mem_idx); |
| 282 | f18cd223 | aurel32 | } else {
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| 283 | 57a92c8e | aurel32 | TCGv zero; |
| 284 | 57a92c8e | aurel32 | if (local)
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| 285 | 57a92c8e | aurel32 | zero = tcg_const_local_i64(0);
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| 286 | 57a92c8e | aurel32 | else
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| 287 | 57a92c8e | aurel32 | zero = tcg_const_i64(0);
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| 288 | 023d8ca2 | aurel32 | tcg_gen_qemu_store(zero, addr, ctx->mem_idx); |
| 289 | 023d8ca2 | aurel32 | tcg_temp_free(zero); |
| 290 | 023d8ca2 | aurel32 | } |
| 291 | 023d8ca2 | aurel32 | tcg_temp_free(addr); |
| 292 | 023d8ca2 | aurel32 | } |
| 293 | 023d8ca2 | aurel32 | |
| 294 | f071b4d3 | j_mayer | static always_inline void gen_bcond (DisasContext *ctx, |
| 295 | 9c29504e | aurel32 | TCGCond cond, |
| 296 | 9c29504e | aurel32 | int ra, int32_t disp16, int mask) |
| 297 | 4c9649a9 | j_mayer | {
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| 298 | 9c29504e | aurel32 | int l1, l2;
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| 299 | 9c29504e | aurel32 | |
| 300 | 9c29504e | aurel32 | l1 = gen_new_label(); |
| 301 | 9c29504e | aurel32 | l2 = gen_new_label(); |
| 302 | 9c29504e | aurel32 | if (likely(ra != 31)) { |
| 303 | 9c29504e | aurel32 | if (mask) {
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| 304 | a7812ae4 | pbrook | TCGv tmp = tcg_temp_new(); |
| 305 | 9c29504e | aurel32 | tcg_gen_andi_i64(tmp, cpu_ir[ra], 1);
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| 306 | 9c29504e | aurel32 | tcg_gen_brcondi_i64(cond, tmp, 0, l1);
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| 307 | 9c29504e | aurel32 | tcg_temp_free(tmp); |
| 308 | 9c29504e | aurel32 | } else
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| 309 | 9c29504e | aurel32 | tcg_gen_brcondi_i64(cond, cpu_ir[ra], 0, l1);
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| 310 | 9c29504e | aurel32 | } else {
|
| 311 | 9c29504e | aurel32 | /* Very uncommon case - Do not bother to optimize. */
|
| 312 | 9c29504e | aurel32 | TCGv tmp = tcg_const_i64(0);
|
| 313 | 9c29504e | aurel32 | tcg_gen_brcondi_i64(cond, tmp, 0, l1);
|
| 314 | 9c29504e | aurel32 | tcg_temp_free(tmp); |
| 315 | 9c29504e | aurel32 | } |
| 316 | 9c29504e | aurel32 | tcg_gen_movi_i64(cpu_pc, ctx->pc); |
| 317 | 9c29504e | aurel32 | tcg_gen_br(l2); |
| 318 | 9c29504e | aurel32 | gen_set_label(l1); |
| 319 | 9c29504e | aurel32 | tcg_gen_movi_i64(cpu_pc, ctx->pc + (int64_t)(disp16 << 2));
|
| 320 | 9c29504e | aurel32 | gen_set_label(l2); |
| 321 | 4c9649a9 | j_mayer | } |
| 322 | 4c9649a9 | j_mayer | |
| 323 | a7812ae4 | pbrook | static always_inline void gen_fbcond (DisasContext *ctx, int opc, |
| 324 | f071b4d3 | j_mayer | int ra, int32_t disp16)
|
| 325 | 4c9649a9 | j_mayer | {
|
| 326 | f18cd223 | aurel32 | int l1, l2;
|
| 327 | f18cd223 | aurel32 | TCGv tmp; |
| 328 | a7812ae4 | pbrook | TCGv src; |
| 329 | f18cd223 | aurel32 | |
| 330 | f18cd223 | aurel32 | l1 = gen_new_label(); |
| 331 | f18cd223 | aurel32 | l2 = gen_new_label(); |
| 332 | f18cd223 | aurel32 | if (ra != 31) { |
| 333 | a7812ae4 | pbrook | tmp = tcg_temp_new(); |
| 334 | a7812ae4 | pbrook | src = cpu_fir[ra]; |
| 335 | f18cd223 | aurel32 | } else {
|
| 336 | f18cd223 | aurel32 | tmp = tcg_const_i64(0);
|
| 337 | a7812ae4 | pbrook | src = tmp; |
| 338 | a7812ae4 | pbrook | } |
| 339 | a7812ae4 | pbrook | switch (opc) {
|
| 340 | a7812ae4 | pbrook | case 0x31: /* FBEQ */ |
| 341 | a7812ae4 | pbrook | gen_helper_cmpfeq(tmp, src); |
| 342 | a7812ae4 | pbrook | break;
|
| 343 | a7812ae4 | pbrook | case 0x32: /* FBLT */ |
| 344 | a7812ae4 | pbrook | gen_helper_cmpflt(tmp, src); |
| 345 | a7812ae4 | pbrook | break;
|
| 346 | a7812ae4 | pbrook | case 0x33: /* FBLE */ |
| 347 | a7812ae4 | pbrook | gen_helper_cmpfle(tmp, src); |
| 348 | a7812ae4 | pbrook | break;
|
| 349 | a7812ae4 | pbrook | case 0x35: /* FBNE */ |
| 350 | a7812ae4 | pbrook | gen_helper_cmpfne(tmp, src); |
| 351 | a7812ae4 | pbrook | break;
|
| 352 | a7812ae4 | pbrook | case 0x36: /* FBGE */ |
| 353 | a7812ae4 | pbrook | gen_helper_cmpfge(tmp, src); |
| 354 | a7812ae4 | pbrook | break;
|
| 355 | a7812ae4 | pbrook | case 0x37: /* FBGT */ |
| 356 | a7812ae4 | pbrook | gen_helper_cmpfgt(tmp, src); |
| 357 | a7812ae4 | pbrook | break;
|
| 358 | a7812ae4 | pbrook | default:
|
| 359 | a7812ae4 | pbrook | abort(); |
| 360 | f18cd223 | aurel32 | } |
| 361 | f18cd223 | aurel32 | tcg_gen_brcondi_i64(TCG_COND_NE, tmp, 0, l1);
|
| 362 | f18cd223 | aurel32 | tcg_gen_movi_i64(cpu_pc, ctx->pc); |
| 363 | f18cd223 | aurel32 | tcg_gen_br(l2); |
| 364 | f18cd223 | aurel32 | gen_set_label(l1); |
| 365 | f18cd223 | aurel32 | tcg_gen_movi_i64(cpu_pc, ctx->pc + (int64_t)(disp16 << 2));
|
| 366 | f18cd223 | aurel32 | gen_set_label(l2); |
| 367 | 4c9649a9 | j_mayer | } |
| 368 | 4c9649a9 | j_mayer | |
| 369 | fe2b269a | aurel32 | static always_inline void gen_cmov (TCGCond inv_cond, |
| 370 | f071b4d3 | j_mayer | int ra, int rb, int rc, |
| 371 | adf3c8b6 | aurel32 | int islit, uint8_t lit, int mask) |
| 372 | 4c9649a9 | j_mayer | {
|
| 373 | 9c29504e | aurel32 | int l1;
|
| 374 | 9c29504e | aurel32 | |
| 375 | 9c29504e | aurel32 | if (unlikely(rc == 31)) |
| 376 | 9c29504e | aurel32 | return;
|
| 377 | 9c29504e | aurel32 | |
| 378 | 9c29504e | aurel32 | l1 = gen_new_label(); |
| 379 | 9c29504e | aurel32 | |
| 380 | 9c29504e | aurel32 | if (ra != 31) { |
| 381 | 9c29504e | aurel32 | if (mask) {
|
| 382 | a7812ae4 | pbrook | TCGv tmp = tcg_temp_new(); |
| 383 | 9c29504e | aurel32 | tcg_gen_andi_i64(tmp, cpu_ir[ra], 1);
|
| 384 | 9c29504e | aurel32 | tcg_gen_brcondi_i64(inv_cond, tmp, 0, l1);
|
| 385 | 9c29504e | aurel32 | tcg_temp_free(tmp); |
| 386 | 9c29504e | aurel32 | } else
|
| 387 | 9c29504e | aurel32 | tcg_gen_brcondi_i64(inv_cond, cpu_ir[ra], 0, l1);
|
| 388 | 9c29504e | aurel32 | } else {
|
| 389 | 9c29504e | aurel32 | /* Very uncommon case - Do not bother to optimize. */
|
| 390 | 9c29504e | aurel32 | TCGv tmp = tcg_const_i64(0);
|
| 391 | 9c29504e | aurel32 | tcg_gen_brcondi_i64(inv_cond, tmp, 0, l1);
|
| 392 | 9c29504e | aurel32 | tcg_temp_free(tmp); |
| 393 | 9c29504e | aurel32 | } |
| 394 | 9c29504e | aurel32 | |
| 395 | 4c9649a9 | j_mayer | if (islit)
|
| 396 | 9c29504e | aurel32 | tcg_gen_movi_i64(cpu_ir[rc], lit); |
| 397 | 4c9649a9 | j_mayer | else
|
| 398 | dfaa8583 | aurel32 | tcg_gen_mov_i64(cpu_ir[rc], cpu_ir[rb]); |
| 399 | 9c29504e | aurel32 | gen_set_label(l1); |
| 400 | 4c9649a9 | j_mayer | } |
| 401 | 4c9649a9 | j_mayer | |
| 402 | a7812ae4 | pbrook | #define FARITH2(name) \
|
| 403 | a7812ae4 | pbrook | static always_inline void glue(gen_f, name)(int rb, int rc) \ |
| 404 | a7812ae4 | pbrook | { \
|
| 405 | a7812ae4 | pbrook | if (unlikely(rc == 31)) \ |
| 406 | a7812ae4 | pbrook | return; \
|
| 407 | a7812ae4 | pbrook | \ |
| 408 | a7812ae4 | pbrook | if (rb != 31) \ |
| 409 | a7812ae4 | pbrook | gen_helper_ ## name (cpu_fir[rc], cpu_fir[rb]); \ |
| 410 | a7812ae4 | pbrook | else { \
|
| 411 | a7812ae4 | pbrook | TCGv tmp = tcg_const_i64(0); \
|
| 412 | a7812ae4 | pbrook | gen_helper_ ## name (cpu_fir[rc], tmp); \ |
| 413 | a7812ae4 | pbrook | tcg_temp_free(tmp); \ |
| 414 | a7812ae4 | pbrook | } \ |
| 415 | 4c9649a9 | j_mayer | } |
| 416 | a7812ae4 | pbrook | FARITH2(sqrts) |
| 417 | a7812ae4 | pbrook | FARITH2(sqrtf) |
| 418 | a7812ae4 | pbrook | FARITH2(sqrtg) |
| 419 | a7812ae4 | pbrook | FARITH2(sqrtt) |
| 420 | a7812ae4 | pbrook | FARITH2(cvtgf) |
| 421 | a7812ae4 | pbrook | FARITH2(cvtgq) |
| 422 | a7812ae4 | pbrook | FARITH2(cvtqf) |
| 423 | a7812ae4 | pbrook | FARITH2(cvtqg) |
| 424 | a7812ae4 | pbrook | FARITH2(cvtst) |
| 425 | a7812ae4 | pbrook | FARITH2(cvtts) |
| 426 | a7812ae4 | pbrook | FARITH2(cvttq) |
| 427 | a7812ae4 | pbrook | FARITH2(cvtqs) |
| 428 | a7812ae4 | pbrook | FARITH2(cvtqt) |
| 429 | a7812ae4 | pbrook | FARITH2(cvtlq) |
| 430 | a7812ae4 | pbrook | FARITH2(cvtql) |
| 431 | a7812ae4 | pbrook | FARITH2(cvtqlv) |
| 432 | a7812ae4 | pbrook | FARITH2(cvtqlsv) |
| 433 | a7812ae4 | pbrook | |
| 434 | a7812ae4 | pbrook | #define FARITH3(name) \
|
| 435 | a7812ae4 | pbrook | static always_inline void glue(gen_f, name) (int ra, int rb, int rc) \ |
| 436 | a7812ae4 | pbrook | { \
|
| 437 | a7812ae4 | pbrook | if (unlikely(rc == 31)) \ |
| 438 | a7812ae4 | pbrook | return; \
|
| 439 | a7812ae4 | pbrook | \ |
| 440 | a7812ae4 | pbrook | if (ra != 31) { \ |
| 441 | a7812ae4 | pbrook | if (rb != 31) \ |
| 442 | a7812ae4 | pbrook | gen_helper_ ## name (cpu_fir[rc], cpu_fir[ra], cpu_fir[rb]); \ |
| 443 | a7812ae4 | pbrook | else { \
|
| 444 | a7812ae4 | pbrook | TCGv tmp = tcg_const_i64(0); \
|
| 445 | a7812ae4 | pbrook | gen_helper_ ## name (cpu_fir[rc], cpu_fir[ra], tmp); \ |
| 446 | a7812ae4 | pbrook | tcg_temp_free(tmp); \ |
| 447 | a7812ae4 | pbrook | } \ |
| 448 | a7812ae4 | pbrook | } else { \
|
| 449 | a7812ae4 | pbrook | TCGv tmp = tcg_const_i64(0); \
|
| 450 | a7812ae4 | pbrook | if (rb != 31) \ |
| 451 | a7812ae4 | pbrook | gen_helper_ ## name (cpu_fir[rc], tmp, cpu_fir[rb]); \ |
| 452 | a7812ae4 | pbrook | else \
|
| 453 | a7812ae4 | pbrook | gen_helper_ ## name (cpu_fir[rc], tmp, tmp); \ |
| 454 | a7812ae4 | pbrook | tcg_temp_free(tmp); \ |
| 455 | a7812ae4 | pbrook | } \ |
| 456 | 4c9649a9 | j_mayer | } |
| 457 | 4c9649a9 | j_mayer | |
| 458 | a7812ae4 | pbrook | FARITH3(addf) |
| 459 | a7812ae4 | pbrook | FARITH3(subf) |
| 460 | a7812ae4 | pbrook | FARITH3(mulf) |
| 461 | a7812ae4 | pbrook | FARITH3(divf) |
| 462 | a7812ae4 | pbrook | FARITH3(addg) |
| 463 | a7812ae4 | pbrook | FARITH3(subg) |
| 464 | a7812ae4 | pbrook | FARITH3(mulg) |
| 465 | a7812ae4 | pbrook | FARITH3(divg) |
| 466 | a7812ae4 | pbrook | FARITH3(cmpgeq) |
| 467 | a7812ae4 | pbrook | FARITH3(cmpglt) |
| 468 | a7812ae4 | pbrook | FARITH3(cmpgle) |
| 469 | a7812ae4 | pbrook | FARITH3(adds) |
| 470 | a7812ae4 | pbrook | FARITH3(subs) |
| 471 | a7812ae4 | pbrook | FARITH3(muls) |
| 472 | a7812ae4 | pbrook | FARITH3(divs) |
| 473 | a7812ae4 | pbrook | FARITH3(addt) |
| 474 | a7812ae4 | pbrook | FARITH3(subt) |
| 475 | a7812ae4 | pbrook | FARITH3(mult) |
| 476 | a7812ae4 | pbrook | FARITH3(divt) |
| 477 | a7812ae4 | pbrook | FARITH3(cmptun) |
| 478 | a7812ae4 | pbrook | FARITH3(cmpteq) |
| 479 | a7812ae4 | pbrook | FARITH3(cmptlt) |
| 480 | a7812ae4 | pbrook | FARITH3(cmptle) |
| 481 | a7812ae4 | pbrook | FARITH3(cpys) |
| 482 | a7812ae4 | pbrook | FARITH3(cpysn) |
| 483 | a7812ae4 | pbrook | FARITH3(cpyse) |
| 484 | a7812ae4 | pbrook | |
| 485 | a7812ae4 | pbrook | #define FCMOV(name) \
|
| 486 | a7812ae4 | pbrook | static always_inline void glue(gen_f, name) (int ra, int rb, int rc) \ |
| 487 | a7812ae4 | pbrook | { \
|
| 488 | a7812ae4 | pbrook | int l1; \
|
| 489 | a7812ae4 | pbrook | TCGv tmp; \ |
| 490 | a7812ae4 | pbrook | \ |
| 491 | a7812ae4 | pbrook | if (unlikely(rc == 31)) \ |
| 492 | a7812ae4 | pbrook | return; \
|
| 493 | a7812ae4 | pbrook | \ |
| 494 | a7812ae4 | pbrook | l1 = gen_new_label(); \ |
| 495 | a7812ae4 | pbrook | tmp = tcg_temp_new(); \ |
| 496 | a7812ae4 | pbrook | if (ra != 31) { \ |
| 497 | a7812ae4 | pbrook | tmp = tcg_temp_new(); \ |
| 498 | a7812ae4 | pbrook | gen_helper_ ## name (tmp, cpu_fir[ra]); \ |
| 499 | a7812ae4 | pbrook | } else { \
|
| 500 | a7812ae4 | pbrook | tmp = tcg_const_i64(0); \
|
| 501 | a7812ae4 | pbrook | gen_helper_ ## name (tmp, tmp); \ |
| 502 | a7812ae4 | pbrook | } \ |
| 503 | a7812ae4 | pbrook | tcg_gen_brcondi_i64(TCG_COND_EQ, tmp, 0, l1); \
|
| 504 | a7812ae4 | pbrook | if (rb != 31) \ |
| 505 | a7812ae4 | pbrook | tcg_gen_mov_i64(cpu_fir[rc], cpu_fir[ra]); \ |
| 506 | a7812ae4 | pbrook | else \
|
| 507 | a7812ae4 | pbrook | tcg_gen_movi_i64(cpu_fir[rc], 0); \
|
| 508 | a7812ae4 | pbrook | gen_set_label(l1); \ |
| 509 | 4c9649a9 | j_mayer | } |
| 510 | a7812ae4 | pbrook | FCMOV(cmpfeq) |
| 511 | a7812ae4 | pbrook | FCMOV(cmpfne) |
| 512 | a7812ae4 | pbrook | FCMOV(cmpflt) |
| 513 | a7812ae4 | pbrook | FCMOV(cmpfge) |
| 514 | a7812ae4 | pbrook | FCMOV(cmpfle) |
| 515 | a7812ae4 | pbrook | FCMOV(cmpfgt) |
| 516 | 4c9649a9 | j_mayer | |
| 517 | b3249f63 | aurel32 | /* EXTWH, EXTWH, EXTLH, EXTQH */
|
| 518 | b3249f63 | aurel32 | static always_inline void gen_ext_h(void (*tcg_gen_ext_i64)(TCGv t0, TCGv t1), |
| 519 | b3249f63 | aurel32 | int ra, int rb, int rc, |
| 520 | adf3c8b6 | aurel32 | int islit, uint8_t lit)
|
| 521 | b3249f63 | aurel32 | {
|
| 522 | b3249f63 | aurel32 | if (unlikely(rc == 31)) |
| 523 | b3249f63 | aurel32 | return;
|
| 524 | b3249f63 | aurel32 | |
| 525 | b3249f63 | aurel32 | if (ra != 31) { |
| 526 | dfaa8583 | aurel32 | if (islit) {
|
| 527 | dfaa8583 | aurel32 | if (lit != 0) |
| 528 | dfaa8583 | aurel32 | tcg_gen_shli_i64(cpu_ir[rc], cpu_ir[ra], 64 - ((lit & 7) * 8)); |
| 529 | dfaa8583 | aurel32 | else
|
| 530 | dfaa8583 | aurel32 | tcg_gen_mov_i64(cpu_ir[rc], cpu_ir[ra]); |
| 531 | fe2b269a | aurel32 | } else {
|
| 532 | b3249f63 | aurel32 | TCGv tmp1, tmp2; |
| 533 | a7812ae4 | pbrook | tmp1 = tcg_temp_new(); |
| 534 | b3249f63 | aurel32 | tcg_gen_andi_i64(tmp1, cpu_ir[rb], 7);
|
| 535 | b3249f63 | aurel32 | tcg_gen_shli_i64(tmp1, tmp1, 3);
|
| 536 | b3249f63 | aurel32 | tmp2 = tcg_const_i64(64);
|
| 537 | b3249f63 | aurel32 | tcg_gen_sub_i64(tmp1, tmp2, tmp1); |
| 538 | b3249f63 | aurel32 | tcg_temp_free(tmp2); |
| 539 | dfaa8583 | aurel32 | tcg_gen_shl_i64(cpu_ir[rc], cpu_ir[ra], tmp1); |
| 540 | b3249f63 | aurel32 | tcg_temp_free(tmp1); |
| 541 | dfaa8583 | aurel32 | } |
| 542 | dfaa8583 | aurel32 | if (tcg_gen_ext_i64)
|
| 543 | dfaa8583 | aurel32 | tcg_gen_ext_i64(cpu_ir[rc], cpu_ir[rc]); |
| 544 | b3249f63 | aurel32 | } else
|
| 545 | b3249f63 | aurel32 | tcg_gen_movi_i64(cpu_ir[rc], 0);
|
| 546 | b3249f63 | aurel32 | } |
| 547 | b3249f63 | aurel32 | |
| 548 | b3249f63 | aurel32 | /* EXTBL, EXTWL, EXTWL, EXTLL, EXTQL */
|
| 549 | b3249f63 | aurel32 | static always_inline void gen_ext_l(void (*tcg_gen_ext_i64)(TCGv t0, TCGv t1), |
| 550 | b3249f63 | aurel32 | int ra, int rb, int rc, |
| 551 | adf3c8b6 | aurel32 | int islit, uint8_t lit)
|
| 552 | b3249f63 | aurel32 | {
|
| 553 | b3249f63 | aurel32 | if (unlikely(rc == 31)) |
| 554 | b3249f63 | aurel32 | return;
|
| 555 | b3249f63 | aurel32 | |
| 556 | b3249f63 | aurel32 | if (ra != 31) { |
| 557 | dfaa8583 | aurel32 | if (islit) {
|
| 558 | dfaa8583 | aurel32 | tcg_gen_shri_i64(cpu_ir[rc], cpu_ir[ra], (lit & 7) * 8); |
| 559 | dfaa8583 | aurel32 | } else {
|
| 560 | a7812ae4 | pbrook | TCGv tmp = tcg_temp_new(); |
| 561 | b3249f63 | aurel32 | tcg_gen_andi_i64(tmp, cpu_ir[rb], 7);
|
| 562 | b3249f63 | aurel32 | tcg_gen_shli_i64(tmp, tmp, 3);
|
| 563 | dfaa8583 | aurel32 | tcg_gen_shr_i64(cpu_ir[rc], cpu_ir[ra], tmp); |
| 564 | b3249f63 | aurel32 | tcg_temp_free(tmp); |
| 565 | fe2b269a | aurel32 | } |
| 566 | dfaa8583 | aurel32 | if (tcg_gen_ext_i64)
|
| 567 | dfaa8583 | aurel32 | tcg_gen_ext_i64(cpu_ir[rc], cpu_ir[rc]); |
| 568 | b3249f63 | aurel32 | } else
|
| 569 | b3249f63 | aurel32 | tcg_gen_movi_i64(cpu_ir[rc], 0);
|
| 570 | b3249f63 | aurel32 | } |
| 571 | b3249f63 | aurel32 | |
| 572 | 04acd307 | aurel32 | /* Code to call arith3 helpers */
|
| 573 | a7812ae4 | pbrook | #define ARITH3(name) \
|
| 574 | a7812ae4 | pbrook | static always_inline void glue(gen_, name) (int ra, int rb, int rc, \ |
| 575 | a7812ae4 | pbrook | int islit, uint8_t lit) \
|
| 576 | a7812ae4 | pbrook | { \
|
| 577 | a7812ae4 | pbrook | if (unlikely(rc == 31)) \ |
| 578 | a7812ae4 | pbrook | return; \
|
| 579 | a7812ae4 | pbrook | \ |
| 580 | a7812ae4 | pbrook | if (ra != 31) { \ |
| 581 | a7812ae4 | pbrook | if (islit) { \
|
| 582 | a7812ae4 | pbrook | TCGv tmp = tcg_const_i64(lit); \ |
| 583 | a7812ae4 | pbrook | gen_helper_ ## name(cpu_ir[rc], cpu_ir[ra], tmp); \ |
| 584 | a7812ae4 | pbrook | tcg_temp_free(tmp); \ |
| 585 | a7812ae4 | pbrook | } else \
|
| 586 | a7812ae4 | pbrook | gen_helper_ ## name (cpu_ir[rc], cpu_ir[ra], cpu_ir[rb]); \ |
| 587 | a7812ae4 | pbrook | } else { \
|
| 588 | a7812ae4 | pbrook | TCGv tmp1 = tcg_const_i64(0); \
|
| 589 | a7812ae4 | pbrook | if (islit) { \
|
| 590 | a7812ae4 | pbrook | TCGv tmp2 = tcg_const_i64(lit); \ |
| 591 | a7812ae4 | pbrook | gen_helper_ ## name (cpu_ir[rc], tmp1, tmp2); \ |
| 592 | a7812ae4 | pbrook | tcg_temp_free(tmp2); \ |
| 593 | a7812ae4 | pbrook | } else \
|
| 594 | a7812ae4 | pbrook | gen_helper_ ## name (cpu_ir[rc], tmp1, cpu_ir[rb]); \ |
| 595 | a7812ae4 | pbrook | tcg_temp_free(tmp1); \ |
| 596 | a7812ae4 | pbrook | } \ |
| 597 | b3249f63 | aurel32 | } |
| 598 | a7812ae4 | pbrook | ARITH3(cmpbge) |
| 599 | a7812ae4 | pbrook | ARITH3(addlv) |
| 600 | a7812ae4 | pbrook | ARITH3(sublv) |
| 601 | a7812ae4 | pbrook | ARITH3(addqv) |
| 602 | a7812ae4 | pbrook | ARITH3(subqv) |
| 603 | a7812ae4 | pbrook | ARITH3(mskbl) |
| 604 | a7812ae4 | pbrook | ARITH3(insbl) |
| 605 | a7812ae4 | pbrook | ARITH3(mskwl) |
| 606 | a7812ae4 | pbrook | ARITH3(inswl) |
| 607 | a7812ae4 | pbrook | ARITH3(mskll) |
| 608 | a7812ae4 | pbrook | ARITH3(insll) |
| 609 | a7812ae4 | pbrook | ARITH3(zap) |
| 610 | a7812ae4 | pbrook | ARITH3(zapnot) |
| 611 | a7812ae4 | pbrook | ARITH3(mskql) |
| 612 | a7812ae4 | pbrook | ARITH3(insql) |
| 613 | a7812ae4 | pbrook | ARITH3(mskwh) |
| 614 | a7812ae4 | pbrook | ARITH3(inswh) |
| 615 | a7812ae4 | pbrook | ARITH3(msklh) |
| 616 | a7812ae4 | pbrook | ARITH3(inslh) |
| 617 | a7812ae4 | pbrook | ARITH3(mskqh) |
| 618 | a7812ae4 | pbrook | ARITH3(insqh) |
| 619 | a7812ae4 | pbrook | ARITH3(umulh) |
| 620 | a7812ae4 | pbrook | ARITH3(mullv) |
| 621 | a7812ae4 | pbrook | ARITH3(mulqv) |
| 622 | b3249f63 | aurel32 | |
| 623 | 01ff9cc8 | aurel32 | static always_inline void gen_cmp(TCGCond cond, |
| 624 | 01ff9cc8 | aurel32 | int ra, int rb, int rc, |
| 625 | a1cf28f4 | aurel32 | int islit, uint8_t lit)
|
| 626 | 01ff9cc8 | aurel32 | {
|
| 627 | 01ff9cc8 | aurel32 | int l1, l2;
|
| 628 | 01ff9cc8 | aurel32 | TCGv tmp; |
| 629 | 01ff9cc8 | aurel32 | |
| 630 | 01ff9cc8 | aurel32 | if (unlikely(rc == 31)) |
| 631 | 01ff9cc8 | aurel32 | return;
|
| 632 | 01ff9cc8 | aurel32 | |
| 633 | 01ff9cc8 | aurel32 | l1 = gen_new_label(); |
| 634 | 01ff9cc8 | aurel32 | l2 = gen_new_label(); |
| 635 | 01ff9cc8 | aurel32 | |
| 636 | 01ff9cc8 | aurel32 | if (ra != 31) { |
| 637 | a7812ae4 | pbrook | tmp = tcg_temp_new(); |
| 638 | 01ff9cc8 | aurel32 | tcg_gen_mov_i64(tmp, cpu_ir[ra]); |
| 639 | 01ff9cc8 | aurel32 | } else
|
| 640 | 01ff9cc8 | aurel32 | tmp = tcg_const_i64(0);
|
| 641 | 01ff9cc8 | aurel32 | if (islit)
|
| 642 | 01ff9cc8 | aurel32 | tcg_gen_brcondi_i64(cond, tmp, lit, l1); |
| 643 | 01ff9cc8 | aurel32 | else
|
| 644 | dfaa8583 | aurel32 | tcg_gen_brcond_i64(cond, tmp, cpu_ir[rb], l1); |
| 645 | 01ff9cc8 | aurel32 | |
| 646 | 01ff9cc8 | aurel32 | tcg_gen_movi_i64(cpu_ir[rc], 0);
|
| 647 | 01ff9cc8 | aurel32 | tcg_gen_br(l2); |
| 648 | 01ff9cc8 | aurel32 | gen_set_label(l1); |
| 649 | 01ff9cc8 | aurel32 | tcg_gen_movi_i64(cpu_ir[rc], 1);
|
| 650 | 01ff9cc8 | aurel32 | gen_set_label(l2); |
| 651 | 01ff9cc8 | aurel32 | } |
| 652 | 01ff9cc8 | aurel32 | |
| 653 | f071b4d3 | j_mayer | static always_inline int translate_one (DisasContext *ctx, uint32_t insn) |
| 654 | 4c9649a9 | j_mayer | {
|
| 655 | 4c9649a9 | j_mayer | uint32_t palcode; |
| 656 | 4c9649a9 | j_mayer | int32_t disp21, disp16, disp12; |
| 657 | 4c9649a9 | j_mayer | uint16_t fn11, fn16; |
| 658 | 4c9649a9 | j_mayer | uint8_t opc, ra, rb, rc, sbz, fpfn, fn7, fn2, islit; |
| 659 | adf3c8b6 | aurel32 | uint8_t lit; |
| 660 | 4c9649a9 | j_mayer | int ret;
|
| 661 | 4c9649a9 | j_mayer | |
| 662 | 4c9649a9 | j_mayer | /* Decode all instruction fields */
|
| 663 | 4c9649a9 | j_mayer | opc = insn >> 26;
|
| 664 | 4c9649a9 | j_mayer | ra = (insn >> 21) & 0x1F; |
| 665 | 4c9649a9 | j_mayer | rb = (insn >> 16) & 0x1F; |
| 666 | 4c9649a9 | j_mayer | rc = insn & 0x1F;
|
| 667 | 4c9649a9 | j_mayer | sbz = (insn >> 13) & 0x07; |
| 668 | 4c9649a9 | j_mayer | islit = (insn >> 12) & 1; |
| 669 | dfaa8583 | aurel32 | if (rb == 31 && !islit) { |
| 670 | dfaa8583 | aurel32 | islit = 1;
|
| 671 | dfaa8583 | aurel32 | lit = 0;
|
| 672 | dfaa8583 | aurel32 | } else
|
| 673 | dfaa8583 | aurel32 | lit = (insn >> 13) & 0xFF; |
| 674 | 4c9649a9 | j_mayer | palcode = insn & 0x03FFFFFF;
|
| 675 | 4c9649a9 | j_mayer | disp21 = ((int32_t)((insn & 0x001FFFFF) << 11)) >> 11; |
| 676 | 4c9649a9 | j_mayer | disp16 = (int16_t)(insn & 0x0000FFFF);
|
| 677 | 4c9649a9 | j_mayer | disp12 = (int32_t)((insn & 0x00000FFF) << 20) >> 20; |
| 678 | 4c9649a9 | j_mayer | fn16 = insn & 0x0000FFFF;
|
| 679 | 4c9649a9 | j_mayer | fn11 = (insn >> 5) & 0x000007FF; |
| 680 | 4c9649a9 | j_mayer | fpfn = fn11 & 0x3F;
|
| 681 | 4c9649a9 | j_mayer | fn7 = (insn >> 5) & 0x0000007F; |
| 682 | 4c9649a9 | j_mayer | fn2 = (insn >> 5) & 0x00000003; |
| 683 | 4c9649a9 | j_mayer | ret = 0;
|
| 684 | d12d51d5 | aliguori | LOG_DISAS("opc %02x ra %d rb %d rc %d disp16 %04x\n",
|
| 685 | d12d51d5 | aliguori | opc, ra, rb, rc, disp16); |
| 686 | 4c9649a9 | j_mayer | switch (opc) {
|
| 687 | 4c9649a9 | j_mayer | case 0x00: |
| 688 | 4c9649a9 | j_mayer | /* CALL_PAL */
|
| 689 | 4c9649a9 | j_mayer | if (palcode >= 0x80 && palcode < 0xC0) { |
| 690 | 4c9649a9 | j_mayer | /* Unprivileged PAL call */
|
| 691 | 4c9649a9 | j_mayer | gen_excp(ctx, EXCP_CALL_PAL + ((palcode & 0x1F) << 6), 0); |
| 692 | 4c9649a9 | j_mayer | #if !defined (CONFIG_USER_ONLY)
|
| 693 | 4c9649a9 | j_mayer | } else if (palcode < 0x40) { |
| 694 | 4c9649a9 | j_mayer | /* Privileged PAL code */
|
| 695 | 4c9649a9 | j_mayer | if (ctx->mem_idx & 1) |
| 696 | 4c9649a9 | j_mayer | goto invalid_opc;
|
| 697 | 4c9649a9 | j_mayer | else
|
| 698 | 4c9649a9 | j_mayer | gen_excp(ctx, EXCP_CALL_PALP + ((palcode & 0x1F) << 6), 0); |
| 699 | 4c9649a9 | j_mayer | #endif
|
| 700 | 4c9649a9 | j_mayer | } else {
|
| 701 | 4c9649a9 | j_mayer | /* Invalid PAL call */
|
| 702 | 4c9649a9 | j_mayer | goto invalid_opc;
|
| 703 | 4c9649a9 | j_mayer | } |
| 704 | 4c9649a9 | j_mayer | ret = 3;
|
| 705 | 4c9649a9 | j_mayer | break;
|
| 706 | 4c9649a9 | j_mayer | case 0x01: |
| 707 | 4c9649a9 | j_mayer | /* OPC01 */
|
| 708 | 4c9649a9 | j_mayer | goto invalid_opc;
|
| 709 | 4c9649a9 | j_mayer | case 0x02: |
| 710 | 4c9649a9 | j_mayer | /* OPC02 */
|
| 711 | 4c9649a9 | j_mayer | goto invalid_opc;
|
| 712 | 4c9649a9 | j_mayer | case 0x03: |
| 713 | 4c9649a9 | j_mayer | /* OPC03 */
|
| 714 | 4c9649a9 | j_mayer | goto invalid_opc;
|
| 715 | 4c9649a9 | j_mayer | case 0x04: |
| 716 | 4c9649a9 | j_mayer | /* OPC04 */
|
| 717 | 4c9649a9 | j_mayer | goto invalid_opc;
|
| 718 | 4c9649a9 | j_mayer | case 0x05: |
| 719 | 4c9649a9 | j_mayer | /* OPC05 */
|
| 720 | 4c9649a9 | j_mayer | goto invalid_opc;
|
| 721 | 4c9649a9 | j_mayer | case 0x06: |
| 722 | 4c9649a9 | j_mayer | /* OPC06 */
|
| 723 | 4c9649a9 | j_mayer | goto invalid_opc;
|
| 724 | 4c9649a9 | j_mayer | case 0x07: |
| 725 | 4c9649a9 | j_mayer | /* OPC07 */
|
| 726 | 4c9649a9 | j_mayer | goto invalid_opc;
|
| 727 | 4c9649a9 | j_mayer | case 0x08: |
| 728 | 4c9649a9 | j_mayer | /* LDA */
|
| 729 | 1ef4ef4e | aurel32 | if (likely(ra != 31)) { |
| 730 | 496cb5b9 | aurel32 | if (rb != 31) |
| 731 | 3761035f | aurel32 | tcg_gen_addi_i64(cpu_ir[ra], cpu_ir[rb], disp16); |
| 732 | 3761035f | aurel32 | else
|
| 733 | 3761035f | aurel32 | tcg_gen_movi_i64(cpu_ir[ra], disp16); |
| 734 | 496cb5b9 | aurel32 | } |
| 735 | 4c9649a9 | j_mayer | break;
|
| 736 | 4c9649a9 | j_mayer | case 0x09: |
| 737 | 4c9649a9 | j_mayer | /* LDAH */
|
| 738 | 1ef4ef4e | aurel32 | if (likely(ra != 31)) { |
| 739 | 496cb5b9 | aurel32 | if (rb != 31) |
| 740 | 3761035f | aurel32 | tcg_gen_addi_i64(cpu_ir[ra], cpu_ir[rb], disp16 << 16);
|
| 741 | 3761035f | aurel32 | else
|
| 742 | 3761035f | aurel32 | tcg_gen_movi_i64(cpu_ir[ra], disp16 << 16);
|
| 743 | 496cb5b9 | aurel32 | } |
| 744 | 4c9649a9 | j_mayer | break;
|
| 745 | 4c9649a9 | j_mayer | case 0x0A: |
| 746 | 4c9649a9 | j_mayer | /* LDBU */
|
| 747 | 4c9649a9 | j_mayer | if (!(ctx->amask & AMASK_BWX))
|
| 748 | 4c9649a9 | j_mayer | goto invalid_opc;
|
| 749 | f18cd223 | aurel32 | gen_load_mem(ctx, &tcg_gen_qemu_ld8u, ra, rb, disp16, 0, 0); |
| 750 | 4c9649a9 | j_mayer | break;
|
| 751 | 4c9649a9 | j_mayer | case 0x0B: |
| 752 | 4c9649a9 | j_mayer | /* LDQ_U */
|
| 753 | f18cd223 | aurel32 | gen_load_mem(ctx, &tcg_gen_qemu_ld64, ra, rb, disp16, 0, 1); |
| 754 | 4c9649a9 | j_mayer | break;
|
| 755 | 4c9649a9 | j_mayer | case 0x0C: |
| 756 | 4c9649a9 | j_mayer | /* LDWU */
|
| 757 | 4c9649a9 | j_mayer | if (!(ctx->amask & AMASK_BWX))
|
| 758 | 4c9649a9 | j_mayer | goto invalid_opc;
|
| 759 | f18cd223 | aurel32 | gen_load_mem(ctx, &tcg_gen_qemu_ld16u, ra, rb, disp16, 0, 1); |
| 760 | 4c9649a9 | j_mayer | break;
|
| 761 | 4c9649a9 | j_mayer | case 0x0D: |
| 762 | 4c9649a9 | j_mayer | /* STW */
|
| 763 | 57a92c8e | aurel32 | gen_store_mem(ctx, &tcg_gen_qemu_st16, ra, rb, disp16, 0, 0, 0); |
| 764 | 4c9649a9 | j_mayer | break;
|
| 765 | 4c9649a9 | j_mayer | case 0x0E: |
| 766 | 4c9649a9 | j_mayer | /* STB */
|
| 767 | 57a92c8e | aurel32 | gen_store_mem(ctx, &tcg_gen_qemu_st8, ra, rb, disp16, 0, 0, 0); |
| 768 | 4c9649a9 | j_mayer | break;
|
| 769 | 4c9649a9 | j_mayer | case 0x0F: |
| 770 | 4c9649a9 | j_mayer | /* STQ_U */
|
| 771 | 57a92c8e | aurel32 | gen_store_mem(ctx, &tcg_gen_qemu_st64, ra, rb, disp16, 0, 1, 0); |
| 772 | 4c9649a9 | j_mayer | break;
|
| 773 | 4c9649a9 | j_mayer | case 0x10: |
| 774 | 4c9649a9 | j_mayer | switch (fn7) {
|
| 775 | 4c9649a9 | j_mayer | case 0x00: |
| 776 | 4c9649a9 | j_mayer | /* ADDL */
|
| 777 | 30c7183b | aurel32 | if (likely(rc != 31)) { |
| 778 | 30c7183b | aurel32 | if (ra != 31) { |
| 779 | 30c7183b | aurel32 | if (islit) {
|
| 780 | 30c7183b | aurel32 | tcg_gen_addi_i64(cpu_ir[rc], cpu_ir[ra], lit); |
| 781 | 30c7183b | aurel32 | tcg_gen_ext32s_i64(cpu_ir[rc], cpu_ir[rc]); |
| 782 | dfaa8583 | aurel32 | } else {
|
| 783 | 30c7183b | aurel32 | tcg_gen_add_i64(cpu_ir[rc], cpu_ir[ra], cpu_ir[rb]); |
| 784 | 30c7183b | aurel32 | tcg_gen_ext32s_i64(cpu_ir[rc], cpu_ir[rc]); |
| 785 | dfaa8583 | aurel32 | } |
| 786 | 30c7183b | aurel32 | } else {
|
| 787 | 30c7183b | aurel32 | if (islit)
|
| 788 | dfaa8583 | aurel32 | tcg_gen_movi_i64(cpu_ir[rc], lit); |
| 789 | 30c7183b | aurel32 | else
|
| 790 | dfaa8583 | aurel32 | tcg_gen_ext32s_i64(cpu_ir[rc], cpu_ir[rb]); |
| 791 | 30c7183b | aurel32 | } |
| 792 | 30c7183b | aurel32 | } |
| 793 | 4c9649a9 | j_mayer | break;
|
| 794 | 4c9649a9 | j_mayer | case 0x02: |
| 795 | 4c9649a9 | j_mayer | /* S4ADDL */
|
| 796 | 30c7183b | aurel32 | if (likely(rc != 31)) { |
| 797 | 30c7183b | aurel32 | if (ra != 31) { |
| 798 | a7812ae4 | pbrook | TCGv tmp = tcg_temp_new(); |
| 799 | dfaa8583 | aurel32 | tcg_gen_shli_i64(tmp, cpu_ir[ra], 2);
|
| 800 | dfaa8583 | aurel32 | if (islit)
|
| 801 | dfaa8583 | aurel32 | tcg_gen_addi_i64(tmp, tmp, lit); |
| 802 | dfaa8583 | aurel32 | else
|
| 803 | dfaa8583 | aurel32 | tcg_gen_add_i64(tmp, tmp, cpu_ir[rb]); |
| 804 | dfaa8583 | aurel32 | tcg_gen_ext32s_i64(cpu_ir[rc], tmp); |
| 805 | dfaa8583 | aurel32 | tcg_temp_free(tmp); |
| 806 | 30c7183b | aurel32 | } else {
|
| 807 | 30c7183b | aurel32 | if (islit)
|
| 808 | 30c7183b | aurel32 | tcg_gen_movi_i64(cpu_ir[rc], lit); |
| 809 | 30c7183b | aurel32 | else
|
| 810 | dfaa8583 | aurel32 | tcg_gen_ext32s_i64(cpu_ir[rc], cpu_ir[rb]); |
| 811 | 30c7183b | aurel32 | } |
| 812 | 30c7183b | aurel32 | } |
| 813 | 4c9649a9 | j_mayer | break;
|
| 814 | 4c9649a9 | j_mayer | case 0x09: |
| 815 | 4c9649a9 | j_mayer | /* SUBL */
|
| 816 | 30c7183b | aurel32 | if (likely(rc != 31)) { |
| 817 | 30c7183b | aurel32 | if (ra != 31) { |
| 818 | dfaa8583 | aurel32 | if (islit)
|
| 819 | 30c7183b | aurel32 | tcg_gen_subi_i64(cpu_ir[rc], cpu_ir[ra], lit); |
| 820 | dfaa8583 | aurel32 | else
|
| 821 | 30c7183b | aurel32 | tcg_gen_sub_i64(cpu_ir[rc], cpu_ir[ra], cpu_ir[rb]); |
| 822 | dfaa8583 | aurel32 | tcg_gen_ext32s_i64(cpu_ir[rc], cpu_ir[rc]); |
| 823 | 30c7183b | aurel32 | } else {
|
| 824 | 30c7183b | aurel32 | if (islit)
|
| 825 | 30c7183b | aurel32 | tcg_gen_movi_i64(cpu_ir[rc], -lit); |
| 826 | dfaa8583 | aurel32 | else {
|
| 827 | 30c7183b | aurel32 | tcg_gen_neg_i64(cpu_ir[rc], cpu_ir[rb]); |
| 828 | 30c7183b | aurel32 | tcg_gen_ext32s_i64(cpu_ir[rc], cpu_ir[rc]); |
| 829 | 30c7183b | aurel32 | } |
| 830 | 30c7183b | aurel32 | } |
| 831 | 4c9649a9 | j_mayer | break;
|
| 832 | 4c9649a9 | j_mayer | case 0x0B: |
| 833 | 4c9649a9 | j_mayer | /* S4SUBL */
|
| 834 | 30c7183b | aurel32 | if (likely(rc != 31)) { |
| 835 | 30c7183b | aurel32 | if (ra != 31) { |
| 836 | a7812ae4 | pbrook | TCGv tmp = tcg_temp_new(); |
| 837 | dfaa8583 | aurel32 | tcg_gen_shli_i64(tmp, cpu_ir[ra], 2);
|
| 838 | dfaa8583 | aurel32 | if (islit)
|
| 839 | dfaa8583 | aurel32 | tcg_gen_subi_i64(tmp, tmp, lit); |
| 840 | dfaa8583 | aurel32 | else
|
| 841 | dfaa8583 | aurel32 | tcg_gen_sub_i64(tmp, tmp, cpu_ir[rb]); |
| 842 | dfaa8583 | aurel32 | tcg_gen_ext32s_i64(cpu_ir[rc], tmp); |
| 843 | dfaa8583 | aurel32 | tcg_temp_free(tmp); |
| 844 | 30c7183b | aurel32 | } else {
|
| 845 | 30c7183b | aurel32 | if (islit)
|
| 846 | 30c7183b | aurel32 | tcg_gen_movi_i64(cpu_ir[rc], -lit); |
| 847 | dfaa8583 | aurel32 | else {
|
| 848 | 30c7183b | aurel32 | tcg_gen_neg_i64(cpu_ir[rc], cpu_ir[rb]); |
| 849 | 30c7183b | aurel32 | tcg_gen_ext32s_i64(cpu_ir[rc], cpu_ir[rc]); |
| 850 | dfaa8583 | aurel32 | } |
| 851 | 30c7183b | aurel32 | } |
| 852 | 30c7183b | aurel32 | } |
| 853 | 4c9649a9 | j_mayer | break;
|
| 854 | 4c9649a9 | j_mayer | case 0x0F: |
| 855 | 4c9649a9 | j_mayer | /* CMPBGE */
|
| 856 | a7812ae4 | pbrook | gen_cmpbge(ra, rb, rc, islit, lit); |
| 857 | 4c9649a9 | j_mayer | break;
|
| 858 | 4c9649a9 | j_mayer | case 0x12: |
| 859 | 4c9649a9 | j_mayer | /* S8ADDL */
|
| 860 | 30c7183b | aurel32 | if (likely(rc != 31)) { |
| 861 | 30c7183b | aurel32 | if (ra != 31) { |
| 862 | a7812ae4 | pbrook | TCGv tmp = tcg_temp_new(); |
| 863 | dfaa8583 | aurel32 | tcg_gen_shli_i64(tmp, cpu_ir[ra], 3);
|
| 864 | dfaa8583 | aurel32 | if (islit)
|
| 865 | dfaa8583 | aurel32 | tcg_gen_addi_i64(tmp, tmp, lit); |
| 866 | dfaa8583 | aurel32 | else
|
| 867 | dfaa8583 | aurel32 | tcg_gen_add_i64(tmp, tmp, cpu_ir[rb]); |
| 868 | dfaa8583 | aurel32 | tcg_gen_ext32s_i64(cpu_ir[rc], tmp); |
| 869 | dfaa8583 | aurel32 | tcg_temp_free(tmp); |
| 870 | 30c7183b | aurel32 | } else {
|
| 871 | 30c7183b | aurel32 | if (islit)
|
| 872 | 30c7183b | aurel32 | tcg_gen_movi_i64(cpu_ir[rc], lit); |
| 873 | 30c7183b | aurel32 | else
|
| 874 | dfaa8583 | aurel32 | tcg_gen_ext32s_i64(cpu_ir[rc], cpu_ir[rb]); |
| 875 | 30c7183b | aurel32 | } |
| 876 | 30c7183b | aurel32 | } |
| 877 | 4c9649a9 | j_mayer | break;
|
| 878 | 4c9649a9 | j_mayer | case 0x1B: |
| 879 | 4c9649a9 | j_mayer | /* S8SUBL */
|
| 880 | 30c7183b | aurel32 | if (likely(rc != 31)) { |
| 881 | 30c7183b | aurel32 | if (ra != 31) { |
| 882 | a7812ae4 | pbrook | TCGv tmp = tcg_temp_new(); |
| 883 | dfaa8583 | aurel32 | tcg_gen_shli_i64(tmp, cpu_ir[ra], 3);
|
| 884 | dfaa8583 | aurel32 | if (islit)
|
| 885 | dfaa8583 | aurel32 | tcg_gen_subi_i64(tmp, tmp, lit); |
| 886 | dfaa8583 | aurel32 | else
|
| 887 | dfaa8583 | aurel32 | tcg_gen_sub_i64(tmp, tmp, cpu_ir[rb]); |
| 888 | dfaa8583 | aurel32 | tcg_gen_ext32s_i64(cpu_ir[rc], tmp); |
| 889 | dfaa8583 | aurel32 | tcg_temp_free(tmp); |
| 890 | 30c7183b | aurel32 | } else {
|
| 891 | 30c7183b | aurel32 | if (islit)
|
| 892 | 30c7183b | aurel32 | tcg_gen_movi_i64(cpu_ir[rc], -lit); |
| 893 | dfaa8583 | aurel32 | else
|
| 894 | 30c7183b | aurel32 | tcg_gen_neg_i64(cpu_ir[rc], cpu_ir[rb]); |
| 895 | 30c7183b | aurel32 | tcg_gen_ext32s_i64(cpu_ir[rc], cpu_ir[rc]); |
| 896 | dfaa8583 | aurel32 | } |
| 897 | 30c7183b | aurel32 | } |
| 898 | 30c7183b | aurel32 | } |
| 899 | 4c9649a9 | j_mayer | break;
|
| 900 | 4c9649a9 | j_mayer | case 0x1D: |
| 901 | 4c9649a9 | j_mayer | /* CMPULT */
|
| 902 | 01ff9cc8 | aurel32 | gen_cmp(TCG_COND_LTU, ra, rb, rc, islit, lit); |
| 903 | 4c9649a9 | j_mayer | break;
|
| 904 | 4c9649a9 | j_mayer | case 0x20: |
| 905 | 4c9649a9 | j_mayer | /* ADDQ */
|
| 906 | 30c7183b | aurel32 | if (likely(rc != 31)) { |
| 907 | 30c7183b | aurel32 | if (ra != 31) { |
| 908 | 30c7183b | aurel32 | if (islit)
|
| 909 | 30c7183b | aurel32 | tcg_gen_addi_i64(cpu_ir[rc], cpu_ir[ra], lit); |
| 910 | 30c7183b | aurel32 | else
|
| 911 | dfaa8583 | aurel32 | tcg_gen_add_i64(cpu_ir[rc], cpu_ir[ra], cpu_ir[rb]); |
| 912 | 30c7183b | aurel32 | } else {
|
| 913 | 30c7183b | aurel32 | if (islit)
|
| 914 | 30c7183b | aurel32 | tcg_gen_movi_i64(cpu_ir[rc], lit); |
| 915 | 30c7183b | aurel32 | else
|
| 916 | dfaa8583 | aurel32 | tcg_gen_mov_i64(cpu_ir[rc], cpu_ir[rb]); |
| 917 | 30c7183b | aurel32 | } |
| 918 | 30c7183b | aurel32 | } |
| 919 | 4c9649a9 | j_mayer | break;
|
| 920 | 4c9649a9 | j_mayer | case 0x22: |
| 921 | 4c9649a9 | j_mayer | /* S4ADDQ */
|
| 922 | 30c7183b | aurel32 | if (likely(rc != 31)) { |
| 923 | 30c7183b | aurel32 | if (ra != 31) { |
| 924 | a7812ae4 | pbrook | TCGv tmp = tcg_temp_new(); |
| 925 | dfaa8583 | aurel32 | tcg_gen_shli_i64(tmp, cpu_ir[ra], 2);
|
| 926 | dfaa8583 | aurel32 | if (islit)
|
| 927 | dfaa8583 | aurel32 | tcg_gen_addi_i64(cpu_ir[rc], tmp, lit); |
| 928 | dfaa8583 | aurel32 | else
|
| 929 | dfaa8583 | aurel32 | tcg_gen_add_i64(cpu_ir[rc], tmp, cpu_ir[rb]); |
| 930 | dfaa8583 | aurel32 | tcg_temp_free(tmp); |
| 931 | 30c7183b | aurel32 | } else {
|
| 932 | 30c7183b | aurel32 | if (islit)
|
| 933 | 30c7183b | aurel32 | tcg_gen_movi_i64(cpu_ir[rc], lit); |
| 934 | 30c7183b | aurel32 | else
|
| 935 | dfaa8583 | aurel32 | tcg_gen_mov_i64(cpu_ir[rc], cpu_ir[rb]); |
| 936 | 30c7183b | aurel32 | } |
| 937 | 30c7183b | aurel32 | } |
| 938 | 4c9649a9 | j_mayer | break;
|
| 939 | 4c9649a9 | j_mayer | case 0x29: |
| 940 | 4c9649a9 | j_mayer | /* SUBQ */
|
| 941 | 30c7183b | aurel32 | if (likely(rc != 31)) { |
| 942 | 30c7183b | aurel32 | if (ra != 31) { |
| 943 | 30c7183b | aurel32 | if (islit)
|
| 944 | 30c7183b | aurel32 | tcg_gen_subi_i64(cpu_ir[rc], cpu_ir[ra], lit); |
| 945 | 30c7183b | aurel32 | else
|
| 946 | dfaa8583 | aurel32 | tcg_gen_sub_i64(cpu_ir[rc], cpu_ir[ra], cpu_ir[rb]); |
| 947 | 30c7183b | aurel32 | } else {
|
| 948 | 30c7183b | aurel32 | if (islit)
|
| 949 | 30c7183b | aurel32 | tcg_gen_movi_i64(cpu_ir[rc], -lit); |
| 950 | 30c7183b | aurel32 | else
|
| 951 | dfaa8583 | aurel32 | tcg_gen_neg_i64(cpu_ir[rc], cpu_ir[rb]); |
| 952 | 30c7183b | aurel32 | } |
| 953 | 30c7183b | aurel32 | } |
| 954 | 4c9649a9 | j_mayer | break;
|
| 955 | 4c9649a9 | j_mayer | case 0x2B: |
| 956 | 4c9649a9 | j_mayer | /* S4SUBQ */
|
| 957 | 30c7183b | aurel32 | if (likely(rc != 31)) { |
| 958 | 30c7183b | aurel32 | if (ra != 31) { |
| 959 | a7812ae4 | pbrook | TCGv tmp = tcg_temp_new(); |
| 960 | dfaa8583 | aurel32 | tcg_gen_shli_i64(tmp, cpu_ir[ra], 2);
|
| 961 | dfaa8583 | aurel32 | if (islit)
|
| 962 | dfaa8583 | aurel32 | tcg_gen_subi_i64(cpu_ir[rc], tmp, lit); |
| 963 | dfaa8583 | aurel32 | else
|
| 964 | dfaa8583 | aurel32 | tcg_gen_sub_i64(cpu_ir[rc], tmp, cpu_ir[rb]); |
| 965 | dfaa8583 | aurel32 | tcg_temp_free(tmp); |
| 966 | 30c7183b | aurel32 | } else {
|
| 967 | 30c7183b | aurel32 | if (islit)
|
| 968 | 30c7183b | aurel32 | tcg_gen_movi_i64(cpu_ir[rc], -lit); |
| 969 | 30c7183b | aurel32 | else
|
| 970 | dfaa8583 | aurel32 | tcg_gen_neg_i64(cpu_ir[rc], cpu_ir[rb]); |
| 971 | 30c7183b | aurel32 | } |
| 972 | 30c7183b | aurel32 | } |
| 973 | 4c9649a9 | j_mayer | break;
|
| 974 | 4c9649a9 | j_mayer | case 0x2D: |
| 975 | 4c9649a9 | j_mayer | /* CMPEQ */
|
| 976 | 01ff9cc8 | aurel32 | gen_cmp(TCG_COND_EQ, ra, rb, rc, islit, lit); |
| 977 | 4c9649a9 | j_mayer | break;
|
| 978 | 4c9649a9 | j_mayer | case 0x32: |
| 979 | 4c9649a9 | j_mayer | /* S8ADDQ */
|
| 980 | 30c7183b | aurel32 | if (likely(rc != 31)) { |
| 981 | 30c7183b | aurel32 | if (ra != 31) { |
| 982 | a7812ae4 | pbrook | TCGv tmp = tcg_temp_new(); |
| 983 | dfaa8583 | aurel32 | tcg_gen_shli_i64(tmp, cpu_ir[ra], 3);
|
| 984 | dfaa8583 | aurel32 | if (islit)
|
| 985 | dfaa8583 | aurel32 | tcg_gen_addi_i64(cpu_ir[rc], tmp, lit); |
| 986 | dfaa8583 | aurel32 | else
|
| 987 | dfaa8583 | aurel32 | tcg_gen_add_i64(cpu_ir[rc], tmp, cpu_ir[rb]); |
| 988 | dfaa8583 | aurel32 | tcg_temp_free(tmp); |
| 989 | 30c7183b | aurel32 | } else {
|
| 990 | 30c7183b | aurel32 | if (islit)
|
| 991 | 30c7183b | aurel32 | tcg_gen_movi_i64(cpu_ir[rc], lit); |
| 992 | 30c7183b | aurel32 | else
|
| 993 | dfaa8583 | aurel32 | tcg_gen_mov_i64(cpu_ir[rc], cpu_ir[rb]); |
| 994 | 30c7183b | aurel32 | } |
| 995 | 30c7183b | aurel32 | } |
| 996 | 4c9649a9 | j_mayer | break;
|
| 997 | 4c9649a9 | j_mayer | case 0x3B: |
| 998 | 4c9649a9 | j_mayer | /* S8SUBQ */
|
| 999 | 30c7183b | aurel32 | if (likely(rc != 31)) { |
| 1000 | 30c7183b | aurel32 | if (ra != 31) { |
| 1001 | a7812ae4 | pbrook | TCGv tmp = tcg_temp_new(); |
| 1002 | dfaa8583 | aurel32 | tcg_gen_shli_i64(tmp, cpu_ir[ra], 3);
|
| 1003 | dfaa8583 | aurel32 | if (islit)
|
| 1004 | dfaa8583 | aurel32 | tcg_gen_subi_i64(cpu_ir[rc], tmp, lit); |
| 1005 | dfaa8583 | aurel32 | else
|
| 1006 | dfaa8583 | aurel32 | tcg_gen_sub_i64(cpu_ir[rc], tmp, cpu_ir[rb]); |
| 1007 | dfaa8583 | aurel32 | tcg_temp_free(tmp); |
| 1008 | 30c7183b | aurel32 | } else {
|
| 1009 | 30c7183b | aurel32 | if (islit)
|
| 1010 | 30c7183b | aurel32 | tcg_gen_movi_i64(cpu_ir[rc], -lit); |
| 1011 | 30c7183b | aurel32 | else
|
| 1012 | dfaa8583 | aurel32 | tcg_gen_neg_i64(cpu_ir[rc], cpu_ir[rb]); |
| 1013 | 30c7183b | aurel32 | } |
| 1014 | 30c7183b | aurel32 | } |
| 1015 | 4c9649a9 | j_mayer | break;
|
| 1016 | 4c9649a9 | j_mayer | case 0x3D: |
| 1017 | 4c9649a9 | j_mayer | /* CMPULE */
|
| 1018 | 01ff9cc8 | aurel32 | gen_cmp(TCG_COND_LEU, ra, rb, rc, islit, lit); |
| 1019 | 4c9649a9 | j_mayer | break;
|
| 1020 | 4c9649a9 | j_mayer | case 0x40: |
| 1021 | 4c9649a9 | j_mayer | /* ADDL/V */
|
| 1022 | a7812ae4 | pbrook | gen_addlv(ra, rb, rc, islit, lit); |
| 1023 | 4c9649a9 | j_mayer | break;
|
| 1024 | 4c9649a9 | j_mayer | case 0x49: |
| 1025 | 4c9649a9 | j_mayer | /* SUBL/V */
|
| 1026 | a7812ae4 | pbrook | gen_sublv(ra, rb, rc, islit, lit); |
| 1027 | 4c9649a9 | j_mayer | break;
|
| 1028 | 4c9649a9 | j_mayer | case 0x4D: |
| 1029 | 4c9649a9 | j_mayer | /* CMPLT */
|
| 1030 | 01ff9cc8 | aurel32 | gen_cmp(TCG_COND_LT, ra, rb, rc, islit, lit); |
| 1031 | 4c9649a9 | j_mayer | break;
|
| 1032 | 4c9649a9 | j_mayer | case 0x60: |
| 1033 | 4c9649a9 | j_mayer | /* ADDQ/V */
|
| 1034 | a7812ae4 | pbrook | gen_addqv(ra, rb, rc, islit, lit); |
| 1035 | 4c9649a9 | j_mayer | break;
|
| 1036 | 4c9649a9 | j_mayer | case 0x69: |
| 1037 | 4c9649a9 | j_mayer | /* SUBQ/V */
|
| 1038 | a7812ae4 | pbrook | gen_subqv(ra, rb, rc, islit, lit); |
| 1039 | 4c9649a9 | j_mayer | break;
|
| 1040 | 4c9649a9 | j_mayer | case 0x6D: |
| 1041 | 4c9649a9 | j_mayer | /* CMPLE */
|
| 1042 | 01ff9cc8 | aurel32 | gen_cmp(TCG_COND_LE, ra, rb, rc, islit, lit); |
| 1043 | 4c9649a9 | j_mayer | break;
|
| 1044 | 4c9649a9 | j_mayer | default:
|
| 1045 | 4c9649a9 | j_mayer | goto invalid_opc;
|
| 1046 | 4c9649a9 | j_mayer | } |
| 1047 | 4c9649a9 | j_mayer | break;
|
| 1048 | 4c9649a9 | j_mayer | case 0x11: |
| 1049 | 4c9649a9 | j_mayer | switch (fn7) {
|
| 1050 | 4c9649a9 | j_mayer | case 0x00: |
| 1051 | 4c9649a9 | j_mayer | /* AND */
|
| 1052 | 30c7183b | aurel32 | if (likely(rc != 31)) { |
| 1053 | dfaa8583 | aurel32 | if (ra == 31) |
| 1054 | 30c7183b | aurel32 | tcg_gen_movi_i64(cpu_ir[rc], 0);
|
| 1055 | 30c7183b | aurel32 | else if (islit) |
| 1056 | 30c7183b | aurel32 | tcg_gen_andi_i64(cpu_ir[rc], cpu_ir[ra], lit); |
| 1057 | 30c7183b | aurel32 | else
|
| 1058 | 30c7183b | aurel32 | tcg_gen_and_i64(cpu_ir[rc], cpu_ir[ra], cpu_ir[rb]); |
| 1059 | 30c7183b | aurel32 | } |
| 1060 | 4c9649a9 | j_mayer | break;
|
| 1061 | 4c9649a9 | j_mayer | case 0x08: |
| 1062 | 4c9649a9 | j_mayer | /* BIC */
|
| 1063 | 30c7183b | aurel32 | if (likely(rc != 31)) { |
| 1064 | 30c7183b | aurel32 | if (ra != 31) { |
| 1065 | 30c7183b | aurel32 | if (islit)
|
| 1066 | 30c7183b | aurel32 | tcg_gen_andi_i64(cpu_ir[rc], cpu_ir[ra], ~lit); |
| 1067 | 1b581c44 | aurel32 | else
|
| 1068 | 1b581c44 | aurel32 | tcg_gen_andc_i64(cpu_ir[rc], cpu_ir[ra], cpu_ir[rb]); |
| 1069 | 30c7183b | aurel32 | } else
|
| 1070 | 30c7183b | aurel32 | tcg_gen_movi_i64(cpu_ir[rc], 0);
|
| 1071 | 30c7183b | aurel32 | } |
| 1072 | 4c9649a9 | j_mayer | break;
|
| 1073 | 4c9649a9 | j_mayer | case 0x14: |
| 1074 | 4c9649a9 | j_mayer | /* CMOVLBS */
|
| 1075 | fe2b269a | aurel32 | gen_cmov(TCG_COND_EQ, ra, rb, rc, islit, lit, 1);
|
| 1076 | 4c9649a9 | j_mayer | break;
|
| 1077 | 4c9649a9 | j_mayer | case 0x16: |
| 1078 | 4c9649a9 | j_mayer | /* CMOVLBC */
|
| 1079 | fe2b269a | aurel32 | gen_cmov(TCG_COND_NE, ra, rb, rc, islit, lit, 1);
|
| 1080 | 4c9649a9 | j_mayer | break;
|
| 1081 | 4c9649a9 | j_mayer | case 0x20: |
| 1082 | 4c9649a9 | j_mayer | /* BIS */
|
| 1083 | 30c7183b | aurel32 | if (likely(rc != 31)) { |
| 1084 | 30c7183b | aurel32 | if (ra != 31) { |
| 1085 | 30c7183b | aurel32 | if (islit)
|
| 1086 | 30c7183b | aurel32 | tcg_gen_ori_i64(cpu_ir[rc], cpu_ir[ra], lit); |
| 1087 | 8bb6e981 | aurel32 | else
|
| 1088 | 30c7183b | aurel32 | tcg_gen_or_i64(cpu_ir[rc], cpu_ir[ra], cpu_ir[rb]); |
| 1089 | 4c9649a9 | j_mayer | } else {
|
| 1090 | 30c7183b | aurel32 | if (islit)
|
| 1091 | 30c7183b | aurel32 | tcg_gen_movi_i64(cpu_ir[rc], lit); |
| 1092 | 30c7183b | aurel32 | else
|
| 1093 | dfaa8583 | aurel32 | tcg_gen_mov_i64(cpu_ir[rc], cpu_ir[rb]); |
| 1094 | 4c9649a9 | j_mayer | } |
| 1095 | 4c9649a9 | j_mayer | } |
| 1096 | 4c9649a9 | j_mayer | break;
|
| 1097 | 4c9649a9 | j_mayer | case 0x24: |
| 1098 | 4c9649a9 | j_mayer | /* CMOVEQ */
|
| 1099 | fe2b269a | aurel32 | gen_cmov(TCG_COND_NE, ra, rb, rc, islit, lit, 0);
|
| 1100 | 4c9649a9 | j_mayer | break;
|
| 1101 | 4c9649a9 | j_mayer | case 0x26: |
| 1102 | 4c9649a9 | j_mayer | /* CMOVNE */
|
| 1103 | fe2b269a | aurel32 | gen_cmov(TCG_COND_EQ, ra, rb, rc, islit, lit, 0);
|
| 1104 | 4c9649a9 | j_mayer | break;
|
| 1105 | 4c9649a9 | j_mayer | case 0x28: |
| 1106 | 4c9649a9 | j_mayer | /* ORNOT */
|
| 1107 | 30c7183b | aurel32 | if (likely(rc != 31)) { |
| 1108 | dfaa8583 | aurel32 | if (ra != 31) { |
| 1109 | 30c7183b | aurel32 | if (islit)
|
| 1110 | 30c7183b | aurel32 | tcg_gen_ori_i64(cpu_ir[rc], cpu_ir[ra], ~lit); |
| 1111 | 1b581c44 | aurel32 | else
|
| 1112 | 1b581c44 | aurel32 | tcg_gen_orc_i64(cpu_ir[rc], cpu_ir[ra], cpu_ir[rb]); |
| 1113 | 30c7183b | aurel32 | } else {
|
| 1114 | 30c7183b | aurel32 | if (islit)
|
| 1115 | 30c7183b | aurel32 | tcg_gen_movi_i64(cpu_ir[rc], ~lit); |
| 1116 | 30c7183b | aurel32 | else
|
| 1117 | 30c7183b | aurel32 | tcg_gen_not_i64(cpu_ir[rc], cpu_ir[rb]); |
| 1118 | 30c7183b | aurel32 | } |
| 1119 | 30c7183b | aurel32 | } |
| 1120 | 4c9649a9 | j_mayer | break;
|
| 1121 | 4c9649a9 | j_mayer | case 0x40: |
| 1122 | 4c9649a9 | j_mayer | /* XOR */
|
| 1123 | 30c7183b | aurel32 | if (likely(rc != 31)) { |
| 1124 | 30c7183b | aurel32 | if (ra != 31) { |
| 1125 | 30c7183b | aurel32 | if (islit)
|
| 1126 | 30c7183b | aurel32 | tcg_gen_xori_i64(cpu_ir[rc], cpu_ir[ra], lit); |
| 1127 | 30c7183b | aurel32 | else
|
| 1128 | dfaa8583 | aurel32 | tcg_gen_xor_i64(cpu_ir[rc], cpu_ir[ra], cpu_ir[rb]); |
| 1129 | 30c7183b | aurel32 | } else {
|
| 1130 | 30c7183b | aurel32 | if (islit)
|
| 1131 | 30c7183b | aurel32 | tcg_gen_movi_i64(cpu_ir[rc], lit); |
| 1132 | 30c7183b | aurel32 | else
|
| 1133 | dfaa8583 | aurel32 | tcg_gen_mov_i64(cpu_ir[rc], cpu_ir[rb]); |
| 1134 | 30c7183b | aurel32 | } |
| 1135 | 30c7183b | aurel32 | } |
| 1136 | 4c9649a9 | j_mayer | break;
|
| 1137 | 4c9649a9 | j_mayer | case 0x44: |
| 1138 | 4c9649a9 | j_mayer | /* CMOVLT */
|
| 1139 | fe2b269a | aurel32 | gen_cmov(TCG_COND_GE, ra, rb, rc, islit, lit, 0);
|
| 1140 | 4c9649a9 | j_mayer | break;
|
| 1141 | 4c9649a9 | j_mayer | case 0x46: |
| 1142 | 4c9649a9 | j_mayer | /* CMOVGE */
|
| 1143 | fe2b269a | aurel32 | gen_cmov(TCG_COND_LT, ra, rb, rc, islit, lit, 0);
|
| 1144 | 4c9649a9 | j_mayer | break;
|
| 1145 | 4c9649a9 | j_mayer | case 0x48: |
| 1146 | 4c9649a9 | j_mayer | /* EQV */
|
| 1147 | 30c7183b | aurel32 | if (likely(rc != 31)) { |
| 1148 | 30c7183b | aurel32 | if (ra != 31) { |
| 1149 | 30c7183b | aurel32 | if (islit)
|
| 1150 | 30c7183b | aurel32 | tcg_gen_xori_i64(cpu_ir[rc], cpu_ir[ra], ~lit); |
| 1151 | 1b581c44 | aurel32 | else
|
| 1152 | 1b581c44 | aurel32 | tcg_gen_eqv_i64(cpu_ir[rc], cpu_ir[ra], cpu_ir[rb]); |
| 1153 | 30c7183b | aurel32 | } else {
|
| 1154 | 30c7183b | aurel32 | if (islit)
|
| 1155 | 30c7183b | aurel32 | tcg_gen_movi_i64(cpu_ir[rc], ~lit); |
| 1156 | 30c7183b | aurel32 | else
|
| 1157 | dfaa8583 | aurel32 | tcg_gen_not_i64(cpu_ir[rc], cpu_ir[rb]); |
| 1158 | 30c7183b | aurel32 | } |
| 1159 | 30c7183b | aurel32 | } |
| 1160 | 4c9649a9 | j_mayer | break;
|
| 1161 | 4c9649a9 | j_mayer | case 0x61: |
| 1162 | 4c9649a9 | j_mayer | /* AMASK */
|
| 1163 | ae8ecd42 | aurel32 | if (likely(rc != 31)) { |
| 1164 | ae8ecd42 | aurel32 | if (islit)
|
| 1165 | ae8ecd42 | aurel32 | tcg_gen_movi_i64(cpu_ir[rc], helper_amask(lit)); |
| 1166 | ae8ecd42 | aurel32 | else
|
| 1167 | a7812ae4 | pbrook | gen_helper_amask(cpu_ir[rc], cpu_ir[rb]); |
| 1168 | ae8ecd42 | aurel32 | } |
| 1169 | 4c9649a9 | j_mayer | break;
|
| 1170 | 4c9649a9 | j_mayer | case 0x64: |
| 1171 | 4c9649a9 | j_mayer | /* CMOVLE */
|
| 1172 | fe2b269a | aurel32 | gen_cmov(TCG_COND_GT, ra, rb, rc, islit, lit, 0);
|
| 1173 | 4c9649a9 | j_mayer | break;
|
| 1174 | 4c9649a9 | j_mayer | case 0x66: |
| 1175 | 4c9649a9 | j_mayer | /* CMOVGT */
|
| 1176 | fe2b269a | aurel32 | gen_cmov(TCG_COND_LE, ra, rb, rc, islit, lit, 0);
|
| 1177 | 4c9649a9 | j_mayer | break;
|
| 1178 | 4c9649a9 | j_mayer | case 0x6C: |
| 1179 | 4c9649a9 | j_mayer | /* IMPLVER */
|
| 1180 | 3761035f | aurel32 | if (rc != 31) |
| 1181 | a7812ae4 | pbrook | gen_helper_load_implver(cpu_ir[rc]); |
| 1182 | 4c9649a9 | j_mayer | break;
|
| 1183 | 4c9649a9 | j_mayer | default:
|
| 1184 | 4c9649a9 | j_mayer | goto invalid_opc;
|
| 1185 | 4c9649a9 | j_mayer | } |
| 1186 | 4c9649a9 | j_mayer | break;
|
| 1187 | 4c9649a9 | j_mayer | case 0x12: |
| 1188 | 4c9649a9 | j_mayer | switch (fn7) {
|
| 1189 | 4c9649a9 | j_mayer | case 0x02: |
| 1190 | 4c9649a9 | j_mayer | /* MSKBL */
|
| 1191 | a7812ae4 | pbrook | gen_mskbl(ra, rb, rc, islit, lit); |
| 1192 | 4c9649a9 | j_mayer | break;
|
| 1193 | 4c9649a9 | j_mayer | case 0x06: |
| 1194 | 4c9649a9 | j_mayer | /* EXTBL */
|
| 1195 | b3249f63 | aurel32 | gen_ext_l(&tcg_gen_ext8u_i64, ra, rb, rc, islit, lit); |
| 1196 | 4c9649a9 | j_mayer | break;
|
| 1197 | 4c9649a9 | j_mayer | case 0x0B: |
| 1198 | 4c9649a9 | j_mayer | /* INSBL */
|
| 1199 | a7812ae4 | pbrook | gen_insbl(ra, rb, rc, islit, lit); |
| 1200 | 4c9649a9 | j_mayer | break;
|
| 1201 | 4c9649a9 | j_mayer | case 0x12: |
| 1202 | 4c9649a9 | j_mayer | /* MSKWL */
|
| 1203 | a7812ae4 | pbrook | gen_mskwl(ra, rb, rc, islit, lit); |
| 1204 | 4c9649a9 | j_mayer | break;
|
| 1205 | 4c9649a9 | j_mayer | case 0x16: |
| 1206 | 4c9649a9 | j_mayer | /* EXTWL */
|
| 1207 | b3249f63 | aurel32 | gen_ext_l(&tcg_gen_ext16u_i64, ra, rb, rc, islit, lit); |
| 1208 | 4c9649a9 | j_mayer | break;
|
| 1209 | 4c9649a9 | j_mayer | case 0x1B: |
| 1210 | 4c9649a9 | j_mayer | /* INSWL */
|
| 1211 | a7812ae4 | pbrook | gen_inswl(ra, rb, rc, islit, lit); |
| 1212 | 4c9649a9 | j_mayer | break;
|
| 1213 | 4c9649a9 | j_mayer | case 0x22: |
| 1214 | 4c9649a9 | j_mayer | /* MSKLL */
|
| 1215 | a7812ae4 | pbrook | gen_mskll(ra, rb, rc, islit, lit); |
| 1216 | 4c9649a9 | j_mayer | break;
|
| 1217 | 4c9649a9 | j_mayer | case 0x26: |
| 1218 | 4c9649a9 | j_mayer | /* EXTLL */
|
| 1219 | b3249f63 | aurel32 | gen_ext_l(&tcg_gen_ext32u_i64, ra, rb, rc, islit, lit); |
| 1220 | 4c9649a9 | j_mayer | break;
|
| 1221 | 4c9649a9 | j_mayer | case 0x2B: |
| 1222 | 4c9649a9 | j_mayer | /* INSLL */
|
| 1223 | a7812ae4 | pbrook | gen_insll(ra, rb, rc, islit, lit); |
| 1224 | 4c9649a9 | j_mayer | break;
|
| 1225 | 4c9649a9 | j_mayer | case 0x30: |
| 1226 | 4c9649a9 | j_mayer | /* ZAP */
|
| 1227 | a7812ae4 | pbrook | gen_zap(ra, rb, rc, islit, lit); |
| 1228 | 4c9649a9 | j_mayer | break;
|
| 1229 | 4c9649a9 | j_mayer | case 0x31: |
| 1230 | 4c9649a9 | j_mayer | /* ZAPNOT */
|
| 1231 | a7812ae4 | pbrook | gen_zapnot(ra, rb, rc, islit, lit); |
| 1232 | 4c9649a9 | j_mayer | break;
|
| 1233 | 4c9649a9 | j_mayer | case 0x32: |
| 1234 | 4c9649a9 | j_mayer | /* MSKQL */
|
| 1235 | a7812ae4 | pbrook | gen_mskql(ra, rb, rc, islit, lit); |
| 1236 | 4c9649a9 | j_mayer | break;
|
| 1237 | 4c9649a9 | j_mayer | case 0x34: |
| 1238 | 4c9649a9 | j_mayer | /* SRL */
|
| 1239 | 30c7183b | aurel32 | if (likely(rc != 31)) { |
| 1240 | 30c7183b | aurel32 | if (ra != 31) { |
| 1241 | 30c7183b | aurel32 | if (islit)
|
| 1242 | 30c7183b | aurel32 | tcg_gen_shri_i64(cpu_ir[rc], cpu_ir[ra], lit & 0x3f);
|
| 1243 | dfaa8583 | aurel32 | else {
|
| 1244 | a7812ae4 | pbrook | TCGv shift = tcg_temp_new(); |
| 1245 | 30c7183b | aurel32 | tcg_gen_andi_i64(shift, cpu_ir[rb], 0x3f);
|
| 1246 | 30c7183b | aurel32 | tcg_gen_shr_i64(cpu_ir[rc], cpu_ir[ra], shift); |
| 1247 | 30c7183b | aurel32 | tcg_temp_free(shift); |
| 1248 | dfaa8583 | aurel32 | } |
| 1249 | 30c7183b | aurel32 | } else
|
| 1250 | 30c7183b | aurel32 | tcg_gen_movi_i64(cpu_ir[rc], 0);
|
| 1251 | 30c7183b | aurel32 | } |
| 1252 | 4c9649a9 | j_mayer | break;
|
| 1253 | 4c9649a9 | j_mayer | case 0x36: |
| 1254 | 4c9649a9 | j_mayer | /* EXTQL */
|
| 1255 | b3249f63 | aurel32 | gen_ext_l(NULL, ra, rb, rc, islit, lit);
|
| 1256 | 4c9649a9 | j_mayer | break;
|
| 1257 | 4c9649a9 | j_mayer | case 0x39: |
| 1258 | 4c9649a9 | j_mayer | /* SLL */
|
| 1259 | 30c7183b | aurel32 | if (likely(rc != 31)) { |
| 1260 | 30c7183b | aurel32 | if (ra != 31) { |
| 1261 | 30c7183b | aurel32 | if (islit)
|
| 1262 | 30c7183b | aurel32 | tcg_gen_shli_i64(cpu_ir[rc], cpu_ir[ra], lit & 0x3f);
|
| 1263 | dfaa8583 | aurel32 | else {
|
| 1264 | a7812ae4 | pbrook | TCGv shift = tcg_temp_new(); |
| 1265 | 30c7183b | aurel32 | tcg_gen_andi_i64(shift, cpu_ir[rb], 0x3f);
|
| 1266 | 30c7183b | aurel32 | tcg_gen_shl_i64(cpu_ir[rc], cpu_ir[ra], shift); |
| 1267 | 30c7183b | aurel32 | tcg_temp_free(shift); |
| 1268 | dfaa8583 | aurel32 | } |
| 1269 | 30c7183b | aurel32 | } else
|
| 1270 | 30c7183b | aurel32 | tcg_gen_movi_i64(cpu_ir[rc], 0);
|
| 1271 | 30c7183b | aurel32 | } |
| 1272 | 4c9649a9 | j_mayer | break;
|
| 1273 | 4c9649a9 | j_mayer | case 0x3B: |
| 1274 | 4c9649a9 | j_mayer | /* INSQL */
|
| 1275 | a7812ae4 | pbrook | gen_insql(ra, rb, rc, islit, lit); |
| 1276 | 4c9649a9 | j_mayer | break;
|
| 1277 | 4c9649a9 | j_mayer | case 0x3C: |
| 1278 | 4c9649a9 | j_mayer | /* SRA */
|
| 1279 | 30c7183b | aurel32 | if (likely(rc != 31)) { |
| 1280 | 30c7183b | aurel32 | if (ra != 31) { |
| 1281 | 30c7183b | aurel32 | if (islit)
|
| 1282 | 30c7183b | aurel32 | tcg_gen_sari_i64(cpu_ir[rc], cpu_ir[ra], lit & 0x3f);
|
| 1283 | dfaa8583 | aurel32 | else {
|
| 1284 | a7812ae4 | pbrook | TCGv shift = tcg_temp_new(); |
| 1285 | 30c7183b | aurel32 | tcg_gen_andi_i64(shift, cpu_ir[rb], 0x3f);
|
| 1286 | 30c7183b | aurel32 | tcg_gen_sar_i64(cpu_ir[rc], cpu_ir[ra], shift); |
| 1287 | 30c7183b | aurel32 | tcg_temp_free(shift); |
| 1288 | dfaa8583 | aurel32 | } |
| 1289 | 30c7183b | aurel32 | } else
|
| 1290 | 30c7183b | aurel32 | tcg_gen_movi_i64(cpu_ir[rc], 0);
|
| 1291 | 30c7183b | aurel32 | } |
| 1292 | 4c9649a9 | j_mayer | break;
|
| 1293 | 4c9649a9 | j_mayer | case 0x52: |
| 1294 | 4c9649a9 | j_mayer | /* MSKWH */
|
| 1295 | a7812ae4 | pbrook | gen_mskwh(ra, rb, rc, islit, lit); |
| 1296 | 4c9649a9 | j_mayer | break;
|
| 1297 | 4c9649a9 | j_mayer | case 0x57: |
| 1298 | 4c9649a9 | j_mayer | /* INSWH */
|
| 1299 | a7812ae4 | pbrook | gen_inswh(ra, rb, rc, islit, lit); |
| 1300 | 4c9649a9 | j_mayer | break;
|
| 1301 | 4c9649a9 | j_mayer | case 0x5A: |
| 1302 | 4c9649a9 | j_mayer | /* EXTWH */
|
| 1303 | b3249f63 | aurel32 | gen_ext_h(&tcg_gen_ext16u_i64, ra, rb, rc, islit, lit); |
| 1304 | 4c9649a9 | j_mayer | break;
|
| 1305 | 4c9649a9 | j_mayer | case 0x62: |
| 1306 | 4c9649a9 | j_mayer | /* MSKLH */
|
| 1307 | a7812ae4 | pbrook | gen_msklh(ra, rb, rc, islit, lit); |
| 1308 | 4c9649a9 | j_mayer | break;
|
| 1309 | 4c9649a9 | j_mayer | case 0x67: |
| 1310 | 4c9649a9 | j_mayer | /* INSLH */
|
| 1311 | a7812ae4 | pbrook | gen_inslh(ra, rb, rc, islit, lit); |
| 1312 | 4c9649a9 | j_mayer | break;
|
| 1313 | 4c9649a9 | j_mayer | case 0x6A: |
| 1314 | 4c9649a9 | j_mayer | /* EXTLH */
|
| 1315 | b3249f63 | aurel32 | gen_ext_h(&tcg_gen_ext16u_i64, ra, rb, rc, islit, lit); |
| 1316 | 4c9649a9 | j_mayer | break;
|
| 1317 | 4c9649a9 | j_mayer | case 0x72: |
| 1318 | 4c9649a9 | j_mayer | /* MSKQH */
|
| 1319 | a7812ae4 | pbrook | gen_mskqh(ra, rb, rc, islit, lit); |
| 1320 | 4c9649a9 | j_mayer | break;
|
| 1321 | 4c9649a9 | j_mayer | case 0x77: |
| 1322 | 4c9649a9 | j_mayer | /* INSQH */
|
| 1323 | a7812ae4 | pbrook | gen_insqh(ra, rb, rc, islit, lit); |
| 1324 | 4c9649a9 | j_mayer | break;
|
| 1325 | 4c9649a9 | j_mayer | case 0x7A: |
| 1326 | 4c9649a9 | j_mayer | /* EXTQH */
|
| 1327 | b3249f63 | aurel32 | gen_ext_h(NULL, ra, rb, rc, islit, lit);
|
| 1328 | 4c9649a9 | j_mayer | break;
|
| 1329 | 4c9649a9 | j_mayer | default:
|
| 1330 | 4c9649a9 | j_mayer | goto invalid_opc;
|
| 1331 | 4c9649a9 | j_mayer | } |
| 1332 | 4c9649a9 | j_mayer | break;
|
| 1333 | 4c9649a9 | j_mayer | case 0x13: |
| 1334 | 4c9649a9 | j_mayer | switch (fn7) {
|
| 1335 | 4c9649a9 | j_mayer | case 0x00: |
| 1336 | 4c9649a9 | j_mayer | /* MULL */
|
| 1337 | 30c7183b | aurel32 | if (likely(rc != 31)) { |
| 1338 | dfaa8583 | aurel32 | if (ra == 31) |
| 1339 | 30c7183b | aurel32 | tcg_gen_movi_i64(cpu_ir[rc], 0);
|
| 1340 | 30c7183b | aurel32 | else {
|
| 1341 | 30c7183b | aurel32 | if (islit)
|
| 1342 | 30c7183b | aurel32 | tcg_gen_muli_i64(cpu_ir[rc], cpu_ir[ra], lit); |
| 1343 | 30c7183b | aurel32 | else
|
| 1344 | 30c7183b | aurel32 | tcg_gen_mul_i64(cpu_ir[rc], cpu_ir[ra], cpu_ir[rb]); |
| 1345 | 30c7183b | aurel32 | tcg_gen_ext32s_i64(cpu_ir[rc], cpu_ir[rc]); |
| 1346 | 30c7183b | aurel32 | } |
| 1347 | 30c7183b | aurel32 | } |
| 1348 | 4c9649a9 | j_mayer | break;
|
| 1349 | 4c9649a9 | j_mayer | case 0x20: |
| 1350 | 4c9649a9 | j_mayer | /* MULQ */
|
| 1351 | 30c7183b | aurel32 | if (likely(rc != 31)) { |
| 1352 | dfaa8583 | aurel32 | if (ra == 31) |
| 1353 | 30c7183b | aurel32 | tcg_gen_movi_i64(cpu_ir[rc], 0);
|
| 1354 | 30c7183b | aurel32 | else if (islit) |
| 1355 | 30c7183b | aurel32 | tcg_gen_muli_i64(cpu_ir[rc], cpu_ir[ra], lit); |
| 1356 | 30c7183b | aurel32 | else
|
| 1357 | 30c7183b | aurel32 | tcg_gen_mul_i64(cpu_ir[rc], cpu_ir[ra], cpu_ir[rb]); |
| 1358 | 30c7183b | aurel32 | } |
| 1359 | 4c9649a9 | j_mayer | break;
|
| 1360 | 4c9649a9 | j_mayer | case 0x30: |
| 1361 | 4c9649a9 | j_mayer | /* UMULH */
|
| 1362 | a7812ae4 | pbrook | gen_umulh(ra, rb, rc, islit, lit); |
| 1363 | 4c9649a9 | j_mayer | break;
|
| 1364 | 4c9649a9 | j_mayer | case 0x40: |
| 1365 | 4c9649a9 | j_mayer | /* MULL/V */
|
| 1366 | a7812ae4 | pbrook | gen_mullv(ra, rb, rc, islit, lit); |
| 1367 | 4c9649a9 | j_mayer | break;
|
| 1368 | 4c9649a9 | j_mayer | case 0x60: |
| 1369 | 4c9649a9 | j_mayer | /* MULQ/V */
|
| 1370 | a7812ae4 | pbrook | gen_mulqv(ra, rb, rc, islit, lit); |
| 1371 | 4c9649a9 | j_mayer | break;
|
| 1372 | 4c9649a9 | j_mayer | default:
|
| 1373 | 4c9649a9 | j_mayer | goto invalid_opc;
|
| 1374 | 4c9649a9 | j_mayer | } |
| 1375 | 4c9649a9 | j_mayer | break;
|
| 1376 | 4c9649a9 | j_mayer | case 0x14: |
| 1377 | 4c9649a9 | j_mayer | switch (fpfn) { /* f11 & 0x3F */ |
| 1378 | 4c9649a9 | j_mayer | case 0x04: |
| 1379 | 4c9649a9 | j_mayer | /* ITOFS */
|
| 1380 | 4c9649a9 | j_mayer | if (!(ctx->amask & AMASK_FIX))
|
| 1381 | 4c9649a9 | j_mayer | goto invalid_opc;
|
| 1382 | f18cd223 | aurel32 | if (likely(rc != 31)) { |
| 1383 | f18cd223 | aurel32 | if (ra != 31) { |
| 1384 | a7812ae4 | pbrook | TCGv_i32 tmp = tcg_temp_new_i32(); |
| 1385 | f18cd223 | aurel32 | tcg_gen_trunc_i64_i32(tmp, cpu_ir[ra]); |
| 1386 | a7812ae4 | pbrook | gen_helper_memory_to_s(cpu_fir[rc], tmp); |
| 1387 | a7812ae4 | pbrook | tcg_temp_free_i32(tmp); |
| 1388 | f18cd223 | aurel32 | } else
|
| 1389 | f18cd223 | aurel32 | tcg_gen_movi_i64(cpu_fir[rc], 0);
|
| 1390 | f18cd223 | aurel32 | } |
| 1391 | 4c9649a9 | j_mayer | break;
|
| 1392 | 4c9649a9 | j_mayer | case 0x0A: |
| 1393 | 4c9649a9 | j_mayer | /* SQRTF */
|
| 1394 | 4c9649a9 | j_mayer | if (!(ctx->amask & AMASK_FIX))
|
| 1395 | 4c9649a9 | j_mayer | goto invalid_opc;
|
| 1396 | a7812ae4 | pbrook | gen_fsqrtf(rb, rc); |
| 1397 | 4c9649a9 | j_mayer | break;
|
| 1398 | 4c9649a9 | j_mayer | case 0x0B: |
| 1399 | 4c9649a9 | j_mayer | /* SQRTS */
|
| 1400 | 4c9649a9 | j_mayer | if (!(ctx->amask & AMASK_FIX))
|
| 1401 | 4c9649a9 | j_mayer | goto invalid_opc;
|
| 1402 | a7812ae4 | pbrook | gen_fsqrts(rb, rc); |
| 1403 | 4c9649a9 | j_mayer | break;
|
| 1404 | 4c9649a9 | j_mayer | case 0x14: |
| 1405 | 4c9649a9 | j_mayer | /* ITOFF */
|
| 1406 | 4c9649a9 | j_mayer | if (!(ctx->amask & AMASK_FIX))
|
| 1407 | 4c9649a9 | j_mayer | goto invalid_opc;
|
| 1408 | f18cd223 | aurel32 | if (likely(rc != 31)) { |
| 1409 | f18cd223 | aurel32 | if (ra != 31) { |
| 1410 | a7812ae4 | pbrook | TCGv_i32 tmp = tcg_temp_new_i32(); |
| 1411 | f18cd223 | aurel32 | tcg_gen_trunc_i64_i32(tmp, cpu_ir[ra]); |
| 1412 | a7812ae4 | pbrook | gen_helper_memory_to_f(cpu_fir[rc], tmp); |
| 1413 | a7812ae4 | pbrook | tcg_temp_free_i32(tmp); |
| 1414 | f18cd223 | aurel32 | } else
|
| 1415 | f18cd223 | aurel32 | tcg_gen_movi_i64(cpu_fir[rc], 0);
|
| 1416 | f18cd223 | aurel32 | } |
| 1417 | 4c9649a9 | j_mayer | break;
|
| 1418 | 4c9649a9 | j_mayer | case 0x24: |
| 1419 | 4c9649a9 | j_mayer | /* ITOFT */
|
| 1420 | 4c9649a9 | j_mayer | if (!(ctx->amask & AMASK_FIX))
|
| 1421 | 4c9649a9 | j_mayer | goto invalid_opc;
|
| 1422 | f18cd223 | aurel32 | if (likely(rc != 31)) { |
| 1423 | f18cd223 | aurel32 | if (ra != 31) |
| 1424 | f18cd223 | aurel32 | tcg_gen_mov_i64(cpu_fir[rc], cpu_ir[ra]); |
| 1425 | f18cd223 | aurel32 | else
|
| 1426 | f18cd223 | aurel32 | tcg_gen_movi_i64(cpu_fir[rc], 0);
|
| 1427 | f18cd223 | aurel32 | } |
| 1428 | 4c9649a9 | j_mayer | break;
|
| 1429 | 4c9649a9 | j_mayer | case 0x2A: |
| 1430 | 4c9649a9 | j_mayer | /* SQRTG */
|
| 1431 | 4c9649a9 | j_mayer | if (!(ctx->amask & AMASK_FIX))
|
| 1432 | 4c9649a9 | j_mayer | goto invalid_opc;
|
| 1433 | a7812ae4 | pbrook | gen_fsqrtg(rb, rc); |
| 1434 | 4c9649a9 | j_mayer | break;
|
| 1435 | 4c9649a9 | j_mayer | case 0x02B: |
| 1436 | 4c9649a9 | j_mayer | /* SQRTT */
|
| 1437 | 4c9649a9 | j_mayer | if (!(ctx->amask & AMASK_FIX))
|
| 1438 | 4c9649a9 | j_mayer | goto invalid_opc;
|
| 1439 | a7812ae4 | pbrook | gen_fsqrtt(rb, rc); |
| 1440 | 4c9649a9 | j_mayer | break;
|
| 1441 | 4c9649a9 | j_mayer | default:
|
| 1442 | 4c9649a9 | j_mayer | goto invalid_opc;
|
| 1443 | 4c9649a9 | j_mayer | } |
| 1444 | 4c9649a9 | j_mayer | break;
|
| 1445 | 4c9649a9 | j_mayer | case 0x15: |
| 1446 | 4c9649a9 | j_mayer | /* VAX floating point */
|
| 1447 | 4c9649a9 | j_mayer | /* XXX: rounding mode and trap are ignored (!) */
|
| 1448 | 4c9649a9 | j_mayer | switch (fpfn) { /* f11 & 0x3F */ |
| 1449 | 4c9649a9 | j_mayer | case 0x00: |
| 1450 | 4c9649a9 | j_mayer | /* ADDF */
|
| 1451 | a7812ae4 | pbrook | gen_faddf(ra, rb, rc); |
| 1452 | 4c9649a9 | j_mayer | break;
|
| 1453 | 4c9649a9 | j_mayer | case 0x01: |
| 1454 | 4c9649a9 | j_mayer | /* SUBF */
|
| 1455 | a7812ae4 | pbrook | gen_fsubf(ra, rb, rc); |
| 1456 | 4c9649a9 | j_mayer | break;
|
| 1457 | 4c9649a9 | j_mayer | case 0x02: |
| 1458 | 4c9649a9 | j_mayer | /* MULF */
|
| 1459 | a7812ae4 | pbrook | gen_fmulf(ra, rb, rc); |
| 1460 | 4c9649a9 | j_mayer | break;
|
| 1461 | 4c9649a9 | j_mayer | case 0x03: |
| 1462 | 4c9649a9 | j_mayer | /* DIVF */
|
| 1463 | a7812ae4 | pbrook | gen_fdivf(ra, rb, rc); |
| 1464 | 4c9649a9 | j_mayer | break;
|
| 1465 | 4c9649a9 | j_mayer | case 0x1E: |
| 1466 | 4c9649a9 | j_mayer | /* CVTDG */
|
| 1467 | 4c9649a9 | j_mayer | #if 0 // TODO
|
| 1468 | a7812ae4 | pbrook | gen_fcvtdg(rb, rc);
|
| 1469 | 4c9649a9 | j_mayer | #else
|
| 1470 | 4c9649a9 | j_mayer | goto invalid_opc;
|
| 1471 | 4c9649a9 | j_mayer | #endif
|
| 1472 | 4c9649a9 | j_mayer | break;
|
| 1473 | 4c9649a9 | j_mayer | case 0x20: |
| 1474 | 4c9649a9 | j_mayer | /* ADDG */
|
| 1475 | a7812ae4 | pbrook | gen_faddg(ra, rb, rc); |
| 1476 | 4c9649a9 | j_mayer | break;
|
| 1477 | 4c9649a9 | j_mayer | case 0x21: |
| 1478 | 4c9649a9 | j_mayer | /* SUBG */
|
| 1479 | a7812ae4 | pbrook | gen_fsubg(ra, rb, rc); |
| 1480 | 4c9649a9 | j_mayer | break;
|
| 1481 | 4c9649a9 | j_mayer | case 0x22: |
| 1482 | 4c9649a9 | j_mayer | /* MULG */
|
| 1483 | a7812ae4 | pbrook | gen_fmulg(ra, rb, rc); |
| 1484 | 4c9649a9 | j_mayer | break;
|
| 1485 | 4c9649a9 | j_mayer | case 0x23: |
| 1486 | 4c9649a9 | j_mayer | /* DIVG */
|
| 1487 | a7812ae4 | pbrook | gen_fdivg(ra, rb, rc); |
| 1488 | 4c9649a9 | j_mayer | break;
|
| 1489 | 4c9649a9 | j_mayer | case 0x25: |
| 1490 | 4c9649a9 | j_mayer | /* CMPGEQ */
|
| 1491 | a7812ae4 | pbrook | gen_fcmpgeq(ra, rb, rc); |
| 1492 | 4c9649a9 | j_mayer | break;
|
| 1493 | 4c9649a9 | j_mayer | case 0x26: |
| 1494 | 4c9649a9 | j_mayer | /* CMPGLT */
|
| 1495 | a7812ae4 | pbrook | gen_fcmpglt(ra, rb, rc); |
| 1496 | 4c9649a9 | j_mayer | break;
|
| 1497 | 4c9649a9 | j_mayer | case 0x27: |
| 1498 | 4c9649a9 | j_mayer | /* CMPGLE */
|
| 1499 | a7812ae4 | pbrook | gen_fcmpgle(ra, rb, rc); |
| 1500 | 4c9649a9 | j_mayer | break;
|
| 1501 | 4c9649a9 | j_mayer | case 0x2C: |
| 1502 | 4c9649a9 | j_mayer | /* CVTGF */
|
| 1503 | a7812ae4 | pbrook | gen_fcvtgf(rb, rc); |
| 1504 | 4c9649a9 | j_mayer | break;
|
| 1505 | 4c9649a9 | j_mayer | case 0x2D: |
| 1506 | 4c9649a9 | j_mayer | /* CVTGD */
|
| 1507 | 4c9649a9 | j_mayer | #if 0 // TODO
|
| 1508 | a7812ae4 | pbrook | gen_fcvtgd(rb, rc);
|
| 1509 | 4c9649a9 | j_mayer | #else
|
| 1510 | 4c9649a9 | j_mayer | goto invalid_opc;
|
| 1511 | 4c9649a9 | j_mayer | #endif
|
| 1512 | 4c9649a9 | j_mayer | break;
|
| 1513 | 4c9649a9 | j_mayer | case 0x2F: |
| 1514 | 4c9649a9 | j_mayer | /* CVTGQ */
|
| 1515 | a7812ae4 | pbrook | gen_fcvtgq(rb, rc); |
| 1516 | 4c9649a9 | j_mayer | break;
|
| 1517 | 4c9649a9 | j_mayer | case 0x3C: |
| 1518 | 4c9649a9 | j_mayer | /* CVTQF */
|
| 1519 | a7812ae4 | pbrook | gen_fcvtqf(rb, rc); |
| 1520 | 4c9649a9 | j_mayer | break;
|
| 1521 | 4c9649a9 | j_mayer | case 0x3E: |
| 1522 | 4c9649a9 | j_mayer | /* CVTQG */
|
| 1523 | a7812ae4 | pbrook | gen_fcvtqg(rb, rc); |
| 1524 | 4c9649a9 | j_mayer | break;
|
| 1525 | 4c9649a9 | j_mayer | default:
|
| 1526 | 4c9649a9 | j_mayer | goto invalid_opc;
|
| 1527 | 4c9649a9 | j_mayer | } |
| 1528 | 4c9649a9 | j_mayer | break;
|
| 1529 | 4c9649a9 | j_mayer | case 0x16: |
| 1530 | 4c9649a9 | j_mayer | /* IEEE floating-point */
|
| 1531 | 4c9649a9 | j_mayer | /* XXX: rounding mode and traps are ignored (!) */
|
| 1532 | 4c9649a9 | j_mayer | switch (fpfn) { /* f11 & 0x3F */ |
| 1533 | 4c9649a9 | j_mayer | case 0x00: |
| 1534 | 4c9649a9 | j_mayer | /* ADDS */
|
| 1535 | a7812ae4 | pbrook | gen_fadds(ra, rb, rc); |
| 1536 | 4c9649a9 | j_mayer | break;
|
| 1537 | 4c9649a9 | j_mayer | case 0x01: |
| 1538 | 4c9649a9 | j_mayer | /* SUBS */
|
| 1539 | a7812ae4 | pbrook | gen_fsubs(ra, rb, rc); |
| 1540 | 4c9649a9 | j_mayer | break;
|
| 1541 | 4c9649a9 | j_mayer | case 0x02: |
| 1542 | 4c9649a9 | j_mayer | /* MULS */
|
| 1543 | a7812ae4 | pbrook | gen_fmuls(ra, rb, rc); |
| 1544 | 4c9649a9 | j_mayer | break;
|
| 1545 | 4c9649a9 | j_mayer | case 0x03: |
| 1546 | 4c9649a9 | j_mayer | /* DIVS */
|
| 1547 | a7812ae4 | pbrook | gen_fdivs(ra, rb, rc); |
| 1548 | 4c9649a9 | j_mayer | break;
|
| 1549 | 4c9649a9 | j_mayer | case 0x20: |
| 1550 | 4c9649a9 | j_mayer | /* ADDT */
|
| 1551 | a7812ae4 | pbrook | gen_faddt(ra, rb, rc); |
| 1552 | 4c9649a9 | j_mayer | break;
|
| 1553 | 4c9649a9 | j_mayer | case 0x21: |
| 1554 | 4c9649a9 | j_mayer | /* SUBT */
|
| 1555 | a7812ae4 | pbrook | gen_fsubt(ra, rb, rc); |
| 1556 | 4c9649a9 | j_mayer | break;
|
| 1557 | 4c9649a9 | j_mayer | case 0x22: |
| 1558 | 4c9649a9 | j_mayer | /* MULT */
|
| 1559 | a7812ae4 | pbrook | gen_fmult(ra, rb, rc); |
| 1560 | 4c9649a9 | j_mayer | break;
|
| 1561 | 4c9649a9 | j_mayer | case 0x23: |
| 1562 | 4c9649a9 | j_mayer | /* DIVT */
|
| 1563 | a7812ae4 | pbrook | gen_fdivt(ra, rb, rc); |
| 1564 | 4c9649a9 | j_mayer | break;
|
| 1565 | 4c9649a9 | j_mayer | case 0x24: |
| 1566 | 4c9649a9 | j_mayer | /* CMPTUN */
|
| 1567 | a7812ae4 | pbrook | gen_fcmptun(ra, rb, rc); |
| 1568 | 4c9649a9 | j_mayer | break;
|
| 1569 | 4c9649a9 | j_mayer | case 0x25: |
| 1570 | 4c9649a9 | j_mayer | /* CMPTEQ */
|
| 1571 | a7812ae4 | pbrook | gen_fcmpteq(ra, rb, rc); |
| 1572 | 4c9649a9 | j_mayer | break;
|
| 1573 | 4c9649a9 | j_mayer | case 0x26: |
| 1574 | 4c9649a9 | j_mayer | /* CMPTLT */
|
| 1575 | a7812ae4 | pbrook | gen_fcmptlt(ra, rb, rc); |
| 1576 | 4c9649a9 | j_mayer | break;
|
| 1577 | 4c9649a9 | j_mayer | case 0x27: |
| 1578 | 4c9649a9 | j_mayer | /* CMPTLE */
|
| 1579 | a7812ae4 | pbrook | gen_fcmptle(ra, rb, rc); |
| 1580 | 4c9649a9 | j_mayer | break;
|
| 1581 | 4c9649a9 | j_mayer | case 0x2C: |
| 1582 | 4c9649a9 | j_mayer | /* XXX: incorrect */
|
| 1583 | a74b4d2c | aurel32 | if (fn11 == 0x2AC || fn11 == 0x6AC) { |
| 1584 | 4c9649a9 | j_mayer | /* CVTST */
|
| 1585 | a7812ae4 | pbrook | gen_fcvtst(rb, rc); |
| 1586 | 4c9649a9 | j_mayer | } else {
|
| 1587 | 4c9649a9 | j_mayer | /* CVTTS */
|
| 1588 | a7812ae4 | pbrook | gen_fcvtts(rb, rc); |
| 1589 | 4c9649a9 | j_mayer | } |
| 1590 | 4c9649a9 | j_mayer | break;
|
| 1591 | 4c9649a9 | j_mayer | case 0x2F: |
| 1592 | 4c9649a9 | j_mayer | /* CVTTQ */
|
| 1593 | a7812ae4 | pbrook | gen_fcvttq(rb, rc); |
| 1594 | 4c9649a9 | j_mayer | break;
|
| 1595 | 4c9649a9 | j_mayer | case 0x3C: |
| 1596 | 4c9649a9 | j_mayer | /* CVTQS */
|
| 1597 | a7812ae4 | pbrook | gen_fcvtqs(rb, rc); |
| 1598 | 4c9649a9 | j_mayer | break;
|
| 1599 | 4c9649a9 | j_mayer | case 0x3E: |
| 1600 | 4c9649a9 | j_mayer | /* CVTQT */
|
| 1601 | a7812ae4 | pbrook | gen_fcvtqt(rb, rc); |
| 1602 | 4c9649a9 | j_mayer | break;
|
| 1603 | 4c9649a9 | j_mayer | default:
|
| 1604 | 4c9649a9 | j_mayer | goto invalid_opc;
|
| 1605 | 4c9649a9 | j_mayer | } |
| 1606 | 4c9649a9 | j_mayer | break;
|
| 1607 | 4c9649a9 | j_mayer | case 0x17: |
| 1608 | 4c9649a9 | j_mayer | switch (fn11) {
|
| 1609 | 4c9649a9 | j_mayer | case 0x010: |
| 1610 | 4c9649a9 | j_mayer | /* CVTLQ */
|
| 1611 | a7812ae4 | pbrook | gen_fcvtlq(rb, rc); |
| 1612 | 4c9649a9 | j_mayer | break;
|
| 1613 | 4c9649a9 | j_mayer | case 0x020: |
| 1614 | f18cd223 | aurel32 | if (likely(rc != 31)) { |
| 1615 | f18cd223 | aurel32 | if (ra == rb)
|
| 1616 | 4c9649a9 | j_mayer | /* FMOV */
|
| 1617 | f18cd223 | aurel32 | tcg_gen_mov_i64(cpu_fir[rc], cpu_fir[ra]); |
| 1618 | f18cd223 | aurel32 | else
|
| 1619 | f18cd223 | aurel32 | /* CPYS */
|
| 1620 | a7812ae4 | pbrook | gen_fcpys(ra, rb, rc); |
| 1621 | 4c9649a9 | j_mayer | } |
| 1622 | 4c9649a9 | j_mayer | break;
|
| 1623 | 4c9649a9 | j_mayer | case 0x021: |
| 1624 | 4c9649a9 | j_mayer | /* CPYSN */
|
| 1625 | a7812ae4 | pbrook | gen_fcpysn(ra, rb, rc); |
| 1626 | 4c9649a9 | j_mayer | break;
|
| 1627 | 4c9649a9 | j_mayer | case 0x022: |
| 1628 | 4c9649a9 | j_mayer | /* CPYSE */
|
| 1629 | a7812ae4 | pbrook | gen_fcpyse(ra, rb, rc); |
| 1630 | 4c9649a9 | j_mayer | break;
|
| 1631 | 4c9649a9 | j_mayer | case 0x024: |
| 1632 | 4c9649a9 | j_mayer | /* MT_FPCR */
|
| 1633 | f18cd223 | aurel32 | if (likely(ra != 31)) |
| 1634 | a7812ae4 | pbrook | gen_helper_store_fpcr(cpu_fir[ra]); |
| 1635 | f18cd223 | aurel32 | else {
|
| 1636 | f18cd223 | aurel32 | TCGv tmp = tcg_const_i64(0);
|
| 1637 | a7812ae4 | pbrook | gen_helper_store_fpcr(tmp); |
| 1638 | f18cd223 | aurel32 | tcg_temp_free(tmp); |
| 1639 | f18cd223 | aurel32 | } |
| 1640 | 4c9649a9 | j_mayer | break;
|
| 1641 | 4c9649a9 | j_mayer | case 0x025: |
| 1642 | 4c9649a9 | j_mayer | /* MF_FPCR */
|
| 1643 | f18cd223 | aurel32 | if (likely(ra != 31)) |
| 1644 | a7812ae4 | pbrook | gen_helper_load_fpcr(cpu_fir[ra]); |
| 1645 | 4c9649a9 | j_mayer | break;
|
| 1646 | 4c9649a9 | j_mayer | case 0x02A: |
| 1647 | 4c9649a9 | j_mayer | /* FCMOVEQ */
|
| 1648 | a7812ae4 | pbrook | gen_fcmpfeq(ra, rb, rc); |
| 1649 | 4c9649a9 | j_mayer | break;
|
| 1650 | 4c9649a9 | j_mayer | case 0x02B: |
| 1651 | 4c9649a9 | j_mayer | /* FCMOVNE */
|
| 1652 | a7812ae4 | pbrook | gen_fcmpfne(ra, rb, rc); |
| 1653 | 4c9649a9 | j_mayer | break;
|
| 1654 | 4c9649a9 | j_mayer | case 0x02C: |
| 1655 | 4c9649a9 | j_mayer | /* FCMOVLT */
|
| 1656 | a7812ae4 | pbrook | gen_fcmpflt(ra, rb, rc); |
| 1657 | 4c9649a9 | j_mayer | break;
|
| 1658 | 4c9649a9 | j_mayer | case 0x02D: |
| 1659 | 4c9649a9 | j_mayer | /* FCMOVGE */
|
| 1660 | a7812ae4 | pbrook | gen_fcmpfge(ra, rb, rc); |
| 1661 | 4c9649a9 | j_mayer | break;
|
| 1662 | 4c9649a9 | j_mayer | case 0x02E: |
| 1663 | 4c9649a9 | j_mayer | /* FCMOVLE */
|
| 1664 | a7812ae4 | pbrook | gen_fcmpfle(ra, rb, rc); |
| 1665 | 4c9649a9 | j_mayer | break;
|
| 1666 | 4c9649a9 | j_mayer | case 0x02F: |
| 1667 | 4c9649a9 | j_mayer | /* FCMOVGT */
|
| 1668 | a7812ae4 | pbrook | gen_fcmpfgt(ra, rb, rc); |
| 1669 | 4c9649a9 | j_mayer | break;
|
| 1670 | 4c9649a9 | j_mayer | case 0x030: |
| 1671 | 4c9649a9 | j_mayer | /* CVTQL */
|
| 1672 | a7812ae4 | pbrook | gen_fcvtql(rb, rc); |
| 1673 | 4c9649a9 | j_mayer | break;
|
| 1674 | 4c9649a9 | j_mayer | case 0x130: |
| 1675 | 4c9649a9 | j_mayer | /* CVTQL/V */
|
| 1676 | a7812ae4 | pbrook | gen_fcvtqlv(rb, rc); |
| 1677 | 4c9649a9 | j_mayer | break;
|
| 1678 | 4c9649a9 | j_mayer | case 0x530: |
| 1679 | 4c9649a9 | j_mayer | /* CVTQL/SV */
|
| 1680 | a7812ae4 | pbrook | gen_fcvtqlsv(rb, rc); |
| 1681 | 4c9649a9 | j_mayer | break;
|
| 1682 | 4c9649a9 | j_mayer | default:
|
| 1683 | 4c9649a9 | j_mayer | goto invalid_opc;
|
| 1684 | 4c9649a9 | j_mayer | } |
| 1685 | 4c9649a9 | j_mayer | break;
|
| 1686 | 4c9649a9 | j_mayer | case 0x18: |
| 1687 | 4c9649a9 | j_mayer | switch ((uint16_t)disp16) {
|
| 1688 | 4c9649a9 | j_mayer | case 0x0000: |
| 1689 | 4c9649a9 | j_mayer | /* TRAPB */
|
| 1690 | 4c9649a9 | j_mayer | /* No-op. Just exit from the current tb */
|
| 1691 | 4c9649a9 | j_mayer | ret = 2;
|
| 1692 | 4c9649a9 | j_mayer | break;
|
| 1693 | 4c9649a9 | j_mayer | case 0x0400: |
| 1694 | 4c9649a9 | j_mayer | /* EXCB */
|
| 1695 | 4c9649a9 | j_mayer | /* No-op. Just exit from the current tb */
|
| 1696 | 4c9649a9 | j_mayer | ret = 2;
|
| 1697 | 4c9649a9 | j_mayer | break;
|
| 1698 | 4c9649a9 | j_mayer | case 0x4000: |
| 1699 | 4c9649a9 | j_mayer | /* MB */
|
| 1700 | 4c9649a9 | j_mayer | /* No-op */
|
| 1701 | 4c9649a9 | j_mayer | break;
|
| 1702 | 4c9649a9 | j_mayer | case 0x4400: |
| 1703 | 4c9649a9 | j_mayer | /* WMB */
|
| 1704 | 4c9649a9 | j_mayer | /* No-op */
|
| 1705 | 4c9649a9 | j_mayer | break;
|
| 1706 | 4c9649a9 | j_mayer | case 0x8000: |
| 1707 | 4c9649a9 | j_mayer | /* FETCH */
|
| 1708 | 4c9649a9 | j_mayer | /* No-op */
|
| 1709 | 4c9649a9 | j_mayer | break;
|
| 1710 | 4c9649a9 | j_mayer | case 0xA000: |
| 1711 | 4c9649a9 | j_mayer | /* FETCH_M */
|
| 1712 | 4c9649a9 | j_mayer | /* No-op */
|
| 1713 | 4c9649a9 | j_mayer | break;
|
| 1714 | 4c9649a9 | j_mayer | case 0xC000: |
| 1715 | 4c9649a9 | j_mayer | /* RPCC */
|
| 1716 | 3761035f | aurel32 | if (ra != 31) |
| 1717 | a7812ae4 | pbrook | gen_helper_load_pcc(cpu_ir[ra]); |
| 1718 | 4c9649a9 | j_mayer | break;
|
| 1719 | 4c9649a9 | j_mayer | case 0xE000: |
| 1720 | 4c9649a9 | j_mayer | /* RC */
|
| 1721 | 3761035f | aurel32 | if (ra != 31) |
| 1722 | a7812ae4 | pbrook | gen_helper_rc(cpu_ir[ra]); |
| 1723 | 4c9649a9 | j_mayer | break;
|
| 1724 | 4c9649a9 | j_mayer | case 0xE800: |
| 1725 | 4c9649a9 | j_mayer | /* ECB */
|
| 1726 | 4c9649a9 | j_mayer | /* XXX: TODO: evict tb cache at address rb */
|
| 1727 | 4c9649a9 | j_mayer | #if 0
|
| 1728 | 4c9649a9 | j_mayer | ret = 2;
|
| 1729 | 4c9649a9 | j_mayer | #else
|
| 1730 | 4c9649a9 | j_mayer | goto invalid_opc;
|
| 1731 | 4c9649a9 | j_mayer | #endif
|
| 1732 | 4c9649a9 | j_mayer | break;
|
| 1733 | 4c9649a9 | j_mayer | case 0xF000: |
| 1734 | 4c9649a9 | j_mayer | /* RS */
|
| 1735 | 3761035f | aurel32 | if (ra != 31) |
| 1736 | a7812ae4 | pbrook | gen_helper_rs(cpu_ir[ra]); |
| 1737 | 4c9649a9 | j_mayer | break;
|
| 1738 | 4c9649a9 | j_mayer | case 0xF800: |
| 1739 | 4c9649a9 | j_mayer | /* WH64 */
|
| 1740 | 4c9649a9 | j_mayer | /* No-op */
|
| 1741 | 4c9649a9 | j_mayer | break;
|
| 1742 | 4c9649a9 | j_mayer | default:
|
| 1743 | 4c9649a9 | j_mayer | goto invalid_opc;
|
| 1744 | 4c9649a9 | j_mayer | } |
| 1745 | 4c9649a9 | j_mayer | break;
|
| 1746 | 4c9649a9 | j_mayer | case 0x19: |
| 1747 | 4c9649a9 | j_mayer | /* HW_MFPR (PALcode) */
|
| 1748 | 4c9649a9 | j_mayer | #if defined (CONFIG_USER_ONLY)
|
| 1749 | 4c9649a9 | j_mayer | goto invalid_opc;
|
| 1750 | 4c9649a9 | j_mayer | #else
|
| 1751 | 4c9649a9 | j_mayer | if (!ctx->pal_mode)
|
| 1752 | 4c9649a9 | j_mayer | goto invalid_opc;
|
| 1753 | 8bb6e981 | aurel32 | if (ra != 31) { |
| 1754 | 8bb6e981 | aurel32 | TCGv tmp = tcg_const_i32(insn & 0xFF);
|
| 1755 | a7812ae4 | pbrook | gen_helper_mfpr(cpu_ir[ra], tmp, cpu_ir[ra]); |
| 1756 | 8bb6e981 | aurel32 | tcg_temp_free(tmp); |
| 1757 | 8bb6e981 | aurel32 | } |
| 1758 | 4c9649a9 | j_mayer | break;
|
| 1759 | 4c9649a9 | j_mayer | #endif
|
| 1760 | 4c9649a9 | j_mayer | case 0x1A: |
| 1761 | 3761035f | aurel32 | if (rb != 31) |
| 1762 | 3761035f | aurel32 | tcg_gen_andi_i64(cpu_pc, cpu_ir[rb], ~3);
|
| 1763 | 3761035f | aurel32 | else
|
| 1764 | 3761035f | aurel32 | tcg_gen_movi_i64(cpu_pc, 0);
|
| 1765 | 1304ca87 | aurel32 | if (ra != 31) |
| 1766 | 1304ca87 | aurel32 | tcg_gen_movi_i64(cpu_ir[ra], ctx->pc); |
| 1767 | 4c9649a9 | j_mayer | /* Those four jumps only differ by the branch prediction hint */
|
| 1768 | 4c9649a9 | j_mayer | switch (fn2) {
|
| 1769 | 4c9649a9 | j_mayer | case 0x0: |
| 1770 | 4c9649a9 | j_mayer | /* JMP */
|
| 1771 | 4c9649a9 | j_mayer | break;
|
| 1772 | 4c9649a9 | j_mayer | case 0x1: |
| 1773 | 4c9649a9 | j_mayer | /* JSR */
|
| 1774 | 4c9649a9 | j_mayer | break;
|
| 1775 | 4c9649a9 | j_mayer | case 0x2: |
| 1776 | 4c9649a9 | j_mayer | /* RET */
|
| 1777 | 4c9649a9 | j_mayer | break;
|
| 1778 | 4c9649a9 | j_mayer | case 0x3: |
| 1779 | 4c9649a9 | j_mayer | /* JSR_COROUTINE */
|
| 1780 | 4c9649a9 | j_mayer | break;
|
| 1781 | 4c9649a9 | j_mayer | } |
| 1782 | 4c9649a9 | j_mayer | ret = 1;
|
| 1783 | 4c9649a9 | j_mayer | break;
|
| 1784 | 4c9649a9 | j_mayer | case 0x1B: |
| 1785 | 4c9649a9 | j_mayer | /* HW_LD (PALcode) */
|
| 1786 | 4c9649a9 | j_mayer | #if defined (CONFIG_USER_ONLY)
|
| 1787 | 4c9649a9 | j_mayer | goto invalid_opc;
|
| 1788 | 4c9649a9 | j_mayer | #else
|
| 1789 | 4c9649a9 | j_mayer | if (!ctx->pal_mode)
|
| 1790 | 4c9649a9 | j_mayer | goto invalid_opc;
|
| 1791 | 8bb6e981 | aurel32 | if (ra != 31) { |
| 1792 | a7812ae4 | pbrook | TCGv addr = tcg_temp_new(); |
| 1793 | 8bb6e981 | aurel32 | if (rb != 31) |
| 1794 | 8bb6e981 | aurel32 | tcg_gen_addi_i64(addr, cpu_ir[rb], disp12); |
| 1795 | 8bb6e981 | aurel32 | else
|
| 1796 | 8bb6e981 | aurel32 | tcg_gen_movi_i64(addr, disp12); |
| 1797 | 8bb6e981 | aurel32 | switch ((insn >> 12) & 0xF) { |
| 1798 | 8bb6e981 | aurel32 | case 0x0: |
| 1799 | 8bb6e981 | aurel32 | /* Longword physical access */
|
| 1800 | a7812ae4 | pbrook | gen_helper_ldl_raw(cpu_ir[ra], addr); |
| 1801 | 8bb6e981 | aurel32 | break;
|
| 1802 | 8bb6e981 | aurel32 | case 0x1: |
| 1803 | 8bb6e981 | aurel32 | /* Quadword physical access */
|
| 1804 | a7812ae4 | pbrook | gen_helper_ldq_raw(cpu_ir[ra], addr); |
| 1805 | 8bb6e981 | aurel32 | break;
|
| 1806 | 8bb6e981 | aurel32 | case 0x2: |
| 1807 | 8bb6e981 | aurel32 | /* Longword physical access with lock */
|
| 1808 | a7812ae4 | pbrook | gen_helper_ldl_l_raw(cpu_ir[ra], addr); |
| 1809 | 8bb6e981 | aurel32 | break;
|
| 1810 | 8bb6e981 | aurel32 | case 0x3: |
| 1811 | 8bb6e981 | aurel32 | /* Quadword physical access with lock */
|
| 1812 | a7812ae4 | pbrook | gen_helper_ldq_l_raw(cpu_ir[ra], addr); |
| 1813 | 8bb6e981 | aurel32 | break;
|
| 1814 | 8bb6e981 | aurel32 | case 0x4: |
| 1815 | 8bb6e981 | aurel32 | /* Longword virtual PTE fetch */
|
| 1816 | a7812ae4 | pbrook | gen_helper_ldl_kernel(cpu_ir[ra], addr); |
| 1817 | 8bb6e981 | aurel32 | break;
|
| 1818 | 8bb6e981 | aurel32 | case 0x5: |
| 1819 | 8bb6e981 | aurel32 | /* Quadword virtual PTE fetch */
|
| 1820 | a7812ae4 | pbrook | gen_helper_ldq_kernel(cpu_ir[ra], addr); |
| 1821 | 8bb6e981 | aurel32 | break;
|
| 1822 | 8bb6e981 | aurel32 | case 0x6: |
| 1823 | 8bb6e981 | aurel32 | /* Incpu_ir[ra]id */
|
| 1824 | 8bb6e981 | aurel32 | goto incpu_ir[ra]id_opc;
|
| 1825 | 8bb6e981 | aurel32 | case 0x7: |
| 1826 | 8bb6e981 | aurel32 | /* Incpu_ir[ra]id */
|
| 1827 | 8bb6e981 | aurel32 | goto incpu_ir[ra]id_opc;
|
| 1828 | 8bb6e981 | aurel32 | case 0x8: |
| 1829 | 8bb6e981 | aurel32 | /* Longword virtual access */
|
| 1830 | a7812ae4 | pbrook | gen_helper_st_virt_to_phys(addr, addr); |
| 1831 | a7812ae4 | pbrook | gen_helper_ldl_raw(cpu_ir[ra], addr); |
| 1832 | 8bb6e981 | aurel32 | break;
|
| 1833 | 8bb6e981 | aurel32 | case 0x9: |
| 1834 | 8bb6e981 | aurel32 | /* Quadword virtual access */
|
| 1835 | a7812ae4 | pbrook | gen_helper_st_virt_to_phys(addr, addr); |
| 1836 | a7812ae4 | pbrook | gen_helper_ldq_raw(cpu_ir[ra], addr); |
| 1837 | 8bb6e981 | aurel32 | break;
|
| 1838 | 8bb6e981 | aurel32 | case 0xA: |
| 1839 | 8bb6e981 | aurel32 | /* Longword virtual access with protection check */
|
| 1840 | 8bb6e981 | aurel32 | tcg_gen_qemu_ld32s(cpu_ir[ra], addr, ctx->flags); |
| 1841 | 8bb6e981 | aurel32 | break;
|
| 1842 | 8bb6e981 | aurel32 | case 0xB: |
| 1843 | 8bb6e981 | aurel32 | /* Quadword virtual access with protection check */
|
| 1844 | 8bb6e981 | aurel32 | tcg_gen_qemu_ld64(cpu_ir[ra], addr, ctx->flags); |
| 1845 | 8bb6e981 | aurel32 | break;
|
| 1846 | 8bb6e981 | aurel32 | case 0xC: |
| 1847 | 8bb6e981 | aurel32 | /* Longword virtual access with altenate access mode */
|
| 1848 | a7812ae4 | pbrook | gen_helper_set_alt_mode(); |
| 1849 | a7812ae4 | pbrook | gen_helper_st_virt_to_phys(addr, addr); |
| 1850 | a7812ae4 | pbrook | gen_helper_ldl_raw(cpu_ir[ra], addr); |
| 1851 | a7812ae4 | pbrook | gen_helper_restore_mode(); |
| 1852 | 8bb6e981 | aurel32 | break;
|
| 1853 | 8bb6e981 | aurel32 | case 0xD: |
| 1854 | 8bb6e981 | aurel32 | /* Quadword virtual access with altenate access mode */
|
| 1855 | a7812ae4 | pbrook | gen_helper_set_alt_mode(); |
| 1856 | a7812ae4 | pbrook | gen_helper_st_virt_to_phys(addr, addr); |
| 1857 | a7812ae4 | pbrook | gen_helper_ldq_raw(cpu_ir[ra], addr); |
| 1858 | a7812ae4 | pbrook | gen_helper_restore_mode(); |
| 1859 | 8bb6e981 | aurel32 | break;
|
| 1860 | 8bb6e981 | aurel32 | case 0xE: |
| 1861 | 8bb6e981 | aurel32 | /* Longword virtual access with alternate access mode and
|
| 1862 | 8bb6e981 | aurel32 | * protection checks
|
| 1863 | 8bb6e981 | aurel32 | */
|
| 1864 | a7812ae4 | pbrook | gen_helper_set_alt_mode(); |
| 1865 | a7812ae4 | pbrook | gen_helper_ldl_data(cpu_ir[ra], addr); |
| 1866 | a7812ae4 | pbrook | gen_helper_restore_mode(); |
| 1867 | 8bb6e981 | aurel32 | break;
|
| 1868 | 8bb6e981 | aurel32 | case 0xF: |
| 1869 | 8bb6e981 | aurel32 | /* Quadword virtual access with alternate access mode and
|
| 1870 | 8bb6e981 | aurel32 | * protection checks
|
| 1871 | 8bb6e981 | aurel32 | */
|
| 1872 | a7812ae4 | pbrook | gen_helper_set_alt_mode(); |
| 1873 | a7812ae4 | pbrook | gen_helper_ldq_data(cpu_ir[ra], addr); |
| 1874 | a7812ae4 | pbrook | gen_helper_restore_mode(); |
| 1875 | 8bb6e981 | aurel32 | break;
|
| 1876 | 8bb6e981 | aurel32 | } |
| 1877 | 8bb6e981 | aurel32 | tcg_temp_free(addr); |
| 1878 | 4c9649a9 | j_mayer | } |
| 1879 | 4c9649a9 | j_mayer | break;
|
| 1880 | 4c9649a9 | j_mayer | #endif
|
| 1881 | 4c9649a9 | j_mayer | case 0x1C: |
| 1882 | 4c9649a9 | j_mayer | switch (fn7) {
|
| 1883 | 4c9649a9 | j_mayer | case 0x00: |
| 1884 | 4c9649a9 | j_mayer | /* SEXTB */
|
| 1885 | 4c9649a9 | j_mayer | if (!(ctx->amask & AMASK_BWX))
|
| 1886 | 4c9649a9 | j_mayer | goto invalid_opc;
|
| 1887 | ae8ecd42 | aurel32 | if (likely(rc != 31)) { |
| 1888 | ae8ecd42 | aurel32 | if (islit)
|
| 1889 | ae8ecd42 | aurel32 | tcg_gen_movi_i64(cpu_ir[rc], (int64_t)((int8_t)lit)); |
| 1890 | ae8ecd42 | aurel32 | else
|
| 1891 | dfaa8583 | aurel32 | tcg_gen_ext8s_i64(cpu_ir[rc], cpu_ir[rb]); |
| 1892 | ae8ecd42 | aurel32 | } |
| 1893 | 4c9649a9 | j_mayer | break;
|
| 1894 | 4c9649a9 | j_mayer | case 0x01: |
| 1895 | 4c9649a9 | j_mayer | /* SEXTW */
|
| 1896 | 4c9649a9 | j_mayer | if (!(ctx->amask & AMASK_BWX))
|
| 1897 | 4c9649a9 | j_mayer | goto invalid_opc;
|
| 1898 | ae8ecd42 | aurel32 | if (likely(rc != 31)) { |
| 1899 | ae8ecd42 | aurel32 | if (islit)
|
| 1900 | ae8ecd42 | aurel32 | tcg_gen_movi_i64(cpu_ir[rc], (int64_t)((int16_t)lit)); |
| 1901 | ae8ecd42 | aurel32 | else
|
| 1902 | dfaa8583 | aurel32 | tcg_gen_ext16s_i64(cpu_ir[rc], cpu_ir[rb]); |
| 1903 | ae8ecd42 | aurel32 | } |
| 1904 | 4c9649a9 | j_mayer | break;
|
| 1905 | 4c9649a9 | j_mayer | case 0x30: |
| 1906 | 4c9649a9 | j_mayer | /* CTPOP */
|
| 1907 | 4c9649a9 | j_mayer | if (!(ctx->amask & AMASK_CIX))
|
| 1908 | 4c9649a9 | j_mayer | goto invalid_opc;
|
| 1909 | ae8ecd42 | aurel32 | if (likely(rc != 31)) { |
| 1910 | ae8ecd42 | aurel32 | if (islit)
|
| 1911 | ae8ecd42 | aurel32 | tcg_gen_movi_i64(cpu_ir[rc], ctpop64(lit)); |
| 1912 | ae8ecd42 | aurel32 | else
|
| 1913 | a7812ae4 | pbrook | gen_helper_ctpop(cpu_ir[rc], cpu_ir[rb]); |
| 1914 | ae8ecd42 | aurel32 | } |
| 1915 | 4c9649a9 | j_mayer | break;
|
| 1916 | 4c9649a9 | j_mayer | case 0x31: |
| 1917 | 4c9649a9 | j_mayer | /* PERR */
|
| 1918 | 4c9649a9 | j_mayer | if (!(ctx->amask & AMASK_MVI))
|
| 1919 | 4c9649a9 | j_mayer | goto invalid_opc;
|
| 1920 | 4c9649a9 | j_mayer | /* XXX: TODO */
|
| 1921 | 4c9649a9 | j_mayer | goto invalid_opc;
|
| 1922 | 4c9649a9 | j_mayer | break;
|
| 1923 | 4c9649a9 | j_mayer | case 0x32: |
| 1924 | 4c9649a9 | j_mayer | /* CTLZ */
|
| 1925 | 4c9649a9 | j_mayer | if (!(ctx->amask & AMASK_CIX))
|
| 1926 | 4c9649a9 | j_mayer | goto invalid_opc;
|
| 1927 | ae8ecd42 | aurel32 | if (likely(rc != 31)) { |
| 1928 | ae8ecd42 | aurel32 | if (islit)
|
| 1929 | ae8ecd42 | aurel32 | tcg_gen_movi_i64(cpu_ir[rc], clz64(lit)); |
| 1930 | ae8ecd42 | aurel32 | else
|
| 1931 | a7812ae4 | pbrook | gen_helper_ctlz(cpu_ir[rc], cpu_ir[rb]); |
| 1932 | ae8ecd42 | aurel32 | } |
| 1933 | 4c9649a9 | j_mayer | break;
|
| 1934 | 4c9649a9 | j_mayer | case 0x33: |
| 1935 | 4c9649a9 | j_mayer | /* CTTZ */
|
| 1936 | 4c9649a9 | j_mayer | if (!(ctx->amask & AMASK_CIX))
|
| 1937 | 4c9649a9 | j_mayer | goto invalid_opc;
|
| 1938 | ae8ecd42 | aurel32 | if (likely(rc != 31)) { |
| 1939 | ae8ecd42 | aurel32 | if (islit)
|
| 1940 | ae8ecd42 | aurel32 | tcg_gen_movi_i64(cpu_ir[rc], ctz64(lit)); |
| 1941 | ae8ecd42 | aurel32 | else
|
| 1942 | a7812ae4 | pbrook | gen_helper_cttz(cpu_ir[rc], cpu_ir[rb]); |
| 1943 | ae8ecd42 | aurel32 | } |
| 1944 | 4c9649a9 | j_mayer | break;
|
| 1945 | 4c9649a9 | j_mayer | case 0x34: |
| 1946 | 4c9649a9 | j_mayer | /* UNPKBW */
|
| 1947 | 4c9649a9 | j_mayer | if (!(ctx->amask & AMASK_MVI))
|
| 1948 | 4c9649a9 | j_mayer | goto invalid_opc;
|
| 1949 | 4c9649a9 | j_mayer | /* XXX: TODO */
|
| 1950 | 4c9649a9 | j_mayer | goto invalid_opc;
|
| 1951 | 4c9649a9 | j_mayer | break;
|
| 1952 | 4c9649a9 | j_mayer | case 0x35: |
| 1953 | 4c9649a9 | j_mayer | /* UNPKWL */
|
| 1954 | 4c9649a9 | j_mayer | if (!(ctx->amask & AMASK_MVI))
|
| 1955 | 4c9649a9 | j_mayer | goto invalid_opc;
|
| 1956 | 4c9649a9 | j_mayer | /* XXX: TODO */
|
| 1957 | 4c9649a9 | j_mayer | goto invalid_opc;
|
| 1958 | 4c9649a9 | j_mayer | break;
|
| 1959 | 4c9649a9 | j_mayer | case 0x36: |
| 1960 | 4c9649a9 | j_mayer | /* PKWB */
|
| 1961 | 4c9649a9 | j_mayer | if (!(ctx->amask & AMASK_MVI))
|
| 1962 | 4c9649a9 | j_mayer | goto invalid_opc;
|
| 1963 | 4c9649a9 | j_mayer | /* XXX: TODO */
|
| 1964 | 4c9649a9 | j_mayer | goto invalid_opc;
|
| 1965 | 4c9649a9 | j_mayer | break;
|
| 1966 | 4c9649a9 | j_mayer | case 0x37: |
| 1967 | 4c9649a9 | j_mayer | /* PKLB */
|
| 1968 | 4c9649a9 | j_mayer | if (!(ctx->amask & AMASK_MVI))
|
| 1969 | 4c9649a9 | j_mayer | goto invalid_opc;
|
| 1970 | 4c9649a9 | j_mayer | /* XXX: TODO */
|
| 1971 | 4c9649a9 | j_mayer | goto invalid_opc;
|
| 1972 | 4c9649a9 | j_mayer | break;
|
| 1973 | 4c9649a9 | j_mayer | case 0x38: |
| 1974 | 4c9649a9 | j_mayer | /* MINSB8 */
|
| 1975 | 4c9649a9 | j_mayer | if (!(ctx->amask & AMASK_MVI))
|
| 1976 | 4c9649a9 | j_mayer | goto invalid_opc;
|
| 1977 | 4c9649a9 | j_mayer | /* XXX: TODO */
|
| 1978 | 4c9649a9 | j_mayer | goto invalid_opc;
|
| 1979 | 4c9649a9 | j_mayer | break;
|
| 1980 | 4c9649a9 | j_mayer | case 0x39: |
| 1981 | 4c9649a9 | j_mayer | /* MINSW4 */
|
| 1982 | 4c9649a9 | j_mayer | if (!(ctx->amask & AMASK_MVI))
|
| 1983 | 4c9649a9 | j_mayer | goto invalid_opc;
|
| 1984 | 4c9649a9 | j_mayer | /* XXX: TODO */
|
| 1985 | 4c9649a9 | j_mayer | goto invalid_opc;
|
| 1986 | 4c9649a9 | j_mayer | break;
|
| 1987 | 4c9649a9 | j_mayer | case 0x3A: |
| 1988 | 4c9649a9 | j_mayer | /* MINUB8 */
|
| 1989 | 4c9649a9 | j_mayer | if (!(ctx->amask & AMASK_MVI))
|
| 1990 | 4c9649a9 | j_mayer | goto invalid_opc;
|
| 1991 | 4c9649a9 | j_mayer | /* XXX: TODO */
|
| 1992 | 4c9649a9 | j_mayer | goto invalid_opc;
|
| 1993 | 4c9649a9 | j_mayer | break;
|
| 1994 | 4c9649a9 | j_mayer | case 0x3B: |
| 1995 | 4c9649a9 | j_mayer | /* MINUW4 */
|
| 1996 | 4c9649a9 | j_mayer | if (!(ctx->amask & AMASK_MVI))
|
| 1997 | 4c9649a9 | j_mayer | goto invalid_opc;
|
| 1998 | 4c9649a9 | j_mayer | /* XXX: TODO */
|
| 1999 | 4c9649a9 | j_mayer | goto invalid_opc;
|
| 2000 | 4c9649a9 | j_mayer | break;
|
| 2001 | 4c9649a9 | j_mayer | case 0x3C: |
| 2002 | 4c9649a9 | j_mayer | /* MAXUB8 */
|
| 2003 | 4c9649a9 | j_mayer | if (!(ctx->amask & AMASK_MVI))
|
| 2004 | 4c9649a9 | j_mayer | goto invalid_opc;
|
| 2005 | 4c9649a9 | j_mayer | /* XXX: TODO */
|
| 2006 | 4c9649a9 | j_mayer | goto invalid_opc;
|
| 2007 | 4c9649a9 | j_mayer | break;
|
| 2008 | 4c9649a9 | j_mayer | case 0x3D: |
| 2009 | 4c9649a9 | j_mayer | /* MAXUW4 */
|
| 2010 | 4c9649a9 | j_mayer | if (!(ctx->amask & AMASK_MVI))
|
| 2011 | 4c9649a9 | j_mayer | goto invalid_opc;
|
| 2012 | 4c9649a9 | j_mayer | /* XXX: TODO */
|
| 2013 | 4c9649a9 | j_mayer | goto invalid_opc;
|
| 2014 | 4c9649a9 | j_mayer | break;
|
| 2015 | 4c9649a9 | j_mayer | case 0x3E: |
| 2016 | 4c9649a9 | j_mayer | /* MAXSB8 */
|
| 2017 | 4c9649a9 | j_mayer | if (!(ctx->amask & AMASK_MVI))
|
| 2018 | 4c9649a9 | j_mayer | goto invalid_opc;
|
| 2019 | 4c9649a9 | j_mayer | /* XXX: TODO */
|
| 2020 | 4c9649a9 | j_mayer | goto invalid_opc;
|
| 2021 | 4c9649a9 | j_mayer | break;
|
| 2022 | 4c9649a9 | j_mayer | case 0x3F: |
| 2023 | 4c9649a9 | j_mayer | /* MAXSW4 */
|
| 2024 | 4c9649a9 | j_mayer | if (!(ctx->amask & AMASK_MVI))
|
| 2025 | 4c9649a9 | j_mayer | goto invalid_opc;
|
| 2026 | 4c9649a9 | j_mayer | /* XXX: TODO */
|
| 2027 | 4c9649a9 | j_mayer | goto invalid_opc;
|
| 2028 | 4c9649a9 | j_mayer | break;
|
| 2029 | 4c9649a9 | j_mayer | case 0x70: |
| 2030 | 4c9649a9 | j_mayer | /* FTOIT */
|
| 2031 | 4c9649a9 | j_mayer | if (!(ctx->amask & AMASK_FIX))
|
| 2032 | 4c9649a9 | j_mayer | goto invalid_opc;
|
| 2033 | f18cd223 | aurel32 | if (likely(rc != 31)) { |
| 2034 | f18cd223 | aurel32 | if (ra != 31) |
| 2035 | f18cd223 | aurel32 | tcg_gen_mov_i64(cpu_ir[rc], cpu_fir[ra]); |
| 2036 | f18cd223 | aurel32 | else
|
| 2037 | f18cd223 | aurel32 | tcg_gen_movi_i64(cpu_ir[rc], 0);
|
| 2038 | f18cd223 | aurel32 | } |
| 2039 | 4c9649a9 | j_mayer | break;
|
| 2040 | 4c9649a9 | j_mayer | case 0x78: |
| 2041 | 4c9649a9 | j_mayer | /* FTOIS */
|
| 2042 | 4c9649a9 | j_mayer | if (!(ctx->amask & AMASK_FIX))
|
| 2043 | 4c9649a9 | j_mayer | goto invalid_opc;
|
| 2044 | f18cd223 | aurel32 | if (rc != 31) { |
| 2045 | a7812ae4 | pbrook | TCGv_i32 tmp1 = tcg_temp_new_i32(); |
| 2046 | f18cd223 | aurel32 | if (ra != 31) |
| 2047 | a7812ae4 | pbrook | gen_helper_s_to_memory(tmp1, cpu_fir[ra]); |
| 2048 | f18cd223 | aurel32 | else {
|
| 2049 | f18cd223 | aurel32 | TCGv tmp2 = tcg_const_i64(0);
|
| 2050 | a7812ae4 | pbrook | gen_helper_s_to_memory(tmp1, tmp2); |
| 2051 | f18cd223 | aurel32 | tcg_temp_free(tmp2); |
| 2052 | f18cd223 | aurel32 | } |
| 2053 | f18cd223 | aurel32 | tcg_gen_ext_i32_i64(cpu_ir[rc], tmp1); |
| 2054 | a7812ae4 | pbrook | tcg_temp_free_i32(tmp1); |
| 2055 | f18cd223 | aurel32 | } |
| 2056 | 4c9649a9 | j_mayer | break;
|
| 2057 | 4c9649a9 | j_mayer | default:
|
| 2058 | 4c9649a9 | j_mayer | goto invalid_opc;
|
| 2059 | 4c9649a9 | j_mayer | } |
| 2060 | 4c9649a9 | j_mayer | break;
|
| 2061 | 4c9649a9 | j_mayer | case 0x1D: |
| 2062 | 4c9649a9 | j_mayer | /* HW_MTPR (PALcode) */
|
| 2063 | 4c9649a9 | j_mayer | #if defined (CONFIG_USER_ONLY)
|
| 2064 | 4c9649a9 | j_mayer | goto invalid_opc;
|
| 2065 | 4c9649a9 | j_mayer | #else
|
| 2066 | 4c9649a9 | j_mayer | if (!ctx->pal_mode)
|
| 2067 | 4c9649a9 | j_mayer | goto invalid_opc;
|
| 2068 | 8bb6e981 | aurel32 | else {
|
| 2069 | 8bb6e981 | aurel32 | TCGv tmp1 = tcg_const_i32(insn & 0xFF);
|
| 2070 | 8bb6e981 | aurel32 | if (ra != 31) |
| 2071 | a7812ae4 | pbrook | gen_helper_mtpr(tmp1, cpu_ir[ra]); |
| 2072 | 8bb6e981 | aurel32 | else {
|
| 2073 | 8bb6e981 | aurel32 | TCGv tmp2 = tcg_const_i64(0);
|
| 2074 | a7812ae4 | pbrook | gen_helper_mtpr(tmp1, tmp2); |
| 2075 | 8bb6e981 | aurel32 | tcg_temp_free(tmp2); |
| 2076 | 8bb6e981 | aurel32 | } |
| 2077 | 8bb6e981 | aurel32 | tcg_temp_free(tmp1); |
| 2078 | 8bb6e981 | aurel32 | ret = 2;
|
| 2079 | 8bb6e981 | aurel32 | } |
| 2080 | 4c9649a9 | j_mayer | break;
|
| 2081 | 4c9649a9 | j_mayer | #endif
|
| 2082 | 4c9649a9 | j_mayer | case 0x1E: |
| 2083 | 4c9649a9 | j_mayer | /* HW_REI (PALcode) */
|
| 2084 | 4c9649a9 | j_mayer | #if defined (CONFIG_USER_ONLY)
|
| 2085 | 4c9649a9 | j_mayer | goto invalid_opc;
|
| 2086 | 4c9649a9 | j_mayer | #else
|
| 2087 | 4c9649a9 | j_mayer | if (!ctx->pal_mode)
|
| 2088 | 4c9649a9 | j_mayer | goto invalid_opc;
|
| 2089 | 4c9649a9 | j_mayer | if (rb == 31) { |
| 2090 | 4c9649a9 | j_mayer | /* "Old" alpha */
|
| 2091 | a7812ae4 | pbrook | gen_helper_hw_rei(); |
| 2092 | 4c9649a9 | j_mayer | } else {
|
| 2093 | 8bb6e981 | aurel32 | TCGv tmp; |
| 2094 | 8bb6e981 | aurel32 | |
| 2095 | 8bb6e981 | aurel32 | if (ra != 31) { |
| 2096 | a7812ae4 | pbrook | tmp = tcg_temp_new(); |
| 2097 | 8bb6e981 | aurel32 | tcg_gen_addi_i64(tmp, cpu_ir[rb], (((int64_t)insn << 51) >> 51)); |
| 2098 | 8bb6e981 | aurel32 | } else
|
| 2099 | 8bb6e981 | aurel32 | tmp = tcg_const_i64(((int64_t)insn << 51) >> 51); |
| 2100 | a7812ae4 | pbrook | gen_helper_hw_ret(tmp); |
| 2101 | 8bb6e981 | aurel32 | tcg_temp_free(tmp); |
| 2102 | 4c9649a9 | j_mayer | } |
| 2103 | 4c9649a9 | j_mayer | ret = 2;
|
| 2104 | 4c9649a9 | j_mayer | break;
|
| 2105 | 4c9649a9 | j_mayer | #endif
|
| 2106 | 4c9649a9 | j_mayer | case 0x1F: |
| 2107 | 4c9649a9 | j_mayer | /* HW_ST (PALcode) */
|
| 2108 | 4c9649a9 | j_mayer | #if defined (CONFIG_USER_ONLY)
|
| 2109 | 4c9649a9 | j_mayer | goto invalid_opc;
|
| 2110 | 4c9649a9 | j_mayer | #else
|
| 2111 | 4c9649a9 | j_mayer | if (!ctx->pal_mode)
|
| 2112 | 4c9649a9 | j_mayer | goto invalid_opc;
|
| 2113 | 8bb6e981 | aurel32 | else {
|
| 2114 | 8bb6e981 | aurel32 | TCGv addr, val; |
| 2115 | a7812ae4 | pbrook | addr = tcg_temp_new(); |
| 2116 | 8bb6e981 | aurel32 | if (rb != 31) |
| 2117 | 8bb6e981 | aurel32 | tcg_gen_addi_i64(addr, cpu_ir[rb], disp12); |
| 2118 | 8bb6e981 | aurel32 | else
|
| 2119 | 8bb6e981 | aurel32 | tcg_gen_movi_i64(addr, disp12); |
| 2120 | 8bb6e981 | aurel32 | if (ra != 31) |
| 2121 | 8bb6e981 | aurel32 | val = cpu_ir[ra]; |
| 2122 | 8bb6e981 | aurel32 | else {
|
| 2123 | a7812ae4 | pbrook | val = tcg_temp_new(); |
| 2124 | 8bb6e981 | aurel32 | tcg_gen_movi_i64(val, 0);
|
| 2125 | 8bb6e981 | aurel32 | } |
| 2126 | 8bb6e981 | aurel32 | switch ((insn >> 12) & 0xF) { |
| 2127 | 8bb6e981 | aurel32 | case 0x0: |
| 2128 | 8bb6e981 | aurel32 | /* Longword physical access */
|
| 2129 | a7812ae4 | pbrook | gen_helper_stl_raw(val, addr); |
| 2130 | 8bb6e981 | aurel32 | break;
|
| 2131 | 8bb6e981 | aurel32 | case 0x1: |
| 2132 | 8bb6e981 | aurel32 | /* Quadword physical access */
|
| 2133 | a7812ae4 | pbrook | gen_helper_stq_raw(val, addr); |
| 2134 | 8bb6e981 | aurel32 | break;
|
| 2135 | 8bb6e981 | aurel32 | case 0x2: |
| 2136 | 8bb6e981 | aurel32 | /* Longword physical access with lock */
|
| 2137 | a7812ae4 | pbrook | gen_helper_stl_c_raw(val, val, addr); |
| 2138 | 8bb6e981 | aurel32 | break;
|
| 2139 | 8bb6e981 | aurel32 | case 0x3: |
| 2140 | 8bb6e981 | aurel32 | /* Quadword physical access with lock */
|
| 2141 | a7812ae4 | pbrook | gen_helper_stq_c_raw(val, val, addr); |
| 2142 | 8bb6e981 | aurel32 | break;
|
| 2143 | 8bb6e981 | aurel32 | case 0x4: |
| 2144 | 8bb6e981 | aurel32 | /* Longword virtual access */
|
| 2145 | a7812ae4 | pbrook | gen_helper_st_virt_to_phys(addr, addr); |
| 2146 | a7812ae4 | pbrook | gen_helper_stl_raw(val, addr); |
| 2147 | 8bb6e981 | aurel32 | break;
|
| 2148 | 8bb6e981 | aurel32 | case 0x5: |
| 2149 | 8bb6e981 | aurel32 | /* Quadword virtual access */
|
| 2150 | a7812ae4 | pbrook | gen_helper_st_virt_to_phys(addr, addr); |
| 2151 | a7812ae4 | pbrook | gen_helper_stq_raw(val, addr); |
| 2152 | 8bb6e981 | aurel32 | break;
|
| 2153 | 8bb6e981 | aurel32 | case 0x6: |
| 2154 | 8bb6e981 | aurel32 | /* Invalid */
|
| 2155 | 8bb6e981 | aurel32 | goto invalid_opc;
|
| 2156 | 8bb6e981 | aurel32 | case 0x7: |
| 2157 | 8bb6e981 | aurel32 | /* Invalid */
|
| 2158 | 8bb6e981 | aurel32 | goto invalid_opc;
|
| 2159 | 8bb6e981 | aurel32 | case 0x8: |
| 2160 | 8bb6e981 | aurel32 | /* Invalid */
|
| 2161 | 8bb6e981 | aurel32 | goto invalid_opc;
|
| 2162 | 8bb6e981 | aurel32 | case 0x9: |
| 2163 | 8bb6e981 | aurel32 | /* Invalid */
|
| 2164 | 8bb6e981 | aurel32 | goto invalid_opc;
|
| 2165 | 8bb6e981 | aurel32 | case 0xA: |
| 2166 | 8bb6e981 | aurel32 | /* Invalid */
|
| 2167 | 8bb6e981 | aurel32 | goto invalid_opc;
|
| 2168 | 8bb6e981 | aurel32 | case 0xB: |
| 2169 | 8bb6e981 | aurel32 | /* Invalid */
|
| 2170 | 8bb6e981 | aurel32 | goto invalid_opc;
|
| 2171 | 8bb6e981 | aurel32 | case 0xC: |
| 2172 | 8bb6e981 | aurel32 | /* Longword virtual access with alternate access mode */
|
| 2173 | a7812ae4 | pbrook | gen_helper_set_alt_mode(); |
| 2174 | a7812ae4 | pbrook | gen_helper_st_virt_to_phys(addr, addr); |
| 2175 | a7812ae4 | pbrook | gen_helper_stl_raw(val, addr); |
| 2176 | a7812ae4 | pbrook | gen_helper_restore_mode(); |
| 2177 | 8bb6e981 | aurel32 | break;
|
| 2178 | 8bb6e981 | aurel32 | case 0xD: |
| 2179 | 8bb6e981 | aurel32 | /* Quadword virtual access with alternate access mode */
|
| 2180 | a7812ae4 | pbrook | gen_helper_set_alt_mode(); |
| 2181 | a7812ae4 | pbrook | gen_helper_st_virt_to_phys(addr, addr); |
| 2182 | a7812ae4 | pbrook | gen_helper_stl_raw(val, addr); |
| 2183 | a7812ae4 | pbrook | gen_helper_restore_mode(); |
| 2184 | 8bb6e981 | aurel32 | break;
|
| 2185 | 8bb6e981 | aurel32 | case 0xE: |
| 2186 | 8bb6e981 | aurel32 | /* Invalid */
|
| 2187 | 8bb6e981 | aurel32 | goto invalid_opc;
|
| 2188 | 8bb6e981 | aurel32 | case 0xF: |
| 2189 | 8bb6e981 | aurel32 | /* Invalid */
|
| 2190 | 8bb6e981 | aurel32 | goto invalid_opc;
|
| 2191 | 8bb6e981 | aurel32 | } |
| 2192 | 8bb6e981 | aurel32 | if (ra != 31) |
| 2193 | 8bb6e981 | aurel32 | tcg_temp_free(val); |
| 2194 | 8bb6e981 | aurel32 | tcg_temp_free(addr); |
| 2195 | 4c9649a9 | j_mayer | } |
| 2196 | 4c9649a9 | j_mayer | ret = 2;
|
| 2197 | 4c9649a9 | j_mayer | break;
|
| 2198 | 4c9649a9 | j_mayer | #endif
|
| 2199 | 4c9649a9 | j_mayer | case 0x20: |
| 2200 | 4c9649a9 | j_mayer | /* LDF */
|
| 2201 | f18cd223 | aurel32 | gen_load_mem(ctx, &gen_qemu_ldf, ra, rb, disp16, 1, 0); |
| 2202 | 4c9649a9 | j_mayer | break;
|
| 2203 | 4c9649a9 | j_mayer | case 0x21: |
| 2204 | 4c9649a9 | j_mayer | /* LDG */
|
| 2205 | f18cd223 | aurel32 | gen_load_mem(ctx, &gen_qemu_ldg, ra, rb, disp16, 1, 0); |
| 2206 | 4c9649a9 | j_mayer | break;
|
| 2207 | 4c9649a9 | j_mayer | case 0x22: |
| 2208 | 4c9649a9 | j_mayer | /* LDS */
|
| 2209 | f18cd223 | aurel32 | gen_load_mem(ctx, &gen_qemu_lds, ra, rb, disp16, 1, 0); |
| 2210 | 4c9649a9 | j_mayer | break;
|
| 2211 | 4c9649a9 | j_mayer | case 0x23: |
| 2212 | 4c9649a9 | j_mayer | /* LDT */
|
| 2213 | f18cd223 | aurel32 | gen_load_mem(ctx, &tcg_gen_qemu_ld64, ra, rb, disp16, 1, 0); |
| 2214 | 4c9649a9 | j_mayer | break;
|
| 2215 | 4c9649a9 | j_mayer | case 0x24: |
| 2216 | 4c9649a9 | j_mayer | /* STF */
|
| 2217 | 57a92c8e | aurel32 | gen_store_mem(ctx, &gen_qemu_stf, ra, rb, disp16, 1, 0, 0); |
| 2218 | 4c9649a9 | j_mayer | break;
|
| 2219 | 4c9649a9 | j_mayer | case 0x25: |
| 2220 | 4c9649a9 | j_mayer | /* STG */
|
| 2221 | 57a92c8e | aurel32 | gen_store_mem(ctx, &gen_qemu_stg, ra, rb, disp16, 1, 0, 0); |
| 2222 | 4c9649a9 | j_mayer | break;
|
| 2223 | 4c9649a9 | j_mayer | case 0x26: |
| 2224 | 4c9649a9 | j_mayer | /* STS */
|
| 2225 | 57a92c8e | aurel32 | gen_store_mem(ctx, &gen_qemu_sts, ra, rb, disp16, 1, 0, 0); |
| 2226 | 4c9649a9 | j_mayer | break;
|
| 2227 | 4c9649a9 | j_mayer | case 0x27: |
| 2228 | 4c9649a9 | j_mayer | /* STT */
|
| 2229 | 57a92c8e | aurel32 | gen_store_mem(ctx, &tcg_gen_qemu_st64, ra, rb, disp16, 1, 0, 0); |
| 2230 | 4c9649a9 | j_mayer | break;
|
| 2231 | 4c9649a9 | j_mayer | case 0x28: |
| 2232 | 4c9649a9 | j_mayer | /* LDL */
|
| 2233 | f18cd223 | aurel32 | gen_load_mem(ctx, &tcg_gen_qemu_ld32s, ra, rb, disp16, 0, 0); |
| 2234 | 4c9649a9 | j_mayer | break;
|
| 2235 | 4c9649a9 | j_mayer | case 0x29: |
| 2236 | 4c9649a9 | j_mayer | /* LDQ */
|
| 2237 | f18cd223 | aurel32 | gen_load_mem(ctx, &tcg_gen_qemu_ld64, ra, rb, disp16, 0, 0); |
| 2238 | 4c9649a9 | j_mayer | break;
|
| 2239 | 4c9649a9 | j_mayer | case 0x2A: |
| 2240 | 4c9649a9 | j_mayer | /* LDL_L */
|
| 2241 | f4ed8679 | aurel32 | gen_load_mem(ctx, &gen_qemu_ldl_l, ra, rb, disp16, 0, 0); |
| 2242 | 4c9649a9 | j_mayer | break;
|
| 2243 | 4c9649a9 | j_mayer | case 0x2B: |
| 2244 | 4c9649a9 | j_mayer | /* LDQ_L */
|
| 2245 | f4ed8679 | aurel32 | gen_load_mem(ctx, &gen_qemu_ldq_l, ra, rb, disp16, 0, 0); |
| 2246 | 4c9649a9 | j_mayer | break;
|
| 2247 | 4c9649a9 | j_mayer | case 0x2C: |
| 2248 | 4c9649a9 | j_mayer | /* STL */
|
| 2249 | 57a92c8e | aurel32 | gen_store_mem(ctx, &tcg_gen_qemu_st32, ra, rb, disp16, 0, 0, 0); |
| 2250 | 4c9649a9 | j_mayer | break;
|
| 2251 | 4c9649a9 | j_mayer | case 0x2D: |
| 2252 | 4c9649a9 | j_mayer | /* STQ */
|
| 2253 | 57a92c8e | aurel32 | gen_store_mem(ctx, &tcg_gen_qemu_st64, ra, rb, disp16, 0, 0, 0); |
| 2254 | 4c9649a9 | j_mayer | break;
|
| 2255 | 4c9649a9 | j_mayer | case 0x2E: |
| 2256 | 4c9649a9 | j_mayer | /* STL_C */
|
| 2257 | 57a92c8e | aurel32 | gen_store_mem(ctx, &gen_qemu_stl_c, ra, rb, disp16, 0, 0, 1); |
| 2258 | 4c9649a9 | j_mayer | break;
|
| 2259 | 4c9649a9 | j_mayer | case 0x2F: |
| 2260 | 4c9649a9 | j_mayer | /* STQ_C */
|
| 2261 | 57a92c8e | aurel32 | gen_store_mem(ctx, &gen_qemu_stq_c, ra, rb, disp16, 0, 0, 1); |
| 2262 | 4c9649a9 | j_mayer | break;
|
| 2263 | 4c9649a9 | j_mayer | case 0x30: |
| 2264 | 4c9649a9 | j_mayer | /* BR */
|
| 2265 | 3761035f | aurel32 | if (ra != 31) |
| 2266 | 3761035f | aurel32 | tcg_gen_movi_i64(cpu_ir[ra], ctx->pc); |
| 2267 | 3761035f | aurel32 | tcg_gen_movi_i64(cpu_pc, ctx->pc + (int64_t)(disp21 << 2));
|
| 2268 | 4c9649a9 | j_mayer | ret = 1;
|
| 2269 | 4c9649a9 | j_mayer | break;
|
| 2270 | a7812ae4 | pbrook | case 0x31: /* FBEQ */ |
| 2271 | a7812ae4 | pbrook | case 0x32: /* FBLT */ |
| 2272 | a7812ae4 | pbrook | case 0x33: /* FBLE */ |
| 2273 | a7812ae4 | pbrook | gen_fbcond(ctx, opc, ra, disp16); |
| 2274 | 4c9649a9 | j_mayer | ret = 1;
|
| 2275 | 4c9649a9 | j_mayer | break;
|
| 2276 | 4c9649a9 | j_mayer | case 0x34: |
| 2277 | 4c9649a9 | j_mayer | /* BSR */
|
| 2278 | 3761035f | aurel32 | if (ra != 31) |
| 2279 | 3761035f | aurel32 | tcg_gen_movi_i64(cpu_ir[ra], ctx->pc); |
| 2280 | 3761035f | aurel32 | tcg_gen_movi_i64(cpu_pc, ctx->pc + (int64_t)(disp21 << 2));
|
| 2281 | 4c9649a9 | j_mayer | ret = 1;
|
| 2282 | 4c9649a9 | j_mayer | break;
|
| 2283 | a7812ae4 | pbrook | case 0x35: /* FBNE */ |
| 2284 | a7812ae4 | pbrook | case 0x36: /* FBGE */ |
| 2285 | a7812ae4 | pbrook | case 0x37: /* FBGT */ |
| 2286 | a7812ae4 | pbrook | gen_fbcond(ctx, opc, ra, disp16); |
| 2287 | 4c9649a9 | j_mayer | ret = 1;
|
| 2288 | 4c9649a9 | j_mayer | break;
|
| 2289 | 4c9649a9 | j_mayer | case 0x38: |
| 2290 | 4c9649a9 | j_mayer | /* BLBC */
|
| 2291 | 9c29504e | aurel32 | gen_bcond(ctx, TCG_COND_EQ, ra, disp16, 1);
|
| 2292 | 4c9649a9 | j_mayer | ret = 1;
|
| 2293 | 4c9649a9 | j_mayer | break;
|
| 2294 | 4c9649a9 | j_mayer | case 0x39: |
| 2295 | 4c9649a9 | j_mayer | /* BEQ */
|
| 2296 | 9c29504e | aurel32 | gen_bcond(ctx, TCG_COND_EQ, ra, disp16, 0);
|
| 2297 | 4c9649a9 | j_mayer | ret = 1;
|
| 2298 | 4c9649a9 | j_mayer | break;
|
| 2299 | 4c9649a9 | j_mayer | case 0x3A: |
| 2300 | 4c9649a9 | j_mayer | /* BLT */
|
| 2301 | 9c29504e | aurel32 | gen_bcond(ctx, TCG_COND_LT, ra, disp16, 0);
|
| 2302 | 4c9649a9 | j_mayer | ret = 1;
|
| 2303 | 4c9649a9 | j_mayer | break;
|
| 2304 | 4c9649a9 | j_mayer | case 0x3B: |
| 2305 | 4c9649a9 | j_mayer | /* BLE */
|
| 2306 | 9c29504e | aurel32 | gen_bcond(ctx, TCG_COND_LE, ra, disp16, 0);
|
| 2307 | 4c9649a9 | j_mayer | ret = 1;
|
| 2308 | 4c9649a9 | j_mayer | break;
|
| 2309 | 4c9649a9 | j_mayer | case 0x3C: |
| 2310 | 4c9649a9 | j_mayer | /* BLBS */
|
| 2311 | 9c29504e | aurel32 | gen_bcond(ctx, TCG_COND_NE, ra, disp16, 1);
|
| 2312 | 4c9649a9 | j_mayer | ret = 1;
|
| 2313 | 4c9649a9 | j_mayer | break;
|
| 2314 | 4c9649a9 | j_mayer | case 0x3D: |
| 2315 | 4c9649a9 | j_mayer | /* BNE */
|
| 2316 | 9c29504e | aurel32 | gen_bcond(ctx, TCG_COND_NE, ra, disp16, 0);
|
| 2317 | 4c9649a9 | j_mayer | ret = 1;
|
| 2318 | 4c9649a9 | j_mayer | break;
|
| 2319 | 4c9649a9 | j_mayer | case 0x3E: |
| 2320 | 4c9649a9 | j_mayer | /* BGE */
|
| 2321 | 9c29504e | aurel32 | gen_bcond(ctx, TCG_COND_GE, ra, disp16, 0);
|
| 2322 | 4c9649a9 | j_mayer | ret = 1;
|
| 2323 | 4c9649a9 | j_mayer | break;
|
| 2324 | 4c9649a9 | j_mayer | case 0x3F: |
| 2325 | 4c9649a9 | j_mayer | /* BGT */
|
| 2326 | 9c29504e | aurel32 | gen_bcond(ctx, TCG_COND_GT, ra, disp16, 0);
|
| 2327 | 4c9649a9 | j_mayer | ret = 1;
|
| 2328 | 4c9649a9 | j_mayer | break;
|
| 2329 | 4c9649a9 | j_mayer | invalid_opc:
|
| 2330 | 4c9649a9 | j_mayer | gen_invalid(ctx); |
| 2331 | 4c9649a9 | j_mayer | ret = 3;
|
| 2332 | 4c9649a9 | j_mayer | break;
|
| 2333 | 4c9649a9 | j_mayer | } |
| 2334 | 4c9649a9 | j_mayer | |
| 2335 | 4c9649a9 | j_mayer | return ret;
|
| 2336 | 4c9649a9 | j_mayer | } |
| 2337 | 4c9649a9 | j_mayer | |
| 2338 | 2cfc5f17 | ths | static always_inline void gen_intermediate_code_internal (CPUState *env, |
| 2339 | 2cfc5f17 | ths | TranslationBlock *tb, |
| 2340 | 2cfc5f17 | ths | int search_pc)
|
| 2341 | 4c9649a9 | j_mayer | {
|
| 2342 | 4c9649a9 | j_mayer | #if defined ALPHA_DEBUG_DISAS
|
| 2343 | 4c9649a9 | j_mayer | static int insn_count; |
| 2344 | 4c9649a9 | j_mayer | #endif
|
| 2345 | 4c9649a9 | j_mayer | DisasContext ctx, *ctxp = &ctx; |
| 2346 | 4c9649a9 | j_mayer | target_ulong pc_start; |
| 2347 | 4c9649a9 | j_mayer | uint32_t insn; |
| 2348 | 4c9649a9 | j_mayer | uint16_t *gen_opc_end; |
| 2349 | a1d1bb31 | aliguori | CPUBreakpoint *bp; |
| 2350 | 4c9649a9 | j_mayer | int j, lj = -1; |
| 2351 | 4c9649a9 | j_mayer | int ret;
|
| 2352 | 2e70f6ef | pbrook | int num_insns;
|
| 2353 | 2e70f6ef | pbrook | int max_insns;
|
| 2354 | 4c9649a9 | j_mayer | |
| 2355 | 4c9649a9 | j_mayer | pc_start = tb->pc; |
| 2356 | 4c9649a9 | j_mayer | gen_opc_end = gen_opc_buf + OPC_MAX_SIZE; |
| 2357 | 4c9649a9 | j_mayer | ctx.pc = pc_start; |
| 2358 | 4c9649a9 | j_mayer | ctx.amask = env->amask; |
| 2359 | 4c9649a9 | j_mayer | #if defined (CONFIG_USER_ONLY)
|
| 2360 | 4c9649a9 | j_mayer | ctx.mem_idx = 0;
|
| 2361 | 4c9649a9 | j_mayer | #else
|
| 2362 | 4c9649a9 | j_mayer | ctx.mem_idx = ((env->ps >> 3) & 3); |
| 2363 | 4c9649a9 | j_mayer | ctx.pal_mode = env->ipr[IPR_EXC_ADDR] & 1;
|
| 2364 | 4c9649a9 | j_mayer | #endif
|
| 2365 | 2e70f6ef | pbrook | num_insns = 0;
|
| 2366 | 2e70f6ef | pbrook | max_insns = tb->cflags & CF_COUNT_MASK; |
| 2367 | 2e70f6ef | pbrook | if (max_insns == 0) |
| 2368 | 2e70f6ef | pbrook | max_insns = CF_COUNT_MASK; |
| 2369 | 2e70f6ef | pbrook | |
| 2370 | 2e70f6ef | pbrook | gen_icount_start(); |
| 2371 | 4c9649a9 | j_mayer | for (ret = 0; ret == 0;) { |
| 2372 | c0ce998e | aliguori | if (unlikely(!TAILQ_EMPTY(&env->breakpoints))) {
|
| 2373 | c0ce998e | aliguori | TAILQ_FOREACH(bp, &env->breakpoints, entry) {
|
| 2374 | a1d1bb31 | aliguori | if (bp->pc == ctx.pc) {
|
| 2375 | 4c9649a9 | j_mayer | gen_excp(&ctx, EXCP_DEBUG, 0);
|
| 2376 | 4c9649a9 | j_mayer | break;
|
| 2377 | 4c9649a9 | j_mayer | } |
| 2378 | 4c9649a9 | j_mayer | } |
| 2379 | 4c9649a9 | j_mayer | } |
| 2380 | 4c9649a9 | j_mayer | if (search_pc) {
|
| 2381 | 4c9649a9 | j_mayer | j = gen_opc_ptr - gen_opc_buf; |
| 2382 | 4c9649a9 | j_mayer | if (lj < j) {
|
| 2383 | 4c9649a9 | j_mayer | lj++; |
| 2384 | 4c9649a9 | j_mayer | while (lj < j)
|
| 2385 | 4c9649a9 | j_mayer | gen_opc_instr_start[lj++] = 0;
|
| 2386 | 4c9649a9 | j_mayer | gen_opc_pc[lj] = ctx.pc; |
| 2387 | 4c9649a9 | j_mayer | gen_opc_instr_start[lj] = 1;
|
| 2388 | 2e70f6ef | pbrook | gen_opc_icount[lj] = num_insns; |
| 2389 | 4c9649a9 | j_mayer | } |
| 2390 | 4c9649a9 | j_mayer | } |
| 2391 | 2e70f6ef | pbrook | if (num_insns + 1 == max_insns && (tb->cflags & CF_LAST_IO)) |
| 2392 | 2e70f6ef | pbrook | gen_io_start(); |
| 2393 | 4c9649a9 | j_mayer | #if defined ALPHA_DEBUG_DISAS
|
| 2394 | 4c9649a9 | j_mayer | insn_count++; |
| 2395 | d12d51d5 | aliguori | LOG_DISAS("pc " TARGET_FMT_lx " mem_idx %d\n", |
| 2396 | d12d51d5 | aliguori | ctx.pc, ctx.mem_idx); |
| 2397 | 4c9649a9 | j_mayer | #endif
|
| 2398 | 4c9649a9 | j_mayer | insn = ldl_code(ctx.pc); |
| 2399 | 4c9649a9 | j_mayer | #if defined ALPHA_DEBUG_DISAS
|
| 2400 | 4c9649a9 | j_mayer | insn_count++; |
| 2401 | d12d51d5 | aliguori | LOG_DISAS("opcode %08x %d\n", insn, insn_count);
|
| 2402 | 4c9649a9 | j_mayer | #endif
|
| 2403 | 2e70f6ef | pbrook | num_insns++; |
| 2404 | 4c9649a9 | j_mayer | ctx.pc += 4;
|
| 2405 | 4c9649a9 | j_mayer | ret = translate_one(ctxp, insn); |
| 2406 | 4c9649a9 | j_mayer | if (ret != 0) |
| 2407 | 4c9649a9 | j_mayer | break;
|
| 2408 | 4c9649a9 | j_mayer | /* if we reach a page boundary or are single stepping, stop
|
| 2409 | 4c9649a9 | j_mayer | * generation
|
| 2410 | 4c9649a9 | j_mayer | */
|
| 2411 | 4c9649a9 | j_mayer | if (((ctx.pc & (TARGET_PAGE_SIZE - 1)) == 0) || |
| 2412 | 2e70f6ef | pbrook | num_insns >= max_insns) {
|
| 2413 | 4c9649a9 | j_mayer | break;
|
| 2414 | 4c9649a9 | j_mayer | } |
| 2415 | 19bf517b | aurel32 | |
| 2416 | 19bf517b | aurel32 | if (env->singlestep_enabled) {
|
| 2417 | 19bf517b | aurel32 | gen_excp(&ctx, EXCP_DEBUG, 0);
|
| 2418 | 19bf517b | aurel32 | break;
|
| 2419 | 19bf517b | aurel32 | } |
| 2420 | 19bf517b | aurel32 | |
| 2421 | 4c9649a9 | j_mayer | #if defined (DO_SINGLE_STEP)
|
| 2422 | 4c9649a9 | j_mayer | break;
|
| 2423 | 4c9649a9 | j_mayer | #endif
|
| 2424 | 4c9649a9 | j_mayer | } |
| 2425 | 4c9649a9 | j_mayer | if (ret != 1 && ret != 3) { |
| 2426 | 496cb5b9 | aurel32 | tcg_gen_movi_i64(cpu_pc, ctx.pc); |
| 2427 | 4c9649a9 | j_mayer | } |
| 2428 | 4c9649a9 | j_mayer | #if defined (DO_TB_FLUSH)
|
| 2429 | a7812ae4 | pbrook | gen_helper_tb_flush(); |
| 2430 | 4c9649a9 | j_mayer | #endif
|
| 2431 | 2e70f6ef | pbrook | if (tb->cflags & CF_LAST_IO)
|
| 2432 | 2e70f6ef | pbrook | gen_io_end(); |
| 2433 | 4c9649a9 | j_mayer | /* Generate the return instruction */
|
| 2434 | 57fec1fe | bellard | tcg_gen_exit_tb(0);
|
| 2435 | 2e70f6ef | pbrook | gen_icount_end(tb, num_insns); |
| 2436 | 4c9649a9 | j_mayer | *gen_opc_ptr = INDEX_op_end; |
| 2437 | 4c9649a9 | j_mayer | if (search_pc) {
|
| 2438 | 4c9649a9 | j_mayer | j = gen_opc_ptr - gen_opc_buf; |
| 2439 | 4c9649a9 | j_mayer | lj++; |
| 2440 | 4c9649a9 | j_mayer | while (lj <= j)
|
| 2441 | 4c9649a9 | j_mayer | gen_opc_instr_start[lj++] = 0;
|
| 2442 | 4c9649a9 | j_mayer | } else {
|
| 2443 | 4c9649a9 | j_mayer | tb->size = ctx.pc - pc_start; |
| 2444 | 2e70f6ef | pbrook | tb->icount = num_insns; |
| 2445 | 4c9649a9 | j_mayer | } |
| 2446 | 4c9649a9 | j_mayer | #if defined ALPHA_DEBUG_DISAS
|
| 2447 | 4c9649a9 | j_mayer | if (loglevel & CPU_LOG_TB_CPU) {
|
| 2448 | 4c9649a9 | j_mayer | cpu_dump_state(env, logfile, fprintf, 0);
|
| 2449 | 4c9649a9 | j_mayer | } |
| 2450 | 4c9649a9 | j_mayer | if (loglevel & CPU_LOG_TB_IN_ASM) {
|
| 2451 | 4c9649a9 | j_mayer | fprintf(logfile, "IN: %s\n", lookup_symbol(pc_start));
|
| 2452 | fe2b269a | aurel32 | target_disas(logfile, pc_start, ctx.pc - pc_start, 1);
|
| 2453 | 4c9649a9 | j_mayer | fprintf(logfile, "\n");
|
| 2454 | 4c9649a9 | j_mayer | } |
| 2455 | 4c9649a9 | j_mayer | #endif
|
| 2456 | 4c9649a9 | j_mayer | } |
| 2457 | 4c9649a9 | j_mayer | |
| 2458 | 2cfc5f17 | ths | void gen_intermediate_code (CPUState *env, struct TranslationBlock *tb) |
| 2459 | 4c9649a9 | j_mayer | {
|
| 2460 | 2cfc5f17 | ths | gen_intermediate_code_internal(env, tb, 0);
|
| 2461 | 4c9649a9 | j_mayer | } |
| 2462 | 4c9649a9 | j_mayer | |
| 2463 | 2cfc5f17 | ths | void gen_intermediate_code_pc (CPUState *env, struct TranslationBlock *tb) |
| 2464 | 4c9649a9 | j_mayer | {
|
| 2465 | 2cfc5f17 | ths | gen_intermediate_code_internal(env, tb, 1);
|
| 2466 | 4c9649a9 | j_mayer | } |
| 2467 | 4c9649a9 | j_mayer | |
| 2468 | aaed909a | bellard | CPUAlphaState * cpu_alpha_init (const char *cpu_model) |
| 2469 | 4c9649a9 | j_mayer | {
|
| 2470 | 4c9649a9 | j_mayer | CPUAlphaState *env; |
| 2471 | 4c9649a9 | j_mayer | uint64_t hwpcb; |
| 2472 | 4c9649a9 | j_mayer | |
| 2473 | 4c9649a9 | j_mayer | env = qemu_mallocz(sizeof(CPUAlphaState));
|
| 2474 | 4c9649a9 | j_mayer | if (!env)
|
| 2475 | 4c9649a9 | j_mayer | return NULL; |
| 2476 | 4c9649a9 | j_mayer | cpu_exec_init(env); |
| 2477 | 2e70f6ef | pbrook | alpha_translate_init(); |
| 2478 | 4c9649a9 | j_mayer | tlb_flush(env, 1);
|
| 2479 | 4c9649a9 | j_mayer | /* XXX: should not be hardcoded */
|
| 2480 | 4c9649a9 | j_mayer | env->implver = IMPLVER_2106x; |
| 2481 | 4c9649a9 | j_mayer | env->ps = 0x1F00;
|
| 2482 | 4c9649a9 | j_mayer | #if defined (CONFIG_USER_ONLY)
|
| 2483 | 4c9649a9 | j_mayer | env->ps |= 1 << 3; |
| 2484 | 4c9649a9 | j_mayer | #endif
|
| 2485 | 4c9649a9 | j_mayer | pal_init(env); |
| 2486 | 4c9649a9 | j_mayer | /* Initialize IPR */
|
| 2487 | 4c9649a9 | j_mayer | hwpcb = env->ipr[IPR_PCBB]; |
| 2488 | 4c9649a9 | j_mayer | env->ipr[IPR_ASN] = 0;
|
| 2489 | 4c9649a9 | j_mayer | env->ipr[IPR_ASTEN] = 0;
|
| 2490 | 4c9649a9 | j_mayer | env->ipr[IPR_ASTSR] = 0;
|
| 2491 | 4c9649a9 | j_mayer | env->ipr[IPR_DATFX] = 0;
|
| 2492 | 4c9649a9 | j_mayer | /* XXX: fix this */
|
| 2493 | 4c9649a9 | j_mayer | // env->ipr[IPR_ESP] = ldq_raw(hwpcb + 8);
|
| 2494 | 4c9649a9 | j_mayer | // env->ipr[IPR_KSP] = ldq_raw(hwpcb + 0);
|
| 2495 | 4c9649a9 | j_mayer | // env->ipr[IPR_SSP] = ldq_raw(hwpcb + 16);
|
| 2496 | 4c9649a9 | j_mayer | // env->ipr[IPR_USP] = ldq_raw(hwpcb + 24);
|
| 2497 | 4c9649a9 | j_mayer | env->ipr[IPR_FEN] = 0;
|
| 2498 | 4c9649a9 | j_mayer | env->ipr[IPR_IPL] = 31;
|
| 2499 | 4c9649a9 | j_mayer | env->ipr[IPR_MCES] = 0;
|
| 2500 | 4c9649a9 | j_mayer | env->ipr[IPR_PERFMON] = 0; /* Implementation specific */ |
| 2501 | 4c9649a9 | j_mayer | // env->ipr[IPR_PTBR] = ldq_raw(hwpcb + 32);
|
| 2502 | 4c9649a9 | j_mayer | env->ipr[IPR_SISR] = 0;
|
| 2503 | 4c9649a9 | j_mayer | env->ipr[IPR_VIRBND] = -1ULL;
|
| 2504 | 4c9649a9 | j_mayer | |
| 2505 | 4c9649a9 | j_mayer | return env;
|
| 2506 | 4c9649a9 | j_mayer | } |
| 2507 | aaed909a | bellard | |
| 2508 | d2856f1a | aurel32 | void gen_pc_load(CPUState *env, TranslationBlock *tb,
|
| 2509 | d2856f1a | aurel32 | unsigned long searched_pc, int pc_pos, void *puc) |
| 2510 | d2856f1a | aurel32 | {
|
| 2511 | d2856f1a | aurel32 | env->pc = gen_opc_pc[pc_pos]; |
| 2512 | d2856f1a | aurel32 | } |