Revision d12d51d5 target-mips/translate.c
| b/target-mips/translate.c | ||
|---|---|---|
| 521 | 521 |
ctx->pc, ctx->opcode , ##args); \ |
| 522 | 522 |
} \ |
| 523 | 523 |
} while (0) |
| 524 |
#define LOG_DISAS(...) \ |
|
| 525 |
do { \
|
|
| 526 |
if (loglevel & CPU_LOG_TB_IN_ASM) \ |
|
| 527 |
fprintf(logfile, ## __VA_ARGS__); \ |
|
| 528 |
} while (0) |
|
| 524 | 529 |
#else |
| 525 | 530 |
#define MIPS_DEBUG(fmt, args...) do { } while(0)
|
| 531 |
#define LOG_DISAS(...) do { } while (0)
|
|
| 526 | 532 |
#endif |
| 527 | 533 |
|
| 528 | 534 |
#define MIPS_INVAL(op) \ |
| ... | ... | |
| 758 | 764 |
|
| 759 | 765 |
static inline void save_cpu_state (DisasContext *ctx, int do_save_pc) |
| 760 | 766 |
{
|
| 761 |
#if defined MIPS_DEBUG_DISAS |
|
| 762 |
if (loglevel & CPU_LOG_TB_IN_ASM) {
|
|
| 763 |
fprintf(logfile, "hflags %08x saved %08x\n", |
|
| 764 |
ctx->hflags, ctx->saved_hflags); |
|
| 765 |
} |
|
| 766 |
#endif |
|
| 767 |
LOG_DISAS("hflags %08x saved %08x\n", ctx->hflags, ctx->saved_hflags);
|
|
| 767 | 768 |
if (do_save_pc && ctx->pc != ctx->saved_pc) {
|
| 768 | 769 |
gen_save_pc(ctx->pc); |
| 769 | 770 |
ctx->saved_pc = ctx->pc; |
| ... | ... | |
| 2314 | 2315 |
|
| 2315 | 2316 |
if (ctx->hflags & MIPS_HFLAG_BMASK) {
|
| 2316 | 2317 |
#ifdef MIPS_DEBUG_DISAS |
| 2317 |
if (loglevel & CPU_LOG_TB_IN_ASM) {
|
|
| 2318 |
fprintf(logfile, |
|
| 2319 |
"Branch in delay slot at PC 0x" TARGET_FMT_lx "\n", |
|
| 2320 |
ctx->pc); |
|
| 2321 |
} |
|
| 2318 |
LOG_DISAS("Branch in delay slot at PC 0x" TARGET_FMT_lx "\n", ctx->pc);
|
|
| 2322 | 2319 |
#endif |
| 2323 | 2320 |
generate_exception(ctx, EXCP_RI); |
| 2324 | 2321 |
goto out; |
| ... | ... | |
| 3295 | 3292 |
default: |
| 3296 | 3293 |
goto die; |
| 3297 | 3294 |
} |
| 3298 |
#if defined MIPS_DEBUG_DISAS |
|
| 3299 |
if (loglevel & CPU_LOG_TB_IN_ASM) {
|
|
| 3300 |
fprintf(logfile, "mfc0 %s (reg %d sel %d)\n", |
|
| 3301 |
rn, reg, sel); |
|
| 3302 |
} |
|
| 3303 |
#endif |
|
| 3295 |
LOG_DISAS("mfc0 %s (reg %d sel %d)\n", rn, reg, sel);
|
|
| 3304 | 3296 |
return; |
| 3305 | 3297 |
|
| 3306 | 3298 |
die: |
| 3307 |
#if defined MIPS_DEBUG_DISAS |
|
| 3308 |
if (loglevel & CPU_LOG_TB_IN_ASM) {
|
|
| 3309 |
fprintf(logfile, "mfc0 %s (reg %d sel %d)\n", |
|
| 3310 |
rn, reg, sel); |
|
| 3311 |
} |
|
| 3312 |
#endif |
|
| 3299 |
LOG_DISAS("mfc0 %s (reg %d sel %d)\n", rn, reg, sel);
|
|
| 3313 | 3300 |
generate_exception(ctx, EXCP_RI); |
| 3314 | 3301 |
} |
| 3315 | 3302 |
|
| ... | ... | |
| 3899 | 3886 |
default: |
| 3900 | 3887 |
goto die; |
| 3901 | 3888 |
} |
| 3902 |
#if defined MIPS_DEBUG_DISAS |
|
| 3903 |
if (loglevel & CPU_LOG_TB_IN_ASM) {
|
|
| 3904 |
fprintf(logfile, "mtc0 %s (reg %d sel %d)\n", |
|
| 3905 |
rn, reg, sel); |
|
| 3906 |
} |
|
| 3907 |
#endif |
|
| 3889 |
LOG_DISAS("mtc0 %s (reg %d sel %d)\n", rn, reg, sel);
|
|
| 3908 | 3890 |
/* For simplicity assume that all writes can cause interrupts. */ |
| 3909 | 3891 |
if (use_icount) {
|
| 3910 | 3892 |
gen_io_end(); |
| ... | ... | |
| 3913 | 3895 |
return; |
| 3914 | 3896 |
|
| 3915 | 3897 |
die: |
| 3916 |
#if defined MIPS_DEBUG_DISAS |
|
| 3917 |
if (loglevel & CPU_LOG_TB_IN_ASM) {
|
|
| 3918 |
fprintf(logfile, "mtc0 %s (reg %d sel %d)\n", |
|
| 3919 |
rn, reg, sel); |
|
| 3920 |
} |
|
| 3921 |
#endif |
|
| 3898 |
LOG_DISAS("mtc0 %s (reg %d sel %d)\n", rn, reg, sel);
|
|
| 3922 | 3899 |
generate_exception(ctx, EXCP_RI); |
| 3923 | 3900 |
} |
| 3924 | 3901 |
|
| ... | ... | |
| 4481 | 4458 |
default: |
| 4482 | 4459 |
goto die; |
| 4483 | 4460 |
} |
| 4484 |
#if defined MIPS_DEBUG_DISAS |
|
| 4485 |
if (loglevel & CPU_LOG_TB_IN_ASM) {
|
|
| 4486 |
fprintf(logfile, "dmfc0 %s (reg %d sel %d)\n", |
|
| 4487 |
rn, reg, sel); |
|
| 4488 |
} |
|
| 4489 |
#endif |
|
| 4461 |
LOG_DISAS("dmfc0 %s (reg %d sel %d)\n", rn, reg, sel);
|
|
| 4490 | 4462 |
return; |
| 4491 | 4463 |
|
| 4492 | 4464 |
die: |
| 4493 |
#if defined MIPS_DEBUG_DISAS |
|
| 4494 |
if (loglevel & CPU_LOG_TB_IN_ASM) {
|
|
| 4495 |
fprintf(logfile, "dmfc0 %s (reg %d sel %d)\n", |
|
| 4496 |
rn, reg, sel); |
|
| 4497 |
} |
|
| 4498 |
#endif |
|
| 4465 |
LOG_DISAS("dmfc0 %s (reg %d sel %d)\n", rn, reg, sel);
|
|
| 4499 | 4466 |
generate_exception(ctx, EXCP_RI); |
| 4500 | 4467 |
} |
| 4501 | 4468 |
|
| ... | ... | |
| 5072 | 5039 |
default: |
| 5073 | 5040 |
goto die; |
| 5074 | 5041 |
} |
| 5075 |
#if defined MIPS_DEBUG_DISAS |
|
| 5076 |
if (loglevel & CPU_LOG_TB_IN_ASM) {
|
|
| 5077 |
fprintf(logfile, "dmtc0 %s (reg %d sel %d)\n", |
|
| 5078 |
rn, reg, sel); |
|
| 5079 |
} |
|
| 5080 |
#endif |
|
| 5042 |
LOG_DISAS("dmtc0 %s (reg %d sel %d)\n", rn, reg, sel);
|
|
| 5081 | 5043 |
/* For simplicity assume that all writes can cause interrupts. */ |
| 5082 | 5044 |
if (use_icount) {
|
| 5083 | 5045 |
gen_io_end(); |
| ... | ... | |
| 5086 | 5048 |
return; |
| 5087 | 5049 |
|
| 5088 | 5050 |
die: |
| 5089 |
#if defined MIPS_DEBUG_DISAS |
|
| 5090 |
if (loglevel & CPU_LOG_TB_IN_ASM) {
|
|
| 5091 |
fprintf(logfile, "dmtc0 %s (reg %d sel %d)\n", |
|
| 5092 |
rn, reg, sel); |
|
| 5093 |
} |
|
| 5094 |
#endif |
|
| 5051 |
LOG_DISAS("dmtc0 %s (reg %d sel %d)\n", rn, reg, sel);
|
|
| 5095 | 5052 |
generate_exception(ctx, EXCP_RI); |
| 5096 | 5053 |
} |
| 5097 | 5054 |
#endif /* TARGET_MIPS64 */ |
| ... | ... | |
| 5249 | 5206 |
default: |
| 5250 | 5207 |
goto die; |
| 5251 | 5208 |
} |
| 5252 |
#if defined MIPS_DEBUG_DISAS |
|
| 5253 |
if (loglevel & CPU_LOG_TB_IN_ASM) {
|
|
| 5254 |
fprintf(logfile, "mftr (reg %d u %d sel %d h %d)\n", |
|
| 5255 |
rt, u, sel, h); |
|
| 5256 |
} |
|
| 5257 |
#endif |
|
| 5209 |
LOG_DISAS("mftr (reg %d u %d sel %d h %d)\n", rt, u, sel, h);
|
|
| 5258 | 5210 |
gen_store_gpr(t0, rd); |
| 5259 | 5211 |
tcg_temp_free(t0); |
| 5260 | 5212 |
return; |
| 5261 | 5213 |
|
| 5262 | 5214 |
die: |
| 5263 | 5215 |
tcg_temp_free(t0); |
| 5264 |
#if defined MIPS_DEBUG_DISAS |
|
| 5265 |
if (loglevel & CPU_LOG_TB_IN_ASM) {
|
|
| 5266 |
fprintf(logfile, "mftr (reg %d u %d sel %d h %d)\n", |
|
| 5267 |
rt, u, sel, h); |
|
| 5268 |
} |
|
| 5269 |
#endif |
|
| 5216 |
LOG_DISAS("mftr (reg %d u %d sel %d h %d)\n", rt, u, sel, h);
|
|
| 5270 | 5217 |
generate_exception(ctx, EXCP_RI); |
| 5271 | 5218 |
} |
| 5272 | 5219 |
|
| ... | ... | |
| 5424 | 5371 |
default: |
| 5425 | 5372 |
goto die; |
| 5426 | 5373 |
} |
| 5427 |
#if defined MIPS_DEBUG_DISAS |
|
| 5428 |
if (loglevel & CPU_LOG_TB_IN_ASM) {
|
|
| 5429 |
fprintf(logfile, "mttr (reg %d u %d sel %d h %d)\n", |
|
| 5430 |
rd, u, sel, h); |
|
| 5431 |
} |
|
| 5432 |
#endif |
|
| 5374 |
LOG_DISAS("mttr (reg %d u %d sel %d h %d)\n", rd, u, sel, h);
|
|
| 5433 | 5375 |
tcg_temp_free(t0); |
| 5434 | 5376 |
return; |
| 5435 | 5377 |
|
| 5436 | 5378 |
die: |
| 5437 | 5379 |
tcg_temp_free(t0); |
| 5438 |
#if defined MIPS_DEBUG_DISAS |
|
| 5439 |
if (loglevel & CPU_LOG_TB_IN_ASM) {
|
|
| 5440 |
fprintf(logfile, "mttr (reg %d u %d sel %d h %d)\n", |
|
| 5441 |
rd, u, sel, h); |
|
| 5442 |
} |
|
| 5443 |
#endif |
|
| 5380 |
LOG_DISAS("mttr (reg %d u %d sel %d h %d)\n", rd, u, sel, h);
|
|
| 5444 | 5381 |
generate_exception(ctx, EXCP_RI); |
| 5445 | 5382 |
} |
| 5446 | 5383 |
|
| ... | ... | |
| 8272 | 8209 |
cpu_dump_state(env, logfile, fprintf, 0); |
| 8273 | 8210 |
} |
| 8274 | 8211 |
#endif |
| 8275 |
#ifdef MIPS_DEBUG_DISAS |
|
| 8276 |
if (loglevel & CPU_LOG_TB_IN_ASM) |
|
| 8277 |
fprintf(logfile, "\ntb %p idx %d hflags %04x\n", |
|
| 8278 |
tb, ctx.mem_idx, ctx.hflags); |
|
| 8279 |
#endif |
|
| 8212 |
LOG_DISAS("\ntb %p idx %d hflags %04x\n", tb, ctx.mem_idx, ctx.hflags);
|
|
| 8280 | 8213 |
gen_icount_start(); |
| 8281 | 8214 |
while (ctx.bstate == BS_NONE) {
|
| 8282 | 8215 |
if (unlikely(!TAILQ_EMPTY(&env->breakpoints))) {
|
| ... | ... | |
| 8364 | 8297 |
tb->icount = num_insns; |
| 8365 | 8298 |
} |
| 8366 | 8299 |
#ifdef DEBUG_DISAS |
| 8367 |
#if defined MIPS_DEBUG_DISAS |
|
| 8368 |
if (loglevel & CPU_LOG_TB_IN_ASM) |
|
| 8369 |
fprintf(logfile, "\n"); |
|
| 8370 |
#endif |
|
| 8300 |
LOG_DISAS("\n");
|
|
| 8371 | 8301 |
if (loglevel & CPU_LOG_TB_IN_ASM) {
|
| 8372 | 8302 |
fprintf(logfile, "IN: %s\n", lookup_symbol(pc_start)); |
| 8373 | 8303 |
target_disas(logfile, pc_start, ctx.pc - pc_start, 0); |
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