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1 | 02d74341 | cmchao | /*
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2 | 02d74341 | cmchao | * TI OMAP processors UART emulation.
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3 | 02d74341 | cmchao | *
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4 | 02d74341 | cmchao | * Copyright (C) 2006-2008 Andrzej Zaborowski <balrog@zabor.org>
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5 | 02d74341 | cmchao | * Copyright (C) 2007-2009 Nokia Corporation
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6 | 02d74341 | cmchao | *
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7 | 02d74341 | cmchao | * This program is free software; you can redistribute it and/or
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8 | 02d74341 | cmchao | * modify it under the terms of the GNU General Public License as
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9 | 02d74341 | cmchao | * published by the Free Software Foundation; either version 2 or
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10 | 02d74341 | cmchao | * (at your option) version 3 of the License.
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11 | 02d74341 | cmchao | *
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12 | 02d74341 | cmchao | * This program is distributed in the hope that it will be useful,
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13 | 02d74341 | cmchao | * but WITHOUT ANY WARRANTY; without even the implied warranty of
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14 | 02d74341 | cmchao | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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15 | 02d74341 | cmchao | * GNU General Public License for more details.
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16 | 02d74341 | cmchao | *
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17 | 02d74341 | cmchao | * You should have received a copy of the GNU General Public License along
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18 | 02d74341 | cmchao | * with this program; if not, see <http://www.gnu.org/licenses/>.
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19 | 02d74341 | cmchao | */
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20 | 02d74341 | cmchao | #include "qemu-char.h" |
21 | 02d74341 | cmchao | #include "hw.h" |
22 | 02d74341 | cmchao | #include "omap.h" |
23 | 02d74341 | cmchao | /* We use pc-style serial ports. */
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24 | 02d74341 | cmchao | #include "pc.h" |
25 | 02d74341 | cmchao | |
26 | 02d74341 | cmchao | /* UARTs */
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27 | 02d74341 | cmchao | struct omap_uart_s {
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28 | 02d74341 | cmchao | target_phys_addr_t base; |
29 | 02d74341 | cmchao | SerialState *serial; /* TODO */
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30 | 02d74341 | cmchao | struct omap_target_agent_s *ta;
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31 | 02d74341 | cmchao | omap_clk fclk; |
32 | 02d74341 | cmchao | qemu_irq irq; |
33 | 02d74341 | cmchao | |
34 | 02d74341 | cmchao | uint8_t eblr; |
35 | 02d74341 | cmchao | uint8_t syscontrol; |
36 | 02d74341 | cmchao | uint8_t wkup; |
37 | 02d74341 | cmchao | uint8_t cfps; |
38 | 02d74341 | cmchao | uint8_t mdr[2];
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39 | 02d74341 | cmchao | uint8_t scr; |
40 | 02d74341 | cmchao | uint8_t clksel; |
41 | 02d74341 | cmchao | }; |
42 | 02d74341 | cmchao | |
43 | 02d74341 | cmchao | void omap_uart_reset(struct omap_uart_s *s) |
44 | 02d74341 | cmchao | { |
45 | 02d74341 | cmchao | s->eblr = 0x00;
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46 | 02d74341 | cmchao | s->syscontrol = 0;
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47 | 02d74341 | cmchao | s->wkup = 0x3f;
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48 | 02d74341 | cmchao | s->cfps = 0x69;
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49 | 02d74341 | cmchao | s->clksel = 0;
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50 | 02d74341 | cmchao | } |
51 | 02d74341 | cmchao | |
52 | 02d74341 | cmchao | struct omap_uart_s *omap_uart_init(target_phys_addr_t base,
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53 | 02d74341 | cmchao | qemu_irq irq, omap_clk fclk, omap_clk iclk, |
54 | 6a8aabd3 | Stefan Weil | qemu_irq txdma, qemu_irq rxdma, |
55 | 6a8aabd3 | Stefan Weil | const char *label, CharDriverState *chr) |
56 | 02d74341 | cmchao | { |
57 | 02d74341 | cmchao | struct omap_uart_s *s = (struct omap_uart_s *) |
58 | 02d74341 | cmchao | qemu_mallocz(sizeof(struct omap_uart_s)); |
59 | 02d74341 | cmchao | |
60 | 02d74341 | cmchao | s->base = base; |
61 | 02d74341 | cmchao | s->fclk = fclk; |
62 | 02d74341 | cmchao | s->irq = irq; |
63 | 02d74341 | cmchao | #ifdef TARGET_WORDS_BIGENDIAN
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64 | 02d74341 | cmchao | s->serial = serial_mm_init(base, 2, irq, omap_clk_getrate(fclk)/16, |
65 | 6a8aabd3 | Stefan Weil | chr ?: qemu_chr_open(label, "null", NULL), 1, |
66 | 02d74341 | cmchao | 1);
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67 | 02d74341 | cmchao | #else
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68 | 02d74341 | cmchao | s->serial = serial_mm_init(base, 2, irq, omap_clk_getrate(fclk)/16, |
69 | 6a8aabd3 | Stefan Weil | chr ?: qemu_chr_open(label, "null", NULL), 1, |
70 | 02d74341 | cmchao | 0);
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71 | 02d74341 | cmchao | #endif
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72 | 02d74341 | cmchao | return s;
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73 | 02d74341 | cmchao | } |
74 | 02d74341 | cmchao | |
75 | 02d74341 | cmchao | static uint32_t omap_uart_read(void *opaque, target_phys_addr_t addr) |
76 | 02d74341 | cmchao | { |
77 | 02d74341 | cmchao | struct omap_uart_s *s = (struct omap_uart_s *) opaque; |
78 | 02d74341 | cmchao | |
79 | 02d74341 | cmchao | addr &= 0xff;
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80 | 02d74341 | cmchao | switch (addr) {
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81 | 02d74341 | cmchao | case 0x20: /* MDR1 */ |
82 | 02d74341 | cmchao | return s->mdr[0]; |
83 | 02d74341 | cmchao | case 0x24: /* MDR2 */ |
84 | 02d74341 | cmchao | return s->mdr[1]; |
85 | 02d74341 | cmchao | case 0x40: /* SCR */ |
86 | 02d74341 | cmchao | return s->scr;
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87 | 02d74341 | cmchao | case 0x44: /* SSR */ |
88 | 02d74341 | cmchao | return 0x0; |
89 | 02d74341 | cmchao | case 0x48: /* EBLR (OMAP2) */ |
90 | 02d74341 | cmchao | return s->eblr;
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91 | 02d74341 | cmchao | case 0x4C: /* OSC_12M_SEL (OMAP1) */ |
92 | 02d74341 | cmchao | return s->clksel;
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93 | 02d74341 | cmchao | case 0x50: /* MVR */ |
94 | 02d74341 | cmchao | return 0x30; |
95 | 02d74341 | cmchao | case 0x54: /* SYSC (OMAP2) */ |
96 | 02d74341 | cmchao | return s->syscontrol;
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97 | 02d74341 | cmchao | case 0x58: /* SYSS (OMAP2) */ |
98 | 02d74341 | cmchao | return 1; |
99 | 02d74341 | cmchao | case 0x5c: /* WER (OMAP2) */ |
100 | 02d74341 | cmchao | return s->wkup;
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101 | 02d74341 | cmchao | case 0x60: /* CFPS (OMAP2) */ |
102 | 02d74341 | cmchao | return s->cfps;
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103 | 02d74341 | cmchao | } |
104 | 02d74341 | cmchao | |
105 | 02d74341 | cmchao | OMAP_BAD_REG(addr); |
106 | 02d74341 | cmchao | return 0; |
107 | 02d74341 | cmchao | } |
108 | 02d74341 | cmchao | |
109 | 02d74341 | cmchao | static void omap_uart_write(void *opaque, target_phys_addr_t addr, |
110 | 02d74341 | cmchao | uint32_t value) |
111 | 02d74341 | cmchao | { |
112 | 02d74341 | cmchao | struct omap_uart_s *s = (struct omap_uart_s *) opaque; |
113 | 02d74341 | cmchao | |
114 | 02d74341 | cmchao | addr &= 0xff;
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115 | 02d74341 | cmchao | switch (addr) {
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116 | 02d74341 | cmchao | case 0x20: /* MDR1 */ |
117 | 02d74341 | cmchao | s->mdr[0] = value & 0x7f; |
118 | 02d74341 | cmchao | break;
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119 | 02d74341 | cmchao | case 0x24: /* MDR2 */ |
120 | 02d74341 | cmchao | s->mdr[1] = value & 0xff; |
121 | 02d74341 | cmchao | break;
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122 | 02d74341 | cmchao | case 0x40: /* SCR */ |
123 | 02d74341 | cmchao | s->scr = value & 0xff;
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124 | 02d74341 | cmchao | break;
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125 | 02d74341 | cmchao | case 0x48: /* EBLR (OMAP2) */ |
126 | 02d74341 | cmchao | s->eblr = value & 0xff;
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127 | 02d74341 | cmchao | break;
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128 | 02d74341 | cmchao | case 0x4C: /* OSC_12M_SEL (OMAP1) */ |
129 | 02d74341 | cmchao | s->clksel = value & 1;
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130 | 02d74341 | cmchao | break;
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131 | 02d74341 | cmchao | case 0x44: /* SSR */ |
132 | 02d74341 | cmchao | case 0x50: /* MVR */ |
133 | 02d74341 | cmchao | case 0x58: /* SYSS (OMAP2) */ |
134 | 02d74341 | cmchao | OMAP_RO_REG(addr); |
135 | 02d74341 | cmchao | break;
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136 | 02d74341 | cmchao | case 0x54: /* SYSC (OMAP2) */ |
137 | 02d74341 | cmchao | s->syscontrol = value & 0x1d;
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138 | 02d74341 | cmchao | if (value & 2) |
139 | 02d74341 | cmchao | omap_uart_reset(s); |
140 | 02d74341 | cmchao | break;
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141 | 02d74341 | cmchao | case 0x5c: /* WER (OMAP2) */ |
142 | 02d74341 | cmchao | s->wkup = value & 0x7f;
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143 | 02d74341 | cmchao | break;
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144 | 02d74341 | cmchao | case 0x60: /* CFPS (OMAP2) */ |
145 | 02d74341 | cmchao | s->cfps = value & 0xff;
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146 | 02d74341 | cmchao | break;
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147 | 02d74341 | cmchao | default:
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148 | 02d74341 | cmchao | OMAP_BAD_REG(addr); |
149 | 02d74341 | cmchao | } |
150 | 02d74341 | cmchao | } |
151 | 02d74341 | cmchao | |
152 | 02d74341 | cmchao | static CPUReadMemoryFunc * const omap_uart_readfn[] = { |
153 | 02d74341 | cmchao | omap_uart_read, |
154 | 02d74341 | cmchao | omap_uart_read, |
155 | 02d74341 | cmchao | omap_badwidth_read8, |
156 | 02d74341 | cmchao | }; |
157 | 02d74341 | cmchao | |
158 | 02d74341 | cmchao | static CPUWriteMemoryFunc * const omap_uart_writefn[] = { |
159 | 02d74341 | cmchao | omap_uart_write, |
160 | 02d74341 | cmchao | omap_uart_write, |
161 | 02d74341 | cmchao | omap_badwidth_write8, |
162 | 02d74341 | cmchao | }; |
163 | 02d74341 | cmchao | |
164 | 02d74341 | cmchao | struct omap_uart_s *omap2_uart_init(struct omap_target_agent_s *ta, |
165 | 02d74341 | cmchao | qemu_irq irq, omap_clk fclk, omap_clk iclk, |
166 | 6a8aabd3 | Stefan Weil | qemu_irq txdma, qemu_irq rxdma, |
167 | 6a8aabd3 | Stefan Weil | const char *label, CharDriverState *chr) |
168 | 02d74341 | cmchao | { |
169 | 02d74341 | cmchao | target_phys_addr_t base = omap_l4_attach(ta, 0, 0); |
170 | 02d74341 | cmchao | struct omap_uart_s *s = omap_uart_init(base, irq,
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171 | 6a8aabd3 | Stefan Weil | fclk, iclk, txdma, rxdma, label, chr); |
172 | 02d74341 | cmchao | int iomemtype = cpu_register_io_memory(omap_uart_readfn,
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173 | 2507c12a | Alexander Graf | omap_uart_writefn, s, DEVICE_NATIVE_ENDIAN); |
174 | 02d74341 | cmchao | |
175 | 02d74341 | cmchao | s->ta = ta; |
176 | 02d74341 | cmchao | |
177 | 02d74341 | cmchao | cpu_register_physical_memory(base + 0x20, 0x100, iomemtype); |
178 | 02d74341 | cmchao | |
179 | 02d74341 | cmchao | return s;
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180 | 02d74341 | cmchao | } |
181 | 02d74341 | cmchao | |
182 | 02d74341 | cmchao | void omap_uart_attach(struct omap_uart_s *s, CharDriverState *chr) |
183 | 02d74341 | cmchao | { |
184 | 02d74341 | cmchao | /* TODO: Should reuse or destroy current s->serial */
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185 | 02d74341 | cmchao | #ifdef TARGET_WORDS_BIGENDIAN
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186 | 02d74341 | cmchao | s->serial = serial_mm_init(s->base, 2, s->irq,
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187 | 02d74341 | cmchao | omap_clk_getrate(s->fclk) / 16,
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188 | 02d74341 | cmchao | chr ?: qemu_chr_open("null", "null", NULL), 1, |
189 | 02d74341 | cmchao | 1);
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190 | 02d74341 | cmchao | #else
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191 | 02d74341 | cmchao | s->serial = serial_mm_init(s->base, 2, s->irq,
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192 | 02d74341 | cmchao | omap_clk_getrate(s->fclk) / 16,
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193 | 02d74341 | cmchao | chr ?: qemu_chr_open("null", "null", NULL), 1, |
194 | 02d74341 | cmchao | 0);
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195 | 02d74341 | cmchao | #endif
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196 | 02d74341 | cmchao | } |