root / target-ppc / mem_helper.c @ d1a0cf73
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1 | 9a64fbe4 | bellard | /*
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2 | 2f5a189c | Blue Swirl | * PowerPC memory access emulation helpers for QEMU.
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3 | 5fafdf24 | ths | *
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4 | 76a66253 | j_mayer | * Copyright (c) 2003-2007 Jocelyn Mayer
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5 | 9a64fbe4 | bellard | *
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6 | 9a64fbe4 | bellard | * This library is free software; you can redistribute it and/or
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7 | 9a64fbe4 | bellard | * modify it under the terms of the GNU Lesser General Public
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8 | 9a64fbe4 | bellard | * License as published by the Free Software Foundation; either
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9 | 9a64fbe4 | bellard | * version 2 of the License, or (at your option) any later version.
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10 | 9a64fbe4 | bellard | *
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11 | 9a64fbe4 | bellard | * This library is distributed in the hope that it will be useful,
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12 | 9a64fbe4 | bellard | * but WITHOUT ANY WARRANTY; without even the implied warranty of
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13 | 9a64fbe4 | bellard | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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14 | 9a64fbe4 | bellard | * Lesser General Public License for more details.
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15 | 9a64fbe4 | bellard | *
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16 | 9a64fbe4 | bellard | * You should have received a copy of the GNU Lesser General Public
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17 | 8167ee88 | Blue Swirl | * License along with this library; if not, see <http://www.gnu.org/licenses/>.
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18 | 9a64fbe4 | bellard | */
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19 | 3e457172 | Blue Swirl | #include "cpu.h" |
20 | 1de7afc9 | Paolo Bonzini | #include "qemu/host-utils.h" |
21 | a7812ae4 | pbrook | #include "helper.h" |
22 | 9a64fbe4 | bellard | |
23 | 0411a972 | j_mayer | #include "helper_regs.h" |
24 | 0487d6a8 | j_mayer | |
25 | 3e457172 | Blue Swirl | #if !defined(CONFIG_USER_ONLY)
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26 | 022c62cb | Paolo Bonzini | #include "exec/softmmu_exec.h" |
27 | 3e457172 | Blue Swirl | #endif /* !defined(CONFIG_USER_ONLY) */ |
28 | 3e457172 | Blue Swirl | |
29 | fdabc366 | bellard | //#define DEBUG_OP
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30 | d12d51d5 | aliguori | |
31 | 9a64fbe4 | bellard | /*****************************************************************************/
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32 | ff4a62cd | aurel32 | /* Memory load and stores */
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33 | ff4a62cd | aurel32 | |
34 | 2f5a189c | Blue Swirl | static inline target_ulong addr_add(CPUPPCState *env, target_ulong addr, |
35 | 2f5a189c | Blue Swirl | target_long arg) |
36 | ff4a62cd | aurel32 | { |
37 | ff4a62cd | aurel32 | #if defined(TARGET_PPC64)
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38 | e42a61f1 | Alexander Graf | if (!msr_is_64bit(env, env->msr)) {
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39 | b327c654 | Blue Swirl | return (uint32_t)(addr + arg);
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40 | b327c654 | Blue Swirl | } else
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41 | ff4a62cd | aurel32 | #endif
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42 | b327c654 | Blue Swirl | { |
43 | b327c654 | Blue Swirl | return addr + arg;
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44 | b327c654 | Blue Swirl | } |
45 | ff4a62cd | aurel32 | } |
46 | ff4a62cd | aurel32 | |
47 | 2f5a189c | Blue Swirl | void helper_lmw(CPUPPCState *env, target_ulong addr, uint32_t reg)
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48 | ff4a62cd | aurel32 | { |
49 | 76db3ba4 | aurel32 | for (; reg < 32; reg++) { |
50 | b327c654 | Blue Swirl | if (msr_le) {
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51 | 2f5a189c | Blue Swirl | env->gpr[reg] = bswap32(cpu_ldl_data(env, addr)); |
52 | b327c654 | Blue Swirl | } else {
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53 | 2f5a189c | Blue Swirl | env->gpr[reg] = cpu_ldl_data(env, addr); |
54 | b327c654 | Blue Swirl | } |
55 | 2f5a189c | Blue Swirl | addr = addr_add(env, addr, 4);
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56 | ff4a62cd | aurel32 | } |
57 | ff4a62cd | aurel32 | } |
58 | ff4a62cd | aurel32 | |
59 | 2f5a189c | Blue Swirl | void helper_stmw(CPUPPCState *env, target_ulong addr, uint32_t reg)
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60 | ff4a62cd | aurel32 | { |
61 | 76db3ba4 | aurel32 | for (; reg < 32; reg++) { |
62 | b327c654 | Blue Swirl | if (msr_le) {
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63 | 2f5a189c | Blue Swirl | cpu_stl_data(env, addr, bswap32((uint32_t)env->gpr[reg])); |
64 | b327c654 | Blue Swirl | } else {
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65 | 2f5a189c | Blue Swirl | cpu_stl_data(env, addr, (uint32_t)env->gpr[reg]); |
66 | b327c654 | Blue Swirl | } |
67 | 2f5a189c | Blue Swirl | addr = addr_add(env, addr, 4);
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68 | ff4a62cd | aurel32 | } |
69 | ff4a62cd | aurel32 | } |
70 | ff4a62cd | aurel32 | |
71 | 2f5a189c | Blue Swirl | void helper_lsw(CPUPPCState *env, target_ulong addr, uint32_t nb, uint32_t reg)
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72 | dfbc799d | aurel32 | { |
73 | dfbc799d | aurel32 | int sh;
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74 | b327c654 | Blue Swirl | |
75 | 76db3ba4 | aurel32 | for (; nb > 3; nb -= 4) { |
76 | 2f5a189c | Blue Swirl | env->gpr[reg] = cpu_ldl_data(env, addr); |
77 | dfbc799d | aurel32 | reg = (reg + 1) % 32; |
78 | 2f5a189c | Blue Swirl | addr = addr_add(env, addr, 4);
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79 | dfbc799d | aurel32 | } |
80 | dfbc799d | aurel32 | if (unlikely(nb > 0)) { |
81 | dfbc799d | aurel32 | env->gpr[reg] = 0;
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82 | 76db3ba4 | aurel32 | for (sh = 24; nb > 0; nb--, sh -= 8) { |
83 | 2f5a189c | Blue Swirl | env->gpr[reg] |= cpu_ldub_data(env, addr) << sh; |
84 | 2f5a189c | Blue Swirl | addr = addr_add(env, addr, 1);
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85 | dfbc799d | aurel32 | } |
86 | dfbc799d | aurel32 | } |
87 | dfbc799d | aurel32 | } |
88 | dfbc799d | aurel32 | /* PPC32 specification says we must generate an exception if
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89 | dfbc799d | aurel32 | * rA is in the range of registers to be loaded.
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90 | dfbc799d | aurel32 | * In an other hand, IBM says this is valid, but rA won't be loaded.
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91 | dfbc799d | aurel32 | * For now, I'll follow the spec...
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92 | dfbc799d | aurel32 | */
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93 | 2f5a189c | Blue Swirl | void helper_lswx(CPUPPCState *env, target_ulong addr, uint32_t reg,
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94 | 2f5a189c | Blue Swirl | uint32_t ra, uint32_t rb) |
95 | dfbc799d | aurel32 | { |
96 | dfbc799d | aurel32 | if (likely(xer_bc != 0)) { |
97 | dfbc799d | aurel32 | if (unlikely((ra != 0 && reg < ra && (reg + xer_bc) > ra) || |
98 | dfbc799d | aurel32 | (reg < rb && (reg + xer_bc) > rb))) { |
99 | e5f17ac6 | Blue Swirl | helper_raise_exception_err(env, POWERPC_EXCP_PROGRAM, |
100 | e06fcd75 | aurel32 | POWERPC_EXCP_INVAL | |
101 | e06fcd75 | aurel32 | POWERPC_EXCP_INVAL_LSWX); |
102 | dfbc799d | aurel32 | } else {
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103 | 2f5a189c | Blue Swirl | helper_lsw(env, addr, xer_bc, reg); |
104 | dfbc799d | aurel32 | } |
105 | dfbc799d | aurel32 | } |
106 | dfbc799d | aurel32 | } |
107 | dfbc799d | aurel32 | |
108 | 2f5a189c | Blue Swirl | void helper_stsw(CPUPPCState *env, target_ulong addr, uint32_t nb,
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109 | 2f5a189c | Blue Swirl | uint32_t reg) |
110 | dfbc799d | aurel32 | { |
111 | dfbc799d | aurel32 | int sh;
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112 | b327c654 | Blue Swirl | |
113 | 76db3ba4 | aurel32 | for (; nb > 3; nb -= 4) { |
114 | 2f5a189c | Blue Swirl | cpu_stl_data(env, addr, env->gpr[reg]); |
115 | dfbc799d | aurel32 | reg = (reg + 1) % 32; |
116 | 2f5a189c | Blue Swirl | addr = addr_add(env, addr, 4);
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117 | dfbc799d | aurel32 | } |
118 | dfbc799d | aurel32 | if (unlikely(nb > 0)) { |
119 | a16b45e7 | aurel32 | for (sh = 24; nb > 0; nb--, sh -= 8) { |
120 | 2f5a189c | Blue Swirl | cpu_stb_data(env, addr, (env->gpr[reg] >> sh) & 0xFF);
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121 | 2f5a189c | Blue Swirl | addr = addr_add(env, addr, 1);
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122 | a16b45e7 | aurel32 | } |
123 | dfbc799d | aurel32 | } |
124 | dfbc799d | aurel32 | } |
125 | dfbc799d | aurel32 | |
126 | 2f5a189c | Blue Swirl | static void do_dcbz(CPUPPCState *env, target_ulong addr, int dcache_line_size) |
127 | 799a8c8d | aurel32 | { |
128 | 799a8c8d | aurel32 | int i;
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129 | b327c654 | Blue Swirl | |
130 | b327c654 | Blue Swirl | addr &= ~(dcache_line_size - 1);
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131 | b327c654 | Blue Swirl | for (i = 0; i < dcache_line_size; i += 4) { |
132 | 2f5a189c | Blue Swirl | cpu_stl_data(env, addr + i, 0);
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133 | 799a8c8d | aurel32 | } |
134 | b327c654 | Blue Swirl | if (env->reserve_addr == addr) {
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135 | 18b21a2f | Nathan Froyd | env->reserve_addr = (target_ulong)-1ULL;
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136 | b327c654 | Blue Swirl | } |
137 | 799a8c8d | aurel32 | } |
138 | 799a8c8d | aurel32 | |
139 | 8e33944f | Alexander Graf | void helper_dcbz(CPUPPCState *env, target_ulong addr, uint32_t is_dcbzl)
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140 | 799a8c8d | aurel32 | { |
141 | 8e33944f | Alexander Graf | int dcbz_size = env->dcache_line_size;
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142 | 799a8c8d | aurel32 | |
143 | 8e33944f | Alexander Graf | #if !defined(CONFIG_USER_ONLY) && defined(TARGET_PPC64)
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144 | 8e33944f | Alexander Graf | if (!is_dcbzl &&
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145 | 8e33944f | Alexander Graf | (env->excp_model == POWERPC_EXCP_970) && |
146 | 8e33944f | Alexander Graf | ((env->spr[SPR_970_HID5] >> 7) & 0x3) == 1) { |
147 | 8e33944f | Alexander Graf | dcbz_size = 32;
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148 | b327c654 | Blue Swirl | } |
149 | 8e33944f | Alexander Graf | #endif
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150 | 8e33944f | Alexander Graf | |
151 | 8e33944f | Alexander Graf | /* XXX add e500mc support */
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152 | 8e33944f | Alexander Graf | |
153 | 8e33944f | Alexander Graf | do_dcbz(env, addr, dcbz_size); |
154 | 799a8c8d | aurel32 | } |
155 | 799a8c8d | aurel32 | |
156 | 2f5a189c | Blue Swirl | void helper_icbi(CPUPPCState *env, target_ulong addr)
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157 | 37d269df | aurel32 | { |
158 | 76db3ba4 | aurel32 | addr &= ~(env->dcache_line_size - 1);
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159 | 37d269df | aurel32 | /* Invalidate one cache line :
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160 | 37d269df | aurel32 | * PowerPC specification says this is to be treated like a load
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161 | 37d269df | aurel32 | * (not a fetch) by the MMU. To be sure it will be so,
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162 | 37d269df | aurel32 | * do the load "by hand".
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163 | 37d269df | aurel32 | */
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164 | 2f5a189c | Blue Swirl | cpu_ldl_data(env, addr); |
165 | 37d269df | aurel32 | } |
166 | 37d269df | aurel32 | |
167 | b327c654 | Blue Swirl | /* XXX: to be tested */
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168 | 2f5a189c | Blue Swirl | target_ulong helper_lscbx(CPUPPCState *env, target_ulong addr, uint32_t reg, |
169 | 2f5a189c | Blue Swirl | uint32_t ra, uint32_t rb) |
170 | bdb4b689 | aurel32 | { |
171 | bdb4b689 | aurel32 | int i, c, d;
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172 | b327c654 | Blue Swirl | |
173 | bdb4b689 | aurel32 | d = 24;
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174 | bdb4b689 | aurel32 | for (i = 0; i < xer_bc; i++) { |
175 | 2f5a189c | Blue Swirl | c = cpu_ldub_data(env, addr); |
176 | 2f5a189c | Blue Swirl | addr = addr_add(env, addr, 1);
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177 | bdb4b689 | aurel32 | /* ra (if not 0) and rb are never modified */
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178 | bdb4b689 | aurel32 | if (likely(reg != rb && (ra == 0 || reg != ra))) { |
179 | bdb4b689 | aurel32 | env->gpr[reg] = (env->gpr[reg] & ~(0xFF << d)) | (c << d);
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180 | bdb4b689 | aurel32 | } |
181 | b327c654 | Blue Swirl | if (unlikely(c == xer_cmp)) {
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182 | bdb4b689 | aurel32 | break;
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183 | b327c654 | Blue Swirl | } |
184 | bdb4b689 | aurel32 | if (likely(d != 0)) { |
185 | bdb4b689 | aurel32 | d -= 8;
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186 | bdb4b689 | aurel32 | } else {
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187 | bdb4b689 | aurel32 | d = 24;
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188 | bdb4b689 | aurel32 | reg++; |
189 | bdb4b689 | aurel32 | reg = reg & 0x1F;
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190 | bdb4b689 | aurel32 | } |
191 | bdb4b689 | aurel32 | } |
192 | bdb4b689 | aurel32 | return i;
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193 | bdb4b689 | aurel32 | } |
194 | bdb4b689 | aurel32 | |
195 | ff4a62cd | aurel32 | /*****************************************************************************/
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196 | d6a46fe8 | aurel32 | /* Altivec extension helpers */
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197 | e2542fe2 | Juan Quintela | #if defined(HOST_WORDS_BIGENDIAN)
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198 | d6a46fe8 | aurel32 | #define HI_IDX 0 |
199 | d6a46fe8 | aurel32 | #define LO_IDX 1 |
200 | d6a46fe8 | aurel32 | #else
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201 | d6a46fe8 | aurel32 | #define HI_IDX 1 |
202 | d6a46fe8 | aurel32 | #define LO_IDX 0 |
203 | d6a46fe8 | aurel32 | #endif
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204 | d6a46fe8 | aurel32 | |
205 | cbfb6ae9 | aurel32 | #define LVE(name, access, swap, element) \
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206 | 2f5a189c | Blue Swirl | void helper_##name(CPUPPCState *env, ppc_avr_t *r, \ |
207 | 2f5a189c | Blue Swirl | target_ulong addr) \ |
208 | cbfb6ae9 | aurel32 | { \ |
209 | cbfb6ae9 | aurel32 | size_t n_elems = ARRAY_SIZE(r->element); \ |
210 | b327c654 | Blue Swirl | int adjust = HI_IDX*(n_elems - 1); \ |
211 | cbfb6ae9 | aurel32 | int sh = sizeof(r->element[0]) >> 1; \ |
212 | cbfb6ae9 | aurel32 | int index = (addr & 0xf) >> sh; \ |
213 | b327c654 | Blue Swirl | \ |
214 | b327c654 | Blue Swirl | if (msr_le) { \
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215 | b327c654 | Blue Swirl | r->element[LO_IDX ? index : (adjust - index)] = \ |
216 | 2f5a189c | Blue Swirl | swap(access(env, addr)); \ |
217 | b327c654 | Blue Swirl | } else { \
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218 | b327c654 | Blue Swirl | r->element[LO_IDX ? index : (adjust - index)] = \ |
219 | 2f5a189c | Blue Swirl | access(env, addr); \ |
220 | b327c654 | Blue Swirl | } \ |
221 | cbfb6ae9 | aurel32 | } |
222 | cbfb6ae9 | aurel32 | #define I(x) (x)
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223 | 2f5a189c | Blue Swirl | LVE(lvebx, cpu_ldub_data, I, u8) |
224 | 2f5a189c | Blue Swirl | LVE(lvehx, cpu_lduw_data, bswap16, u16) |
225 | 2f5a189c | Blue Swirl | LVE(lvewx, cpu_ldl_data, bswap32, u32) |
226 | cbfb6ae9 | aurel32 | #undef I
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227 | cbfb6ae9 | aurel32 | #undef LVE
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228 | cbfb6ae9 | aurel32 | |
229 | b327c654 | Blue Swirl | #define STVE(name, access, swap, element) \
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230 | 2f5a189c | Blue Swirl | void helper_##name(CPUPPCState *env, ppc_avr_t *r, \ |
231 | 2f5a189c | Blue Swirl | target_ulong addr) \ |
232 | b327c654 | Blue Swirl | { \ |
233 | b327c654 | Blue Swirl | size_t n_elems = ARRAY_SIZE(r->element); \ |
234 | b327c654 | Blue Swirl | int adjust = HI_IDX * (n_elems - 1); \ |
235 | b327c654 | Blue Swirl | int sh = sizeof(r->element[0]) >> 1; \ |
236 | b327c654 | Blue Swirl | int index = (addr & 0xf) >> sh; \ |
237 | b327c654 | Blue Swirl | \ |
238 | b327c654 | Blue Swirl | if (msr_le) { \
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239 | 2f5a189c | Blue Swirl | access(env, addr, swap(r->element[LO_IDX ? index : \ |
240 | 2f5a189c | Blue Swirl | (adjust - index)])); \ |
241 | cbfb6ae9 | aurel32 | } else { \
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242 | 2f5a189c | Blue Swirl | access(env, addr, r->element[LO_IDX ? index : \ |
243 | 2f5a189c | Blue Swirl | (adjust - index)]); \ |
244 | cbfb6ae9 | aurel32 | } \ |
245 | cbfb6ae9 | aurel32 | } |
246 | cbfb6ae9 | aurel32 | #define I(x) (x)
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247 | 2f5a189c | Blue Swirl | STVE(stvebx, cpu_stb_data, I, u8) |
248 | 2f5a189c | Blue Swirl | STVE(stvehx, cpu_stw_data, bswap16, u16) |
249 | 2f5a189c | Blue Swirl | STVE(stvewx, cpu_stl_data, bswap32, u32) |
250 | cbfb6ae9 | aurel32 | #undef I
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251 | cbfb6ae9 | aurel32 | #undef LVE
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252 | cbfb6ae9 | aurel32 | |
253 | d6a46fe8 | aurel32 | #undef HI_IDX
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254 | d6a46fe8 | aurel32 | #undef LO_IDX
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255 | d6a46fe8 | aurel32 | |
256 | d6a46fe8 | aurel32 | /*****************************************************************************/
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257 | fdabc366 | bellard | /* Softmmu support */
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258 | b327c654 | Blue Swirl | #if !defined(CONFIG_USER_ONLY)
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259 | fdabc366 | bellard | |
260 | fdabc366 | bellard | #define MMUSUFFIX _mmu
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261 | fdabc366 | bellard | |
262 | fdabc366 | bellard | #define SHIFT 0 |
263 | 022c62cb | Paolo Bonzini | #include "exec/softmmu_template.h" |
264 | fdabc366 | bellard | |
265 | fdabc366 | bellard | #define SHIFT 1 |
266 | 022c62cb | Paolo Bonzini | #include "exec/softmmu_template.h" |
267 | fdabc366 | bellard | |
268 | fdabc366 | bellard | #define SHIFT 2 |
269 | 022c62cb | Paolo Bonzini | #include "exec/softmmu_template.h" |
270 | fdabc366 | bellard | |
271 | fdabc366 | bellard | #define SHIFT 3 |
272 | 022c62cb | Paolo Bonzini | #include "exec/softmmu_template.h" |
273 | fdabc366 | bellard | |
274 | fdabc366 | bellard | /* try to fill the TLB and return an exception if error. If retaddr is
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275 | fdabc366 | bellard | NULL, it means that the function was called in C code (i.e. not
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276 | fdabc366 | bellard | from generated code or from helper.c) */
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277 | fdabc366 | bellard | /* XXX: fix it to restore all registers */
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278 | 2f5a189c | Blue Swirl | void tlb_fill(CPUPPCState *env, target_ulong addr, int is_write, int mmu_idx, |
279 | 20503968 | Blue Swirl | uintptr_t retaddr) |
280 | fdabc366 | bellard | { |
281 | fdabc366 | bellard | int ret;
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282 | fdabc366 | bellard | |
283 | 97b348e7 | Blue Swirl | ret = cpu_ppc_handle_mmu_fault(env, addr, is_write, mmu_idx); |
284 | 76a66253 | j_mayer | if (unlikely(ret != 0)) { |
285 | fdabc366 | bellard | if (likely(retaddr)) {
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286 | fdabc366 | bellard | /* now we have a real cpu fault */
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287 | a8a826a3 | Blue Swirl | cpu_restore_state(env, retaddr); |
288 | fdabc366 | bellard | } |
289 | e5f17ac6 | Blue Swirl | helper_raise_exception_err(env, env->exception_index, env->error_code); |
290 | fdabc366 | bellard | } |
291 | 9a64fbe4 | bellard | } |
292 | 76a66253 | j_mayer | #endif /* !CONFIG_USER_ONLY */ |