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/*
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SPARC translation
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Copyright (C) 2003 Thomas M. Ogrisegg <tom@fnord.at>
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Copyright (C) 2003 Fabrice Bellard
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This library is free software; you can redistribute it and/or
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modify it under the terms of the GNU Lesser General Public
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License as published by the Free Software Foundation; either
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version 2 of the License, or (at your option) any later version.
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This library is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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Lesser General Public License for more details.
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You should have received a copy of the GNU Lesser General Public
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License along with this library; if not, write to the Free Software
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Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
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*/
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/*
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TODO-list:
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NPC/PC static optimisations (use JUMP_TB when possible)
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FPU-Instructions
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Privileged instructions
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Coprocessor-Instructions
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Optimize synthetic instructions
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Optional alignment and privileged instruction check
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*/
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#include <stdarg.h> |
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#include <stdlib.h> |
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#include <stdio.h> |
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#include <string.h> |
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#include <inttypes.h> |
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#include "cpu.h" |
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#include "exec-all.h" |
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#include "disas.h" |
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#define DEBUG_DISAS
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|
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#define DYNAMIC_PC 1 /* dynamic pc value */ |
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#define JUMP_PC 2 /* dynamic pc value which takes only two values |
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according to jump_pc[T2] */
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|
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typedef struct DisasContext { |
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target_ulong pc; /* current Program Counter: integer or DYNAMIC_PC */
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target_ulong npc; /* next PC: integer or DYNAMIC_PC or JUMP_PC */
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target_ulong jump_pc[2]; /* used when JUMP_PC pc value is used */ |
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int is_br;
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struct TranslationBlock *tb;
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} DisasContext; |
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static uint16_t *gen_opc_ptr;
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static uint32_t *gen_opparam_ptr;
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extern FILE *logfile;
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extern int loglevel; |
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enum {
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#define DEF(s,n,copy_size) INDEX_op_ ## s, |
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#include "opc.h" |
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#undef DEF
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NB_OPS |
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}; |
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#include "gen-op.h" |
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|
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#define GET_FIELD(X, FROM, TO) \
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((X) >> (31 - (TO)) & ((1 << ((TO) - (FROM) + 1)) - 1)) |
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|
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#define IS_IMM (insn & (1<<13)) |
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static void disas_sparc_insn(DisasContext * dc); |
77 |
|
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static GenOpFunc *gen_op_movl_TN_reg[2][32] = { |
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{ |
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gen_op_movl_g0_T0, |
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gen_op_movl_g1_T0, |
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gen_op_movl_g2_T0, |
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gen_op_movl_g3_T0, |
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gen_op_movl_g4_T0, |
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gen_op_movl_g5_T0, |
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gen_op_movl_g6_T0, |
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gen_op_movl_g7_T0, |
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gen_op_movl_o0_T0, |
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gen_op_movl_o1_T0, |
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gen_op_movl_o2_T0, |
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gen_op_movl_o3_T0, |
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gen_op_movl_o4_T0, |
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gen_op_movl_o5_T0, |
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gen_op_movl_o6_T0, |
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gen_op_movl_o7_T0, |
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gen_op_movl_l0_T0, |
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gen_op_movl_l1_T0, |
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gen_op_movl_l2_T0, |
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gen_op_movl_l3_T0, |
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gen_op_movl_l4_T0, |
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gen_op_movl_l5_T0, |
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gen_op_movl_l6_T0, |
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gen_op_movl_l7_T0, |
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gen_op_movl_i0_T0, |
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gen_op_movl_i1_T0, |
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gen_op_movl_i2_T0, |
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gen_op_movl_i3_T0, |
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gen_op_movl_i4_T0, |
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gen_op_movl_i5_T0, |
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gen_op_movl_i6_T0, |
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gen_op_movl_i7_T0, |
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}, |
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{ |
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gen_op_movl_g0_T1, |
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gen_op_movl_g1_T1, |
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gen_op_movl_g2_T1, |
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gen_op_movl_g3_T1, |
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gen_op_movl_g4_T1, |
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gen_op_movl_g5_T1, |
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gen_op_movl_g6_T1, |
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gen_op_movl_g7_T1, |
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gen_op_movl_o0_T1, |
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gen_op_movl_o1_T1, |
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gen_op_movl_o2_T1, |
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gen_op_movl_o3_T1, |
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gen_op_movl_o4_T1, |
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gen_op_movl_o5_T1, |
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gen_op_movl_o6_T1, |
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gen_op_movl_o7_T1, |
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gen_op_movl_l0_T1, |
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gen_op_movl_l1_T1, |
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gen_op_movl_l2_T1, |
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gen_op_movl_l3_T1, |
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gen_op_movl_l4_T1, |
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gen_op_movl_l5_T1, |
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gen_op_movl_l6_T1, |
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gen_op_movl_l7_T1, |
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gen_op_movl_i0_T1, |
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gen_op_movl_i1_T1, |
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gen_op_movl_i2_T1, |
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gen_op_movl_i3_T1, |
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gen_op_movl_i4_T1, |
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gen_op_movl_i5_T1, |
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gen_op_movl_i6_T1, |
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gen_op_movl_i7_T1, |
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} |
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}; |
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static GenOpFunc *gen_op_movl_reg_TN[3][32] = { |
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{ |
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gen_op_movl_T0_g0, |
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gen_op_movl_T0_g1, |
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gen_op_movl_T0_g2, |
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gen_op_movl_T0_g3, |
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gen_op_movl_T0_g4, |
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gen_op_movl_T0_g5, |
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gen_op_movl_T0_g6, |
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gen_op_movl_T0_g7, |
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gen_op_movl_T0_o0, |
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gen_op_movl_T0_o1, |
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gen_op_movl_T0_o2, |
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gen_op_movl_T0_o3, |
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gen_op_movl_T0_o4, |
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gen_op_movl_T0_o5, |
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gen_op_movl_T0_o6, |
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gen_op_movl_T0_o7, |
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gen_op_movl_T0_l0, |
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gen_op_movl_T0_l1, |
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gen_op_movl_T0_l2, |
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gen_op_movl_T0_l3, |
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gen_op_movl_T0_l4, |
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gen_op_movl_T0_l5, |
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gen_op_movl_T0_l6, |
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gen_op_movl_T0_l7, |
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gen_op_movl_T0_i0, |
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gen_op_movl_T0_i1, |
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gen_op_movl_T0_i2, |
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gen_op_movl_T0_i3, |
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gen_op_movl_T0_i4, |
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gen_op_movl_T0_i5, |
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gen_op_movl_T0_i6, |
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gen_op_movl_T0_i7, |
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}, |
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{ |
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gen_op_movl_T1_g0, |
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gen_op_movl_T1_g1, |
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gen_op_movl_T1_g2, |
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gen_op_movl_T1_g3, |
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gen_op_movl_T1_g4, |
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gen_op_movl_T1_g5, |
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gen_op_movl_T1_g6, |
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gen_op_movl_T1_g7, |
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gen_op_movl_T1_o0, |
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gen_op_movl_T1_o1, |
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gen_op_movl_T1_o2, |
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gen_op_movl_T1_o3, |
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gen_op_movl_T1_o4, |
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gen_op_movl_T1_o5, |
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gen_op_movl_T1_o6, |
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gen_op_movl_T1_o7, |
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gen_op_movl_T1_l0, |
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gen_op_movl_T1_l1, |
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gen_op_movl_T1_l2, |
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gen_op_movl_T1_l3, |
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gen_op_movl_T1_l4, |
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gen_op_movl_T1_l5, |
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gen_op_movl_T1_l6, |
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gen_op_movl_T1_l7, |
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gen_op_movl_T1_i0, |
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gen_op_movl_T1_i1, |
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gen_op_movl_T1_i2, |
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gen_op_movl_T1_i3, |
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gen_op_movl_T1_i4, |
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gen_op_movl_T1_i5, |
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gen_op_movl_T1_i6, |
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gen_op_movl_T1_i7, |
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}, |
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{ |
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gen_op_movl_T2_g0, |
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gen_op_movl_T2_g1, |
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gen_op_movl_T2_g2, |
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gen_op_movl_T2_g3, |
223 |
gen_op_movl_T2_g4, |
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gen_op_movl_T2_g5, |
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gen_op_movl_T2_g6, |
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gen_op_movl_T2_g7, |
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gen_op_movl_T2_o0, |
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gen_op_movl_T2_o1, |
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gen_op_movl_T2_o2, |
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gen_op_movl_T2_o3, |
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gen_op_movl_T2_o4, |
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gen_op_movl_T2_o5, |
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gen_op_movl_T2_o6, |
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gen_op_movl_T2_o7, |
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gen_op_movl_T2_l0, |
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gen_op_movl_T2_l1, |
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gen_op_movl_T2_l2, |
238 |
gen_op_movl_T2_l3, |
239 |
gen_op_movl_T2_l4, |
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gen_op_movl_T2_l5, |
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gen_op_movl_T2_l6, |
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gen_op_movl_T2_l7, |
243 |
gen_op_movl_T2_i0, |
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gen_op_movl_T2_i1, |
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gen_op_movl_T2_i2, |
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gen_op_movl_T2_i3, |
247 |
gen_op_movl_T2_i4, |
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gen_op_movl_T2_i5, |
249 |
gen_op_movl_T2_i6, |
250 |
gen_op_movl_T2_i7, |
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} |
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}; |
253 |
|
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static GenOpFunc1 *gen_op_movl_TN_im[3] = { |
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gen_op_movl_T0_im, |
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gen_op_movl_T1_im, |
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gen_op_movl_T2_im |
258 |
}; |
259 |
|
260 |
static inline void gen_movl_imm_TN(int reg, int imm) |
261 |
{ |
262 |
gen_op_movl_TN_im[reg] (imm); |
263 |
} |
264 |
|
265 |
static inline void gen_movl_imm_T1(int val) |
266 |
{ |
267 |
gen_movl_imm_TN(1, val);
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} |
269 |
|
270 |
static inline void gen_movl_imm_T0(int val) |
271 |
{ |
272 |
gen_movl_imm_TN(0, val);
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273 |
} |
274 |
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static inline void gen_movl_reg_TN(int reg, int t) |
276 |
{ |
277 |
if (reg)
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gen_op_movl_reg_TN[t][reg] (); |
279 |
else
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gen_movl_imm_TN(t, 0);
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281 |
} |
282 |
|
283 |
static inline void gen_movl_reg_T0(int reg) |
284 |
{ |
285 |
gen_movl_reg_TN(reg, 0);
|
286 |
} |
287 |
|
288 |
static inline void gen_movl_reg_T1(int reg) |
289 |
{ |
290 |
gen_movl_reg_TN(reg, 1);
|
291 |
} |
292 |
|
293 |
static inline void gen_movl_reg_T2(int reg) |
294 |
{ |
295 |
gen_movl_reg_TN(reg, 2);
|
296 |
} |
297 |
|
298 |
static inline void gen_movl_TN_reg(int reg, int t) |
299 |
{ |
300 |
if (reg)
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301 |
gen_op_movl_TN_reg[t][reg] (); |
302 |
} |
303 |
|
304 |
static inline void gen_movl_T0_reg(int reg) |
305 |
{ |
306 |
gen_movl_TN_reg(reg, 0);
|
307 |
} |
308 |
|
309 |
static inline void gen_movl_T1_reg(int reg) |
310 |
{ |
311 |
gen_movl_TN_reg(reg, 1);
|
312 |
} |
313 |
|
314 |
/* call this function before using T2 as it may have been set for a jump */
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315 |
static inline void flush_T2(DisasContext * dc) |
316 |
{ |
317 |
if (dc->npc == JUMP_PC) {
|
318 |
gen_op_generic_branch(dc->jump_pc[0], dc->jump_pc[1]); |
319 |
dc->npc = DYNAMIC_PC; |
320 |
} |
321 |
} |
322 |
|
323 |
static inline void save_npc(DisasContext * dc) |
324 |
{ |
325 |
if (dc->npc == JUMP_PC) {
|
326 |
gen_op_generic_branch(dc->jump_pc[0], dc->jump_pc[1]); |
327 |
dc->npc = DYNAMIC_PC; |
328 |
} else if (dc->npc != DYNAMIC_PC) { |
329 |
gen_op_movl_npc_im(dc->npc); |
330 |
} |
331 |
} |
332 |
|
333 |
static inline void save_state(DisasContext * dc) |
334 |
{ |
335 |
gen_op_jmp_im((uint32_t)dc->pc); |
336 |
save_npc(dc); |
337 |
} |
338 |
|
339 |
static void gen_cond(int cond) |
340 |
{ |
341 |
switch (cond) {
|
342 |
case 0x0: |
343 |
gen_op_movl_T2_0(); |
344 |
break;
|
345 |
case 0x1: |
346 |
gen_op_eval_be(); |
347 |
break;
|
348 |
case 0x2: |
349 |
gen_op_eval_ble(); |
350 |
break;
|
351 |
case 0x3: |
352 |
gen_op_eval_bl(); |
353 |
break;
|
354 |
case 0x4: |
355 |
gen_op_eval_bleu(); |
356 |
break;
|
357 |
case 0x5: |
358 |
gen_op_eval_bcs(); |
359 |
break;
|
360 |
case 0x6: |
361 |
gen_op_eval_bneg(); |
362 |
break;
|
363 |
case 0x7: |
364 |
gen_op_eval_bvs(); |
365 |
break;
|
366 |
case 0x8: |
367 |
gen_op_movl_T2_1(); |
368 |
break;
|
369 |
case 0x9: |
370 |
gen_op_eval_bne(); |
371 |
break;
|
372 |
case 0xa: |
373 |
gen_op_eval_bg(); |
374 |
break;
|
375 |
case 0xb: |
376 |
gen_op_eval_bge(); |
377 |
break;
|
378 |
case 0xc: |
379 |
gen_op_eval_bgu(); |
380 |
break;
|
381 |
case 0xd: |
382 |
gen_op_eval_bcc(); |
383 |
break;
|
384 |
case 0xe: |
385 |
gen_op_eval_bpos(); |
386 |
break;
|
387 |
default:
|
388 |
case 0xf: |
389 |
gen_op_eval_bvc(); |
390 |
break;
|
391 |
} |
392 |
} |
393 |
|
394 |
|
395 |
static void do_branch(DisasContext * dc, uint32_t target, uint32_t insn) |
396 |
{ |
397 |
unsigned int cond = GET_FIELD(insn, 3, 6), a = (insn & (1 << 29)); |
398 |
target += (uint32_t) dc->pc; |
399 |
if (cond == 0x0) { |
400 |
/* unconditional not taken */
|
401 |
if (a) {
|
402 |
dc->pc = dc->npc + 4;
|
403 |
dc->npc = dc->pc + 4;
|
404 |
} else {
|
405 |
dc->pc = dc->npc; |
406 |
dc->npc = dc->pc + 4;
|
407 |
} |
408 |
} else if (cond == 0x8) { |
409 |
/* unconditional taken */
|
410 |
if (a) {
|
411 |
dc->pc = target; |
412 |
dc->npc = dc->pc + 4;
|
413 |
} else {
|
414 |
dc->pc = dc->npc; |
415 |
dc->npc = target; |
416 |
} |
417 |
} else {
|
418 |
flush_T2(dc); |
419 |
gen_cond(cond); |
420 |
if (a) {
|
421 |
gen_op_branch_a((long)dc->tb, target, dc->npc);
|
422 |
dc->is_br = 1;
|
423 |
} else {
|
424 |
dc->pc = dc->npc; |
425 |
dc->jump_pc[0] = target;
|
426 |
dc->jump_pc[1] = dc->npc + 4; |
427 |
dc->npc = JUMP_PC; |
428 |
} |
429 |
} |
430 |
} |
431 |
|
432 |
#define GET_FIELDs(x,a,b) sign_extend (GET_FIELD(x,a,b), (b) - (a) + 1) |
433 |
|
434 |
static int sign_extend(int x, int len) |
435 |
{ |
436 |
len = 32 - len;
|
437 |
return (x << len) >> len;
|
438 |
} |
439 |
|
440 |
static void disas_sparc_insn(DisasContext * dc) |
441 |
{ |
442 |
unsigned int insn, opc, rs1, rs2, rd; |
443 |
|
444 |
insn = ldl_code((uint8_t *)dc->pc); |
445 |
opc = GET_FIELD(insn, 0, 1); |
446 |
|
447 |
rd = GET_FIELD(insn, 2, 6); |
448 |
switch (opc) {
|
449 |
case 0: /* branches/sethi */ |
450 |
{ |
451 |
unsigned int xop = GET_FIELD(insn, 7, 9); |
452 |
int target;
|
453 |
target = GET_FIELD(insn, 10, 31); |
454 |
switch (xop) {
|
455 |
case 0x0: |
456 |
case 0x1: /* UNIMPL */ |
457 |
goto illegal_insn;
|
458 |
case 0x2: /* BN+x */ |
459 |
{ |
460 |
target <<= 2;
|
461 |
target = sign_extend(target, 22);
|
462 |
do_branch(dc, target, insn); |
463 |
goto jmp_insn;
|
464 |
} |
465 |
case 0x3: /* FBN+x */ |
466 |
break;
|
467 |
case 0x4: /* SETHI */ |
468 |
gen_movl_imm_T0(target << 10);
|
469 |
gen_movl_T0_reg(rd); |
470 |
break;
|
471 |
case 0x5: /*CBN+x */ |
472 |
break;
|
473 |
} |
474 |
break;
|
475 |
} |
476 |
case 1: |
477 |
/*CALL*/ {
|
478 |
unsigned int target = GET_FIELDs(insn, 2, 31) << 2; |
479 |
|
480 |
gen_op_movl_T0_im((long) (dc->pc));
|
481 |
gen_movl_T0_reg(15);
|
482 |
target = dc->pc + target; |
483 |
dc->pc = dc->npc; |
484 |
dc->npc = target; |
485 |
} |
486 |
goto jmp_insn;
|
487 |
case 2: /* FPU & Logical Operations */ |
488 |
{ |
489 |
unsigned int xop = GET_FIELD(insn, 7, 12); |
490 |
if (xop == 0x3a) { /* generate trap */ |
491 |
int cond;
|
492 |
rs1 = GET_FIELD(insn, 13, 17); |
493 |
gen_movl_reg_T0(rs1); |
494 |
if (IS_IMM) {
|
495 |
gen_movl_imm_T1(GET_FIELD(insn, 25, 31)); |
496 |
} else {
|
497 |
rs2 = GET_FIELD(insn, 27, 31); |
498 |
gen_movl_reg_T1(rs2); |
499 |
} |
500 |
gen_op_add_T1_T0(); |
501 |
save_state(dc); |
502 |
cond = GET_FIELD(insn, 3, 6); |
503 |
if (cond == 0x8) { |
504 |
gen_op_trap_T0(); |
505 |
dc->is_br = 1;
|
506 |
goto jmp_insn;
|
507 |
} else {
|
508 |
gen_op_trapcc_T0(); |
509 |
} |
510 |
} else if (xop == 0x28) { |
511 |
rs1 = GET_FIELD(insn, 13, 17); |
512 |
switch(rs1) {
|
513 |
case 0: /* rdy */ |
514 |
gen_op_rdy(); |
515 |
gen_movl_T0_reg(rd); |
516 |
break;
|
517 |
default:
|
518 |
goto illegal_insn;
|
519 |
} |
520 |
} else if (xop == 0x34 || xop == 0x35) { /* FPU Operations */ |
521 |
goto illegal_insn;
|
522 |
} else {
|
523 |
rs1 = GET_FIELD(insn, 13, 17); |
524 |
gen_movl_reg_T0(rs1); |
525 |
if (IS_IMM) { /* immediate */ |
526 |
rs2 = GET_FIELDs(insn, 19, 31); |
527 |
gen_movl_imm_T1(rs2); |
528 |
} else { /* register */ |
529 |
rs2 = GET_FIELD(insn, 27, 31); |
530 |
gen_movl_reg_T1(rs2); |
531 |
} |
532 |
if (xop < 0x20) { |
533 |
switch (xop & ~0x10) { |
534 |
case 0x0: |
535 |
if (xop & 0x10) |
536 |
gen_op_add_T1_T0_cc(); |
537 |
else
|
538 |
gen_op_add_T1_T0(); |
539 |
break;
|
540 |
case 0x1: |
541 |
gen_op_and_T1_T0(); |
542 |
if (xop & 0x10) |
543 |
gen_op_logic_T0_cc(); |
544 |
break;
|
545 |
case 0x2: |
546 |
gen_op_or_T1_T0(); |
547 |
if (xop & 0x10) |
548 |
gen_op_logic_T0_cc(); |
549 |
break;
|
550 |
case 0x3: |
551 |
gen_op_xor_T1_T0(); |
552 |
if (xop & 0x10) |
553 |
gen_op_logic_T0_cc(); |
554 |
break;
|
555 |
case 0x4: |
556 |
if (xop & 0x10) |
557 |
gen_op_sub_T1_T0_cc(); |
558 |
else
|
559 |
gen_op_sub_T1_T0(); |
560 |
break;
|
561 |
case 0x5: |
562 |
gen_op_andn_T1_T0(); |
563 |
if (xop & 0x10) |
564 |
gen_op_logic_T0_cc(); |
565 |
break;
|
566 |
case 0x6: |
567 |
gen_op_orn_T1_T0(); |
568 |
if (xop & 0x10) |
569 |
gen_op_logic_T0_cc(); |
570 |
break;
|
571 |
case 0x7: |
572 |
gen_op_xnor_T1_T0(); |
573 |
if (xop & 0x10) |
574 |
gen_op_logic_T0_cc(); |
575 |
break;
|
576 |
case 0x8: |
577 |
gen_op_addx_T1_T0(); |
578 |
if (xop & 0x10) |
579 |
gen_op_set_flags(); |
580 |
break;
|
581 |
case 0xa: |
582 |
gen_op_umul_T1_T0(); |
583 |
if (xop & 0x10) |
584 |
gen_op_logic_T0_cc(); |
585 |
break;
|
586 |
case 0xb: |
587 |
gen_op_smul_T1_T0(); |
588 |
if (xop & 0x10) |
589 |
gen_op_logic_T0_cc(); |
590 |
break;
|
591 |
case 0xc: |
592 |
gen_op_subx_T1_T0(); |
593 |
if (xop & 0x10) |
594 |
gen_op_set_flags(); |
595 |
break;
|
596 |
case 0xe: |
597 |
gen_op_udiv_T1_T0(); |
598 |
if (xop & 0x10) |
599 |
gen_op_div_cc(); |
600 |
break;
|
601 |
case 0xf: |
602 |
gen_op_sdiv_T1_T0(); |
603 |
if (xop & 0x10) |
604 |
gen_op_div_cc(); |
605 |
break;
|
606 |
default:
|
607 |
goto illegal_insn;
|
608 |
} |
609 |
gen_movl_T0_reg(rd); |
610 |
} else {
|
611 |
switch (xop) {
|
612 |
case 0x24: /* mulscc */ |
613 |
gen_op_mulscc_T1_T0(); |
614 |
gen_movl_T0_reg(rd); |
615 |
break;
|
616 |
case 0x25: /* SLL */ |
617 |
gen_op_sll(); |
618 |
gen_movl_T0_reg(rd); |
619 |
break;
|
620 |
case 0x26: |
621 |
gen_op_srl(); |
622 |
gen_movl_T0_reg(rd); |
623 |
break;
|
624 |
case 0x27: |
625 |
gen_op_sra(); |
626 |
gen_movl_T0_reg(rd); |
627 |
break;
|
628 |
case 0x30: |
629 |
{ |
630 |
gen_op_xor_T1_T0(); |
631 |
switch(rd) {
|
632 |
case 0: |
633 |
gen_op_wry(); |
634 |
break;
|
635 |
default:
|
636 |
goto illegal_insn;
|
637 |
} |
638 |
} |
639 |
break;
|
640 |
case 0x38: /* jmpl */ |
641 |
{ |
642 |
gen_op_add_T1_T0(); |
643 |
gen_op_movl_npc_T0(); |
644 |
if (rd != 0) { |
645 |
gen_op_movl_T0_im((long) (dc->pc));
|
646 |
gen_movl_T0_reg(rd); |
647 |
} |
648 |
dc->pc = dc->npc; |
649 |
dc->npc = DYNAMIC_PC; |
650 |
} |
651 |
goto jmp_insn;
|
652 |
case 0x3b: /* flush */ |
653 |
gen_op_add_T1_T0(); |
654 |
gen_op_flush_T0(); |
655 |
break;
|
656 |
case 0x3c: /* save */ |
657 |
save_state(dc); |
658 |
gen_op_add_T1_T0(); |
659 |
gen_op_save(); |
660 |
gen_movl_T0_reg(rd); |
661 |
break;
|
662 |
case 0x3d: /* restore */ |
663 |
save_state(dc); |
664 |
gen_op_add_T1_T0(); |
665 |
gen_op_restore(); |
666 |
gen_movl_T0_reg(rd); |
667 |
break;
|
668 |
default:
|
669 |
goto illegal_insn;
|
670 |
} |
671 |
} |
672 |
} |
673 |
break;
|
674 |
} |
675 |
case 3: /* load/store instructions */ |
676 |
{ |
677 |
unsigned int xop = GET_FIELD(insn, 7, 12); |
678 |
rs1 = GET_FIELD(insn, 13, 17); |
679 |
gen_movl_reg_T0(rs1); |
680 |
if (IS_IMM) { /* immediate */ |
681 |
rs2 = GET_FIELDs(insn, 19, 31); |
682 |
gen_movl_imm_T1(rs2); |
683 |
} else { /* register */ |
684 |
rs2 = GET_FIELD(insn, 27, 31); |
685 |
gen_movl_reg_T1(rs2); |
686 |
} |
687 |
gen_op_add_T1_T0(); |
688 |
if (xop < 4 || xop > 7) { |
689 |
switch (xop) {
|
690 |
case 0x0: /* load word */ |
691 |
gen_op_ld(); |
692 |
break;
|
693 |
case 0x1: /* load unsigned byte */ |
694 |
gen_op_ldub(); |
695 |
break;
|
696 |
case 0x2: /* load unsigned halfword */ |
697 |
gen_op_lduh(); |
698 |
break;
|
699 |
case 0x3: /* load double word */ |
700 |
gen_op_ldd(); |
701 |
gen_movl_T0_reg(rd + 1);
|
702 |
break;
|
703 |
case 0x9: /* load signed byte */ |
704 |
gen_op_ldsb(); |
705 |
break;
|
706 |
case 0xa: /* load signed halfword */ |
707 |
gen_op_ldsh(); |
708 |
break;
|
709 |
case 0xd: /* ldstub -- XXX: should be atomically */ |
710 |
gen_op_ldstub(); |
711 |
break;
|
712 |
case 0x0f: /* swap register with memory. Also atomically */ |
713 |
gen_op_swap(); |
714 |
break;
|
715 |
} |
716 |
gen_movl_T1_reg(rd); |
717 |
} else if (xop < 8) { |
718 |
gen_movl_reg_T1(rd); |
719 |
switch (xop) {
|
720 |
case 0x4: |
721 |
gen_op_st(); |
722 |
break;
|
723 |
case 0x5: |
724 |
gen_op_stb(); |
725 |
break;
|
726 |
case 0x6: |
727 |
gen_op_sth(); |
728 |
break;
|
729 |
case 0x7: |
730 |
flush_T2(dc); |
731 |
gen_movl_reg_T2(rd + 1);
|
732 |
gen_op_std(); |
733 |
break;
|
734 |
} |
735 |
} |
736 |
} |
737 |
} |
738 |
/* default case for non jump instructions */
|
739 |
if (dc->npc == DYNAMIC_PC) {
|
740 |
dc->pc = DYNAMIC_PC; |
741 |
gen_op_next_insn(); |
742 |
} else if (dc->npc == JUMP_PC) { |
743 |
/* we can do a static jump */
|
744 |
gen_op_branch2((long)dc->tb, dc->jump_pc[0], dc->jump_pc[1]); |
745 |
dc->is_br = 1;
|
746 |
} else {
|
747 |
dc->pc = dc->npc; |
748 |
dc->npc = dc->npc + 4;
|
749 |
} |
750 |
jmp_insn:;
|
751 |
return;
|
752 |
illegal_insn:
|
753 |
save_state(dc); |
754 |
gen_op_exception(TT_ILL_INSN); |
755 |
dc->is_br = 1;
|
756 |
} |
757 |
|
758 |
static inline int gen_intermediate_code_internal(TranslationBlock * tb, |
759 |
int spc)
|
760 |
{ |
761 |
target_ulong pc_start, last_pc; |
762 |
uint16_t *gen_opc_end; |
763 |
DisasContext dc1, *dc = &dc1; |
764 |
|
765 |
memset(dc, 0, sizeof(DisasContext)); |
766 |
if (spc) {
|
767 |
printf("SearchPC not yet supported\n");
|
768 |
exit(0);
|
769 |
} |
770 |
dc->tb = tb; |
771 |
pc_start = tb->pc; |
772 |
dc->pc = pc_start; |
773 |
dc->npc = (target_ulong) tb->cs_base; |
774 |
|
775 |
gen_opc_ptr = gen_opc_buf; |
776 |
gen_opc_end = gen_opc_buf + OPC_MAX_SIZE; |
777 |
gen_opparam_ptr = gen_opparam_buf; |
778 |
|
779 |
do {
|
780 |
last_pc = dc->pc; |
781 |
disas_sparc_insn(dc); |
782 |
if (dc->is_br)
|
783 |
break;
|
784 |
/* if the next PC is different, we abort now */
|
785 |
if (dc->pc != (last_pc + 4)) |
786 |
break;
|
787 |
} while ((gen_opc_ptr < gen_opc_end) &&
|
788 |
(dc->pc - pc_start) < (TARGET_PAGE_SIZE - 32));
|
789 |
if (!dc->is_br) {
|
790 |
if (dc->pc != DYNAMIC_PC &&
|
791 |
(dc->npc != DYNAMIC_PC && dc->npc != JUMP_PC)) { |
792 |
/* static PC and NPC: we can use direct chaining */
|
793 |
gen_op_branch((long)tb, dc->pc, dc->npc);
|
794 |
} else {
|
795 |
if (dc->pc != DYNAMIC_PC)
|
796 |
gen_op_jmp_im(dc->pc); |
797 |
save_npc(dc); |
798 |
gen_op_movl_T0_0(); |
799 |
gen_op_exit_tb(); |
800 |
} |
801 |
} |
802 |
*gen_opc_ptr = INDEX_op_end; |
803 |
#ifdef DEBUG_DISAS
|
804 |
if (loglevel & CPU_LOG_TB_IN_ASM) {
|
805 |
fprintf(logfile, "--------------\n");
|
806 |
fprintf(logfile, "IN: %s\n", lookup_symbol((uint8_t *)pc_start));
|
807 |
disas(logfile, (uint8_t *)pc_start, last_pc + 4 - pc_start, 0, 0); |
808 |
fprintf(logfile, "\n");
|
809 |
if (loglevel & CPU_LOG_TB_OP) {
|
810 |
fprintf(logfile, "OP:\n");
|
811 |
dump_ops(gen_opc_buf, gen_opparam_buf); |
812 |
fprintf(logfile, "\n");
|
813 |
} |
814 |
} |
815 |
#endif
|
816 |
|
817 |
return 0; |
818 |
} |
819 |
|
820 |
int gen_intermediate_code(CPUSPARCState * env, TranslationBlock * tb)
|
821 |
{ |
822 |
return gen_intermediate_code_internal(tb, 0); |
823 |
} |
824 |
|
825 |
int gen_intermediate_code_pc(CPUSPARCState * env, TranslationBlock * tb)
|
826 |
{ |
827 |
return gen_intermediate_code_internal(tb, 1); |
828 |
} |
829 |
|
830 |
CPUSPARCState *cpu_sparc_init(void)
|
831 |
{ |
832 |
CPUSPARCState *env; |
833 |
|
834 |
cpu_exec_init(); |
835 |
|
836 |
if (!(env = malloc(sizeof(CPUSPARCState)))) |
837 |
return (NULL); |
838 |
memset(env, 0, sizeof(*env)); |
839 |
env->cwp = 0;
|
840 |
env->wim = 1;
|
841 |
env->regwptr = env->regbase + (env->cwp * 16);
|
842 |
env->user_mode_only = 1;
|
843 |
cpu_single_env = env; |
844 |
return (env);
|
845 |
} |
846 |
|
847 |
#define GET_FLAG(a,b) ((env->psr & a)?b:'-') |
848 |
|
849 |
void cpu_sparc_dump_state(CPUSPARCState * env, FILE * f, int flags) |
850 |
{ |
851 |
int i, x;
|
852 |
|
853 |
fprintf(f, "pc: 0x%08x npc: 0x%08x\n", (int) env->pc, (int) env->npc); |
854 |
fprintf(f, "General Registers:\n");
|
855 |
for (i = 0; i < 4; i++) |
856 |
fprintf(f, "%%g%c: 0x%08x\t", i + '0', env->gregs[i]); |
857 |
fprintf(f, "\n");
|
858 |
for (; i < 8; i++) |
859 |
fprintf(f, "%%g%c: 0x%08x\t", i + '0', env->gregs[i]); |
860 |
fprintf(f, "\nCurrent Register Window:\n");
|
861 |
for (x = 0; x < 3; x++) { |
862 |
for (i = 0; i < 4; i++) |
863 |
fprintf(f, "%%%c%d: 0x%08x\t",
|
864 |
(x == 0 ? 'o' : (x == 1 ? 'l' : 'i')), i, |
865 |
env->regwptr[i + x * 8]);
|
866 |
fprintf(f, "\n");
|
867 |
for (; i < 8; i++) |
868 |
fprintf(f, "%%%c%d: 0x%08x\t",
|
869 |
(x == 0 ? 'o' : x == 1 ? 'l' : 'i'), i, |
870 |
env->regwptr[i + x * 8]);
|
871 |
fprintf(f, "\n");
|
872 |
} |
873 |
fprintf(f, "psr: 0x%08x -> %c%c%c%c wim: 0x%08x\n", env->psr | env->cwp,
|
874 |
GET_FLAG(PSR_ZERO, 'Z'), GET_FLAG(PSR_OVF, 'V'), |
875 |
GET_FLAG(PSR_NEG, 'N'), GET_FLAG(PSR_CARRY, 'C'), |
876 |
env->wim); |
877 |
} |
878 |
|
879 |
target_ulong cpu_get_phys_page_debug(CPUState *env, target_ulong addr) |
880 |
{ |
881 |
return addr;
|
882 |
} |
883 |
|
884 |
void helper_flush(target_ulong addr)
|
885 |
{ |
886 |
addr &= ~7;
|
887 |
tb_invalidate_page_range(addr, addr + 8);
|
888 |
} |