Revision d1e42c5c

b/target-i386/translate.c
2905 2905 
            break;
2906 2906 
        case 0xc4: /* pinsrw */
2907 2907 
        case 0x1c4:
2908 
            s->rip_offset = 1;
2908 2909 
            gen_ldst_modrm(s, modrm, OT_WORD, OR_TMP0, 0);
2909 2910 
            val = ldub_code(s->pc++);
2910 2911 
            if (b1) {
......
2975 2976 
        }
2976 2977 
    } else {
2977 2978 
        /* generic MMX or SSE operation */
2978 
        if (b == 0xf7) {
2979 
        switch(b) {
2980 
        case 0xf7:
2979 2981 
            /* maskmov : we must prepare A0 */
2980 2982 
            if (mod != 3)
2981 2983 
                goto illegal_op;
......
2990 2992 
                    gen_op_andl_A0_ffff();
2991 2993 
            }
2992 2994 
            gen_add_A0_ds_seg(s);
2995 
            break;
2996 
        case 0x70: /* pshufx insn */
2997 
        case 0xc6: /* pshufx insn */
2998 
        case 0xc2: /* compare insns */
2999 
            s->rip_offset = 1;
3000 
            break;
3001 
        default:
3002 
            break;
2993 3003 
        }
2994 3004 
        if (is_xmm) {
2995 3005 
            op1_offset = offsetof(CPUX86State,xmm_regs[reg]);

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