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1 | c1713132 | balrog | /*
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2 | c1713132 | balrog | * Intel XScale PXA255/270 DMA controller.
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3 | c1713132 | balrog | *
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4 | c1713132 | balrog | * Copyright (c) 2006 Openedhand Ltd.
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5 | c1713132 | balrog | * Copyright (c) 2006 Thorsten Zitterell
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6 | c1713132 | balrog | * Written by Andrzej Zaborowski <balrog@zabor.org>
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7 | c1713132 | balrog | *
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8 | c1713132 | balrog | * This code is licenced under the GPL.
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9 | c1713132 | balrog | */
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10 | c1713132 | balrog | |
11 | 87ecb68b | pbrook | #include "hw.h" |
12 | 87ecb68b | pbrook | #include "pxa.h" |
13 | 2115c019 | Andrzej Zaborowski | #include "sysbus.h" |
14 | 2115c019 | Andrzej Zaborowski | |
15 | 2115c019 | Andrzej Zaborowski | #define PXA255_DMA_NUM_CHANNELS 16 |
16 | 2115c019 | Andrzej Zaborowski | #define PXA27X_DMA_NUM_CHANNELS 32 |
17 | 2115c019 | Andrzej Zaborowski | |
18 | 2115c019 | Andrzej Zaborowski | #define PXA2XX_DMA_NUM_REQUESTS 75 |
19 | c1713132 | balrog | |
20 | bc24a225 | Paul Brook | typedef struct { |
21 | c227f099 | Anthony Liguori | target_phys_addr_t descr; |
22 | c227f099 | Anthony Liguori | target_phys_addr_t src; |
23 | c227f099 | Anthony Liguori | target_phys_addr_t dest; |
24 | c1713132 | balrog | uint32_t cmd; |
25 | c1713132 | balrog | uint32_t state; |
26 | c1713132 | balrog | int request;
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27 | bc24a225 | Paul Brook | } PXA2xxDMAChannel; |
28 | c1713132 | balrog | |
29 | 2115c019 | Andrzej Zaborowski | typedef struct PXA2xxDMAState { |
30 | 2115c019 | Andrzej Zaborowski | SysBusDevice busdev; |
31 | c1713132 | balrog | qemu_irq irq; |
32 | c1713132 | balrog | |
33 | c1713132 | balrog | uint32_t stopintr; |
34 | c1713132 | balrog | uint32_t eorintr; |
35 | c1713132 | balrog | uint32_t rasintr; |
36 | c1713132 | balrog | uint32_t startintr; |
37 | c1713132 | balrog | uint32_t endintr; |
38 | c1713132 | balrog | |
39 | c1713132 | balrog | uint32_t align; |
40 | c1713132 | balrog | uint32_t pio; |
41 | c1713132 | balrog | |
42 | c1713132 | balrog | int channels;
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43 | bc24a225 | Paul Brook | PXA2xxDMAChannel *chan; |
44 | c1713132 | balrog | |
45 | 2115c019 | Andrzej Zaborowski | uint8_t req[PXA2XX_DMA_NUM_REQUESTS]; |
46 | c1713132 | balrog | |
47 | c1713132 | balrog | /* Flag to avoid recursive DMA invocations. */
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48 | c1713132 | balrog | int running;
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49 | 2115c019 | Andrzej Zaborowski | } PXA2xxDMAState; |
50 | c1713132 | balrog | |
51 | c1713132 | balrog | #define DCSR0 0x0000 /* DMA Control / Status register for Channel 0 */ |
52 | c1713132 | balrog | #define DCSR31 0x007c /* DMA Control / Status register for Channel 31 */ |
53 | c1713132 | balrog | #define DALGN 0x00a0 /* DMA Alignment register */ |
54 | c1713132 | balrog | #define DPCSR 0x00a4 /* DMA Programmed I/O Control Status register */ |
55 | c1713132 | balrog | #define DRQSR0 0x00e0 /* DMA DREQ<0> Status register */ |
56 | c1713132 | balrog | #define DRQSR1 0x00e4 /* DMA DREQ<1> Status register */ |
57 | c1713132 | balrog | #define DRQSR2 0x00e8 /* DMA DREQ<2> Status register */ |
58 | c1713132 | balrog | #define DINT 0x00f0 /* DMA Interrupt register */ |
59 | c1713132 | balrog | #define DRCMR0 0x0100 /* Request to Channel Map register 0 */ |
60 | c1713132 | balrog | #define DRCMR63 0x01fc /* Request to Channel Map register 63 */ |
61 | c1713132 | balrog | #define D_CH0 0x0200 /* Channel 0 Descriptor start */ |
62 | c1713132 | balrog | #define DRCMR64 0x1100 /* Request to Channel Map register 64 */ |
63 | c1713132 | balrog | #define DRCMR74 0x1128 /* Request to Channel Map register 74 */ |
64 | c1713132 | balrog | |
65 | c1713132 | balrog | /* Per-channel register */
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66 | c1713132 | balrog | #define DDADR 0x00 |
67 | c1713132 | balrog | #define DSADR 0x01 |
68 | c1713132 | balrog | #define DTADR 0x02 |
69 | c1713132 | balrog | #define DCMD 0x03 |
70 | c1713132 | balrog | |
71 | c1713132 | balrog | /* Bit-field masks */
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72 | c1713132 | balrog | #define DRCMR_CHLNUM 0x1f |
73 | c1713132 | balrog | #define DRCMR_MAPVLD (1 << 7) |
74 | c1713132 | balrog | #define DDADR_STOP (1 << 0) |
75 | c1713132 | balrog | #define DDADR_BREN (1 << 1) |
76 | c1713132 | balrog | #define DCMD_LEN 0x1fff |
77 | c1713132 | balrog | #define DCMD_WIDTH(x) (1 << ((((x) >> 14) & 3) - 1)) |
78 | c1713132 | balrog | #define DCMD_SIZE(x) (4 << (((x) >> 16) & 3)) |
79 | c1713132 | balrog | #define DCMD_FLYBYT (1 << 19) |
80 | c1713132 | balrog | #define DCMD_FLYBYS (1 << 20) |
81 | c1713132 | balrog | #define DCMD_ENDIRQEN (1 << 21) |
82 | c1713132 | balrog | #define DCMD_STARTIRQEN (1 << 22) |
83 | c1713132 | balrog | #define DCMD_CMPEN (1 << 25) |
84 | c1713132 | balrog | #define DCMD_FLOWTRG (1 << 28) |
85 | c1713132 | balrog | #define DCMD_FLOWSRC (1 << 29) |
86 | c1713132 | balrog | #define DCMD_INCTRGADDR (1 << 30) |
87 | c1713132 | balrog | #define DCMD_INCSRCADDR (1 << 31) |
88 | c1713132 | balrog | #define DCSR_BUSERRINTR (1 << 0) |
89 | c1713132 | balrog | #define DCSR_STARTINTR (1 << 1) |
90 | c1713132 | balrog | #define DCSR_ENDINTR (1 << 2) |
91 | c1713132 | balrog | #define DCSR_STOPINTR (1 << 3) |
92 | c1713132 | balrog | #define DCSR_RASINTR (1 << 4) |
93 | c1713132 | balrog | #define DCSR_REQPEND (1 << 8) |
94 | c1713132 | balrog | #define DCSR_EORINT (1 << 9) |
95 | c1713132 | balrog | #define DCSR_CMPST (1 << 10) |
96 | c1713132 | balrog | #define DCSR_MASKRUN (1 << 22) |
97 | c1713132 | balrog | #define DCSR_RASIRQEN (1 << 23) |
98 | c1713132 | balrog | #define DCSR_CLRCMPST (1 << 24) |
99 | c1713132 | balrog | #define DCSR_SETCMPST (1 << 25) |
100 | c1713132 | balrog | #define DCSR_EORSTOPEN (1 << 26) |
101 | c1713132 | balrog | #define DCSR_EORJMPEN (1 << 27) |
102 | c1713132 | balrog | #define DCSR_EORIRQEN (1 << 28) |
103 | c1713132 | balrog | #define DCSR_STOPIRQEN (1 << 29) |
104 | c1713132 | balrog | #define DCSR_NODESCFETCH (1 << 30) |
105 | c1713132 | balrog | #define DCSR_RUN (1 << 31) |
106 | c1713132 | balrog | |
107 | bc24a225 | Paul Brook | static inline void pxa2xx_dma_update(PXA2xxDMAState *s, int ch) |
108 | c1713132 | balrog | { |
109 | c1713132 | balrog | if (ch >= 0) { |
110 | c1713132 | balrog | if ((s->chan[ch].state & DCSR_STOPIRQEN) &&
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111 | c1713132 | balrog | (s->chan[ch].state & DCSR_STOPINTR)) |
112 | c1713132 | balrog | s->stopintr |= 1 << ch;
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113 | c1713132 | balrog | else
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114 | c1713132 | balrog | s->stopintr &= ~(1 << ch);
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115 | c1713132 | balrog | |
116 | c1713132 | balrog | if ((s->chan[ch].state & DCSR_EORIRQEN) &&
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117 | c1713132 | balrog | (s->chan[ch].state & DCSR_EORINT)) |
118 | c1713132 | balrog | s->eorintr |= 1 << ch;
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119 | c1713132 | balrog | else
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120 | c1713132 | balrog | s->eorintr &= ~(1 << ch);
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121 | c1713132 | balrog | |
122 | c1713132 | balrog | if ((s->chan[ch].state & DCSR_RASIRQEN) &&
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123 | c1713132 | balrog | (s->chan[ch].state & DCSR_RASINTR)) |
124 | c1713132 | balrog | s->rasintr |= 1 << ch;
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125 | c1713132 | balrog | else
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126 | c1713132 | balrog | s->rasintr &= ~(1 << ch);
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127 | c1713132 | balrog | |
128 | c1713132 | balrog | if (s->chan[ch].state & DCSR_STARTINTR)
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129 | c1713132 | balrog | s->startintr |= 1 << ch;
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130 | c1713132 | balrog | else
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131 | c1713132 | balrog | s->startintr &= ~(1 << ch);
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132 | c1713132 | balrog | |
133 | c1713132 | balrog | if (s->chan[ch].state & DCSR_ENDINTR)
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134 | c1713132 | balrog | s->endintr |= 1 << ch;
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135 | c1713132 | balrog | else
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136 | c1713132 | balrog | s->endintr &= ~(1 << ch);
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137 | c1713132 | balrog | } |
138 | c1713132 | balrog | |
139 | c1713132 | balrog | if (s->stopintr | s->eorintr | s->rasintr | s->startintr | s->endintr)
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140 | c1713132 | balrog | qemu_irq_raise(s->irq); |
141 | c1713132 | balrog | else
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142 | c1713132 | balrog | qemu_irq_lower(s->irq); |
143 | c1713132 | balrog | } |
144 | c1713132 | balrog | |
145 | c1713132 | balrog | static inline void pxa2xx_dma_descriptor_fetch( |
146 | bc24a225 | Paul Brook | PXA2xxDMAState *s, int ch)
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147 | c1713132 | balrog | { |
148 | c1713132 | balrog | uint32_t desc[4];
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149 | c227f099 | Anthony Liguori | target_phys_addr_t daddr = s->chan[ch].descr & ~0xf;
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150 | c1713132 | balrog | if ((s->chan[ch].descr & DDADR_BREN) && (s->chan[ch].state & DCSR_CMPST))
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151 | c1713132 | balrog | daddr += 32;
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152 | c1713132 | balrog | |
153 | c1713132 | balrog | cpu_physical_memory_read(daddr, (uint8_t *) desc, 16);
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154 | c1713132 | balrog | s->chan[ch].descr = desc[DDADR]; |
155 | c1713132 | balrog | s->chan[ch].src = desc[DSADR]; |
156 | c1713132 | balrog | s->chan[ch].dest = desc[DTADR]; |
157 | c1713132 | balrog | s->chan[ch].cmd = desc[DCMD]; |
158 | c1713132 | balrog | |
159 | c1713132 | balrog | if (s->chan[ch].cmd & DCMD_FLOWSRC)
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160 | c1713132 | balrog | s->chan[ch].src &= ~3;
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161 | c1713132 | balrog | if (s->chan[ch].cmd & DCMD_FLOWTRG)
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162 | c1713132 | balrog | s->chan[ch].dest &= ~3;
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163 | c1713132 | balrog | |
164 | c1713132 | balrog | if (s->chan[ch].cmd & (DCMD_CMPEN | DCMD_FLYBYS | DCMD_FLYBYT))
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165 | c1713132 | balrog | printf("%s: unsupported mode in channel %i\n", __FUNCTION__, ch);
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166 | c1713132 | balrog | |
167 | c1713132 | balrog | if (s->chan[ch].cmd & DCMD_STARTIRQEN)
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168 | c1713132 | balrog | s->chan[ch].state |= DCSR_STARTINTR; |
169 | c1713132 | balrog | } |
170 | c1713132 | balrog | |
171 | bc24a225 | Paul Brook | static void pxa2xx_dma_run(PXA2xxDMAState *s) |
172 | c1713132 | balrog | { |
173 | c1713132 | balrog | int c, srcinc, destinc;
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174 | c1713132 | balrog | uint32_t n, size; |
175 | c1713132 | balrog | uint32_t width; |
176 | c1713132 | balrog | uint32_t length; |
177 | b55266b5 | blueswir1 | uint8_t buffer[32];
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178 | bc24a225 | Paul Brook | PXA2xxDMAChannel *ch; |
179 | c1713132 | balrog | |
180 | c1713132 | balrog | if (s->running ++)
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181 | c1713132 | balrog | return;
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182 | c1713132 | balrog | |
183 | c1713132 | balrog | while (s->running) {
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184 | c1713132 | balrog | s->running = 1;
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185 | c1713132 | balrog | for (c = 0; c < s->channels; c ++) { |
186 | c1713132 | balrog | ch = &s->chan[c]; |
187 | c1713132 | balrog | |
188 | c1713132 | balrog | while ((ch->state & DCSR_RUN) && !(ch->state & DCSR_STOPINTR)) {
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189 | c1713132 | balrog | /* Test for pending requests */
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190 | c1713132 | balrog | if ((ch->cmd & (DCMD_FLOWSRC | DCMD_FLOWTRG)) && !ch->request)
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191 | c1713132 | balrog | break;
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192 | c1713132 | balrog | |
193 | c1713132 | balrog | length = ch->cmd & DCMD_LEN; |
194 | c1713132 | balrog | size = DCMD_SIZE(ch->cmd); |
195 | c1713132 | balrog | width = DCMD_WIDTH(ch->cmd); |
196 | c1713132 | balrog | |
197 | c1713132 | balrog | srcinc = (ch->cmd & DCMD_INCSRCADDR) ? width : 0;
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198 | c1713132 | balrog | destinc = (ch->cmd & DCMD_INCTRGADDR) ? width : 0;
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199 | c1713132 | balrog | |
200 | c1713132 | balrog | while (length) {
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201 | c1713132 | balrog | size = MIN(length, size); |
202 | c1713132 | balrog | |
203 | c1713132 | balrog | for (n = 0; n < size; n += width) { |
204 | c1713132 | balrog | cpu_physical_memory_read(ch->src, buffer + n, width); |
205 | c1713132 | balrog | ch->src += srcinc; |
206 | c1713132 | balrog | } |
207 | c1713132 | balrog | |
208 | c1713132 | balrog | for (n = 0; n < size; n += width) { |
209 | c1713132 | balrog | cpu_physical_memory_write(ch->dest, buffer + n, width); |
210 | c1713132 | balrog | ch->dest += destinc; |
211 | c1713132 | balrog | } |
212 | c1713132 | balrog | |
213 | c1713132 | balrog | length -= size; |
214 | c1713132 | balrog | |
215 | c1713132 | balrog | if ((ch->cmd & (DCMD_FLOWSRC | DCMD_FLOWTRG)) &&
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216 | c1713132 | balrog | !ch->request) { |
217 | c1713132 | balrog | ch->state |= DCSR_EORINT; |
218 | c1713132 | balrog | if (ch->state & DCSR_EORSTOPEN)
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219 | c1713132 | balrog | ch->state |= DCSR_STOPINTR; |
220 | c1713132 | balrog | if ((ch->state & DCSR_EORJMPEN) &&
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221 | c1713132 | balrog | !(ch->state & DCSR_NODESCFETCH)) |
222 | c1713132 | balrog | pxa2xx_dma_descriptor_fetch(s, c); |
223 | c1713132 | balrog | break;
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224 | c1713132 | balrog | } |
225 | c1713132 | balrog | } |
226 | c1713132 | balrog | |
227 | c1713132 | balrog | ch->cmd = (ch->cmd & ~DCMD_LEN) | length; |
228 | c1713132 | balrog | |
229 | c1713132 | balrog | /* Is the transfer complete now? */
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230 | c1713132 | balrog | if (!length) {
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231 | c1713132 | balrog | if (ch->cmd & DCMD_ENDIRQEN)
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232 | c1713132 | balrog | ch->state |= DCSR_ENDINTR; |
233 | c1713132 | balrog | |
234 | c1713132 | balrog | if ((ch->state & DCSR_NODESCFETCH) ||
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235 | c1713132 | balrog | (ch->descr & DDADR_STOP) || |
236 | c1713132 | balrog | (ch->state & DCSR_EORSTOPEN)) { |
237 | c1713132 | balrog | ch->state |= DCSR_STOPINTR; |
238 | c1713132 | balrog | ch->state &= ~DCSR_RUN; |
239 | c1713132 | balrog | |
240 | c1713132 | balrog | break;
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241 | c1713132 | balrog | } |
242 | c1713132 | balrog | |
243 | c1713132 | balrog | ch->state |= DCSR_STOPINTR; |
244 | c1713132 | balrog | break;
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245 | c1713132 | balrog | } |
246 | c1713132 | balrog | } |
247 | c1713132 | balrog | } |
248 | c1713132 | balrog | |
249 | c1713132 | balrog | s->running --; |
250 | c1713132 | balrog | } |
251 | c1713132 | balrog | } |
252 | c1713132 | balrog | |
253 | c227f099 | Anthony Liguori | static uint32_t pxa2xx_dma_read(void *opaque, target_phys_addr_t offset) |
254 | c1713132 | balrog | { |
255 | bc24a225 | Paul Brook | PXA2xxDMAState *s = (PXA2xxDMAState *) opaque; |
256 | c1713132 | balrog | unsigned int channel; |
257 | c1713132 | balrog | |
258 | c1713132 | balrog | switch (offset) {
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259 | c1713132 | balrog | case DRCMR64 ... DRCMR74:
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260 | c1713132 | balrog | offset -= DRCMR64 - DRCMR0 - (64 << 2); |
261 | c1713132 | balrog | /* Fall through */
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262 | c1713132 | balrog | case DRCMR0 ... DRCMR63:
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263 | c1713132 | balrog | channel = (offset - DRCMR0) >> 2;
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264 | c1713132 | balrog | return s->req[channel];
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265 | c1713132 | balrog | |
266 | c1713132 | balrog | case DRQSR0:
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267 | c1713132 | balrog | case DRQSR1:
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268 | c1713132 | balrog | case DRQSR2:
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269 | c1713132 | balrog | return 0; |
270 | c1713132 | balrog | |
271 | c1713132 | balrog | case DCSR0 ... DCSR31:
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272 | c1713132 | balrog | channel = offset >> 2;
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273 | c1713132 | balrog | if (s->chan[channel].request)
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274 | c1713132 | balrog | return s->chan[channel].state | DCSR_REQPEND;
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275 | c1713132 | balrog | return s->chan[channel].state;
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276 | c1713132 | balrog | |
277 | c1713132 | balrog | case DINT:
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278 | c1713132 | balrog | return s->stopintr | s->eorintr | s->rasintr |
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279 | c1713132 | balrog | s->startintr | s->endintr; |
280 | c1713132 | balrog | |
281 | c1713132 | balrog | case DALGN:
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282 | c1713132 | balrog | return s->align;
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283 | c1713132 | balrog | |
284 | c1713132 | balrog | case DPCSR:
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285 | c1713132 | balrog | return s->pio;
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286 | c1713132 | balrog | } |
287 | c1713132 | balrog | |
288 | c1713132 | balrog | if (offset >= D_CH0 && offset < D_CH0 + (s->channels << 4)) { |
289 | c1713132 | balrog | channel = (offset - D_CH0) >> 4;
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290 | c1713132 | balrog | switch ((offset & 0x0f) >> 2) { |
291 | c1713132 | balrog | case DDADR:
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292 | c1713132 | balrog | return s->chan[channel].descr;
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293 | c1713132 | balrog | case DSADR:
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294 | c1713132 | balrog | return s->chan[channel].src;
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295 | c1713132 | balrog | case DTADR:
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296 | c1713132 | balrog | return s->chan[channel].dest;
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297 | c1713132 | balrog | case DCMD:
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298 | c1713132 | balrog | return s->chan[channel].cmd;
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299 | c1713132 | balrog | } |
300 | c1713132 | balrog | } |
301 | c1713132 | balrog | |
302 | 2ac71179 | Paul Brook | hw_error("%s: Bad offset 0x" TARGET_FMT_plx "\n", __FUNCTION__, offset); |
303 | c1713132 | balrog | return 7; |
304 | c1713132 | balrog | } |
305 | c1713132 | balrog | |
306 | c1713132 | balrog | static void pxa2xx_dma_write(void *opaque, |
307 | c227f099 | Anthony Liguori | target_phys_addr_t offset, uint32_t value) |
308 | c1713132 | balrog | { |
309 | bc24a225 | Paul Brook | PXA2xxDMAState *s = (PXA2xxDMAState *) opaque; |
310 | c1713132 | balrog | unsigned int channel; |
311 | c1713132 | balrog | |
312 | c1713132 | balrog | switch (offset) {
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313 | c1713132 | balrog | case DRCMR64 ... DRCMR74:
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314 | c1713132 | balrog | offset -= DRCMR64 - DRCMR0 - (64 << 2); |
315 | c1713132 | balrog | /* Fall through */
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316 | c1713132 | balrog | case DRCMR0 ... DRCMR63:
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317 | c1713132 | balrog | channel = (offset - DRCMR0) >> 2;
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318 | c1713132 | balrog | |
319 | c1713132 | balrog | if (value & DRCMR_MAPVLD)
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320 | c1713132 | balrog | if ((value & DRCMR_CHLNUM) > s->channels)
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321 | 2ac71179 | Paul Brook | hw_error("%s: Bad DMA channel %i\n",
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322 | 2ac71179 | Paul Brook | __FUNCTION__, value & DRCMR_CHLNUM); |
323 | c1713132 | balrog | |
324 | c1713132 | balrog | s->req[channel] = value; |
325 | c1713132 | balrog | break;
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326 | c1713132 | balrog | |
327 | c1713132 | balrog | case DRQSR0:
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328 | c1713132 | balrog | case DRQSR1:
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329 | c1713132 | balrog | case DRQSR2:
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330 | c1713132 | balrog | /* Nothing to do */
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331 | c1713132 | balrog | break;
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332 | c1713132 | balrog | |
333 | c1713132 | balrog | case DCSR0 ... DCSR31:
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334 | c1713132 | balrog | channel = offset >> 2;
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335 | c1713132 | balrog | s->chan[channel].state &= 0x0000071f & ~(value &
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336 | c1713132 | balrog | (DCSR_EORINT | DCSR_ENDINTR | |
337 | c1713132 | balrog | DCSR_STARTINTR | DCSR_BUSERRINTR)); |
338 | c1713132 | balrog | s->chan[channel].state |= value & 0xfc800000;
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339 | c1713132 | balrog | |
340 | c1713132 | balrog | if (s->chan[channel].state & DCSR_STOPIRQEN)
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341 | c1713132 | balrog | s->chan[channel].state &= ~DCSR_STOPINTR; |
342 | c1713132 | balrog | |
343 | c1713132 | balrog | if (value & DCSR_NODESCFETCH) {
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344 | c1713132 | balrog | /* No-descriptor-fetch mode */
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345 | e1dad5a6 | balrog | if (value & DCSR_RUN) {
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346 | e1dad5a6 | balrog | s->chan[channel].state &= ~DCSR_STOPINTR; |
347 | c1713132 | balrog | pxa2xx_dma_run(s); |
348 | e1dad5a6 | balrog | } |
349 | c1713132 | balrog | } else {
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350 | c1713132 | balrog | /* Descriptor-fetch mode */
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351 | c1713132 | balrog | if (value & DCSR_RUN) {
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352 | c1713132 | balrog | s->chan[channel].state &= ~DCSR_STOPINTR; |
353 | c1713132 | balrog | pxa2xx_dma_descriptor_fetch(s, channel); |
354 | c1713132 | balrog | pxa2xx_dma_run(s); |
355 | c1713132 | balrog | } |
356 | c1713132 | balrog | } |
357 | c1713132 | balrog | |
358 | c1713132 | balrog | /* Shouldn't matter as our DMA is synchronous. */
|
359 | c1713132 | balrog | if (!(value & (DCSR_RUN | DCSR_MASKRUN)))
|
360 | c1713132 | balrog | s->chan[channel].state |= DCSR_STOPINTR; |
361 | c1713132 | balrog | |
362 | c1713132 | balrog | if (value & DCSR_CLRCMPST)
|
363 | c1713132 | balrog | s->chan[channel].state &= ~DCSR_CMPST; |
364 | c1713132 | balrog | if (value & DCSR_SETCMPST)
|
365 | c1713132 | balrog | s->chan[channel].state |= DCSR_CMPST; |
366 | c1713132 | balrog | |
367 | c1713132 | balrog | pxa2xx_dma_update(s, channel); |
368 | c1713132 | balrog | break;
|
369 | c1713132 | balrog | |
370 | c1713132 | balrog | case DALGN:
|
371 | c1713132 | balrog | s->align = value; |
372 | c1713132 | balrog | break;
|
373 | c1713132 | balrog | |
374 | c1713132 | balrog | case DPCSR:
|
375 | c1713132 | balrog | s->pio = value & 0x80000001;
|
376 | c1713132 | balrog | break;
|
377 | c1713132 | balrog | |
378 | c1713132 | balrog | default:
|
379 | c1713132 | balrog | if (offset >= D_CH0 && offset < D_CH0 + (s->channels << 4)) { |
380 | c1713132 | balrog | channel = (offset - D_CH0) >> 4;
|
381 | c1713132 | balrog | switch ((offset & 0x0f) >> 2) { |
382 | c1713132 | balrog | case DDADR:
|
383 | c1713132 | balrog | s->chan[channel].descr = value; |
384 | c1713132 | balrog | break;
|
385 | c1713132 | balrog | case DSADR:
|
386 | c1713132 | balrog | s->chan[channel].src = value; |
387 | c1713132 | balrog | break;
|
388 | c1713132 | balrog | case DTADR:
|
389 | c1713132 | balrog | s->chan[channel].dest = value; |
390 | c1713132 | balrog | break;
|
391 | c1713132 | balrog | case DCMD:
|
392 | c1713132 | balrog | s->chan[channel].cmd = value; |
393 | c1713132 | balrog | break;
|
394 | c1713132 | balrog | default:
|
395 | c1713132 | balrog | goto fail;
|
396 | c1713132 | balrog | } |
397 | c1713132 | balrog | |
398 | c1713132 | balrog | break;
|
399 | c1713132 | balrog | } |
400 | c1713132 | balrog | fail:
|
401 | 2ac71179 | Paul Brook | hw_error("%s: Bad offset " TARGET_FMT_plx "\n", __FUNCTION__, offset); |
402 | c1713132 | balrog | } |
403 | c1713132 | balrog | } |
404 | c1713132 | balrog | |
405 | c227f099 | Anthony Liguori | static uint32_t pxa2xx_dma_readbad(void *opaque, target_phys_addr_t offset) |
406 | c1713132 | balrog | { |
407 | 2ac71179 | Paul Brook | hw_error("%s: Bad access width\n", __FUNCTION__);
|
408 | c1713132 | balrog | return 5; |
409 | c1713132 | balrog | } |
410 | c1713132 | balrog | |
411 | c1713132 | balrog | static void pxa2xx_dma_writebad(void *opaque, |
412 | c227f099 | Anthony Liguori | target_phys_addr_t offset, uint32_t value) |
413 | c1713132 | balrog | { |
414 | 2ac71179 | Paul Brook | hw_error("%s: Bad access width\n", __FUNCTION__);
|
415 | c1713132 | balrog | } |
416 | c1713132 | balrog | |
417 | d60efc6b | Blue Swirl | static CPUReadMemoryFunc * const pxa2xx_dma_readfn[] = { |
418 | c1713132 | balrog | pxa2xx_dma_readbad, |
419 | c1713132 | balrog | pxa2xx_dma_readbad, |
420 | c1713132 | balrog | pxa2xx_dma_read |
421 | c1713132 | balrog | }; |
422 | c1713132 | balrog | |
423 | d60efc6b | Blue Swirl | static CPUWriteMemoryFunc * const pxa2xx_dma_writefn[] = { |
424 | c1713132 | balrog | pxa2xx_dma_writebad, |
425 | c1713132 | balrog | pxa2xx_dma_writebad, |
426 | c1713132 | balrog | pxa2xx_dma_write |
427 | c1713132 | balrog | }; |
428 | c1713132 | balrog | |
429 | f114c826 | Andrzej Zaborowski | static void pxa2xx_dma_request(void *opaque, int req_num, int on) |
430 | f114c826 | Andrzej Zaborowski | { |
431 | f114c826 | Andrzej Zaborowski | PXA2xxDMAState *s = opaque; |
432 | f114c826 | Andrzej Zaborowski | int ch;
|
433 | f114c826 | Andrzej Zaborowski | if (req_num < 0 || req_num >= PXA2XX_DMA_NUM_REQUESTS) |
434 | f114c826 | Andrzej Zaborowski | hw_error("%s: Bad DMA request %i\n", __FUNCTION__, req_num);
|
435 | f114c826 | Andrzej Zaborowski | |
436 | f114c826 | Andrzej Zaborowski | if (!(s->req[req_num] & DRCMR_MAPVLD))
|
437 | f114c826 | Andrzej Zaborowski | return;
|
438 | f114c826 | Andrzej Zaborowski | ch = s->req[req_num] & DRCMR_CHLNUM; |
439 | f114c826 | Andrzej Zaborowski | |
440 | f114c826 | Andrzej Zaborowski | if (!s->chan[ch].request && on)
|
441 | f114c826 | Andrzej Zaborowski | s->chan[ch].state |= DCSR_RASINTR; |
442 | f114c826 | Andrzej Zaborowski | else
|
443 | f114c826 | Andrzej Zaborowski | s->chan[ch].state &= ~DCSR_RASINTR; |
444 | f114c826 | Andrzej Zaborowski | if (s->chan[ch].request && !on)
|
445 | f114c826 | Andrzej Zaborowski | s->chan[ch].state |= DCSR_EORINT; |
446 | f114c826 | Andrzej Zaborowski | |
447 | f114c826 | Andrzej Zaborowski | s->chan[ch].request = on; |
448 | f114c826 | Andrzej Zaborowski | if (on) {
|
449 | f114c826 | Andrzej Zaborowski | pxa2xx_dma_run(s); |
450 | f114c826 | Andrzej Zaborowski | pxa2xx_dma_update(s, ch); |
451 | f114c826 | Andrzej Zaborowski | } |
452 | f114c826 | Andrzej Zaborowski | } |
453 | aa941b94 | balrog | |
454 | 2115c019 | Andrzej Zaborowski | static int pxa2xx_dma_init(SysBusDevice *dev) |
455 | c1713132 | balrog | { |
456 | c1713132 | balrog | int i, iomemtype;
|
457 | bc24a225 | Paul Brook | PXA2xxDMAState *s; |
458 | 2115c019 | Andrzej Zaborowski | s = FROM_SYSBUS(PXA2xxDMAState, dev); |
459 | 2115c019 | Andrzej Zaborowski | |
460 | 2115c019 | Andrzej Zaborowski | if (s->channels <= 0) { |
461 | 2115c019 | Andrzej Zaborowski | return -1; |
462 | 2115c019 | Andrzej Zaborowski | } |
463 | c1713132 | balrog | |
464 | bc24a225 | Paul Brook | s->chan = qemu_mallocz(sizeof(PXA2xxDMAChannel) * s->channels);
|
465 | c1713132 | balrog | |
466 | bc24a225 | Paul Brook | memset(s->chan, 0, sizeof(PXA2xxDMAChannel) * s->channels); |
467 | c1713132 | balrog | for (i = 0; i < s->channels; i ++) |
468 | c1713132 | balrog | s->chan[i].state = DCSR_STOPINTR; |
469 | c1713132 | balrog | |
470 | 3f582262 | balrog | memset(s->req, 0, sizeof(uint8_t) * PXA2XX_DMA_NUM_REQUESTS); |
471 | c1713132 | balrog | |
472 | 2115c019 | Andrzej Zaborowski | qdev_init_gpio_in(&dev->qdev, pxa2xx_dma_request, PXA2XX_DMA_NUM_REQUESTS); |
473 | 2115c019 | Andrzej Zaborowski | |
474 | 1eed09cb | Avi Kivity | iomemtype = cpu_register_io_memory(pxa2xx_dma_readfn, |
475 | 2507c12a | Alexander Graf | pxa2xx_dma_writefn, s, DEVICE_NATIVE_ENDIAN); |
476 | 2115c019 | Andrzej Zaborowski | sysbus_init_mmio(dev, 0x00010000, iomemtype);
|
477 | 2115c019 | Andrzej Zaborowski | sysbus_init_irq(dev, &s->irq); |
478 | c1713132 | balrog | |
479 | 2115c019 | Andrzej Zaborowski | return 0; |
480 | c1713132 | balrog | } |
481 | c1713132 | balrog | |
482 | 2115c019 | Andrzej Zaborowski | DeviceState *pxa27x_dma_init(target_phys_addr_t base, qemu_irq irq) |
483 | c1713132 | balrog | { |
484 | 2115c019 | Andrzej Zaborowski | DeviceState *dev; |
485 | 2115c019 | Andrzej Zaborowski | |
486 | 2115c019 | Andrzej Zaborowski | dev = qdev_create(NULL, "pxa2xx-dma"); |
487 | 2115c019 | Andrzej Zaborowski | qdev_prop_set_int32(dev, "channels", PXA27X_DMA_NUM_CHANNELS);
|
488 | 2115c019 | Andrzej Zaborowski | qdev_init_nofail(dev); |
489 | 2115c019 | Andrzej Zaborowski | |
490 | 2115c019 | Andrzej Zaborowski | sysbus_mmio_map(sysbus_from_qdev(dev), 0, base);
|
491 | 2115c019 | Andrzej Zaborowski | sysbus_connect_irq(sysbus_from_qdev(dev), 0, irq);
|
492 | 2115c019 | Andrzej Zaborowski | |
493 | 2115c019 | Andrzej Zaborowski | return dev;
|
494 | c1713132 | balrog | } |
495 | c1713132 | balrog | |
496 | 2115c019 | Andrzej Zaborowski | DeviceState *pxa255_dma_init(target_phys_addr_t base, qemu_irq irq) |
497 | c1713132 | balrog | { |
498 | 2115c019 | Andrzej Zaborowski | DeviceState *dev; |
499 | 2115c019 | Andrzej Zaborowski | |
500 | 2115c019 | Andrzej Zaborowski | dev = qdev_create(NULL, "pxa2xx-dma"); |
501 | 2115c019 | Andrzej Zaborowski | qdev_prop_set_int32(dev, "channels", PXA27X_DMA_NUM_CHANNELS);
|
502 | 2115c019 | Andrzej Zaborowski | qdev_init_nofail(dev); |
503 | 2115c019 | Andrzej Zaborowski | |
504 | 2115c019 | Andrzej Zaborowski | sysbus_mmio_map(sysbus_from_qdev(dev), 0, base);
|
505 | 2115c019 | Andrzej Zaborowski | sysbus_connect_irq(sysbus_from_qdev(dev), 0, irq);
|
506 | 2115c019 | Andrzej Zaborowski | |
507 | 2115c019 | Andrzej Zaborowski | return dev;
|
508 | c1713132 | balrog | } |
509 | c1713132 | balrog | |
510 | 2115c019 | Andrzej Zaborowski | static bool is_version_0(void *opaque, int version_id) |
511 | 2115c019 | Andrzej Zaborowski | { |
512 | 2115c019 | Andrzej Zaborowski | return version_id == 0; |
513 | 2115c019 | Andrzej Zaborowski | } |
514 | 2115c019 | Andrzej Zaborowski | |
515 | 2115c019 | Andrzej Zaborowski | static VMStateDescription vmstate_pxa2xx_dma_chan = {
|
516 | 2115c019 | Andrzej Zaborowski | .name = "pxa2xx_dma_chan",
|
517 | 2115c019 | Andrzej Zaborowski | .version_id = 1,
|
518 | 2115c019 | Andrzej Zaborowski | .minimum_version_id = 1,
|
519 | 2115c019 | Andrzej Zaborowski | .minimum_version_id_old = 1,
|
520 | 2115c019 | Andrzej Zaborowski | .fields = (VMStateField[]) { |
521 | 2115c019 | Andrzej Zaborowski | VMSTATE_UINTTL(descr, PXA2xxDMAChannel), |
522 | 2115c019 | Andrzej Zaborowski | VMSTATE_UINTTL(src, PXA2xxDMAChannel), |
523 | 2115c019 | Andrzej Zaborowski | VMSTATE_UINTTL(dest, PXA2xxDMAChannel), |
524 | 2115c019 | Andrzej Zaborowski | VMSTATE_UINT32(cmd, PXA2xxDMAChannel), |
525 | 2115c019 | Andrzej Zaborowski | VMSTATE_UINT32(state, PXA2xxDMAChannel), |
526 | 2115c019 | Andrzej Zaborowski | VMSTATE_INT32(request, PXA2xxDMAChannel), |
527 | 2115c019 | Andrzej Zaborowski | VMSTATE_END_OF_LIST(), |
528 | 2115c019 | Andrzej Zaborowski | }, |
529 | 2115c019 | Andrzej Zaborowski | }; |
530 | 2115c019 | Andrzej Zaborowski | |
531 | 2115c019 | Andrzej Zaborowski | static VMStateDescription vmstate_pxa2xx_dma = {
|
532 | 2115c019 | Andrzej Zaborowski | .name = "pxa2xx_dma",
|
533 | 2115c019 | Andrzej Zaborowski | .version_id = 1,
|
534 | 2115c019 | Andrzej Zaborowski | .minimum_version_id = 0,
|
535 | 2115c019 | Andrzej Zaborowski | .minimum_version_id_old = 0,
|
536 | 2115c019 | Andrzej Zaborowski | .fields = (VMStateField[]) { |
537 | 2115c019 | Andrzej Zaborowski | VMSTATE_UNUSED_TEST(is_version_0, 4),
|
538 | 2115c019 | Andrzej Zaborowski | VMSTATE_UINT32(stopintr, PXA2xxDMAState), |
539 | 2115c019 | Andrzej Zaborowski | VMSTATE_UINT32(eorintr, PXA2xxDMAState), |
540 | 2115c019 | Andrzej Zaborowski | VMSTATE_UINT32(rasintr, PXA2xxDMAState), |
541 | 2115c019 | Andrzej Zaborowski | VMSTATE_UINT32(startintr, PXA2xxDMAState), |
542 | 2115c019 | Andrzej Zaborowski | VMSTATE_UINT32(endintr, PXA2xxDMAState), |
543 | 2115c019 | Andrzej Zaborowski | VMSTATE_UINT32(align, PXA2xxDMAState), |
544 | 2115c019 | Andrzej Zaborowski | VMSTATE_UINT32(pio, PXA2xxDMAState), |
545 | 2115c019 | Andrzej Zaborowski | VMSTATE_BUFFER(req, PXA2xxDMAState), |
546 | 2115c019 | Andrzej Zaborowski | VMSTATE_STRUCT_VARRAY_POINTER_INT32(chan, PXA2xxDMAState, channels, |
547 | 2115c019 | Andrzej Zaborowski | vmstate_pxa2xx_dma_chan, PXA2xxDMAChannel), |
548 | 2115c019 | Andrzej Zaborowski | VMSTATE_END_OF_LIST(), |
549 | 2115c019 | Andrzej Zaborowski | }, |
550 | 2115c019 | Andrzej Zaborowski | }; |
551 | 2115c019 | Andrzej Zaborowski | |
552 | 2115c019 | Andrzej Zaborowski | static SysBusDeviceInfo pxa2xx_dma_info = {
|
553 | 2115c019 | Andrzej Zaborowski | .init = pxa2xx_dma_init, |
554 | 2115c019 | Andrzej Zaborowski | .qdev.name = "pxa2xx-dma",
|
555 | 2115c019 | Andrzej Zaborowski | .qdev.desc = "PXA2xx DMA controller",
|
556 | 2115c019 | Andrzej Zaborowski | .qdev.size = sizeof(PXA2xxDMAState),
|
557 | 2115c019 | Andrzej Zaborowski | .qdev.vmsd = &vmstate_pxa2xx_dma, |
558 | 2115c019 | Andrzej Zaborowski | .qdev.props = (Property[]) { |
559 | 2115c019 | Andrzej Zaborowski | DEFINE_PROP_INT32("channels", PXA2xxDMAState, channels, -1), |
560 | 2115c019 | Andrzej Zaborowski | DEFINE_PROP_END_OF_LIST(), |
561 | 2115c019 | Andrzej Zaborowski | }, |
562 | 2115c019 | Andrzej Zaborowski | }; |
563 | 2115c019 | Andrzej Zaborowski | |
564 | 2115c019 | Andrzej Zaborowski | static void pxa2xx_dma_register(void) |
565 | 2115c019 | Andrzej Zaborowski | { |
566 | 2115c019 | Andrzej Zaborowski | sysbus_register_withprop(&pxa2xx_dma_info); |
567 | 2115c019 | Andrzej Zaborowski | } |
568 | 2115c019 | Andrzej Zaborowski | device_init(pxa2xx_dma_register); |