root / hw / rc4030.c @ d2d979c6
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1 | 4ce7ff6e | aurel32 | /*
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2 | 4ce7ff6e | aurel32 | * QEMU JAZZ RC4030 chipset
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3 | 4ce7ff6e | aurel32 | *
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4 | 9ea0b7a1 | aurel32 | * Copyright (c) 2007-2009 Herve Poussineau
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5 | 4ce7ff6e | aurel32 | *
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6 | 4ce7ff6e | aurel32 | * Permission is hereby granted, free of charge, to any person obtaining a copy
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7 | 4ce7ff6e | aurel32 | * of this software and associated documentation files (the "Software"), to deal
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8 | 4ce7ff6e | aurel32 | * in the Software without restriction, including without limitation the rights
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9 | 4ce7ff6e | aurel32 | * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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10 | 4ce7ff6e | aurel32 | * copies of the Software, and to permit persons to whom the Software is
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11 | 4ce7ff6e | aurel32 | * furnished to do so, subject to the following conditions:
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12 | 4ce7ff6e | aurel32 | *
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13 | 4ce7ff6e | aurel32 | * The above copyright notice and this permission notice shall be included in
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14 | 4ce7ff6e | aurel32 | * all copies or substantial portions of the Software.
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15 | 4ce7ff6e | aurel32 | *
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16 | 4ce7ff6e | aurel32 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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17 | 4ce7ff6e | aurel32 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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18 | 4ce7ff6e | aurel32 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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19 | 4ce7ff6e | aurel32 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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20 | 4ce7ff6e | aurel32 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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21 | 4ce7ff6e | aurel32 | * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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22 | 4ce7ff6e | aurel32 | * THE SOFTWARE.
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23 | 4ce7ff6e | aurel32 | */
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24 | 4ce7ff6e | aurel32 | |
25 | 4ce7ff6e | aurel32 | #include "hw.h" |
26 | cd5158ea | aurel32 | #include "mips.h" |
27 | 4ce7ff6e | aurel32 | #include "qemu-timer.h" |
28 | 4ce7ff6e | aurel32 | |
29 | c6945b15 | aurel32 | /********************************************************/
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30 | c6945b15 | aurel32 | /* debug rc4030 */
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31 | c6945b15 | aurel32 | |
32 | 4ce7ff6e | aurel32 | //#define DEBUG_RC4030
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33 | c6945b15 | aurel32 | //#define DEBUG_RC4030_DMA
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34 | 4ce7ff6e | aurel32 | |
35 | 4ce7ff6e | aurel32 | #ifdef DEBUG_RC4030
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36 | 001faf32 | Blue Swirl | #define DPRINTF(fmt, ...) \
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37 | 001faf32 | Blue Swirl | do { printf("rc4030: " fmt , ## __VA_ARGS__); } while (0) |
38 | 4ce7ff6e | aurel32 | static const char* irq_names[] = { "parallel", "floppy", "sound", "video", |
39 | 4ce7ff6e | aurel32 | "network", "scsi", "keyboard", "mouse", "serial0", "serial1" }; |
40 | c6945b15 | aurel32 | #else
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41 | 001faf32 | Blue Swirl | #define DPRINTF(fmt, ...)
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42 | 4ce7ff6e | aurel32 | #endif
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43 | 4ce7ff6e | aurel32 | |
44 | 001faf32 | Blue Swirl | #define RC4030_ERROR(fmt, ...) \
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45 | 001faf32 | Blue Swirl | do { fprintf(stderr, "rc4030 ERROR: %s: " fmt, __func__ , ## __VA_ARGS__); } while (0) |
46 | c6945b15 | aurel32 | |
47 | c6945b15 | aurel32 | /********************************************************/
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48 | c6945b15 | aurel32 | /* rc4030 emulation */
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49 | c6945b15 | aurel32 | |
50 | c6945b15 | aurel32 | typedef struct dma_pagetable_entry { |
51 | c6945b15 | aurel32 | int32_t frame; |
52 | c6945b15 | aurel32 | int32_t owner; |
53 | c6945b15 | aurel32 | } __attribute__((packed)) dma_pagetable_entry; |
54 | c6945b15 | aurel32 | |
55 | c6945b15 | aurel32 | #define DMA_PAGESIZE 4096 |
56 | c6945b15 | aurel32 | #define DMA_REG_ENABLE 1 |
57 | c6945b15 | aurel32 | #define DMA_REG_COUNT 2 |
58 | c6945b15 | aurel32 | #define DMA_REG_ADDRESS 3 |
59 | c6945b15 | aurel32 | |
60 | c6945b15 | aurel32 | #define DMA_FLAG_ENABLE 0x0001 |
61 | c6945b15 | aurel32 | #define DMA_FLAG_MEM_TO_DEV 0x0002 |
62 | c6945b15 | aurel32 | #define DMA_FLAG_TC_INTR 0x0100 |
63 | c6945b15 | aurel32 | #define DMA_FLAG_MEM_INTR 0x0200 |
64 | c6945b15 | aurel32 | #define DMA_FLAG_ADDR_INTR 0x0400 |
65 | c6945b15 | aurel32 | |
66 | 4ce7ff6e | aurel32 | typedef struct rc4030State |
67 | 4ce7ff6e | aurel32 | { |
68 | 4ce7ff6e | aurel32 | uint32_t config; /* 0x0000: RC4030 config register */
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69 | 9ea0b7a1 | aurel32 | uint32_t revision; /* 0x0008: RC4030 Revision register */
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70 | 4ce7ff6e | aurel32 | uint32_t invalid_address_register; /* 0x0010: Invalid Address register */
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71 | 4ce7ff6e | aurel32 | |
72 | 4ce7ff6e | aurel32 | /* DMA */
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73 | 4ce7ff6e | aurel32 | uint32_t dma_regs[8][4]; |
74 | 4ce7ff6e | aurel32 | uint32_t dma_tl_base; /* 0x0018: DMA transl. table base */
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75 | 4ce7ff6e | aurel32 | uint32_t dma_tl_limit; /* 0x0020: DMA transl. table limit */
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76 | 4ce7ff6e | aurel32 | |
77 | 4ce7ff6e | aurel32 | /* cache */
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78 | 9ea0b7a1 | aurel32 | uint32_t cache_maint; /* 0x0030: Cache Maintenance */
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79 | 4ce7ff6e | aurel32 | uint32_t remote_failed_address; /* 0x0038: Remote Failed Address */
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80 | 4ce7ff6e | aurel32 | uint32_t memory_failed_address; /* 0x0040: Memory Failed Address */
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81 | 4ce7ff6e | aurel32 | uint32_t cache_ptag; /* 0x0048: I/O Cache Physical Tag */
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82 | 4ce7ff6e | aurel32 | uint32_t cache_ltag; /* 0x0050: I/O Cache Logical Tag */
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83 | 4ce7ff6e | aurel32 | uint32_t cache_bmask; /* 0x0058: I/O Cache Byte Mask */
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84 | 4ce7ff6e | aurel32 | |
85 | 9ea0b7a1 | aurel32 | uint32_t nmi_interrupt; /* 0x0200: interrupt source */
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86 | 4ce7ff6e | aurel32 | uint32_t offset210; |
87 | 4ce7ff6e | aurel32 | uint32_t nvram_protect; /* 0x0220: NV ram protect register */
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88 | 9ea0b7a1 | aurel32 | uint32_t rem_speed[16];
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89 | 4ce7ff6e | aurel32 | uint32_t imr_jazz; /* Local bus int enable mask */
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90 | 4ce7ff6e | aurel32 | uint32_t isr_jazz; /* Local bus int source */
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91 | 4ce7ff6e | aurel32 | |
92 | 4ce7ff6e | aurel32 | /* timer */
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93 | 4ce7ff6e | aurel32 | QEMUTimer *periodic_timer; |
94 | 4ce7ff6e | aurel32 | uint32_t itr; /* Interval timer reload */
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95 | 4ce7ff6e | aurel32 | |
96 | 4ce7ff6e | aurel32 | qemu_irq timer_irq; |
97 | 4ce7ff6e | aurel32 | qemu_irq jazz_bus_irq; |
98 | 4ce7ff6e | aurel32 | } rc4030State; |
99 | 4ce7ff6e | aurel32 | |
100 | 4ce7ff6e | aurel32 | static void set_next_tick(rc4030State *s) |
101 | 4ce7ff6e | aurel32 | { |
102 | 4ce7ff6e | aurel32 | qemu_irq_lower(s->timer_irq); |
103 | b0f74c87 | balrog | uint32_t tm_hz; |
104 | 4ce7ff6e | aurel32 | |
105 | b0f74c87 | balrog | tm_hz = 1000 / (s->itr + 1); |
106 | 4ce7ff6e | aurel32 | |
107 | 74475455 | Paolo Bonzini | qemu_mod_timer(s->periodic_timer, qemu_get_clock_ns(vm_clock) + |
108 | 6ee093c9 | Juan Quintela | get_ticks_per_sec() / tm_hz); |
109 | 4ce7ff6e | aurel32 | } |
110 | 4ce7ff6e | aurel32 | |
111 | 4ce7ff6e | aurel32 | /* called for accesses to rc4030 */
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112 | c227f099 | Anthony Liguori | static uint32_t rc4030_readl(void *opaque, target_phys_addr_t addr) |
113 | 4ce7ff6e | aurel32 | { |
114 | 4ce7ff6e | aurel32 | rc4030State *s = opaque; |
115 | 4ce7ff6e | aurel32 | uint32_t val; |
116 | 4ce7ff6e | aurel32 | |
117 | 4ce7ff6e | aurel32 | addr &= 0x3fff;
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118 | 4ce7ff6e | aurel32 | switch (addr & ~0x3) { |
119 | 4ce7ff6e | aurel32 | /* Global config register */
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120 | 4ce7ff6e | aurel32 | case 0x0000: |
121 | 4ce7ff6e | aurel32 | val = s->config; |
122 | 4ce7ff6e | aurel32 | break;
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123 | 9ea0b7a1 | aurel32 | /* Revision register */
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124 | 9ea0b7a1 | aurel32 | case 0x0008: |
125 | 9ea0b7a1 | aurel32 | val = s->revision; |
126 | 9ea0b7a1 | aurel32 | break;
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127 | 4ce7ff6e | aurel32 | /* Invalid Address register */
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128 | 4ce7ff6e | aurel32 | case 0x0010: |
129 | 4ce7ff6e | aurel32 | val = s->invalid_address_register; |
130 | 4ce7ff6e | aurel32 | break;
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131 | 4ce7ff6e | aurel32 | /* DMA transl. table base */
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132 | 4ce7ff6e | aurel32 | case 0x0018: |
133 | 4ce7ff6e | aurel32 | val = s->dma_tl_base; |
134 | 4ce7ff6e | aurel32 | break;
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135 | 4ce7ff6e | aurel32 | /* DMA transl. table limit */
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136 | 4ce7ff6e | aurel32 | case 0x0020: |
137 | 4ce7ff6e | aurel32 | val = s->dma_tl_limit; |
138 | 4ce7ff6e | aurel32 | break;
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139 | 4ce7ff6e | aurel32 | /* Remote Failed Address */
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140 | 4ce7ff6e | aurel32 | case 0x0038: |
141 | 4ce7ff6e | aurel32 | val = s->remote_failed_address; |
142 | 4ce7ff6e | aurel32 | break;
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143 | 4ce7ff6e | aurel32 | /* Memory Failed Address */
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144 | 4ce7ff6e | aurel32 | case 0x0040: |
145 | 4ce7ff6e | aurel32 | val = s->memory_failed_address; |
146 | 4ce7ff6e | aurel32 | break;
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147 | 4ce7ff6e | aurel32 | /* I/O Cache Byte Mask */
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148 | 4ce7ff6e | aurel32 | case 0x0058: |
149 | 4ce7ff6e | aurel32 | val = s->cache_bmask; |
150 | 4ce7ff6e | aurel32 | /* HACK */
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151 | 4ce7ff6e | aurel32 | if (s->cache_bmask == (uint32_t)-1) |
152 | 4ce7ff6e | aurel32 | s->cache_bmask = 0;
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153 | 4ce7ff6e | aurel32 | break;
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154 | 4ce7ff6e | aurel32 | /* Remote Speed Registers */
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155 | 4ce7ff6e | aurel32 | case 0x0070: |
156 | 4ce7ff6e | aurel32 | case 0x0078: |
157 | 4ce7ff6e | aurel32 | case 0x0080: |
158 | 4ce7ff6e | aurel32 | case 0x0088: |
159 | 4ce7ff6e | aurel32 | case 0x0090: |
160 | 4ce7ff6e | aurel32 | case 0x0098: |
161 | 4ce7ff6e | aurel32 | case 0x00a0: |
162 | 4ce7ff6e | aurel32 | case 0x00a8: |
163 | 4ce7ff6e | aurel32 | case 0x00b0: |
164 | 4ce7ff6e | aurel32 | case 0x00b8: |
165 | 4ce7ff6e | aurel32 | case 0x00c0: |
166 | 4ce7ff6e | aurel32 | case 0x00c8: |
167 | 4ce7ff6e | aurel32 | case 0x00d0: |
168 | 4ce7ff6e | aurel32 | case 0x00d8: |
169 | 4ce7ff6e | aurel32 | case 0x00e0: |
170 | 9ea0b7a1 | aurel32 | case 0x00e8: |
171 | 4ce7ff6e | aurel32 | val = s->rem_speed[(addr - 0x0070) >> 3]; |
172 | 4ce7ff6e | aurel32 | break;
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173 | 4ce7ff6e | aurel32 | /* DMA channel base address */
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174 | 4ce7ff6e | aurel32 | case 0x0100: |
175 | 4ce7ff6e | aurel32 | case 0x0108: |
176 | 4ce7ff6e | aurel32 | case 0x0110: |
177 | 4ce7ff6e | aurel32 | case 0x0118: |
178 | 4ce7ff6e | aurel32 | case 0x0120: |
179 | 4ce7ff6e | aurel32 | case 0x0128: |
180 | 4ce7ff6e | aurel32 | case 0x0130: |
181 | 4ce7ff6e | aurel32 | case 0x0138: |
182 | 4ce7ff6e | aurel32 | case 0x0140: |
183 | 4ce7ff6e | aurel32 | case 0x0148: |
184 | 4ce7ff6e | aurel32 | case 0x0150: |
185 | 4ce7ff6e | aurel32 | case 0x0158: |
186 | 4ce7ff6e | aurel32 | case 0x0160: |
187 | 4ce7ff6e | aurel32 | case 0x0168: |
188 | 4ce7ff6e | aurel32 | case 0x0170: |
189 | 4ce7ff6e | aurel32 | case 0x0178: |
190 | 4ce7ff6e | aurel32 | case 0x0180: |
191 | 4ce7ff6e | aurel32 | case 0x0188: |
192 | 4ce7ff6e | aurel32 | case 0x0190: |
193 | 4ce7ff6e | aurel32 | case 0x0198: |
194 | 4ce7ff6e | aurel32 | case 0x01a0: |
195 | 4ce7ff6e | aurel32 | case 0x01a8: |
196 | 4ce7ff6e | aurel32 | case 0x01b0: |
197 | 4ce7ff6e | aurel32 | case 0x01b8: |
198 | 4ce7ff6e | aurel32 | case 0x01c0: |
199 | 4ce7ff6e | aurel32 | case 0x01c8: |
200 | 4ce7ff6e | aurel32 | case 0x01d0: |
201 | 4ce7ff6e | aurel32 | case 0x01d8: |
202 | 4ce7ff6e | aurel32 | case 0x01e0: |
203 | c6945b15 | aurel32 | case 0x01e8: |
204 | 4ce7ff6e | aurel32 | case 0x01f0: |
205 | 4ce7ff6e | aurel32 | case 0x01f8: |
206 | 4ce7ff6e | aurel32 | { |
207 | 4ce7ff6e | aurel32 | int entry = (addr - 0x0100) >> 5; |
208 | 4ce7ff6e | aurel32 | int idx = (addr & 0x1f) >> 3; |
209 | 4ce7ff6e | aurel32 | val = s->dma_regs[entry][idx]; |
210 | 4ce7ff6e | aurel32 | } |
211 | 4ce7ff6e | aurel32 | break;
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212 | 9ea0b7a1 | aurel32 | /* Interrupt source */
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213 | 9ea0b7a1 | aurel32 | case 0x0200: |
214 | 9ea0b7a1 | aurel32 | val = s->nmi_interrupt; |
215 | 9ea0b7a1 | aurel32 | break;
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216 | 9ea0b7a1 | aurel32 | /* Error type */
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217 | 4ce7ff6e | aurel32 | case 0x0208: |
218 | c6945b15 | aurel32 | val = 0;
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219 | 4ce7ff6e | aurel32 | break;
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220 | 4ce7ff6e | aurel32 | /* Offset 0x0210 */
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221 | 4ce7ff6e | aurel32 | case 0x0210: |
222 | 4ce7ff6e | aurel32 | val = s->offset210; |
223 | 4ce7ff6e | aurel32 | break;
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224 | 4ce7ff6e | aurel32 | /* NV ram protect register */
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225 | 4ce7ff6e | aurel32 | case 0x0220: |
226 | 4ce7ff6e | aurel32 | val = s->nvram_protect; |
227 | 4ce7ff6e | aurel32 | break;
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228 | 4ce7ff6e | aurel32 | /* Interval timer count */
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229 | 4ce7ff6e | aurel32 | case 0x0230: |
230 | c6945b15 | aurel32 | val = 0;
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231 | 4ce7ff6e | aurel32 | qemu_irq_lower(s->timer_irq); |
232 | 4ce7ff6e | aurel32 | break;
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233 | 9ea0b7a1 | aurel32 | /* EISA interrupt */
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234 | 4ce7ff6e | aurel32 | case 0x0238: |
235 | 9ea0b7a1 | aurel32 | val = 7; /* FIXME: should be read from EISA controller */ |
236 | 4ce7ff6e | aurel32 | break;
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237 | 4ce7ff6e | aurel32 | default:
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238 | c6945b15 | aurel32 | RC4030_ERROR("invalid read [" TARGET_FMT_plx "]\n", addr); |
239 | 4ce7ff6e | aurel32 | val = 0;
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240 | 4ce7ff6e | aurel32 | break;
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241 | 4ce7ff6e | aurel32 | } |
242 | 4ce7ff6e | aurel32 | |
243 | 4aa720f7 | Blue Swirl | if ((addr & ~3) != 0x230) { |
244 | c6945b15 | aurel32 | DPRINTF("read 0x%02x at " TARGET_FMT_plx "\n", val, addr); |
245 | 4aa720f7 | Blue Swirl | } |
246 | 4ce7ff6e | aurel32 | |
247 | 4ce7ff6e | aurel32 | return val;
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248 | 4ce7ff6e | aurel32 | } |
249 | 4ce7ff6e | aurel32 | |
250 | c227f099 | Anthony Liguori | static uint32_t rc4030_readw(void *opaque, target_phys_addr_t addr) |
251 | 4ce7ff6e | aurel32 | { |
252 | 4ce7ff6e | aurel32 | uint32_t v = rc4030_readl(opaque, addr & ~0x3);
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253 | 4ce7ff6e | aurel32 | if (addr & 0x2) |
254 | 4ce7ff6e | aurel32 | return v >> 16; |
255 | 4ce7ff6e | aurel32 | else
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256 | 4ce7ff6e | aurel32 | return v & 0xffff; |
257 | 4ce7ff6e | aurel32 | } |
258 | 4ce7ff6e | aurel32 | |
259 | c227f099 | Anthony Liguori | static uint32_t rc4030_readb(void *opaque, target_phys_addr_t addr) |
260 | 4ce7ff6e | aurel32 | { |
261 | 4ce7ff6e | aurel32 | uint32_t v = rc4030_readl(opaque, addr & ~0x3);
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262 | 4ce7ff6e | aurel32 | return (v >> (8 * (addr & 0x3))) & 0xff; |
263 | 4ce7ff6e | aurel32 | } |
264 | 4ce7ff6e | aurel32 | |
265 | c227f099 | Anthony Liguori | static void rc4030_writel(void *opaque, target_phys_addr_t addr, uint32_t val) |
266 | 4ce7ff6e | aurel32 | { |
267 | 4ce7ff6e | aurel32 | rc4030State *s = opaque; |
268 | 4ce7ff6e | aurel32 | addr &= 0x3fff;
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269 | 4ce7ff6e | aurel32 | |
270 | c6945b15 | aurel32 | DPRINTF("write 0x%02x at " TARGET_FMT_plx "\n", val, addr); |
271 | 4ce7ff6e | aurel32 | |
272 | 4ce7ff6e | aurel32 | switch (addr & ~0x3) { |
273 | 4ce7ff6e | aurel32 | /* Global config register */
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274 | 4ce7ff6e | aurel32 | case 0x0000: |
275 | 4ce7ff6e | aurel32 | s->config = val; |
276 | 4ce7ff6e | aurel32 | break;
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277 | 4ce7ff6e | aurel32 | /* DMA transl. table base */
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278 | 4ce7ff6e | aurel32 | case 0x0018: |
279 | 4ce7ff6e | aurel32 | s->dma_tl_base = val; |
280 | 4ce7ff6e | aurel32 | break;
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281 | 4ce7ff6e | aurel32 | /* DMA transl. table limit */
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282 | 4ce7ff6e | aurel32 | case 0x0020: |
283 | 4ce7ff6e | aurel32 | s->dma_tl_limit = val; |
284 | 4ce7ff6e | aurel32 | break;
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285 | c6945b15 | aurel32 | /* DMA transl. table invalidated */
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286 | c6945b15 | aurel32 | case 0x0028: |
287 | c6945b15 | aurel32 | break;
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288 | c6945b15 | aurel32 | /* Cache Maintenance */
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289 | c6945b15 | aurel32 | case 0x0030: |
290 | 9ea0b7a1 | aurel32 | s->cache_maint = val; |
291 | c6945b15 | aurel32 | break;
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292 | 4ce7ff6e | aurel32 | /* I/O Cache Physical Tag */
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293 | 4ce7ff6e | aurel32 | case 0x0048: |
294 | 4ce7ff6e | aurel32 | s->cache_ptag = val; |
295 | 4ce7ff6e | aurel32 | break;
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296 | 4ce7ff6e | aurel32 | /* I/O Cache Logical Tag */
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297 | 4ce7ff6e | aurel32 | case 0x0050: |
298 | 4ce7ff6e | aurel32 | s->cache_ltag = val; |
299 | 4ce7ff6e | aurel32 | break;
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300 | 4ce7ff6e | aurel32 | /* I/O Cache Byte Mask */
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301 | 4ce7ff6e | aurel32 | case 0x0058: |
302 | 4ce7ff6e | aurel32 | s->cache_bmask |= val; /* HACK */
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303 | 4ce7ff6e | aurel32 | break;
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304 | 4ce7ff6e | aurel32 | /* I/O Cache Buffer Window */
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305 | 4ce7ff6e | aurel32 | case 0x0060: |
306 | 4ce7ff6e | aurel32 | /* HACK */
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307 | 4ce7ff6e | aurel32 | if (s->cache_ltag == 0x80000001 && s->cache_bmask == 0xf0f0f0f) { |
308 | c227f099 | Anthony Liguori | target_phys_addr_t dest = s->cache_ptag & ~0x1;
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309 | 9ea0b7a1 | aurel32 | dest += (s->cache_maint & 0x3) << 3; |
310 | 54f7b4a3 | Stefan Weil | cpu_physical_memory_write(dest, &val, 4);
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311 | 4ce7ff6e | aurel32 | } |
312 | 4ce7ff6e | aurel32 | break;
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313 | 4ce7ff6e | aurel32 | /* Remote Speed Registers */
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314 | 4ce7ff6e | aurel32 | case 0x0070: |
315 | 4ce7ff6e | aurel32 | case 0x0078: |
316 | 4ce7ff6e | aurel32 | case 0x0080: |
317 | 4ce7ff6e | aurel32 | case 0x0088: |
318 | 4ce7ff6e | aurel32 | case 0x0090: |
319 | 4ce7ff6e | aurel32 | case 0x0098: |
320 | 4ce7ff6e | aurel32 | case 0x00a0: |
321 | 4ce7ff6e | aurel32 | case 0x00a8: |
322 | 4ce7ff6e | aurel32 | case 0x00b0: |
323 | 4ce7ff6e | aurel32 | case 0x00b8: |
324 | 4ce7ff6e | aurel32 | case 0x00c0: |
325 | 4ce7ff6e | aurel32 | case 0x00c8: |
326 | 4ce7ff6e | aurel32 | case 0x00d0: |
327 | 4ce7ff6e | aurel32 | case 0x00d8: |
328 | 4ce7ff6e | aurel32 | case 0x00e0: |
329 | 9ea0b7a1 | aurel32 | case 0x00e8: |
330 | 4ce7ff6e | aurel32 | s->rem_speed[(addr - 0x0070) >> 3] = val; |
331 | 4ce7ff6e | aurel32 | break;
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332 | 4ce7ff6e | aurel32 | /* DMA channel base address */
|
333 | 4ce7ff6e | aurel32 | case 0x0100: |
334 | 4ce7ff6e | aurel32 | case 0x0108: |
335 | 4ce7ff6e | aurel32 | case 0x0110: |
336 | 4ce7ff6e | aurel32 | case 0x0118: |
337 | 4ce7ff6e | aurel32 | case 0x0120: |
338 | 4ce7ff6e | aurel32 | case 0x0128: |
339 | 4ce7ff6e | aurel32 | case 0x0130: |
340 | 4ce7ff6e | aurel32 | case 0x0138: |
341 | 4ce7ff6e | aurel32 | case 0x0140: |
342 | 4ce7ff6e | aurel32 | case 0x0148: |
343 | 4ce7ff6e | aurel32 | case 0x0150: |
344 | 4ce7ff6e | aurel32 | case 0x0158: |
345 | 4ce7ff6e | aurel32 | case 0x0160: |
346 | 4ce7ff6e | aurel32 | case 0x0168: |
347 | 4ce7ff6e | aurel32 | case 0x0170: |
348 | 4ce7ff6e | aurel32 | case 0x0178: |
349 | 4ce7ff6e | aurel32 | case 0x0180: |
350 | 4ce7ff6e | aurel32 | case 0x0188: |
351 | 4ce7ff6e | aurel32 | case 0x0190: |
352 | 4ce7ff6e | aurel32 | case 0x0198: |
353 | 4ce7ff6e | aurel32 | case 0x01a0: |
354 | 4ce7ff6e | aurel32 | case 0x01a8: |
355 | 4ce7ff6e | aurel32 | case 0x01b0: |
356 | 4ce7ff6e | aurel32 | case 0x01b8: |
357 | 4ce7ff6e | aurel32 | case 0x01c0: |
358 | 4ce7ff6e | aurel32 | case 0x01c8: |
359 | 4ce7ff6e | aurel32 | case 0x01d0: |
360 | 4ce7ff6e | aurel32 | case 0x01d8: |
361 | 4ce7ff6e | aurel32 | case 0x01e0: |
362 | c6945b15 | aurel32 | case 0x01e8: |
363 | 4ce7ff6e | aurel32 | case 0x01f0: |
364 | 4ce7ff6e | aurel32 | case 0x01f8: |
365 | 4ce7ff6e | aurel32 | { |
366 | 4ce7ff6e | aurel32 | int entry = (addr - 0x0100) >> 5; |
367 | 4ce7ff6e | aurel32 | int idx = (addr & 0x1f) >> 3; |
368 | 4ce7ff6e | aurel32 | s->dma_regs[entry][idx] = val; |
369 | 4ce7ff6e | aurel32 | } |
370 | 4ce7ff6e | aurel32 | break;
|
371 | 4ce7ff6e | aurel32 | /* Offset 0x0210 */
|
372 | 4ce7ff6e | aurel32 | case 0x0210: |
373 | 4ce7ff6e | aurel32 | s->offset210 = val; |
374 | 4ce7ff6e | aurel32 | break;
|
375 | 4ce7ff6e | aurel32 | /* Interval timer reload */
|
376 | 4ce7ff6e | aurel32 | case 0x0228: |
377 | 4ce7ff6e | aurel32 | s->itr = val; |
378 | 4ce7ff6e | aurel32 | qemu_irq_lower(s->timer_irq); |
379 | 4ce7ff6e | aurel32 | set_next_tick(s); |
380 | 4ce7ff6e | aurel32 | break;
|
381 | 9ea0b7a1 | aurel32 | /* EISA interrupt */
|
382 | 9ea0b7a1 | aurel32 | case 0x0238: |
383 | 9ea0b7a1 | aurel32 | break;
|
384 | 4ce7ff6e | aurel32 | default:
|
385 | c6945b15 | aurel32 | RC4030_ERROR("invalid write of 0x%02x at [" TARGET_FMT_plx "]\n", val, addr); |
386 | 4ce7ff6e | aurel32 | break;
|
387 | 4ce7ff6e | aurel32 | } |
388 | 4ce7ff6e | aurel32 | } |
389 | 4ce7ff6e | aurel32 | |
390 | c227f099 | Anthony Liguori | static void rc4030_writew(void *opaque, target_phys_addr_t addr, uint32_t val) |
391 | 4ce7ff6e | aurel32 | { |
392 | 4ce7ff6e | aurel32 | uint32_t old_val = rc4030_readl(opaque, addr & ~0x3);
|
393 | 4ce7ff6e | aurel32 | |
394 | 4ce7ff6e | aurel32 | if (addr & 0x2) |
395 | 4ce7ff6e | aurel32 | val = (val << 16) | (old_val & 0x0000ffff); |
396 | 4ce7ff6e | aurel32 | else
|
397 | 4ce7ff6e | aurel32 | val = val | (old_val & 0xffff0000);
|
398 | 4ce7ff6e | aurel32 | rc4030_writel(opaque, addr & ~0x3, val);
|
399 | 4ce7ff6e | aurel32 | } |
400 | 4ce7ff6e | aurel32 | |
401 | c227f099 | Anthony Liguori | static void rc4030_writeb(void *opaque, target_phys_addr_t addr, uint32_t val) |
402 | 4ce7ff6e | aurel32 | { |
403 | 4ce7ff6e | aurel32 | uint32_t old_val = rc4030_readl(opaque, addr & ~0x3);
|
404 | 4ce7ff6e | aurel32 | |
405 | 4ce7ff6e | aurel32 | switch (addr & 3) { |
406 | 4ce7ff6e | aurel32 | case 0: |
407 | 4ce7ff6e | aurel32 | val = val | (old_val & 0xffffff00);
|
408 | 4ce7ff6e | aurel32 | break;
|
409 | 4ce7ff6e | aurel32 | case 1: |
410 | 4ce7ff6e | aurel32 | val = (val << 8) | (old_val & 0xffff00ff); |
411 | 4ce7ff6e | aurel32 | break;
|
412 | 4ce7ff6e | aurel32 | case 2: |
413 | 4ce7ff6e | aurel32 | val = (val << 16) | (old_val & 0xff00ffff); |
414 | 4ce7ff6e | aurel32 | break;
|
415 | 4ce7ff6e | aurel32 | case 3: |
416 | 4ce7ff6e | aurel32 | val = (val << 24) | (old_val & 0x00ffffff); |
417 | 4ce7ff6e | aurel32 | break;
|
418 | 4ce7ff6e | aurel32 | } |
419 | 4ce7ff6e | aurel32 | rc4030_writel(opaque, addr & ~0x3, val);
|
420 | 4ce7ff6e | aurel32 | } |
421 | 4ce7ff6e | aurel32 | |
422 | d60efc6b | Blue Swirl | static CPUReadMemoryFunc * const rc4030_read[3] = { |
423 | 4ce7ff6e | aurel32 | rc4030_readb, |
424 | 4ce7ff6e | aurel32 | rc4030_readw, |
425 | 4ce7ff6e | aurel32 | rc4030_readl, |
426 | 4ce7ff6e | aurel32 | }; |
427 | 4ce7ff6e | aurel32 | |
428 | d60efc6b | Blue Swirl | static CPUWriteMemoryFunc * const rc4030_write[3] = { |
429 | 4ce7ff6e | aurel32 | rc4030_writeb, |
430 | 4ce7ff6e | aurel32 | rc4030_writew, |
431 | 4ce7ff6e | aurel32 | rc4030_writel, |
432 | 4ce7ff6e | aurel32 | }; |
433 | 4ce7ff6e | aurel32 | |
434 | 4ce7ff6e | aurel32 | static void update_jazz_irq(rc4030State *s) |
435 | 4ce7ff6e | aurel32 | { |
436 | 4ce7ff6e | aurel32 | uint16_t pending; |
437 | 4ce7ff6e | aurel32 | |
438 | 4ce7ff6e | aurel32 | pending = s->isr_jazz & s->imr_jazz; |
439 | 4ce7ff6e | aurel32 | |
440 | 4ce7ff6e | aurel32 | #ifdef DEBUG_RC4030
|
441 | 4ce7ff6e | aurel32 | if (s->isr_jazz != 0) { |
442 | 4ce7ff6e | aurel32 | uint32_t irq = 0;
|
443 | c6945b15 | aurel32 | DPRINTF("pending irqs:");
|
444 | b1503cda | malc | for (irq = 0; irq < ARRAY_SIZE(irq_names); irq++) { |
445 | 4ce7ff6e | aurel32 | if (s->isr_jazz & (1 << irq)) { |
446 | 4ce7ff6e | aurel32 | printf(" %s", irq_names[irq]);
|
447 | 4ce7ff6e | aurel32 | if (!(s->imr_jazz & (1 << irq))) { |
448 | 4ce7ff6e | aurel32 | printf("(ignored)");
|
449 | 4ce7ff6e | aurel32 | } |
450 | 4ce7ff6e | aurel32 | } |
451 | 4ce7ff6e | aurel32 | } |
452 | 4ce7ff6e | aurel32 | printf("\n");
|
453 | 4ce7ff6e | aurel32 | } |
454 | 4ce7ff6e | aurel32 | #endif
|
455 | 4ce7ff6e | aurel32 | |
456 | 4ce7ff6e | aurel32 | if (pending != 0) |
457 | 4ce7ff6e | aurel32 | qemu_irq_raise(s->jazz_bus_irq); |
458 | 4ce7ff6e | aurel32 | else
|
459 | 4ce7ff6e | aurel32 | qemu_irq_lower(s->jazz_bus_irq); |
460 | 4ce7ff6e | aurel32 | } |
461 | 4ce7ff6e | aurel32 | |
462 | 4ce7ff6e | aurel32 | static void rc4030_irq_jazz_request(void *opaque, int irq, int level) |
463 | 4ce7ff6e | aurel32 | { |
464 | 4ce7ff6e | aurel32 | rc4030State *s = opaque; |
465 | 4ce7ff6e | aurel32 | |
466 | 4ce7ff6e | aurel32 | if (level) {
|
467 | 4ce7ff6e | aurel32 | s->isr_jazz |= 1 << irq;
|
468 | 4ce7ff6e | aurel32 | } else {
|
469 | 4ce7ff6e | aurel32 | s->isr_jazz &= ~(1 << irq);
|
470 | 4ce7ff6e | aurel32 | } |
471 | 4ce7ff6e | aurel32 | |
472 | 4ce7ff6e | aurel32 | update_jazz_irq(s); |
473 | 4ce7ff6e | aurel32 | } |
474 | 4ce7ff6e | aurel32 | |
475 | 4ce7ff6e | aurel32 | static void rc4030_periodic_timer(void *opaque) |
476 | 4ce7ff6e | aurel32 | { |
477 | 4ce7ff6e | aurel32 | rc4030State *s = opaque; |
478 | 4ce7ff6e | aurel32 | |
479 | 4ce7ff6e | aurel32 | set_next_tick(s); |
480 | 4ce7ff6e | aurel32 | qemu_irq_raise(s->timer_irq); |
481 | 4ce7ff6e | aurel32 | } |
482 | 4ce7ff6e | aurel32 | |
483 | c227f099 | Anthony Liguori | static uint32_t jazzio_readw(void *opaque, target_phys_addr_t addr) |
484 | 4ce7ff6e | aurel32 | { |
485 | 4ce7ff6e | aurel32 | rc4030State *s = opaque; |
486 | 4ce7ff6e | aurel32 | uint32_t val; |
487 | 4ce7ff6e | aurel32 | uint32_t irq; |
488 | 4ce7ff6e | aurel32 | addr &= 0xfff;
|
489 | 4ce7ff6e | aurel32 | |
490 | 4ce7ff6e | aurel32 | switch (addr) {
|
491 | c6945b15 | aurel32 | /* Local bus int source */
|
492 | 4ce7ff6e | aurel32 | case 0x00: { |
493 | 4ce7ff6e | aurel32 | uint32_t pending = s->isr_jazz & s->imr_jazz; |
494 | 4ce7ff6e | aurel32 | val = 0;
|
495 | 4ce7ff6e | aurel32 | irq = 0;
|
496 | 4ce7ff6e | aurel32 | while (pending) {
|
497 | 4ce7ff6e | aurel32 | if (pending & 1) { |
498 | c6945b15 | aurel32 | DPRINTF("returning irq %s\n", irq_names[irq]);
|
499 | 4ce7ff6e | aurel32 | val = (irq + 1) << 2; |
500 | 4ce7ff6e | aurel32 | break;
|
501 | 4ce7ff6e | aurel32 | } |
502 | 4ce7ff6e | aurel32 | irq++; |
503 | 4ce7ff6e | aurel32 | pending >>= 1;
|
504 | 4ce7ff6e | aurel32 | } |
505 | 4ce7ff6e | aurel32 | break;
|
506 | 4ce7ff6e | aurel32 | } |
507 | c6945b15 | aurel32 | /* Local bus int enable mask */
|
508 | c6945b15 | aurel32 | case 0x02: |
509 | c6945b15 | aurel32 | val = s->imr_jazz; |
510 | c6945b15 | aurel32 | break;
|
511 | 4ce7ff6e | aurel32 | default:
|
512 | c6945b15 | aurel32 | RC4030_ERROR("(jazz io controller) invalid read [" TARGET_FMT_plx "]\n", addr); |
513 | c6945b15 | aurel32 | val = 0;
|
514 | 4ce7ff6e | aurel32 | } |
515 | 4ce7ff6e | aurel32 | |
516 | c6945b15 | aurel32 | DPRINTF("(jazz io controller) read 0x%04x at " TARGET_FMT_plx "\n", val, addr); |
517 | 4ce7ff6e | aurel32 | |
518 | 4ce7ff6e | aurel32 | return val;
|
519 | 4ce7ff6e | aurel32 | } |
520 | 4ce7ff6e | aurel32 | |
521 | c227f099 | Anthony Liguori | static uint32_t jazzio_readb(void *opaque, target_phys_addr_t addr) |
522 | 4ce7ff6e | aurel32 | { |
523 | 4ce7ff6e | aurel32 | uint32_t v; |
524 | c6945b15 | aurel32 | v = jazzio_readw(opaque, addr & ~0x1);
|
525 | c6945b15 | aurel32 | return (v >> (8 * (addr & 0x1))) & 0xff; |
526 | 4ce7ff6e | aurel32 | } |
527 | 4ce7ff6e | aurel32 | |
528 | c227f099 | Anthony Liguori | static uint32_t jazzio_readl(void *opaque, target_phys_addr_t addr) |
529 | 4ce7ff6e | aurel32 | { |
530 | 4ce7ff6e | aurel32 | uint32_t v; |
531 | c6945b15 | aurel32 | v = jazzio_readw(opaque, addr); |
532 | c6945b15 | aurel32 | v |= jazzio_readw(opaque, addr + 2) << 16; |
533 | 4ce7ff6e | aurel32 | return v;
|
534 | 4ce7ff6e | aurel32 | } |
535 | 4ce7ff6e | aurel32 | |
536 | c227f099 | Anthony Liguori | static void jazzio_writew(void *opaque, target_phys_addr_t addr, uint32_t val) |
537 | 4ce7ff6e | aurel32 | { |
538 | 4ce7ff6e | aurel32 | rc4030State *s = opaque; |
539 | 4ce7ff6e | aurel32 | addr &= 0xfff;
|
540 | 4ce7ff6e | aurel32 | |
541 | c6945b15 | aurel32 | DPRINTF("(jazz io controller) write 0x%04x at " TARGET_FMT_plx "\n", val, addr); |
542 | 4ce7ff6e | aurel32 | |
543 | 4ce7ff6e | aurel32 | switch (addr) {
|
544 | 4ce7ff6e | aurel32 | /* Local bus int enable mask */
|
545 | 4ce7ff6e | aurel32 | case 0x02: |
546 | c6945b15 | aurel32 | s->imr_jazz = val; |
547 | c6945b15 | aurel32 | update_jazz_irq(s); |
548 | 4ce7ff6e | aurel32 | break;
|
549 | 4ce7ff6e | aurel32 | default:
|
550 | c6945b15 | aurel32 | RC4030_ERROR("(jazz io controller) invalid write of 0x%04x at [" TARGET_FMT_plx "]\n", val, addr); |
551 | 4ce7ff6e | aurel32 | break;
|
552 | 4ce7ff6e | aurel32 | } |
553 | 4ce7ff6e | aurel32 | } |
554 | 4ce7ff6e | aurel32 | |
555 | c227f099 | Anthony Liguori | static void jazzio_writeb(void *opaque, target_phys_addr_t addr, uint32_t val) |
556 | 4ce7ff6e | aurel32 | { |
557 | c6945b15 | aurel32 | uint32_t old_val = jazzio_readw(opaque, addr & ~0x1);
|
558 | c6945b15 | aurel32 | |
559 | c6945b15 | aurel32 | switch (addr & 1) { |
560 | c6945b15 | aurel32 | case 0: |
561 | c6945b15 | aurel32 | val = val | (old_val & 0xff00);
|
562 | c6945b15 | aurel32 | break;
|
563 | c6945b15 | aurel32 | case 1: |
564 | c6945b15 | aurel32 | val = (val << 8) | (old_val & 0x00ff); |
565 | c6945b15 | aurel32 | break;
|
566 | c6945b15 | aurel32 | } |
567 | c6945b15 | aurel32 | jazzio_writew(opaque, addr & ~0x1, val);
|
568 | 4ce7ff6e | aurel32 | } |
569 | 4ce7ff6e | aurel32 | |
570 | c227f099 | Anthony Liguori | static void jazzio_writel(void *opaque, target_phys_addr_t addr, uint32_t val) |
571 | 4ce7ff6e | aurel32 | { |
572 | c6945b15 | aurel32 | jazzio_writew(opaque, addr, val & 0xffff);
|
573 | c6945b15 | aurel32 | jazzio_writew(opaque, addr + 2, (val >> 16) & 0xffff); |
574 | 4ce7ff6e | aurel32 | } |
575 | 4ce7ff6e | aurel32 | |
576 | d60efc6b | Blue Swirl | static CPUReadMemoryFunc * const jazzio_read[3] = { |
577 | c6945b15 | aurel32 | jazzio_readb, |
578 | c6945b15 | aurel32 | jazzio_readw, |
579 | c6945b15 | aurel32 | jazzio_readl, |
580 | 4ce7ff6e | aurel32 | }; |
581 | 4ce7ff6e | aurel32 | |
582 | d60efc6b | Blue Swirl | static CPUWriteMemoryFunc * const jazzio_write[3] = { |
583 | c6945b15 | aurel32 | jazzio_writeb, |
584 | c6945b15 | aurel32 | jazzio_writew, |
585 | c6945b15 | aurel32 | jazzio_writel, |
586 | 4ce7ff6e | aurel32 | }; |
587 | 4ce7ff6e | aurel32 | |
588 | 4ce7ff6e | aurel32 | static void rc4030_reset(void *opaque) |
589 | 4ce7ff6e | aurel32 | { |
590 | 4ce7ff6e | aurel32 | rc4030State *s = opaque; |
591 | 4ce7ff6e | aurel32 | int i;
|
592 | 4ce7ff6e | aurel32 | |
593 | c6945b15 | aurel32 | s->config = 0x410; /* some boards seem to accept 0x104 too */ |
594 | 9ea0b7a1 | aurel32 | s->revision = 1;
|
595 | 4ce7ff6e | aurel32 | s->invalid_address_register = 0;
|
596 | 4ce7ff6e | aurel32 | |
597 | 4ce7ff6e | aurel32 | memset(s->dma_regs, 0, sizeof(s->dma_regs)); |
598 | 4ce7ff6e | aurel32 | s->dma_tl_base = s->dma_tl_limit = 0;
|
599 | 4ce7ff6e | aurel32 | |
600 | 4ce7ff6e | aurel32 | s->remote_failed_address = s->memory_failed_address = 0;
|
601 | 9ea0b7a1 | aurel32 | s->cache_maint = 0;
|
602 | 4ce7ff6e | aurel32 | s->cache_ptag = s->cache_ltag = 0;
|
603 | 9ea0b7a1 | aurel32 | s->cache_bmask = 0;
|
604 | 4ce7ff6e | aurel32 | |
605 | 4ce7ff6e | aurel32 | s->offset210 = 0x18186;
|
606 | 4ce7ff6e | aurel32 | s->nvram_protect = 7;
|
607 | 4ce7ff6e | aurel32 | for (i = 0; i < 15; i++) |
608 | 4ce7ff6e | aurel32 | s->rem_speed[i] = 7;
|
609 | 9ea0b7a1 | aurel32 | s->imr_jazz = 0x10; /* XXX: required by firmware, but why? */ |
610 | 9ea0b7a1 | aurel32 | s->isr_jazz = 0;
|
611 | 4ce7ff6e | aurel32 | |
612 | 4ce7ff6e | aurel32 | s->itr = 0;
|
613 | 4ce7ff6e | aurel32 | |
614 | 4ce7ff6e | aurel32 | qemu_irq_lower(s->timer_irq); |
615 | 4ce7ff6e | aurel32 | qemu_irq_lower(s->jazz_bus_irq); |
616 | 4ce7ff6e | aurel32 | } |
617 | 4ce7ff6e | aurel32 | |
618 | d5853c20 | aurel32 | static int rc4030_load(QEMUFile *f, void *opaque, int version_id) |
619 | d5853c20 | aurel32 | { |
620 | d5853c20 | aurel32 | rc4030State* s = opaque; |
621 | d5853c20 | aurel32 | int i, j;
|
622 | d5853c20 | aurel32 | |
623 | 9ea0b7a1 | aurel32 | if (version_id != 2) |
624 | d5853c20 | aurel32 | return -EINVAL;
|
625 | d5853c20 | aurel32 | |
626 | d5853c20 | aurel32 | s->config = qemu_get_be32(f); |
627 | d5853c20 | aurel32 | s->invalid_address_register = qemu_get_be32(f); |
628 | d5853c20 | aurel32 | for (i = 0; i < 8; i++) |
629 | d5853c20 | aurel32 | for (j = 0; j < 4; j++) |
630 | d5853c20 | aurel32 | s->dma_regs[i][j] = qemu_get_be32(f); |
631 | d5853c20 | aurel32 | s->dma_tl_base = qemu_get_be32(f); |
632 | d5853c20 | aurel32 | s->dma_tl_limit = qemu_get_be32(f); |
633 | 9ea0b7a1 | aurel32 | s->cache_maint = qemu_get_be32(f); |
634 | d5853c20 | aurel32 | s->remote_failed_address = qemu_get_be32(f); |
635 | d5853c20 | aurel32 | s->memory_failed_address = qemu_get_be32(f); |
636 | d5853c20 | aurel32 | s->cache_ptag = qemu_get_be32(f); |
637 | d5853c20 | aurel32 | s->cache_ltag = qemu_get_be32(f); |
638 | d5853c20 | aurel32 | s->cache_bmask = qemu_get_be32(f); |
639 | d5853c20 | aurel32 | s->offset210 = qemu_get_be32(f); |
640 | d5853c20 | aurel32 | s->nvram_protect = qemu_get_be32(f); |
641 | d5853c20 | aurel32 | for (i = 0; i < 15; i++) |
642 | d5853c20 | aurel32 | s->rem_speed[i] = qemu_get_be32(f); |
643 | d5853c20 | aurel32 | s->imr_jazz = qemu_get_be32(f); |
644 | d5853c20 | aurel32 | s->isr_jazz = qemu_get_be32(f); |
645 | d5853c20 | aurel32 | s->itr = qemu_get_be32(f); |
646 | d5853c20 | aurel32 | |
647 | d5853c20 | aurel32 | set_next_tick(s); |
648 | d5853c20 | aurel32 | update_jazz_irq(s); |
649 | d5853c20 | aurel32 | |
650 | d5853c20 | aurel32 | return 0; |
651 | d5853c20 | aurel32 | } |
652 | d5853c20 | aurel32 | |
653 | d5853c20 | aurel32 | static void rc4030_save(QEMUFile *f, void *opaque) |
654 | d5853c20 | aurel32 | { |
655 | d5853c20 | aurel32 | rc4030State* s = opaque; |
656 | d5853c20 | aurel32 | int i, j;
|
657 | d5853c20 | aurel32 | |
658 | d5853c20 | aurel32 | qemu_put_be32(f, s->config); |
659 | d5853c20 | aurel32 | qemu_put_be32(f, s->invalid_address_register); |
660 | d5853c20 | aurel32 | for (i = 0; i < 8; i++) |
661 | d5853c20 | aurel32 | for (j = 0; j < 4; j++) |
662 | d5853c20 | aurel32 | qemu_put_be32(f, s->dma_regs[i][j]); |
663 | d5853c20 | aurel32 | qemu_put_be32(f, s->dma_tl_base); |
664 | d5853c20 | aurel32 | qemu_put_be32(f, s->dma_tl_limit); |
665 | 9ea0b7a1 | aurel32 | qemu_put_be32(f, s->cache_maint); |
666 | d5853c20 | aurel32 | qemu_put_be32(f, s->remote_failed_address); |
667 | d5853c20 | aurel32 | qemu_put_be32(f, s->memory_failed_address); |
668 | d5853c20 | aurel32 | qemu_put_be32(f, s->cache_ptag); |
669 | d5853c20 | aurel32 | qemu_put_be32(f, s->cache_ltag); |
670 | d5853c20 | aurel32 | qemu_put_be32(f, s->cache_bmask); |
671 | d5853c20 | aurel32 | qemu_put_be32(f, s->offset210); |
672 | d5853c20 | aurel32 | qemu_put_be32(f, s->nvram_protect); |
673 | d5853c20 | aurel32 | for (i = 0; i < 15; i++) |
674 | d5853c20 | aurel32 | qemu_put_be32(f, s->rem_speed[i]); |
675 | d5853c20 | aurel32 | qemu_put_be32(f, s->imr_jazz); |
676 | d5853c20 | aurel32 | qemu_put_be32(f, s->isr_jazz); |
677 | d5853c20 | aurel32 | qemu_put_be32(f, s->itr); |
678 | d5853c20 | aurel32 | } |
679 | d5853c20 | aurel32 | |
680 | c227f099 | Anthony Liguori | void rc4030_dma_memory_rw(void *opaque, target_phys_addr_t addr, uint8_t *buf, int len, int is_write) |
681 | c6945b15 | aurel32 | { |
682 | c6945b15 | aurel32 | rc4030State *s = opaque; |
683 | c227f099 | Anthony Liguori | target_phys_addr_t entry_addr; |
684 | c227f099 | Anthony Liguori | target_phys_addr_t phys_addr; |
685 | c6945b15 | aurel32 | dma_pagetable_entry entry; |
686 | 9ea0b7a1 | aurel32 | int index;
|
687 | c6945b15 | aurel32 | int ncpy, i;
|
688 | c6945b15 | aurel32 | |
689 | c6945b15 | aurel32 | i = 0;
|
690 | c6945b15 | aurel32 | for (;;) {
|
691 | c6945b15 | aurel32 | if (i == len) {
|
692 | c6945b15 | aurel32 | break;
|
693 | c6945b15 | aurel32 | } |
694 | c6945b15 | aurel32 | |
695 | 9ea0b7a1 | aurel32 | ncpy = DMA_PAGESIZE - (addr & (DMA_PAGESIZE - 1));
|
696 | c6945b15 | aurel32 | if (ncpy > len - i)
|
697 | c6945b15 | aurel32 | ncpy = len - i; |
698 | c6945b15 | aurel32 | |
699 | c6945b15 | aurel32 | /* Get DMA translation table entry */
|
700 | 9ea0b7a1 | aurel32 | index = addr / DMA_PAGESIZE; |
701 | c6945b15 | aurel32 | if (index >= s->dma_tl_limit / sizeof(dma_pagetable_entry)) { |
702 | c6945b15 | aurel32 | break;
|
703 | c6945b15 | aurel32 | } |
704 | c6945b15 | aurel32 | entry_addr = s->dma_tl_base + index * sizeof(dma_pagetable_entry);
|
705 | c6945b15 | aurel32 | /* XXX: not sure. should we really use only lowest bits? */
|
706 | c6945b15 | aurel32 | entry_addr &= 0x7fffffff;
|
707 | 54f7b4a3 | Stefan Weil | cpu_physical_memory_read(entry_addr, &entry, sizeof(entry));
|
708 | c6945b15 | aurel32 | |
709 | c6945b15 | aurel32 | /* Read/write data at right place */
|
710 | 9ea0b7a1 | aurel32 | phys_addr = entry.frame + (addr & (DMA_PAGESIZE - 1));
|
711 | c6945b15 | aurel32 | cpu_physical_memory_rw(phys_addr, &buf[i], ncpy, is_write); |
712 | c6945b15 | aurel32 | |
713 | c6945b15 | aurel32 | i += ncpy; |
714 | 9ea0b7a1 | aurel32 | addr += ncpy; |
715 | 9ea0b7a1 | aurel32 | } |
716 | 9ea0b7a1 | aurel32 | } |
717 | 9ea0b7a1 | aurel32 | |
718 | 9ea0b7a1 | aurel32 | static void rc4030_do_dma(void *opaque, int n, uint8_t *buf, int len, int is_write) |
719 | 9ea0b7a1 | aurel32 | { |
720 | 9ea0b7a1 | aurel32 | rc4030State *s = opaque; |
721 | c227f099 | Anthony Liguori | target_phys_addr_t dma_addr; |
722 | 9ea0b7a1 | aurel32 | int dev_to_mem;
|
723 | 9ea0b7a1 | aurel32 | |
724 | 9ea0b7a1 | aurel32 | s->dma_regs[n][DMA_REG_ENABLE] &= ~(DMA_FLAG_TC_INTR | DMA_FLAG_MEM_INTR | DMA_FLAG_ADDR_INTR); |
725 | 9ea0b7a1 | aurel32 | |
726 | 9ea0b7a1 | aurel32 | /* Check DMA channel consistency */
|
727 | 9ea0b7a1 | aurel32 | dev_to_mem = (s->dma_regs[n][DMA_REG_ENABLE] & DMA_FLAG_MEM_TO_DEV) ? 0 : 1; |
728 | 9ea0b7a1 | aurel32 | if (!(s->dma_regs[n][DMA_REG_ENABLE] & DMA_FLAG_ENABLE) ||
|
729 | 9ea0b7a1 | aurel32 | (is_write != dev_to_mem)) { |
730 | 9ea0b7a1 | aurel32 | s->dma_regs[n][DMA_REG_ENABLE] |= DMA_FLAG_MEM_INTR; |
731 | 9ea0b7a1 | aurel32 | s->nmi_interrupt |= 1 << n;
|
732 | 9ea0b7a1 | aurel32 | return;
|
733 | c6945b15 | aurel32 | } |
734 | c6945b15 | aurel32 | |
735 | 9ea0b7a1 | aurel32 | /* Get start address and len */
|
736 | 9ea0b7a1 | aurel32 | if (len > s->dma_regs[n][DMA_REG_COUNT])
|
737 | 9ea0b7a1 | aurel32 | len = s->dma_regs[n][DMA_REG_COUNT]; |
738 | 9ea0b7a1 | aurel32 | dma_addr = s->dma_regs[n][DMA_REG_ADDRESS]; |
739 | 9ea0b7a1 | aurel32 | |
740 | 9ea0b7a1 | aurel32 | /* Read/write data at right place */
|
741 | 9ea0b7a1 | aurel32 | rc4030_dma_memory_rw(opaque, dma_addr, buf, len, is_write); |
742 | 9ea0b7a1 | aurel32 | |
743 | 9ea0b7a1 | aurel32 | s->dma_regs[n][DMA_REG_ENABLE] |= DMA_FLAG_TC_INTR; |
744 | 9ea0b7a1 | aurel32 | s->dma_regs[n][DMA_REG_COUNT] -= len; |
745 | 9ea0b7a1 | aurel32 | |
746 | c6945b15 | aurel32 | #ifdef DEBUG_RC4030_DMA
|
747 | c6945b15 | aurel32 | { |
748 | c6945b15 | aurel32 | int i, j;
|
749 | c6945b15 | aurel32 | printf("rc4030 dma: Copying %d bytes %s host %p\n",
|
750 | c6945b15 | aurel32 | len, is_write ? "from" : "to", buf); |
751 | c6945b15 | aurel32 | for (i = 0; i < len; i += 16) { |
752 | b832134d | Stefan Weil | int n = 16; |
753 | b832134d | Stefan Weil | if (n > len - i) {
|
754 | b832134d | Stefan Weil | n = len - i; |
755 | b832134d | Stefan Weil | } |
756 | c6945b15 | aurel32 | for (j = 0; j < n; j++) |
757 | c6945b15 | aurel32 | printf("%02x ", buf[i + j]);
|
758 | c6945b15 | aurel32 | while (j++ < 16) |
759 | c6945b15 | aurel32 | printf(" ");
|
760 | c6945b15 | aurel32 | printf("| ");
|
761 | c6945b15 | aurel32 | for (j = 0; j < n; j++) |
762 | c6945b15 | aurel32 | printf("%c", isprint(buf[i + j]) ? buf[i + j] : '.'); |
763 | c6945b15 | aurel32 | printf("\n");
|
764 | c6945b15 | aurel32 | } |
765 | c6945b15 | aurel32 | } |
766 | c6945b15 | aurel32 | #endif
|
767 | c6945b15 | aurel32 | } |
768 | c6945b15 | aurel32 | |
769 | c6945b15 | aurel32 | struct rc4030DMAState {
|
770 | c6945b15 | aurel32 | void *opaque;
|
771 | c6945b15 | aurel32 | int n;
|
772 | c6945b15 | aurel32 | }; |
773 | c6945b15 | aurel32 | |
774 | 68238a9e | aurel32 | void rc4030_dma_read(void *dma, uint8_t *buf, int len) |
775 | c6945b15 | aurel32 | { |
776 | c6945b15 | aurel32 | rc4030_dma s = dma; |
777 | c6945b15 | aurel32 | rc4030_do_dma(s->opaque, s->n, buf, len, 0);
|
778 | c6945b15 | aurel32 | } |
779 | c6945b15 | aurel32 | |
780 | 68238a9e | aurel32 | void rc4030_dma_write(void *dma, uint8_t *buf, int len) |
781 | c6945b15 | aurel32 | { |
782 | c6945b15 | aurel32 | rc4030_dma s = dma; |
783 | c6945b15 | aurel32 | rc4030_do_dma(s->opaque, s->n, buf, len, 1);
|
784 | c6945b15 | aurel32 | } |
785 | c6945b15 | aurel32 | |
786 | c6945b15 | aurel32 | static rc4030_dma *rc4030_allocate_dmas(void *opaque, int n) |
787 | c6945b15 | aurel32 | { |
788 | c6945b15 | aurel32 | rc4030_dma *s; |
789 | c6945b15 | aurel32 | struct rc4030DMAState *p;
|
790 | c6945b15 | aurel32 | int i;
|
791 | c6945b15 | aurel32 | |
792 | c6945b15 | aurel32 | s = (rc4030_dma *)qemu_mallocz(sizeof(rc4030_dma) * n);
|
793 | c6945b15 | aurel32 | p = (struct rc4030DMAState *)qemu_mallocz(sizeof(struct rc4030DMAState) * n); |
794 | c6945b15 | aurel32 | for (i = 0; i < n; i++) { |
795 | c6945b15 | aurel32 | p->opaque = opaque; |
796 | c6945b15 | aurel32 | p->n = i; |
797 | c6945b15 | aurel32 | s[i] = p; |
798 | c6945b15 | aurel32 | p++; |
799 | c6945b15 | aurel32 | } |
800 | c6945b15 | aurel32 | return s;
|
801 | c6945b15 | aurel32 | } |
802 | c6945b15 | aurel32 | |
803 | 68238a9e | aurel32 | void *rc4030_init(qemu_irq timer, qemu_irq jazz_bus,
|
804 | 68238a9e | aurel32 | qemu_irq **irqs, rc4030_dma **dmas) |
805 | 4ce7ff6e | aurel32 | { |
806 | 4ce7ff6e | aurel32 | rc4030State *s; |
807 | c6945b15 | aurel32 | int s_chipset, s_jazzio;
|
808 | 4ce7ff6e | aurel32 | |
809 | 4ce7ff6e | aurel32 | s = qemu_mallocz(sizeof(rc4030State));
|
810 | 4ce7ff6e | aurel32 | |
811 | 68238a9e | aurel32 | *irqs = qemu_allocate_irqs(rc4030_irq_jazz_request, s, 16);
|
812 | c6945b15 | aurel32 | *dmas = rc4030_allocate_dmas(s, 4);
|
813 | c6945b15 | aurel32 | |
814 | 74475455 | Paolo Bonzini | s->periodic_timer = qemu_new_timer_ns(vm_clock, rc4030_periodic_timer, s); |
815 | 4ce7ff6e | aurel32 | s->timer_irq = timer; |
816 | 4ce7ff6e | aurel32 | s->jazz_bus_irq = jazz_bus; |
817 | 4ce7ff6e | aurel32 | |
818 | a08d4367 | Jan Kiszka | qemu_register_reset(rc4030_reset, s); |
819 | 0be71e32 | Alex Williamson | register_savevm(NULL, "rc4030", 0, 2, rc4030_save, rc4030_load, s); |
820 | 4ce7ff6e | aurel32 | rc4030_reset(s); |
821 | 4ce7ff6e | aurel32 | |
822 | 2507c12a | Alexander Graf | s_chipset = cpu_register_io_memory(rc4030_read, rc4030_write, s, |
823 | 2507c12a | Alexander Graf | DEVICE_NATIVE_ENDIAN); |
824 | 4ce7ff6e | aurel32 | cpu_register_physical_memory(0x80000000, 0x300, s_chipset); |
825 | 2507c12a | Alexander Graf | s_jazzio = cpu_register_io_memory(jazzio_read, jazzio_write, s, |
826 | 2507c12a | Alexander Graf | DEVICE_NATIVE_ENDIAN); |
827 | c6945b15 | aurel32 | cpu_register_physical_memory(0xf0000000, 0x00001000, s_jazzio); |
828 | 4ce7ff6e | aurel32 | |
829 | 68238a9e | aurel32 | return s;
|
830 | 4ce7ff6e | aurel32 | } |