root / hw / slavio_timer.c @ d2d979c6
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1 | e80cfcfc | bellard | /*
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2 | e80cfcfc | bellard | * QEMU Sparc SLAVIO timer controller emulation
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3 | e80cfcfc | bellard | *
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4 | 66321a11 | bellard | * Copyright (c) 2003-2005 Fabrice Bellard
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5 | 5fafdf24 | ths | *
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6 | e80cfcfc | bellard | * Permission is hereby granted, free of charge, to any person obtaining a copy
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7 | e80cfcfc | bellard | * of this software and associated documentation files (the "Software"), to deal
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8 | e80cfcfc | bellard | * in the Software without restriction, including without limitation the rights
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9 | e80cfcfc | bellard | * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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10 | e80cfcfc | bellard | * copies of the Software, and to permit persons to whom the Software is
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11 | e80cfcfc | bellard | * furnished to do so, subject to the following conditions:
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12 | e80cfcfc | bellard | *
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13 | e80cfcfc | bellard | * The above copyright notice and this permission notice shall be included in
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14 | e80cfcfc | bellard | * all copies or substantial portions of the Software.
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15 | e80cfcfc | bellard | *
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16 | e80cfcfc | bellard | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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17 | e80cfcfc | bellard | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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18 | e80cfcfc | bellard | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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19 | e80cfcfc | bellard | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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20 | e80cfcfc | bellard | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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21 | e80cfcfc | bellard | * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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22 | e80cfcfc | bellard | * THE SOFTWARE.
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23 | e80cfcfc | bellard | */
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24 | c70c59ee | Blue Swirl | |
25 | 87ecb68b | pbrook | #include "sun4m.h" |
26 | 87ecb68b | pbrook | #include "qemu-timer.h" |
27 | c70c59ee | Blue Swirl | #include "sysbus.h" |
28 | 97bf4851 | Blue Swirl | #include "trace.h" |
29 | 66321a11 | bellard | |
30 | e80cfcfc | bellard | /*
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31 | e80cfcfc | bellard | * Registers of hardware timer in sun4m.
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32 | e80cfcfc | bellard | *
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33 | e80cfcfc | bellard | * This is the timer/counter part of chip STP2001 (Slave I/O), also
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34 | e80cfcfc | bellard | * produced as NCR89C105. See
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35 | e80cfcfc | bellard | * http://www.ibiblio.org/pub/historic-linux/early-ports/Sparc/NCR/NCR89C105.txt
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36 | 5fafdf24 | ths | *
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37 | e80cfcfc | bellard | * The 31-bit counter is incremented every 500ns by bit 9. Bits 8..0
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38 | e80cfcfc | bellard | * are zero. Bit 31 is 1 when count has been reached.
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39 | e80cfcfc | bellard | *
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40 | ba3c64fb | bellard | * Per-CPU timers interrupt local CPU, system timer uses normal
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41 | ba3c64fb | bellard | * interrupt routing.
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42 | ba3c64fb | bellard | *
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43 | e80cfcfc | bellard | */
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44 | e80cfcfc | bellard | |
45 | 81732d19 | blueswir1 | #define MAX_CPUS 16 |
46 | 81732d19 | blueswir1 | |
47 | 7204ff9c | Blue Swirl | typedef struct CPUTimerState { |
48 | d7edfd27 | blueswir1 | qemu_irq irq; |
49 | 8d05ea8a | blueswir1 | ptimer_state *timer; |
50 | 8d05ea8a | blueswir1 | uint32_t count, counthigh, reached; |
51 | 8d05ea8a | blueswir1 | uint64_t limit; |
52 | 115646b6 | blueswir1 | // processor only
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53 | 22548760 | blueswir1 | uint32_t running; |
54 | 7204ff9c | Blue Swirl | } CPUTimerState; |
55 | 7204ff9c | Blue Swirl | |
56 | 7204ff9c | Blue Swirl | typedef struct SLAVIO_TIMERState { |
57 | 7204ff9c | Blue Swirl | SysBusDevice busdev; |
58 | 7204ff9c | Blue Swirl | uint32_t num_cpus; |
59 | 7204ff9c | Blue Swirl | CPUTimerState cputimer[MAX_CPUS + 1];
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60 | 7204ff9c | Blue Swirl | uint32_t cputimer_mode; |
61 | e80cfcfc | bellard | } SLAVIO_TIMERState; |
62 | e80cfcfc | bellard | |
63 | 7204ff9c | Blue Swirl | typedef struct TimerContext { |
64 | 7204ff9c | Blue Swirl | SLAVIO_TIMERState *s; |
65 | 7204ff9c | Blue Swirl | unsigned int timer_index; /* 0 for system, 1 ... MAX_CPUS for CPU timers */ |
66 | 7204ff9c | Blue Swirl | } TimerContext; |
67 | 7204ff9c | Blue Swirl | |
68 | 115646b6 | blueswir1 | #define SYS_TIMER_SIZE 0x14 |
69 | 81732d19 | blueswir1 | #define CPU_TIMER_SIZE 0x10 |
70 | e80cfcfc | bellard | |
71 | d2c38b24 | blueswir1 | #define TIMER_LIMIT 0 |
72 | d2c38b24 | blueswir1 | #define TIMER_COUNTER 1 |
73 | d2c38b24 | blueswir1 | #define TIMER_COUNTER_NORST 2 |
74 | d2c38b24 | blueswir1 | #define TIMER_STATUS 3 |
75 | d2c38b24 | blueswir1 | #define TIMER_MODE 4 |
76 | d2c38b24 | blueswir1 | |
77 | d2c38b24 | blueswir1 | #define TIMER_COUNT_MASK32 0xfffffe00 |
78 | d2c38b24 | blueswir1 | #define TIMER_LIMIT_MASK32 0x7fffffff |
79 | d2c38b24 | blueswir1 | #define TIMER_MAX_COUNT64 0x7ffffffffffffe00ULL |
80 | d2c38b24 | blueswir1 | #define TIMER_MAX_COUNT32 0x7ffffe00ULL |
81 | d2c38b24 | blueswir1 | #define TIMER_REACHED 0x80000000 |
82 | d2c38b24 | blueswir1 | #define TIMER_PERIOD 500ULL // 500ns |
83 | 68fb89a2 | Blue Swirl | #define LIMIT_TO_PERIODS(l) (((l) >> 9) - 1) |
84 | 68fb89a2 | Blue Swirl | #define PERIODS_TO_LIMIT(l) (((l) + 1) << 9) |
85 | d2c38b24 | blueswir1 | |
86 | 7204ff9c | Blue Swirl | static int slavio_timer_is_user(TimerContext *tc) |
87 | 115646b6 | blueswir1 | { |
88 | 7204ff9c | Blue Swirl | SLAVIO_TIMERState *s = tc->s; |
89 | 7204ff9c | Blue Swirl | unsigned int timer_index = tc->timer_index; |
90 | 7204ff9c | Blue Swirl | |
91 | 7204ff9c | Blue Swirl | return timer_index != 0 && (s->cputimer_mode & (1 << (timer_index - 1))); |
92 | 115646b6 | blueswir1 | } |
93 | 115646b6 | blueswir1 | |
94 | e80cfcfc | bellard | // Update count, set irq, update expire_time
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95 | 8d05ea8a | blueswir1 | // Convert from ptimer countdown units
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96 | 7204ff9c | Blue Swirl | static void slavio_timer_get_out(CPUTimerState *t) |
97 | e80cfcfc | bellard | { |
98 | bd7e2875 | blueswir1 | uint64_t count, limit; |
99 | e80cfcfc | bellard | |
100 | 7204ff9c | Blue Swirl | if (t->limit == 0) { /* free-run system or processor counter */ |
101 | bd7e2875 | blueswir1 | limit = TIMER_MAX_COUNT32; |
102 | 7204ff9c | Blue Swirl | } else {
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103 | 7204ff9c | Blue Swirl | limit = t->limit; |
104 | 7204ff9c | Blue Swirl | } |
105 | 9ebec28b | Blue Swirl | count = limit - PERIODS_TO_LIMIT(ptimer_get_count(t->timer)); |
106 | 9ebec28b | Blue Swirl | |
107 | 97bf4851 | Blue Swirl | trace_slavio_timer_get_out(t->limit, t->counthigh, t->count); |
108 | 7204ff9c | Blue Swirl | t->count = count & TIMER_COUNT_MASK32; |
109 | 7204ff9c | Blue Swirl | t->counthigh = count >> 32;
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110 | e80cfcfc | bellard | } |
111 | e80cfcfc | bellard | |
112 | e80cfcfc | bellard | // timer callback
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113 | e80cfcfc | bellard | static void slavio_timer_irq(void *opaque) |
114 | e80cfcfc | bellard | { |
115 | 7204ff9c | Blue Swirl | TimerContext *tc = opaque; |
116 | 7204ff9c | Blue Swirl | SLAVIO_TIMERState *s = tc->s; |
117 | 7204ff9c | Blue Swirl | CPUTimerState *t = &s->cputimer[tc->timer_index]; |
118 | 7204ff9c | Blue Swirl | |
119 | 7204ff9c | Blue Swirl | slavio_timer_get_out(t); |
120 | 97bf4851 | Blue Swirl | trace_slavio_timer_irq(t->counthigh, t->count); |
121 | 68fb89a2 | Blue Swirl | /* if limit is 0 (free-run), there will be no match */
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122 | 68fb89a2 | Blue Swirl | if (t->limit != 0) { |
123 | 68fb89a2 | Blue Swirl | t->reached = TIMER_REACHED; |
124 | 68fb89a2 | Blue Swirl | } |
125 | 452efba6 | Blue Swirl | /* there is no interrupt if user timer or free-run */
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126 | 452efba6 | Blue Swirl | if (!slavio_timer_is_user(tc) && t->limit != 0) { |
127 | 7204ff9c | Blue Swirl | qemu_irq_raise(t->irq); |
128 | 7204ff9c | Blue Swirl | } |
129 | e80cfcfc | bellard | } |
130 | e80cfcfc | bellard | |
131 | c227f099 | Anthony Liguori | static uint32_t slavio_timer_mem_readl(void *opaque, target_phys_addr_t addr) |
132 | e80cfcfc | bellard | { |
133 | 7204ff9c | Blue Swirl | TimerContext *tc = opaque; |
134 | 7204ff9c | Blue Swirl | SLAVIO_TIMERState *s = tc->s; |
135 | 8d05ea8a | blueswir1 | uint32_t saddr, ret; |
136 | 7204ff9c | Blue Swirl | unsigned int timer_index = tc->timer_index; |
137 | 7204ff9c | Blue Swirl | CPUTimerState *t = &s->cputimer[timer_index]; |
138 | e80cfcfc | bellard | |
139 | e64d7d59 | blueswir1 | saddr = addr >> 2;
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140 | e80cfcfc | bellard | switch (saddr) {
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141 | d2c38b24 | blueswir1 | case TIMER_LIMIT:
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142 | f930d07e | blueswir1 | // read limit (system counter mode) or read most signifying
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143 | f930d07e | blueswir1 | // part of counter (user mode)
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144 | 7204ff9c | Blue Swirl | if (slavio_timer_is_user(tc)) {
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145 | 115646b6 | blueswir1 | // read user timer MSW
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146 | 7204ff9c | Blue Swirl | slavio_timer_get_out(t); |
147 | 7204ff9c | Blue Swirl | ret = t->counthigh | t->reached; |
148 | 115646b6 | blueswir1 | } else {
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149 | 115646b6 | blueswir1 | // read limit
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150 | f930d07e | blueswir1 | // clear irq
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151 | 7204ff9c | Blue Swirl | qemu_irq_lower(t->irq); |
152 | 7204ff9c | Blue Swirl | t->reached = 0;
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153 | 7204ff9c | Blue Swirl | ret = t->limit & TIMER_LIMIT_MASK32; |
154 | f930d07e | blueswir1 | } |
155 | 8d05ea8a | blueswir1 | break;
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156 | d2c38b24 | blueswir1 | case TIMER_COUNTER:
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157 | f930d07e | blueswir1 | // read counter and reached bit (system mode) or read lsbits
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158 | f930d07e | blueswir1 | // of counter (user mode)
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159 | 7204ff9c | Blue Swirl | slavio_timer_get_out(t); |
160 | 7204ff9c | Blue Swirl | if (slavio_timer_is_user(tc)) { // read user timer LSW |
161 | 7204ff9c | Blue Swirl | ret = t->count & TIMER_MAX_COUNT64; |
162 | 7204ff9c | Blue Swirl | } else { // read limit |
163 | 7204ff9c | Blue Swirl | ret = (t->count & TIMER_MAX_COUNT32) | |
164 | 7204ff9c | Blue Swirl | t->reached; |
165 | 7204ff9c | Blue Swirl | } |
166 | 8d05ea8a | blueswir1 | break;
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167 | d2c38b24 | blueswir1 | case TIMER_STATUS:
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168 | 115646b6 | blueswir1 | // only available in processor counter/timer
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169 | f930d07e | blueswir1 | // read start/stop status
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170 | 7204ff9c | Blue Swirl | if (timer_index > 0) { |
171 | 7204ff9c | Blue Swirl | ret = t->running; |
172 | 7204ff9c | Blue Swirl | } else {
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173 | 7204ff9c | Blue Swirl | ret = 0;
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174 | 7204ff9c | Blue Swirl | } |
175 | 8d05ea8a | blueswir1 | break;
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176 | d2c38b24 | blueswir1 | case TIMER_MODE:
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177 | 115646b6 | blueswir1 | // only available in system counter
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178 | f930d07e | blueswir1 | // read user/system mode
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179 | 7204ff9c | Blue Swirl | ret = s->cputimer_mode; |
180 | 8d05ea8a | blueswir1 | break;
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181 | e80cfcfc | bellard | default:
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182 | 97bf4851 | Blue Swirl | trace_slavio_timer_mem_readl_invalid(addr); |
183 | 8d05ea8a | blueswir1 | ret = 0;
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184 | 8d05ea8a | blueswir1 | break;
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185 | e80cfcfc | bellard | } |
186 | 97bf4851 | Blue Swirl | trace_slavio_timer_mem_readl(addr, ret); |
187 | 8d05ea8a | blueswir1 | return ret;
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188 | e80cfcfc | bellard | } |
189 | e80cfcfc | bellard | |
190 | c227f099 | Anthony Liguori | static void slavio_timer_mem_writel(void *opaque, target_phys_addr_t addr, |
191 | d2c38b24 | blueswir1 | uint32_t val) |
192 | e80cfcfc | bellard | { |
193 | 7204ff9c | Blue Swirl | TimerContext *tc = opaque; |
194 | 7204ff9c | Blue Swirl | SLAVIO_TIMERState *s = tc->s; |
195 | e80cfcfc | bellard | uint32_t saddr; |
196 | 7204ff9c | Blue Swirl | unsigned int timer_index = tc->timer_index; |
197 | 7204ff9c | Blue Swirl | CPUTimerState *t = &s->cputimer[timer_index]; |
198 | e80cfcfc | bellard | |
199 | 97bf4851 | Blue Swirl | trace_slavio_timer_mem_writel(addr, val); |
200 | e64d7d59 | blueswir1 | saddr = addr >> 2;
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201 | e80cfcfc | bellard | switch (saddr) {
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202 | d2c38b24 | blueswir1 | case TIMER_LIMIT:
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203 | 7204ff9c | Blue Swirl | if (slavio_timer_is_user(tc)) {
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204 | e1cb9502 | blueswir1 | uint64_t count; |
205 | e1cb9502 | blueswir1 | |
206 | 115646b6 | blueswir1 | // set user counter MSW, reset counter
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207 | 7204ff9c | Blue Swirl | t->limit = TIMER_MAX_COUNT64; |
208 | 7204ff9c | Blue Swirl | t->counthigh = val & (TIMER_MAX_COUNT64 >> 32);
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209 | 7204ff9c | Blue Swirl | t->reached = 0;
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210 | 7204ff9c | Blue Swirl | count = ((uint64_t)t->counthigh << 32) | t->count;
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211 | 97bf4851 | Blue Swirl | trace_slavio_timer_mem_writel_limit(timer_index, count); |
212 | 9ebec28b | Blue Swirl | ptimer_set_count(t->timer, LIMIT_TO_PERIODS(t->limit - count)); |
213 | 115646b6 | blueswir1 | } else {
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214 | 115646b6 | blueswir1 | // set limit, reset counter
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215 | 7204ff9c | Blue Swirl | qemu_irq_lower(t->irq); |
216 | 7204ff9c | Blue Swirl | t->limit = val & TIMER_MAX_COUNT32; |
217 | 7204ff9c | Blue Swirl | if (t->timer) {
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218 | 7204ff9c | Blue Swirl | if (t->limit == 0) { /* free-run */ |
219 | 7204ff9c | Blue Swirl | ptimer_set_limit(t->timer, |
220 | 77f193da | blueswir1 | LIMIT_TO_PERIODS(TIMER_MAX_COUNT32), 1);
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221 | 7204ff9c | Blue Swirl | } else {
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222 | 7204ff9c | Blue Swirl | ptimer_set_limit(t->timer, LIMIT_TO_PERIODS(t->limit), 1);
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223 | 7204ff9c | Blue Swirl | } |
224 | 85e3023e | blueswir1 | } |
225 | 81732d19 | blueswir1 | } |
226 | 115646b6 | blueswir1 | break;
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227 | d2c38b24 | blueswir1 | case TIMER_COUNTER:
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228 | 7204ff9c | Blue Swirl | if (slavio_timer_is_user(tc)) {
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229 | e1cb9502 | blueswir1 | uint64_t count; |
230 | e1cb9502 | blueswir1 | |
231 | 115646b6 | blueswir1 | // set user counter LSW, reset counter
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232 | 7204ff9c | Blue Swirl | t->limit = TIMER_MAX_COUNT64; |
233 | 7204ff9c | Blue Swirl | t->count = val & TIMER_MAX_COUNT64; |
234 | 7204ff9c | Blue Swirl | t->reached = 0;
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235 | 7204ff9c | Blue Swirl | count = ((uint64_t)t->counthigh) << 32 | t->count;
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236 | 97bf4851 | Blue Swirl | trace_slavio_timer_mem_writel_limit(timer_index, count); |
237 | 9ebec28b | Blue Swirl | ptimer_set_count(t->timer, LIMIT_TO_PERIODS(t->limit - count)); |
238 | 97bf4851 | Blue Swirl | } else {
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239 | 97bf4851 | Blue Swirl | trace_slavio_timer_mem_writel_counter_invalid(); |
240 | 97bf4851 | Blue Swirl | } |
241 | 115646b6 | blueswir1 | break;
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242 | d2c38b24 | blueswir1 | case TIMER_COUNTER_NORST:
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243 | f930d07e | blueswir1 | // set limit without resetting counter
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244 | 7204ff9c | Blue Swirl | t->limit = val & TIMER_MAX_COUNT32; |
245 | 9ebec28b | Blue Swirl | if (t->limit == 0) { /* free-run */ |
246 | 9ebec28b | Blue Swirl | ptimer_set_limit(t->timer, LIMIT_TO_PERIODS(TIMER_MAX_COUNT32), 0);
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247 | 9ebec28b | Blue Swirl | } else {
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248 | 9ebec28b | Blue Swirl | ptimer_set_limit(t->timer, LIMIT_TO_PERIODS(t->limit), 0);
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249 | 85e3023e | blueswir1 | } |
250 | f930d07e | blueswir1 | break;
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251 | d2c38b24 | blueswir1 | case TIMER_STATUS:
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252 | 7204ff9c | Blue Swirl | if (slavio_timer_is_user(tc)) {
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253 | 115646b6 | blueswir1 | // start/stop user counter
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254 | 7204ff9c | Blue Swirl | if ((val & 1) && !t->running) { |
255 | 97bf4851 | Blue Swirl | trace_slavio_timer_mem_writel_status_start(timer_index); |
256 | 9ebec28b | Blue Swirl | ptimer_run(t->timer, 0);
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257 | 7204ff9c | Blue Swirl | t->running = 1;
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258 | 7204ff9c | Blue Swirl | } else if (!(val & 1) && t->running) { |
259 | 97bf4851 | Blue Swirl | trace_slavio_timer_mem_writel_status_stop(timer_index); |
260 | 9ebec28b | Blue Swirl | ptimer_stop(t->timer); |
261 | 7204ff9c | Blue Swirl | t->running = 0;
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262 | f930d07e | blueswir1 | } |
263 | f930d07e | blueswir1 | } |
264 | f930d07e | blueswir1 | break;
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265 | d2c38b24 | blueswir1 | case TIMER_MODE:
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266 | 7204ff9c | Blue Swirl | if (timer_index == 0) { |
267 | 81732d19 | blueswir1 | unsigned int i; |
268 | 81732d19 | blueswir1 | |
269 | 7204ff9c | Blue Swirl | for (i = 0; i < s->num_cpus; i++) { |
270 | 67e42751 | blueswir1 | unsigned int processor = 1 << i; |
271 | 7204ff9c | Blue Swirl | CPUTimerState *curr_timer = &s->cputimer[i + 1];
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272 | 67e42751 | blueswir1 | |
273 | 67e42751 | blueswir1 | // check for a change in timer mode for this processor
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274 | 7204ff9c | Blue Swirl | if ((val & processor) != (s->cputimer_mode & processor)) {
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275 | 67e42751 | blueswir1 | if (val & processor) { // counter -> user timer |
276 | 7204ff9c | Blue Swirl | qemu_irq_lower(curr_timer->irq); |
277 | 67e42751 | blueswir1 | // counters are always running
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278 | 7204ff9c | Blue Swirl | ptimer_stop(curr_timer->timer); |
279 | 7204ff9c | Blue Swirl | curr_timer->running = 0;
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280 | 67e42751 | blueswir1 | // user timer limit is always the same
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281 | 7204ff9c | Blue Swirl | curr_timer->limit = TIMER_MAX_COUNT64; |
282 | 7204ff9c | Blue Swirl | ptimer_set_limit(curr_timer->timer, |
283 | 7204ff9c | Blue Swirl | LIMIT_TO_PERIODS(curr_timer->limit), |
284 | 77f193da | blueswir1 | 1);
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285 | 67e42751 | blueswir1 | // set this processors user timer bit in config
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286 | 67e42751 | blueswir1 | // register
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287 | 7204ff9c | Blue Swirl | s->cputimer_mode |= processor; |
288 | 97bf4851 | Blue Swirl | trace_slavio_timer_mem_writel_mode_user(timer_index); |
289 | 67e42751 | blueswir1 | } else { // user timer -> counter |
290 | 67e42751 | blueswir1 | // stop the user timer if it is running
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291 | 7204ff9c | Blue Swirl | if (curr_timer->running) {
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292 | 7204ff9c | Blue Swirl | ptimer_stop(curr_timer->timer); |
293 | 7204ff9c | Blue Swirl | } |
294 | 67e42751 | blueswir1 | // start the counter
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295 | 7204ff9c | Blue Swirl | ptimer_run(curr_timer->timer, 0);
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296 | 7204ff9c | Blue Swirl | curr_timer->running = 1;
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297 | 67e42751 | blueswir1 | // clear this processors user timer bit in config
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298 | 67e42751 | blueswir1 | // register
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299 | 7204ff9c | Blue Swirl | s->cputimer_mode &= ~processor; |
300 | 97bf4851 | Blue Swirl | trace_slavio_timer_mem_writel_mode_counter(timer_index); |
301 | 67e42751 | blueswir1 | } |
302 | 115646b6 | blueswir1 | } |
303 | 81732d19 | blueswir1 | } |
304 | 7204ff9c | Blue Swirl | } else {
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305 | 97bf4851 | Blue Swirl | trace_slavio_timer_mem_writel_mode_invalid(); |
306 | 7204ff9c | Blue Swirl | } |
307 | f930d07e | blueswir1 | break;
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308 | e80cfcfc | bellard | default:
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309 | 97bf4851 | Blue Swirl | trace_slavio_timer_mem_writel_invalid(addr); |
310 | f930d07e | blueswir1 | break;
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311 | e80cfcfc | bellard | } |
312 | e80cfcfc | bellard | } |
313 | e80cfcfc | bellard | |
314 | d60efc6b | Blue Swirl | static CPUReadMemoryFunc * const slavio_timer_mem_read[3] = { |
315 | 7c560456 | blueswir1 | NULL,
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316 | 7c560456 | blueswir1 | NULL,
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317 | e80cfcfc | bellard | slavio_timer_mem_readl, |
318 | e80cfcfc | bellard | }; |
319 | e80cfcfc | bellard | |
320 | d60efc6b | Blue Swirl | static CPUWriteMemoryFunc * const slavio_timer_mem_write[3] = { |
321 | 7c560456 | blueswir1 | NULL,
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322 | 7c560456 | blueswir1 | NULL,
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323 | e80cfcfc | bellard | slavio_timer_mem_writel, |
324 | e80cfcfc | bellard | }; |
325 | e80cfcfc | bellard | |
326 | f4b19cd0 | Blue Swirl | static const VMStateDescription vmstate_timer = { |
327 | f4b19cd0 | Blue Swirl | .name ="timer",
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328 | f4b19cd0 | Blue Swirl | .version_id = 3,
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329 | f4b19cd0 | Blue Swirl | .minimum_version_id = 3,
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330 | f4b19cd0 | Blue Swirl | .minimum_version_id_old = 3,
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331 | f4b19cd0 | Blue Swirl | .fields = (VMStateField []) { |
332 | f4b19cd0 | Blue Swirl | VMSTATE_UINT64(limit, CPUTimerState), |
333 | f4b19cd0 | Blue Swirl | VMSTATE_UINT32(count, CPUTimerState), |
334 | f4b19cd0 | Blue Swirl | VMSTATE_UINT32(counthigh, CPUTimerState), |
335 | f4b19cd0 | Blue Swirl | VMSTATE_UINT32(reached, CPUTimerState), |
336 | f4b19cd0 | Blue Swirl | VMSTATE_UINT32(running, CPUTimerState), |
337 | f4b19cd0 | Blue Swirl | VMSTATE_PTIMER(timer, CPUTimerState), |
338 | f4b19cd0 | Blue Swirl | VMSTATE_END_OF_LIST() |
339 | 7204ff9c | Blue Swirl | } |
340 | f4b19cd0 | Blue Swirl | }; |
341 | e80cfcfc | bellard | |
342 | f4b19cd0 | Blue Swirl | static const VMStateDescription vmstate_slavio_timer = { |
343 | f4b19cd0 | Blue Swirl | .name ="slavio_timer",
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344 | f4b19cd0 | Blue Swirl | .version_id = 3,
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345 | f4b19cd0 | Blue Swirl | .minimum_version_id = 3,
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346 | f4b19cd0 | Blue Swirl | .minimum_version_id_old = 3,
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347 | f4b19cd0 | Blue Swirl | .fields = (VMStateField []) { |
348 | f4b19cd0 | Blue Swirl | VMSTATE_STRUCT_ARRAY(cputimer, SLAVIO_TIMERState, MAX_CPUS + 1, 3, |
349 | f4b19cd0 | Blue Swirl | vmstate_timer, CPUTimerState), |
350 | f4b19cd0 | Blue Swirl | VMSTATE_END_OF_LIST() |
351 | 7204ff9c | Blue Swirl | } |
352 | f4b19cd0 | Blue Swirl | }; |
353 | e80cfcfc | bellard | |
354 | 0e0bfeea | Blue Swirl | static void slavio_timer_reset(DeviceState *d) |
355 | e80cfcfc | bellard | { |
356 | 0e0bfeea | Blue Swirl | SLAVIO_TIMERState *s = container_of(d, SLAVIO_TIMERState, busdev.qdev); |
357 | 7204ff9c | Blue Swirl | unsigned int i; |
358 | 7204ff9c | Blue Swirl | CPUTimerState *curr_timer; |
359 | 7204ff9c | Blue Swirl | |
360 | 7204ff9c | Blue Swirl | for (i = 0; i <= MAX_CPUS; i++) { |
361 | 7204ff9c | Blue Swirl | curr_timer = &s->cputimer[i]; |
362 | 7204ff9c | Blue Swirl | curr_timer->limit = 0;
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363 | 7204ff9c | Blue Swirl | curr_timer->count = 0;
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364 | 7204ff9c | Blue Swirl | curr_timer->reached = 0;
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365 | 5933e8a9 | Artyom Tarasenko | if (i <= s->num_cpus) {
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366 | 7204ff9c | Blue Swirl | ptimer_set_limit(curr_timer->timer, |
367 | 7204ff9c | Blue Swirl | LIMIT_TO_PERIODS(TIMER_MAX_COUNT32), 1);
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368 | 7204ff9c | Blue Swirl | ptimer_run(curr_timer->timer, 0);
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369 | 5933e8a9 | Artyom Tarasenko | curr_timer->running = 1;
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370 | 7204ff9c | Blue Swirl | } |
371 | 85e3023e | blueswir1 | } |
372 | 7204ff9c | Blue Swirl | s->cputimer_mode = 0;
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373 | e80cfcfc | bellard | } |
374 | e80cfcfc | bellard | |
375 | 81a322d4 | Gerd Hoffmann | static int slavio_timer_init1(SysBusDevice *dev) |
376 | c70c59ee | Blue Swirl | { |
377 | c70c59ee | Blue Swirl | int io;
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378 | c70c59ee | Blue Swirl | SLAVIO_TIMERState *s = FROM_SYSBUS(SLAVIO_TIMERState, dev); |
379 | 8d05ea8a | blueswir1 | QEMUBH *bh; |
380 | 7204ff9c | Blue Swirl | unsigned int i; |
381 | 7204ff9c | Blue Swirl | TimerContext *tc; |
382 | e80cfcfc | bellard | |
383 | 7204ff9c | Blue Swirl | for (i = 0; i <= MAX_CPUS; i++) { |
384 | 7204ff9c | Blue Swirl | tc = qemu_mallocz(sizeof(TimerContext));
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385 | 7204ff9c | Blue Swirl | tc->s = s; |
386 | 7204ff9c | Blue Swirl | tc->timer_index = i; |
387 | c70c59ee | Blue Swirl | |
388 | 7204ff9c | Blue Swirl | bh = qemu_bh_new(slavio_timer_irq, tc); |
389 | 7204ff9c | Blue Swirl | s->cputimer[i].timer = ptimer_init(bh); |
390 | 7204ff9c | Blue Swirl | ptimer_set_period(s->cputimer[i].timer, TIMER_PERIOD); |
391 | e80cfcfc | bellard | |
392 | 7204ff9c | Blue Swirl | io = cpu_register_io_memory(slavio_timer_mem_read, |
393 | 2507c12a | Alexander Graf | slavio_timer_mem_write, tc, |
394 | 2507c12a | Alexander Graf | DEVICE_NATIVE_ENDIAN); |
395 | 7204ff9c | Blue Swirl | if (i == 0) { |
396 | 7204ff9c | Blue Swirl | sysbus_init_mmio(dev, SYS_TIMER_SIZE, io); |
397 | 7204ff9c | Blue Swirl | } else {
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398 | 7204ff9c | Blue Swirl | sysbus_init_mmio(dev, CPU_TIMER_SIZE, io); |
399 | 7204ff9c | Blue Swirl | } |
400 | 7204ff9c | Blue Swirl | |
401 | 7204ff9c | Blue Swirl | sysbus_init_irq(dev, &s->cputimer[i].irq); |
402 | c70c59ee | Blue Swirl | } |
403 | c70c59ee | Blue Swirl | |
404 | 81a322d4 | Gerd Hoffmann | return 0; |
405 | 81732d19 | blueswir1 | } |
406 | 81732d19 | blueswir1 | |
407 | c70c59ee | Blue Swirl | static SysBusDeviceInfo slavio_timer_info = {
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408 | c70c59ee | Blue Swirl | .init = slavio_timer_init1, |
409 | c70c59ee | Blue Swirl | .qdev.name = "slavio_timer",
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410 | c70c59ee | Blue Swirl | .qdev.size = sizeof(SLAVIO_TIMERState),
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411 | 0e0bfeea | Blue Swirl | .qdev.vmsd = &vmstate_slavio_timer, |
412 | 0e0bfeea | Blue Swirl | .qdev.reset = slavio_timer_reset, |
413 | ee6847d1 | Gerd Hoffmann | .qdev.props = (Property[]) { |
414 | 18c637dc | Gerd Hoffmann | DEFINE_PROP_UINT32("num_cpus", SLAVIO_TIMERState, num_cpus, 0), |
415 | 18c637dc | Gerd Hoffmann | DEFINE_PROP_END_OF_LIST(), |
416 | c70c59ee | Blue Swirl | } |
417 | c70c59ee | Blue Swirl | }; |
418 | c70c59ee | Blue Swirl | |
419 | c70c59ee | Blue Swirl | static void slavio_timer_register_devices(void) |
420 | c70c59ee | Blue Swirl | { |
421 | c70c59ee | Blue Swirl | sysbus_register_withprop(&slavio_timer_info); |
422 | c70c59ee | Blue Swirl | } |
423 | c70c59ee | Blue Swirl | |
424 | c70c59ee | Blue Swirl | device_init(slavio_timer_register_devices) |