Revision d34defbc target-ppc/translate_init.c
| b/target-ppc/translate_init.c | ||
|---|---|---|
| 448 | 448 |
} |
| 449 | 449 |
#endif |
| 450 | 450 |
|
| 451 |
/* SPE specific registers */ |
|
| 452 |
static void spr_read_spefscr (void *opaque, int gprn, int sprn) |
|
| 453 |
{
|
|
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TCGv_i32 t0 = tcg_temp_new_i32(); |
|
| 455 |
tcg_gen_ld_tl(t0, cpu_env, offsetof(CPUState, spe_fscr)); |
|
| 456 |
tcg_gen_extu_i32_tl(cpu_gpr[gprn], t0); |
|
| 457 |
tcg_temp_free_i32(t0); |
|
| 458 |
} |
|
| 459 |
|
|
| 460 |
static void spr_write_spefscr (void *opaque, int sprn, int gprn) |
|
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{
|
|
| 462 |
TCGv_i32 t0 = tcg_temp_new_i32(); |
|
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tcg_gen_trunc_tl_i32(t0, cpu_gpr[gprn]); |
|
| 464 |
tcg_gen_st_tl(t0, cpu_env, offsetof(CPUState, spe_fscr)); |
|
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tcg_temp_free_i32(t0); |
|
| 466 |
} |
|
| 467 |
|
|
| 451 | 468 |
#if !defined(CONFIG_USER_ONLY) |
| 452 | 469 |
/* Callback used to write the exception vector base */ |
| 453 | 470 |
static void spr_write_excp_prefix (void *opaque, int sprn, int gprn) |
| ... | ... | |
| 2565 | 2582 |
* HSRR1 => SPR 315 (Power 2.04 hypv) |
| 2566 | 2583 |
* LPCR => SPR 316 (970) |
| 2567 | 2584 |
* LPIDR => SPR 317 (970) |
| 2568 |
* SPEFSCR => SPR 512 (Power 2.04 emb) |
|
| 2569 | 2585 |
* EPR => SPR 702 (Power 2.04 emb) |
| 2570 | 2586 |
* perf => 768-783 (Power 2.04) |
| 2571 | 2587 |
* perf => 784-799 (Power 2.04) |
| ... | ... | |
| 4021 | 4037 |
gen_spr_BookE(env, 0x000000070000FFFFULL); |
| 4022 | 4038 |
/* XXX : not implemented */ |
| 4023 | 4039 |
spr_register(env, SPR_BOOKE_SPEFSCR, "SPEFSCR", |
| 4024 |
SPR_NOACCESS, SPR_NOACCESS,
|
|
| 4025 |
&spr_read_generic, &spr_write_generic,
|
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| 4040 |
&spr_read_spefscr, &spr_write_spefscr,
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&spr_read_spefscr, &spr_write_spefscr,
|
|
| 4026 | 4042 |
0x00000000); |
| 4027 | 4043 |
/* Memory management */ |
| 4028 | 4044 |
gen_spr_BookE_FSL(env, 0x0000005D); |
| ... | ... | |
| 4210 | 4226 |
0x00000000); |
| 4211 | 4227 |
/* XXX : not implemented */ |
| 4212 | 4228 |
spr_register(env, SPR_BOOKE_SPEFSCR, "SPEFSCR", |
| 4213 |
SPR_NOACCESS, SPR_NOACCESS,
|
|
| 4214 |
&spr_read_generic, &spr_write_generic,
|
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| 4229 |
&spr_read_spefscr, &spr_write_spefscr,
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|
| 4230 |
&spr_read_spefscr, &spr_write_spefscr,
|
|
| 4215 | 4231 |
0x00000000); |
| 4216 | 4232 |
/* Memory management */ |
| 4217 | 4233 |
#if !defined(CONFIG_USER_ONLY) |
| ... | ... | |
| 9428 | 9444 |
return 8; |
| 9429 | 9445 |
} |
| 9430 | 9446 |
if (n == 33) {
|
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/* SPEFSCR not implemented */ |
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memset(mem_buf, 0, 4); |
|
| 9447 |
stl_p(mem_buf, env->spe_fscr); |
|
| 9433 | 9448 |
return 4; |
| 9434 | 9449 |
} |
| 9435 | 9450 |
return 0; |
| ... | ... | |
| 9452 | 9467 |
return 8; |
| 9453 | 9468 |
} |
| 9454 | 9469 |
if (n == 33) {
|
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/* SPEFSCR not implemented */
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env->spe_fscr = ldl_p(mem_buf);
|
|
| 9456 | 9471 |
return 4; |
| 9457 | 9472 |
} |
| 9458 | 9473 |
return 0; |
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