root / hw / rtl8139.c @ d3674c57
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1 | a41b2ff2 | pbrook | /**
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2 | a41b2ff2 | pbrook | * QEMU RTL8139 emulation
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3 | 5fafdf24 | ths | *
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4 | a41b2ff2 | pbrook | * Copyright (c) 2006 Igor Kovalenko
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5 | 5fafdf24 | ths | *
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6 | a41b2ff2 | pbrook | * Permission is hereby granted, free of charge, to any person obtaining a copy
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7 | a41b2ff2 | pbrook | * of this software and associated documentation files (the "Software"), to deal
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8 | a41b2ff2 | pbrook | * in the Software without restriction, including without limitation the rights
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9 | a41b2ff2 | pbrook | * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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10 | a41b2ff2 | pbrook | * copies of the Software, and to permit persons to whom the Software is
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11 | a41b2ff2 | pbrook | * furnished to do so, subject to the following conditions:
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12 | a41b2ff2 | pbrook | *
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13 | a41b2ff2 | pbrook | * The above copyright notice and this permission notice shall be included in
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14 | a41b2ff2 | pbrook | * all copies or substantial portions of the Software.
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15 | a41b2ff2 | pbrook | *
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16 | a41b2ff2 | pbrook | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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17 | a41b2ff2 | pbrook | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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18 | a41b2ff2 | pbrook | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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19 | a41b2ff2 | pbrook | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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20 | a41b2ff2 | pbrook | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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21 | a41b2ff2 | pbrook | * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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22 | a41b2ff2 | pbrook | * THE SOFTWARE.
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23 | 5fafdf24 | ths | |
24 | a41b2ff2 | pbrook | * Modifications:
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25 | a41b2ff2 | pbrook | * 2006-Jan-28 Mark Malakanov : TSAD and CSCR implementation (for Windows driver)
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26 | 5fafdf24 | ths | *
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27 | 6cadb320 | bellard | * 2006-Apr-28 Juergen Lock : EEPROM emulation changes for FreeBSD driver
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28 | 6cadb320 | bellard | * HW revision ID changes for FreeBSD driver
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29 | 5fafdf24 | ths | *
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30 | 6cadb320 | bellard | * 2006-Jul-01 Igor Kovalenko : Implemented loopback mode for FreeBSD driver
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31 | 6cadb320 | bellard | * Corrected packet transfer reassembly routine for 8139C+ mode
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32 | 6cadb320 | bellard | * Rearranged debugging print statements
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33 | 6cadb320 | bellard | * Implemented PCI timer interrupt (disabled by default)
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34 | 6cadb320 | bellard | * Implemented Tally Counters, increased VM load/save version
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35 | 6cadb320 | bellard | * Implemented IP/TCP/UDP checksum task offloading
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36 | 718da2b9 | bellard | *
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37 | 718da2b9 | bellard | * 2006-Jul-04 Igor Kovalenko : Implemented TCP segmentation offloading
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38 | 718da2b9 | bellard | * Fixed MTU=1500 for produced ethernet frames
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39 | 718da2b9 | bellard | *
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40 | 718da2b9 | bellard | * 2006-Jul-09 Igor Kovalenko : Fixed TCP header length calculation while processing
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41 | 718da2b9 | bellard | * segmentation offloading
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42 | 718da2b9 | bellard | * Removed slirp.h dependency
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43 | 718da2b9 | bellard | * Added rx/tx buffer reset when enabling rx/tx operation
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44 | 05447803 | Frediano Ziglio | *
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45 | 05447803 | Frediano Ziglio | * 2010-Feb-04 Frediano Ziglio: Rewrote timer support using QEMU timer only
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46 | 05447803 | Frediano Ziglio | * when strictly needed (required for for
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47 | 05447803 | Frediano Ziglio | * Darwin)
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48 | bf6b87a8 | Benjamin Poirier | * 2011-Mar-22 Benjamin Poirier: Implemented VLAN offloading
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49 | a41b2ff2 | pbrook | */
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50 | a41b2ff2 | pbrook | |
51 | 2c406b8f | Benjamin Poirier | /* For crc32 */
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52 | 2c406b8f | Benjamin Poirier | #include <zlib.h> |
53 | 2c406b8f | Benjamin Poirier | |
54 | 87ecb68b | pbrook | #include "hw.h" |
55 | 87ecb68b | pbrook | #include "pci.h" |
56 | 87ecb68b | pbrook | #include "qemu-timer.h" |
57 | 87ecb68b | pbrook | #include "net.h" |
58 | 254111ec | Gerd Hoffmann | #include "loader.h" |
59 | 1ca4d09a | Gleb Natapov | #include "sysemu.h" |
60 | bf6b87a8 | Benjamin Poirier | #include "iov.h" |
61 | a41b2ff2 | pbrook | |
62 | a41b2ff2 | pbrook | /* debug RTL8139 card */
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63 | a41b2ff2 | pbrook | //#define DEBUG_RTL8139 1
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64 | a41b2ff2 | pbrook | |
65 | 6cadb320 | bellard | #define PCI_FREQUENCY 33000000L |
66 | 6cadb320 | bellard | |
67 | a41b2ff2 | pbrook | /* debug RTL8139 card C+ mode only */
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68 | a41b2ff2 | pbrook | //#define DEBUG_RTL8139CP 1
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69 | a41b2ff2 | pbrook | |
70 | a41b2ff2 | pbrook | #define SET_MASKED(input, mask, curr) \
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71 | a41b2ff2 | pbrook | ( ( (input) & ~(mask) ) | ( (curr) & (mask) ) ) |
72 | a41b2ff2 | pbrook | |
73 | a41b2ff2 | pbrook | /* arg % size for size which is a power of 2 */
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74 | a41b2ff2 | pbrook | #define MOD2(input, size) \
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75 | a41b2ff2 | pbrook | ( ( input ) & ( size - 1 ) )
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76 | a41b2ff2 | pbrook | |
77 | 18dabfd1 | Benjamin Poirier | #define ETHER_ADDR_LEN 6 |
78 | 18dabfd1 | Benjamin Poirier | #define ETHER_TYPE_LEN 2 |
79 | 18dabfd1 | Benjamin Poirier | #define ETH_HLEN (ETHER_ADDR_LEN * 2 + ETHER_TYPE_LEN) |
80 | 18dabfd1 | Benjamin Poirier | #define ETH_P_IP 0x0800 /* Internet Protocol packet */ |
81 | 18dabfd1 | Benjamin Poirier | #define ETH_P_8021Q 0x8100 /* 802.1Q VLAN Extended Header */ |
82 | 18dabfd1 | Benjamin Poirier | #define ETH_MTU 1500 |
83 | 18dabfd1 | Benjamin Poirier | |
84 | 18dabfd1 | Benjamin Poirier | #define VLAN_TCI_LEN 2 |
85 | 18dabfd1 | Benjamin Poirier | #define VLAN_HLEN (ETHER_TYPE_LEN + VLAN_TCI_LEN)
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86 | 18dabfd1 | Benjamin Poirier | |
87 | 6cadb320 | bellard | #if defined (DEBUG_RTL8139)
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88 | 7cdeb319 | Benjamin Poirier | # define DPRINTF(fmt, ...) \
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89 | 7cdeb319 | Benjamin Poirier | do { fprintf(stderr, "RTL8139: " fmt, ## __VA_ARGS__); } while (0) |
90 | 6cadb320 | bellard | #else
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91 | c6a0487b | Stefan Weil | static inline GCC_FMT_ATTR(1, 2) int DPRINTF(const char *fmt, ...) |
92 | ec48c774 | Benjamin Poirier | { |
93 | ec48c774 | Benjamin Poirier | return 0; |
94 | ec48c774 | Benjamin Poirier | } |
95 | 6cadb320 | bellard | #endif
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96 | 6cadb320 | bellard | |
97 | a41b2ff2 | pbrook | /* Symbolic offsets to registers. */
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98 | a41b2ff2 | pbrook | enum RTL8139_registers {
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99 | a41b2ff2 | pbrook | MAC0 = 0, /* Ethernet hardware address. */ |
100 | a41b2ff2 | pbrook | MAR0 = 8, /* Multicast filter. */ |
101 | 6cadb320 | bellard | TxStatus0 = 0x10,/* Transmit status (Four 32bit registers). C mode only */ |
102 | 6cadb320 | bellard | /* Dump Tally Conter control register(64bit). C+ mode only */
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103 | 6cadb320 | bellard | TxAddr0 = 0x20, /* Tx descriptors (also four 32bit). */ |
104 | a41b2ff2 | pbrook | RxBuf = 0x30,
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105 | a41b2ff2 | pbrook | ChipCmd = 0x37,
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106 | a41b2ff2 | pbrook | RxBufPtr = 0x38,
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107 | a41b2ff2 | pbrook | RxBufAddr = 0x3A,
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108 | a41b2ff2 | pbrook | IntrMask = 0x3C,
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109 | a41b2ff2 | pbrook | IntrStatus = 0x3E,
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110 | a41b2ff2 | pbrook | TxConfig = 0x40,
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111 | a41b2ff2 | pbrook | RxConfig = 0x44,
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112 | a41b2ff2 | pbrook | Timer = 0x48, /* A general-purpose counter. */ |
113 | a41b2ff2 | pbrook | RxMissed = 0x4C, /* 24 bits valid, write clears. */ |
114 | a41b2ff2 | pbrook | Cfg9346 = 0x50,
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115 | a41b2ff2 | pbrook | Config0 = 0x51,
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116 | a41b2ff2 | pbrook | Config1 = 0x52,
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117 | a41b2ff2 | pbrook | FlashReg = 0x54,
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118 | a41b2ff2 | pbrook | MediaStatus = 0x58,
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119 | a41b2ff2 | pbrook | Config3 = 0x59,
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120 | a41b2ff2 | pbrook | Config4 = 0x5A, /* absent on RTL-8139A */ |
121 | a41b2ff2 | pbrook | HltClk = 0x5B,
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122 | a41b2ff2 | pbrook | MultiIntr = 0x5C,
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123 | a41b2ff2 | pbrook | PCIRevisionID = 0x5E,
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124 | a41b2ff2 | pbrook | TxSummary = 0x60, /* TSAD register. Transmit Status of All Descriptors*/ |
125 | a41b2ff2 | pbrook | BasicModeCtrl = 0x62,
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126 | a41b2ff2 | pbrook | BasicModeStatus = 0x64,
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127 | a41b2ff2 | pbrook | NWayAdvert = 0x66,
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128 | a41b2ff2 | pbrook | NWayLPAR = 0x68,
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129 | a41b2ff2 | pbrook | NWayExpansion = 0x6A,
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130 | a41b2ff2 | pbrook | /* Undocumented registers, but required for proper operation. */
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131 | a41b2ff2 | pbrook | FIFOTMS = 0x70, /* FIFO Control and test. */ |
132 | a41b2ff2 | pbrook | CSCR = 0x74, /* Chip Status and Configuration Register. */ |
133 | a41b2ff2 | pbrook | PARA78 = 0x78,
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134 | a41b2ff2 | pbrook | PARA7c = 0x7c, /* Magic transceiver parameter register. */ |
135 | a41b2ff2 | pbrook | Config5 = 0xD8, /* absent on RTL-8139A */ |
136 | a41b2ff2 | pbrook | /* C+ mode */
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137 | a41b2ff2 | pbrook | TxPoll = 0xD9, /* Tell chip to check Tx descriptors for work */ |
138 | a41b2ff2 | pbrook | RxMaxSize = 0xDA, /* Max size of an Rx packet (8169 only) */ |
139 | a41b2ff2 | pbrook | CpCmd = 0xE0, /* C+ Command register (C+ mode only) */ |
140 | a41b2ff2 | pbrook | IntrMitigate = 0xE2, /* rx/tx interrupt mitigation control */ |
141 | a41b2ff2 | pbrook | RxRingAddrLO = 0xE4, /* 64-bit start addr of Rx ring */ |
142 | a41b2ff2 | pbrook | RxRingAddrHI = 0xE8, /* 64-bit start addr of Rx ring */ |
143 | a41b2ff2 | pbrook | TxThresh = 0xEC, /* Early Tx threshold */ |
144 | a41b2ff2 | pbrook | }; |
145 | a41b2ff2 | pbrook | |
146 | a41b2ff2 | pbrook | enum ClearBitMasks {
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147 | a41b2ff2 | pbrook | MultiIntrClear = 0xF000,
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148 | a41b2ff2 | pbrook | ChipCmdClear = 0xE2,
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149 | a41b2ff2 | pbrook | Config1Clear = (1<<7)|(1<<6)|(1<<3)|(1<<2)|(1<<1), |
150 | a41b2ff2 | pbrook | }; |
151 | a41b2ff2 | pbrook | |
152 | a41b2ff2 | pbrook | enum ChipCmdBits {
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153 | a41b2ff2 | pbrook | CmdReset = 0x10,
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154 | a41b2ff2 | pbrook | CmdRxEnb = 0x08,
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155 | a41b2ff2 | pbrook | CmdTxEnb = 0x04,
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156 | a41b2ff2 | pbrook | RxBufEmpty = 0x01,
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157 | a41b2ff2 | pbrook | }; |
158 | a41b2ff2 | pbrook | |
159 | a41b2ff2 | pbrook | /* C+ mode */
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160 | a41b2ff2 | pbrook | enum CplusCmdBits {
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161 | 6cadb320 | bellard | CPlusRxVLAN = 0x0040, /* enable receive VLAN detagging */ |
162 | 6cadb320 | bellard | CPlusRxChkSum = 0x0020, /* enable receive checksum offloading */ |
163 | 6cadb320 | bellard | CPlusRxEnb = 0x0002,
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164 | 6cadb320 | bellard | CPlusTxEnb = 0x0001,
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165 | a41b2ff2 | pbrook | }; |
166 | a41b2ff2 | pbrook | |
167 | a41b2ff2 | pbrook | /* Interrupt register bits, using my own meaningful names. */
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168 | a41b2ff2 | pbrook | enum IntrStatusBits {
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169 | a41b2ff2 | pbrook | PCIErr = 0x8000,
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170 | a41b2ff2 | pbrook | PCSTimeout = 0x4000,
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171 | a41b2ff2 | pbrook | RxFIFOOver = 0x40,
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172 | a41b2ff2 | pbrook | RxUnderrun = 0x20,
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173 | a41b2ff2 | pbrook | RxOverflow = 0x10,
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174 | a41b2ff2 | pbrook | TxErr = 0x08,
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175 | a41b2ff2 | pbrook | TxOK = 0x04,
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176 | a41b2ff2 | pbrook | RxErr = 0x02,
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177 | a41b2ff2 | pbrook | RxOK = 0x01,
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178 | a41b2ff2 | pbrook | |
179 | a41b2ff2 | pbrook | RxAckBits = RxFIFOOver | RxOverflow | RxOK, |
180 | a41b2ff2 | pbrook | }; |
181 | a41b2ff2 | pbrook | |
182 | a41b2ff2 | pbrook | enum TxStatusBits {
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183 | a41b2ff2 | pbrook | TxHostOwns = 0x2000,
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184 | a41b2ff2 | pbrook | TxUnderrun = 0x4000,
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185 | a41b2ff2 | pbrook | TxStatOK = 0x8000,
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186 | a41b2ff2 | pbrook | TxOutOfWindow = 0x20000000,
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187 | a41b2ff2 | pbrook | TxAborted = 0x40000000,
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188 | a41b2ff2 | pbrook | TxCarrierLost = 0x80000000,
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189 | a41b2ff2 | pbrook | }; |
190 | a41b2ff2 | pbrook | enum RxStatusBits {
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191 | a41b2ff2 | pbrook | RxMulticast = 0x8000,
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192 | a41b2ff2 | pbrook | RxPhysical = 0x4000,
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193 | a41b2ff2 | pbrook | RxBroadcast = 0x2000,
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194 | a41b2ff2 | pbrook | RxBadSymbol = 0x0020,
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195 | a41b2ff2 | pbrook | RxRunt = 0x0010,
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196 | a41b2ff2 | pbrook | RxTooLong = 0x0008,
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197 | a41b2ff2 | pbrook | RxCRCErr = 0x0004,
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198 | a41b2ff2 | pbrook | RxBadAlign = 0x0002,
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199 | a41b2ff2 | pbrook | RxStatusOK = 0x0001,
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200 | a41b2ff2 | pbrook | }; |
201 | a41b2ff2 | pbrook | |
202 | a41b2ff2 | pbrook | /* Bits in RxConfig. */
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203 | a41b2ff2 | pbrook | enum rx_mode_bits {
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204 | a41b2ff2 | pbrook | AcceptErr = 0x20,
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205 | a41b2ff2 | pbrook | AcceptRunt = 0x10,
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206 | a41b2ff2 | pbrook | AcceptBroadcast = 0x08,
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207 | a41b2ff2 | pbrook | AcceptMulticast = 0x04,
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208 | a41b2ff2 | pbrook | AcceptMyPhys = 0x02,
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209 | a41b2ff2 | pbrook | AcceptAllPhys = 0x01,
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210 | a41b2ff2 | pbrook | }; |
211 | a41b2ff2 | pbrook | |
212 | a41b2ff2 | pbrook | /* Bits in TxConfig. */
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213 | a41b2ff2 | pbrook | enum tx_config_bits {
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214 | a41b2ff2 | pbrook | |
215 | a41b2ff2 | pbrook | /* Interframe Gap Time. Only TxIFG96 doesn't violate IEEE 802.3 */
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216 | a41b2ff2 | pbrook | TxIFGShift = 24,
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217 | a41b2ff2 | pbrook | TxIFG84 = (0 << TxIFGShift), /* 8.4us / 840ns (10 / 100Mbps) */ |
218 | a41b2ff2 | pbrook | TxIFG88 = (1 << TxIFGShift), /* 8.8us / 880ns (10 / 100Mbps) */ |
219 | a41b2ff2 | pbrook | TxIFG92 = (2 << TxIFGShift), /* 9.2us / 920ns (10 / 100Mbps) */ |
220 | a41b2ff2 | pbrook | TxIFG96 = (3 << TxIFGShift), /* 9.6us / 960ns (10 / 100Mbps) */ |
221 | a41b2ff2 | pbrook | |
222 | a41b2ff2 | pbrook | TxLoopBack = (1 << 18) | (1 << 17), /* enable loopback test mode */ |
223 | a41b2ff2 | pbrook | TxCRC = (1 << 16), /* DISABLE appending CRC to end of Tx packets */ |
224 | a41b2ff2 | pbrook | TxClearAbt = (1 << 0), /* Clear abort (WO) */ |
225 | a41b2ff2 | pbrook | TxDMAShift = 8, /* DMA burst value (0-7) is shifted this many bits */ |
226 | a41b2ff2 | pbrook | TxRetryShift = 4, /* TXRR value (0-15) is shifted this many bits */ |
227 | a41b2ff2 | pbrook | |
228 | a41b2ff2 | pbrook | TxVersionMask = 0x7C800000, /* mask out version bits 30-26, 23 */ |
229 | a41b2ff2 | pbrook | }; |
230 | a41b2ff2 | pbrook | |
231 | a41b2ff2 | pbrook | |
232 | a41b2ff2 | pbrook | /* Transmit Status of All Descriptors (TSAD) Register */
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233 | a41b2ff2 | pbrook | enum TSAD_bits {
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234 | a41b2ff2 | pbrook | TSAD_TOK3 = 1<<15, // TOK bit of Descriptor 3 |
235 | a41b2ff2 | pbrook | TSAD_TOK2 = 1<<14, // TOK bit of Descriptor 2 |
236 | a41b2ff2 | pbrook | TSAD_TOK1 = 1<<13, // TOK bit of Descriptor 1 |
237 | a41b2ff2 | pbrook | TSAD_TOK0 = 1<<12, // TOK bit of Descriptor 0 |
238 | a41b2ff2 | pbrook | TSAD_TUN3 = 1<<11, // TUN bit of Descriptor 3 |
239 | a41b2ff2 | pbrook | TSAD_TUN2 = 1<<10, // TUN bit of Descriptor 2 |
240 | a41b2ff2 | pbrook | TSAD_TUN1 = 1<<9, // TUN bit of Descriptor 1 |
241 | a41b2ff2 | pbrook | TSAD_TUN0 = 1<<8, // TUN bit of Descriptor 0 |
242 | a41b2ff2 | pbrook | TSAD_TABT3 = 1<<07, // TABT bit of Descriptor 3 |
243 | a41b2ff2 | pbrook | TSAD_TABT2 = 1<<06, // TABT bit of Descriptor 2 |
244 | a41b2ff2 | pbrook | TSAD_TABT1 = 1<<05, // TABT bit of Descriptor 1 |
245 | a41b2ff2 | pbrook | TSAD_TABT0 = 1<<04, // TABT bit of Descriptor 0 |
246 | a41b2ff2 | pbrook | TSAD_OWN3 = 1<<03, // OWN bit of Descriptor 3 |
247 | a41b2ff2 | pbrook | TSAD_OWN2 = 1<<02, // OWN bit of Descriptor 2 |
248 | a41b2ff2 | pbrook | TSAD_OWN1 = 1<<01, // OWN bit of Descriptor 1 |
249 | a41b2ff2 | pbrook | TSAD_OWN0 = 1<<00, // OWN bit of Descriptor 0 |
250 | a41b2ff2 | pbrook | }; |
251 | a41b2ff2 | pbrook | |
252 | a41b2ff2 | pbrook | |
253 | a41b2ff2 | pbrook | /* Bits in Config1 */
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254 | a41b2ff2 | pbrook | enum Config1Bits {
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255 | a41b2ff2 | pbrook | Cfg1_PM_Enable = 0x01,
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256 | a41b2ff2 | pbrook | Cfg1_VPD_Enable = 0x02,
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257 | a41b2ff2 | pbrook | Cfg1_PIO = 0x04,
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258 | a41b2ff2 | pbrook | Cfg1_MMIO = 0x08,
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259 | a41b2ff2 | pbrook | LWAKE = 0x10, /* not on 8139, 8139A */ |
260 | a41b2ff2 | pbrook | Cfg1_Driver_Load = 0x20,
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261 | a41b2ff2 | pbrook | Cfg1_LED0 = 0x40,
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262 | a41b2ff2 | pbrook | Cfg1_LED1 = 0x80,
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263 | a41b2ff2 | pbrook | SLEEP = (1 << 1), /* only on 8139, 8139A */ |
264 | a41b2ff2 | pbrook | PWRDN = (1 << 0), /* only on 8139, 8139A */ |
265 | a41b2ff2 | pbrook | }; |
266 | a41b2ff2 | pbrook | |
267 | a41b2ff2 | pbrook | /* Bits in Config3 */
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268 | a41b2ff2 | pbrook | enum Config3Bits {
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269 | a41b2ff2 | pbrook | Cfg3_FBtBEn = (1 << 0), /* 1 = Fast Back to Back */ |
270 | a41b2ff2 | pbrook | Cfg3_FuncRegEn = (1 << 1), /* 1 = enable CardBus Function registers */ |
271 | a41b2ff2 | pbrook | Cfg3_CLKRUN_En = (1 << 2), /* 1 = enable CLKRUN */ |
272 | a41b2ff2 | pbrook | Cfg3_CardB_En = (1 << 3), /* 1 = enable CardBus registers */ |
273 | a41b2ff2 | pbrook | Cfg3_LinkUp = (1 << 4), /* 1 = wake up on link up */ |
274 | a41b2ff2 | pbrook | Cfg3_Magic = (1 << 5), /* 1 = wake up on Magic Packet (tm) */ |
275 | a41b2ff2 | pbrook | Cfg3_PARM_En = (1 << 6), /* 0 = software can set twister parameters */ |
276 | a41b2ff2 | pbrook | Cfg3_GNTSel = (1 << 7), /* 1 = delay 1 clock from PCI GNT signal */ |
277 | a41b2ff2 | pbrook | }; |
278 | a41b2ff2 | pbrook | |
279 | a41b2ff2 | pbrook | /* Bits in Config4 */
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280 | a41b2ff2 | pbrook | enum Config4Bits {
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281 | a41b2ff2 | pbrook | LWPTN = (1 << 2), /* not on 8139, 8139A */ |
282 | a41b2ff2 | pbrook | }; |
283 | a41b2ff2 | pbrook | |
284 | a41b2ff2 | pbrook | /* Bits in Config5 */
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285 | a41b2ff2 | pbrook | enum Config5Bits {
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286 | a41b2ff2 | pbrook | Cfg5_PME_STS = (1 << 0), /* 1 = PCI reset resets PME_Status */ |
287 | a41b2ff2 | pbrook | Cfg5_LANWake = (1 << 1), /* 1 = enable LANWake signal */ |
288 | a41b2ff2 | pbrook | Cfg5_LDPS = (1 << 2), /* 0 = save power when link is down */ |
289 | a41b2ff2 | pbrook | Cfg5_FIFOAddrPtr = (1 << 3), /* Realtek internal SRAM testing */ |
290 | a41b2ff2 | pbrook | Cfg5_UWF = (1 << 4), /* 1 = accept unicast wakeup frame */ |
291 | a41b2ff2 | pbrook | Cfg5_MWF = (1 << 5), /* 1 = accept multicast wakeup frame */ |
292 | a41b2ff2 | pbrook | Cfg5_BWF = (1 << 6), /* 1 = accept broadcast wakeup frame */ |
293 | a41b2ff2 | pbrook | }; |
294 | a41b2ff2 | pbrook | |
295 | a41b2ff2 | pbrook | enum RxConfigBits {
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296 | a41b2ff2 | pbrook | /* rx fifo threshold */
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297 | a41b2ff2 | pbrook | RxCfgFIFOShift = 13,
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298 | a41b2ff2 | pbrook | RxCfgFIFONone = (7 << RxCfgFIFOShift),
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299 | a41b2ff2 | pbrook | |
300 | a41b2ff2 | pbrook | /* Max DMA burst */
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301 | a41b2ff2 | pbrook | RxCfgDMAShift = 8,
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302 | a41b2ff2 | pbrook | RxCfgDMAUnlimited = (7 << RxCfgDMAShift),
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303 | a41b2ff2 | pbrook | |
304 | a41b2ff2 | pbrook | /* rx ring buffer length */
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305 | a41b2ff2 | pbrook | RxCfgRcv8K = 0,
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306 | a41b2ff2 | pbrook | RxCfgRcv16K = (1 << 11), |
307 | a41b2ff2 | pbrook | RxCfgRcv32K = (1 << 12), |
308 | a41b2ff2 | pbrook | RxCfgRcv64K = (1 << 11) | (1 << 12), |
309 | a41b2ff2 | pbrook | |
310 | a41b2ff2 | pbrook | /* Disable packet wrap at end of Rx buffer. (not possible with 64k) */
|
311 | a41b2ff2 | pbrook | RxNoWrap = (1 << 7), |
312 | a41b2ff2 | pbrook | }; |
313 | a41b2ff2 | pbrook | |
314 | a41b2ff2 | pbrook | /* Twister tuning parameters from RealTek.
|
315 | a41b2ff2 | pbrook | Completely undocumented, but required to tune bad links on some boards. */
|
316 | a41b2ff2 | pbrook | /*
|
317 | a41b2ff2 | pbrook | enum CSCRBits {
|
318 | a41b2ff2 | pbrook | CSCR_LinkOKBit = 0x0400,
|
319 | a41b2ff2 | pbrook | CSCR_LinkChangeBit = 0x0800,
|
320 | a41b2ff2 | pbrook | CSCR_LinkStatusBits = 0x0f000,
|
321 | a41b2ff2 | pbrook | CSCR_LinkDownOffCmd = 0x003c0,
|
322 | a41b2ff2 | pbrook | CSCR_LinkDownCmd = 0x0f3c0,
|
323 | a41b2ff2 | pbrook | */
|
324 | a41b2ff2 | pbrook | enum CSCRBits {
|
325 | 5fafdf24 | ths | CSCR_Testfun = 1<<15, /* 1 = Auto-neg speeds up internal timer, WO, def 0 */ |
326 | a41b2ff2 | pbrook | CSCR_LD = 1<<9, /* Active low TPI link disable signal. When low, TPI still transmits link pulses and TPI stays in good link state. def 1*/ |
327 | a41b2ff2 | pbrook | CSCR_HEART_BIT = 1<<8, /* 1 = HEART BEAT enable, 0 = HEART BEAT disable. HEART BEAT function is only valid in 10Mbps mode. def 1*/ |
328 | a41b2ff2 | pbrook | CSCR_JBEN = 1<<7, /* 1 = enable jabber function. 0 = disable jabber function, def 1*/ |
329 | 5fafdf24 | ths | CSCR_F_LINK_100 = 1<<6, /* Used to login force good link in 100Mbps for diagnostic purposes. 1 = DISABLE, 0 = ENABLE. def 1*/ |
330 | a41b2ff2 | pbrook | CSCR_F_Connect = 1<<5, /* Assertion of this bit forces the disconnect function to be bypassed. def 0*/ |
331 | a41b2ff2 | pbrook | CSCR_Con_status = 1<<3, /* This bit indicates the status of the connection. 1 = valid connected link detected; 0 = disconnected link detected. RO def 0*/ |
332 | a41b2ff2 | pbrook | CSCR_Con_status_En = 1<<2, /* Assertion of this bit configures LED1 pin to indicate connection status. def 0*/ |
333 | a41b2ff2 | pbrook | CSCR_PASS_SCR = 1<<0, /* Bypass Scramble, def 0*/ |
334 | a41b2ff2 | pbrook | }; |
335 | a41b2ff2 | pbrook | |
336 | a41b2ff2 | pbrook | enum Cfg9346Bits {
|
337 | a41b2ff2 | pbrook | Cfg9346_Lock = 0x00,
|
338 | a41b2ff2 | pbrook | Cfg9346_Unlock = 0xC0,
|
339 | a41b2ff2 | pbrook | }; |
340 | a41b2ff2 | pbrook | |
341 | a41b2ff2 | pbrook | typedef enum { |
342 | a41b2ff2 | pbrook | CH_8139 = 0,
|
343 | a41b2ff2 | pbrook | CH_8139_K, |
344 | a41b2ff2 | pbrook | CH_8139A, |
345 | a41b2ff2 | pbrook | CH_8139A_G, |
346 | a41b2ff2 | pbrook | CH_8139B, |
347 | a41b2ff2 | pbrook | CH_8130, |
348 | a41b2ff2 | pbrook | CH_8139C, |
349 | a41b2ff2 | pbrook | CH_8100, |
350 | a41b2ff2 | pbrook | CH_8100B_8139D, |
351 | a41b2ff2 | pbrook | CH_8101, |
352 | c227f099 | Anthony Liguori | } chip_t; |
353 | a41b2ff2 | pbrook | |
354 | a41b2ff2 | pbrook | enum chip_flags {
|
355 | a41b2ff2 | pbrook | HasHltClk = (1 << 0), |
356 | a41b2ff2 | pbrook | HasLWake = (1 << 1), |
357 | a41b2ff2 | pbrook | }; |
358 | a41b2ff2 | pbrook | |
359 | a41b2ff2 | pbrook | #define HW_REVID(b30, b29, b28, b27, b26, b23, b22) \
|
360 | a41b2ff2 | pbrook | (b30<<30 | b29<<29 | b28<<28 | b27<<27 | b26<<26 | b23<<23 | b22<<22) |
361 | a41b2ff2 | pbrook | #define HW_REVID_MASK HW_REVID(1, 1, 1, 1, 1, 1, 1) |
362 | a41b2ff2 | pbrook | |
363 | 6cadb320 | bellard | #define RTL8139_PCI_REVID_8139 0x10 |
364 | 6cadb320 | bellard | #define RTL8139_PCI_REVID_8139CPLUS 0x20 |
365 | 6cadb320 | bellard | |
366 | 6cadb320 | bellard | #define RTL8139_PCI_REVID RTL8139_PCI_REVID_8139CPLUS
|
367 | 6cadb320 | bellard | |
368 | a41b2ff2 | pbrook | /* Size is 64 * 16bit words */
|
369 | a41b2ff2 | pbrook | #define EEPROM_9346_ADDR_BITS 6 |
370 | a41b2ff2 | pbrook | #define EEPROM_9346_SIZE (1 << EEPROM_9346_ADDR_BITS) |
371 | a41b2ff2 | pbrook | #define EEPROM_9346_ADDR_MASK (EEPROM_9346_SIZE - 1) |
372 | a41b2ff2 | pbrook | |
373 | a41b2ff2 | pbrook | enum Chip9346Operation
|
374 | a41b2ff2 | pbrook | { |
375 | a41b2ff2 | pbrook | Chip9346_op_mask = 0xc0, /* 10 zzzzzz */ |
376 | a41b2ff2 | pbrook | Chip9346_op_read = 0x80, /* 10 AAAAAA */ |
377 | a41b2ff2 | pbrook | Chip9346_op_write = 0x40, /* 01 AAAAAA D(15)..D(0) */ |
378 | a41b2ff2 | pbrook | Chip9346_op_ext_mask = 0xf0, /* 11 zzzzzz */ |
379 | a41b2ff2 | pbrook | Chip9346_op_write_enable = 0x30, /* 00 11zzzz */ |
380 | a41b2ff2 | pbrook | Chip9346_op_write_all = 0x10, /* 00 01zzzz */ |
381 | a41b2ff2 | pbrook | Chip9346_op_write_disable = 0x00, /* 00 00zzzz */ |
382 | a41b2ff2 | pbrook | }; |
383 | a41b2ff2 | pbrook | |
384 | a41b2ff2 | pbrook | enum Chip9346Mode
|
385 | a41b2ff2 | pbrook | { |
386 | a41b2ff2 | pbrook | Chip9346_none = 0,
|
387 | a41b2ff2 | pbrook | Chip9346_enter_command_mode, |
388 | a41b2ff2 | pbrook | Chip9346_read_command, |
389 | a41b2ff2 | pbrook | Chip9346_data_read, /* from output register */
|
390 | a41b2ff2 | pbrook | Chip9346_data_write, /* to input register, then to contents at specified address */
|
391 | a41b2ff2 | pbrook | Chip9346_data_write_all, /* to input register, then filling contents */
|
392 | a41b2ff2 | pbrook | }; |
393 | a41b2ff2 | pbrook | |
394 | a41b2ff2 | pbrook | typedef struct EEprom9346 |
395 | a41b2ff2 | pbrook | { |
396 | a41b2ff2 | pbrook | uint16_t contents[EEPROM_9346_SIZE]; |
397 | a41b2ff2 | pbrook | int mode;
|
398 | a41b2ff2 | pbrook | uint32_t tick; |
399 | a41b2ff2 | pbrook | uint8_t address; |
400 | a41b2ff2 | pbrook | uint16_t input; |
401 | a41b2ff2 | pbrook | uint16_t output; |
402 | a41b2ff2 | pbrook | |
403 | a41b2ff2 | pbrook | uint8_t eecs; |
404 | a41b2ff2 | pbrook | uint8_t eesk; |
405 | a41b2ff2 | pbrook | uint8_t eedi; |
406 | a41b2ff2 | pbrook | uint8_t eedo; |
407 | a41b2ff2 | pbrook | } EEprom9346; |
408 | a41b2ff2 | pbrook | |
409 | 6cadb320 | bellard | typedef struct RTL8139TallyCounters |
410 | 6cadb320 | bellard | { |
411 | 6cadb320 | bellard | /* Tally counters */
|
412 | 6cadb320 | bellard | uint64_t TxOk; |
413 | 6cadb320 | bellard | uint64_t RxOk; |
414 | 6cadb320 | bellard | uint64_t TxERR; |
415 | 6cadb320 | bellard | uint32_t RxERR; |
416 | 6cadb320 | bellard | uint16_t MissPkt; |
417 | 6cadb320 | bellard | uint16_t FAE; |
418 | 6cadb320 | bellard | uint32_t Tx1Col; |
419 | 6cadb320 | bellard | uint32_t TxMCol; |
420 | 6cadb320 | bellard | uint64_t RxOkPhy; |
421 | 6cadb320 | bellard | uint64_t RxOkBrd; |
422 | 6cadb320 | bellard | uint32_t RxOkMul; |
423 | 6cadb320 | bellard | uint16_t TxAbt; |
424 | 6cadb320 | bellard | uint16_t TxUndrn; |
425 | 6cadb320 | bellard | } RTL8139TallyCounters; |
426 | 6cadb320 | bellard | |
427 | 6cadb320 | bellard | /* Clears all tally counters */
|
428 | 6cadb320 | bellard | static void RTL8139TallyCounters_clear(RTL8139TallyCounters* counters); |
429 | 6cadb320 | bellard | |
430 | 6cadb320 | bellard | /* Writes tally counters to specified physical memory address */
|
431 | c227f099 | Anthony Liguori | static void RTL8139TallyCounters_physical_memory_write(target_phys_addr_t tc_addr, RTL8139TallyCounters* counters); |
432 | 6cadb320 | bellard | |
433 | a41b2ff2 | pbrook | typedef struct RTL8139State { |
434 | efd6dd45 | Juan Quintela | PCIDevice dev; |
435 | a41b2ff2 | pbrook | uint8_t phys[8]; /* mac address */ |
436 | a41b2ff2 | pbrook | uint8_t mult[8]; /* multicast mask array */ |
437 | a41b2ff2 | pbrook | |
438 | 6cadb320 | bellard | uint32_t TxStatus[4]; /* TxStatus0 in C mode*/ /* also DTCCR[0] and DTCCR[1] in C+ mode */ |
439 | a41b2ff2 | pbrook | uint32_t TxAddr[4]; /* TxAddr0 */ |
440 | a41b2ff2 | pbrook | uint32_t RxBuf; /* Receive buffer */
|
441 | a41b2ff2 | pbrook | uint32_t RxBufferSize;/* internal variable, receive ring buffer size in C mode */
|
442 | a41b2ff2 | pbrook | uint32_t RxBufPtr; |
443 | a41b2ff2 | pbrook | uint32_t RxBufAddr; |
444 | a41b2ff2 | pbrook | |
445 | a41b2ff2 | pbrook | uint16_t IntrStatus; |
446 | a41b2ff2 | pbrook | uint16_t IntrMask; |
447 | a41b2ff2 | pbrook | |
448 | a41b2ff2 | pbrook | uint32_t TxConfig; |
449 | a41b2ff2 | pbrook | uint32_t RxConfig; |
450 | a41b2ff2 | pbrook | uint32_t RxMissed; |
451 | a41b2ff2 | pbrook | |
452 | a41b2ff2 | pbrook | uint16_t CSCR; |
453 | a41b2ff2 | pbrook | |
454 | a41b2ff2 | pbrook | uint8_t Cfg9346; |
455 | a41b2ff2 | pbrook | uint8_t Config0; |
456 | a41b2ff2 | pbrook | uint8_t Config1; |
457 | a41b2ff2 | pbrook | uint8_t Config3; |
458 | a41b2ff2 | pbrook | uint8_t Config4; |
459 | a41b2ff2 | pbrook | uint8_t Config5; |
460 | a41b2ff2 | pbrook | |
461 | a41b2ff2 | pbrook | uint8_t clock_enabled; |
462 | a41b2ff2 | pbrook | uint8_t bChipCmdState; |
463 | a41b2ff2 | pbrook | |
464 | a41b2ff2 | pbrook | uint16_t MultiIntr; |
465 | a41b2ff2 | pbrook | |
466 | a41b2ff2 | pbrook | uint16_t BasicModeCtrl; |
467 | a41b2ff2 | pbrook | uint16_t BasicModeStatus; |
468 | a41b2ff2 | pbrook | uint16_t NWayAdvert; |
469 | a41b2ff2 | pbrook | uint16_t NWayLPAR; |
470 | a41b2ff2 | pbrook | uint16_t NWayExpansion; |
471 | a41b2ff2 | pbrook | |
472 | a41b2ff2 | pbrook | uint16_t CpCmd; |
473 | a41b2ff2 | pbrook | uint8_t TxThresh; |
474 | a41b2ff2 | pbrook | |
475 | 1673ad51 | Mark McLoughlin | NICState *nic; |
476 | 254111ec | Gerd Hoffmann | NICConf conf; |
477 | a41b2ff2 | pbrook | int rtl8139_mmio_io_addr;
|
478 | a41b2ff2 | pbrook | |
479 | a41b2ff2 | pbrook | /* C ring mode */
|
480 | a41b2ff2 | pbrook | uint32_t currTxDesc; |
481 | a41b2ff2 | pbrook | |
482 | a41b2ff2 | pbrook | /* C+ mode */
|
483 | 2c3891ab | aliguori | uint32_t cplus_enabled; |
484 | 2c3891ab | aliguori | |
485 | a41b2ff2 | pbrook | uint32_t currCPlusRxDesc; |
486 | a41b2ff2 | pbrook | uint32_t currCPlusTxDesc; |
487 | a41b2ff2 | pbrook | |
488 | a41b2ff2 | pbrook | uint32_t RxRingAddrLO; |
489 | a41b2ff2 | pbrook | uint32_t RxRingAddrHI; |
490 | a41b2ff2 | pbrook | |
491 | a41b2ff2 | pbrook | EEprom9346 eeprom; |
492 | 6cadb320 | bellard | |
493 | 6cadb320 | bellard | uint32_t TCTR; |
494 | 6cadb320 | bellard | uint32_t TimerInt; |
495 | 6cadb320 | bellard | int64_t TCTR_base; |
496 | 6cadb320 | bellard | |
497 | 6cadb320 | bellard | /* Tally counters */
|
498 | 6cadb320 | bellard | RTL8139TallyCounters tally_counters; |
499 | 6cadb320 | bellard | |
500 | 6cadb320 | bellard | /* Non-persistent data */
|
501 | 6cadb320 | bellard | uint8_t *cplus_txbuffer; |
502 | 6cadb320 | bellard | int cplus_txbuffer_len;
|
503 | 6cadb320 | bellard | int cplus_txbuffer_offset;
|
504 | 6cadb320 | bellard | |
505 | 6cadb320 | bellard | /* PCI interrupt timer */
|
506 | 6cadb320 | bellard | QEMUTimer *timer; |
507 | 05447803 | Frediano Ziglio | int64_t TimerExpire; |
508 | 6cadb320 | bellard | |
509 | c574ba5a | Alex Williamson | /* Support migration to/from old versions */
|
510 | c574ba5a | Alex Williamson | int rtl8139_mmio_io_addr_dummy;
|
511 | a41b2ff2 | pbrook | } RTL8139State; |
512 | a41b2ff2 | pbrook | |
513 | 05447803 | Frediano Ziglio | static void rtl8139_set_next_tctr_time(RTL8139State *s, int64_t current_time); |
514 | 05447803 | Frediano Ziglio | |
515 | 9596ebb7 | pbrook | static void prom9346_decode_command(EEprom9346 *eeprom, uint8_t command) |
516 | a41b2ff2 | pbrook | { |
517 | 7cdeb319 | Benjamin Poirier | DPRINTF("eeprom command 0x%02x\n", command);
|
518 | a41b2ff2 | pbrook | |
519 | a41b2ff2 | pbrook | switch (command & Chip9346_op_mask)
|
520 | a41b2ff2 | pbrook | { |
521 | a41b2ff2 | pbrook | case Chip9346_op_read:
|
522 | a41b2ff2 | pbrook | { |
523 | a41b2ff2 | pbrook | eeprom->address = command & EEPROM_9346_ADDR_MASK; |
524 | a41b2ff2 | pbrook | eeprom->output = eeprom->contents[eeprom->address]; |
525 | a41b2ff2 | pbrook | eeprom->eedo = 0;
|
526 | a41b2ff2 | pbrook | eeprom->tick = 0;
|
527 | a41b2ff2 | pbrook | eeprom->mode = Chip9346_data_read; |
528 | 7cdeb319 | Benjamin Poirier | DPRINTF("eeprom read from address 0x%02x data=0x%04x\n",
|
529 | 7cdeb319 | Benjamin Poirier | eeprom->address, eeprom->output); |
530 | a41b2ff2 | pbrook | } |
531 | a41b2ff2 | pbrook | break;
|
532 | a41b2ff2 | pbrook | |
533 | a41b2ff2 | pbrook | case Chip9346_op_write:
|
534 | a41b2ff2 | pbrook | { |
535 | a41b2ff2 | pbrook | eeprom->address = command & EEPROM_9346_ADDR_MASK; |
536 | a41b2ff2 | pbrook | eeprom->input = 0;
|
537 | a41b2ff2 | pbrook | eeprom->tick = 0;
|
538 | a41b2ff2 | pbrook | eeprom->mode = Chip9346_none; /* Chip9346_data_write */
|
539 | 7cdeb319 | Benjamin Poirier | DPRINTF("eeprom begin write to address 0x%02x\n",
|
540 | 7cdeb319 | Benjamin Poirier | eeprom->address); |
541 | a41b2ff2 | pbrook | } |
542 | a41b2ff2 | pbrook | break;
|
543 | a41b2ff2 | pbrook | default:
|
544 | a41b2ff2 | pbrook | eeprom->mode = Chip9346_none; |
545 | a41b2ff2 | pbrook | switch (command & Chip9346_op_ext_mask)
|
546 | a41b2ff2 | pbrook | { |
547 | a41b2ff2 | pbrook | case Chip9346_op_write_enable:
|
548 | 7cdeb319 | Benjamin Poirier | DPRINTF("eeprom write enabled\n");
|
549 | a41b2ff2 | pbrook | break;
|
550 | a41b2ff2 | pbrook | case Chip9346_op_write_all:
|
551 | 7cdeb319 | Benjamin Poirier | DPRINTF("eeprom begin write all\n");
|
552 | a41b2ff2 | pbrook | break;
|
553 | a41b2ff2 | pbrook | case Chip9346_op_write_disable:
|
554 | 7cdeb319 | Benjamin Poirier | DPRINTF("eeprom write disabled\n");
|
555 | a41b2ff2 | pbrook | break;
|
556 | a41b2ff2 | pbrook | } |
557 | a41b2ff2 | pbrook | break;
|
558 | a41b2ff2 | pbrook | } |
559 | a41b2ff2 | pbrook | } |
560 | a41b2ff2 | pbrook | |
561 | 9596ebb7 | pbrook | static void prom9346_shift_clock(EEprom9346 *eeprom) |
562 | a41b2ff2 | pbrook | { |
563 | a41b2ff2 | pbrook | int bit = eeprom->eedi?1:0; |
564 | a41b2ff2 | pbrook | |
565 | a41b2ff2 | pbrook | ++ eeprom->tick; |
566 | a41b2ff2 | pbrook | |
567 | 7cdeb319 | Benjamin Poirier | DPRINTF("eeprom: tick %d eedi=%d eedo=%d\n", eeprom->tick, eeprom->eedi,
|
568 | 7cdeb319 | Benjamin Poirier | eeprom->eedo); |
569 | a41b2ff2 | pbrook | |
570 | a41b2ff2 | pbrook | switch (eeprom->mode)
|
571 | a41b2ff2 | pbrook | { |
572 | a41b2ff2 | pbrook | case Chip9346_enter_command_mode:
|
573 | a41b2ff2 | pbrook | if (bit)
|
574 | a41b2ff2 | pbrook | { |
575 | a41b2ff2 | pbrook | eeprom->mode = Chip9346_read_command; |
576 | a41b2ff2 | pbrook | eeprom->tick = 0;
|
577 | a41b2ff2 | pbrook | eeprom->input = 0;
|
578 | 7cdeb319 | Benjamin Poirier | DPRINTF("eeprom: +++ synchronized, begin command read\n");
|
579 | a41b2ff2 | pbrook | } |
580 | a41b2ff2 | pbrook | break;
|
581 | a41b2ff2 | pbrook | |
582 | a41b2ff2 | pbrook | case Chip9346_read_command:
|
583 | a41b2ff2 | pbrook | eeprom->input = (eeprom->input << 1) | (bit & 1); |
584 | a41b2ff2 | pbrook | if (eeprom->tick == 8) |
585 | a41b2ff2 | pbrook | { |
586 | a41b2ff2 | pbrook | prom9346_decode_command(eeprom, eeprom->input & 0xff);
|
587 | a41b2ff2 | pbrook | } |
588 | a41b2ff2 | pbrook | break;
|
589 | a41b2ff2 | pbrook | |
590 | a41b2ff2 | pbrook | case Chip9346_data_read:
|
591 | a41b2ff2 | pbrook | eeprom->eedo = (eeprom->output & 0x8000)?1:0; |
592 | a41b2ff2 | pbrook | eeprom->output <<= 1;
|
593 | a41b2ff2 | pbrook | if (eeprom->tick == 16) |
594 | a41b2ff2 | pbrook | { |
595 | 6cadb320 | bellard | #if 1 |
596 | 6cadb320 | bellard | // the FreeBSD drivers (rl and re) don't explicitly toggle
|
597 | 6cadb320 | bellard | // CS between reads (or does setting Cfg9346 to 0 count too?),
|
598 | 6cadb320 | bellard | // so we need to enter wait-for-command state here
|
599 | 6cadb320 | bellard | eeprom->mode = Chip9346_enter_command_mode; |
600 | 6cadb320 | bellard | eeprom->input = 0;
|
601 | 6cadb320 | bellard | eeprom->tick = 0;
|
602 | 6cadb320 | bellard | |
603 | 7cdeb319 | Benjamin Poirier | DPRINTF("eeprom: +++ end of read, awaiting next command\n");
|
604 | 6cadb320 | bellard | #else
|
605 | 6cadb320 | bellard | // original behaviour
|
606 | a41b2ff2 | pbrook | ++eeprom->address; |
607 | a41b2ff2 | pbrook | eeprom->address &= EEPROM_9346_ADDR_MASK; |
608 | a41b2ff2 | pbrook | eeprom->output = eeprom->contents[eeprom->address]; |
609 | a41b2ff2 | pbrook | eeprom->tick = 0;
|
610 | a41b2ff2 | pbrook | |
611 | 7cdeb319 | Benjamin Poirier | DPRINTF("eeprom: +++ read next address 0x%02x data=0x%04x\n",
|
612 | 7cdeb319 | Benjamin Poirier | eeprom->address, eeprom->output); |
613 | a41b2ff2 | pbrook | #endif
|
614 | a41b2ff2 | pbrook | } |
615 | a41b2ff2 | pbrook | break;
|
616 | a41b2ff2 | pbrook | |
617 | a41b2ff2 | pbrook | case Chip9346_data_write:
|
618 | a41b2ff2 | pbrook | eeprom->input = (eeprom->input << 1) | (bit & 1); |
619 | a41b2ff2 | pbrook | if (eeprom->tick == 16) |
620 | a41b2ff2 | pbrook | { |
621 | 7cdeb319 | Benjamin Poirier | DPRINTF("eeprom write to address 0x%02x data=0x%04x\n",
|
622 | 7cdeb319 | Benjamin Poirier | eeprom->address, eeprom->input); |
623 | 6cadb320 | bellard | |
624 | a41b2ff2 | pbrook | eeprom->contents[eeprom->address] = eeprom->input; |
625 | a41b2ff2 | pbrook | eeprom->mode = Chip9346_none; /* waiting for next command after CS cycle */
|
626 | a41b2ff2 | pbrook | eeprom->tick = 0;
|
627 | a41b2ff2 | pbrook | eeprom->input = 0;
|
628 | a41b2ff2 | pbrook | } |
629 | a41b2ff2 | pbrook | break;
|
630 | a41b2ff2 | pbrook | |
631 | a41b2ff2 | pbrook | case Chip9346_data_write_all:
|
632 | a41b2ff2 | pbrook | eeprom->input = (eeprom->input << 1) | (bit & 1); |
633 | a41b2ff2 | pbrook | if (eeprom->tick == 16) |
634 | a41b2ff2 | pbrook | { |
635 | a41b2ff2 | pbrook | int i;
|
636 | a41b2ff2 | pbrook | for (i = 0; i < EEPROM_9346_SIZE; i++) |
637 | a41b2ff2 | pbrook | { |
638 | a41b2ff2 | pbrook | eeprom->contents[i] = eeprom->input; |
639 | a41b2ff2 | pbrook | } |
640 | 7cdeb319 | Benjamin Poirier | DPRINTF("eeprom filled with data=0x%04x\n", eeprom->input);
|
641 | 6cadb320 | bellard | |
642 | a41b2ff2 | pbrook | eeprom->mode = Chip9346_enter_command_mode; |
643 | a41b2ff2 | pbrook | eeprom->tick = 0;
|
644 | a41b2ff2 | pbrook | eeprom->input = 0;
|
645 | a41b2ff2 | pbrook | } |
646 | a41b2ff2 | pbrook | break;
|
647 | a41b2ff2 | pbrook | |
648 | a41b2ff2 | pbrook | default:
|
649 | a41b2ff2 | pbrook | break;
|
650 | a41b2ff2 | pbrook | } |
651 | a41b2ff2 | pbrook | } |
652 | a41b2ff2 | pbrook | |
653 | 9596ebb7 | pbrook | static int prom9346_get_wire(RTL8139State *s) |
654 | a41b2ff2 | pbrook | { |
655 | a41b2ff2 | pbrook | EEprom9346 *eeprom = &s->eeprom; |
656 | a41b2ff2 | pbrook | if (!eeprom->eecs)
|
657 | a41b2ff2 | pbrook | return 0; |
658 | a41b2ff2 | pbrook | |
659 | a41b2ff2 | pbrook | return eeprom->eedo;
|
660 | a41b2ff2 | pbrook | } |
661 | a41b2ff2 | pbrook | |
662 | 9596ebb7 | pbrook | /* FIXME: This should be merged into/replaced by eeprom93xx.c. */
|
663 | 9596ebb7 | pbrook | static void prom9346_set_wire(RTL8139State *s, int eecs, int eesk, int eedi) |
664 | a41b2ff2 | pbrook | { |
665 | a41b2ff2 | pbrook | EEprom9346 *eeprom = &s->eeprom; |
666 | a41b2ff2 | pbrook | uint8_t old_eecs = eeprom->eecs; |
667 | a41b2ff2 | pbrook | uint8_t old_eesk = eeprom->eesk; |
668 | a41b2ff2 | pbrook | |
669 | a41b2ff2 | pbrook | eeprom->eecs = eecs; |
670 | a41b2ff2 | pbrook | eeprom->eesk = eesk; |
671 | a41b2ff2 | pbrook | eeprom->eedi = eedi; |
672 | a41b2ff2 | pbrook | |
673 | 7cdeb319 | Benjamin Poirier | DPRINTF("eeprom: +++ wires CS=%d SK=%d DI=%d DO=%d\n", eeprom->eecs,
|
674 | 7cdeb319 | Benjamin Poirier | eeprom->eesk, eeprom->eedi, eeprom->eedo); |
675 | a41b2ff2 | pbrook | |
676 | a41b2ff2 | pbrook | if (!old_eecs && eecs)
|
677 | a41b2ff2 | pbrook | { |
678 | a41b2ff2 | pbrook | /* Synchronize start */
|
679 | a41b2ff2 | pbrook | eeprom->tick = 0;
|
680 | a41b2ff2 | pbrook | eeprom->input = 0;
|
681 | a41b2ff2 | pbrook | eeprom->output = 0;
|
682 | a41b2ff2 | pbrook | eeprom->mode = Chip9346_enter_command_mode; |
683 | a41b2ff2 | pbrook | |
684 | 7cdeb319 | Benjamin Poirier | DPRINTF("=== eeprom: begin access, enter command mode\n");
|
685 | a41b2ff2 | pbrook | } |
686 | a41b2ff2 | pbrook | |
687 | a41b2ff2 | pbrook | if (!eecs)
|
688 | a41b2ff2 | pbrook | { |
689 | 7cdeb319 | Benjamin Poirier | DPRINTF("=== eeprom: end access\n");
|
690 | a41b2ff2 | pbrook | return;
|
691 | a41b2ff2 | pbrook | } |
692 | a41b2ff2 | pbrook | |
693 | a41b2ff2 | pbrook | if (!old_eesk && eesk)
|
694 | a41b2ff2 | pbrook | { |
695 | a41b2ff2 | pbrook | /* SK front rules */
|
696 | a41b2ff2 | pbrook | prom9346_shift_clock(eeprom); |
697 | a41b2ff2 | pbrook | } |
698 | a41b2ff2 | pbrook | } |
699 | a41b2ff2 | pbrook | |
700 | a41b2ff2 | pbrook | static void rtl8139_update_irq(RTL8139State *s) |
701 | a41b2ff2 | pbrook | { |
702 | a41b2ff2 | pbrook | int isr;
|
703 | a41b2ff2 | pbrook | isr = (s->IntrStatus & s->IntrMask) & 0xffff;
|
704 | 6cadb320 | bellard | |
705 | 7cdeb319 | Benjamin Poirier | DPRINTF("Set IRQ to %d (%04x %04x)\n", isr ? 1 : 0, s->IntrStatus, |
706 | 7cdeb319 | Benjamin Poirier | s->IntrMask); |
707 | 6cadb320 | bellard | |
708 | efd6dd45 | Juan Quintela | qemu_set_irq(s->dev.irq[0], (isr != 0)); |
709 | a41b2ff2 | pbrook | } |
710 | a41b2ff2 | pbrook | |
711 | a41b2ff2 | pbrook | #define POLYNOMIAL 0x04c11db6 |
712 | a41b2ff2 | pbrook | |
713 | a41b2ff2 | pbrook | /* From FreeBSD */
|
714 | a41b2ff2 | pbrook | /* XXX: optimize */
|
715 | a41b2ff2 | pbrook | static int compute_mcast_idx(const uint8_t *ep) |
716 | a41b2ff2 | pbrook | { |
717 | a41b2ff2 | pbrook | uint32_t crc; |
718 | a41b2ff2 | pbrook | int carry, i, j;
|
719 | a41b2ff2 | pbrook | uint8_t b; |
720 | a41b2ff2 | pbrook | |
721 | a41b2ff2 | pbrook | crc = 0xffffffff;
|
722 | a41b2ff2 | pbrook | for (i = 0; i < 6; i++) { |
723 | a41b2ff2 | pbrook | b = *ep++; |
724 | a41b2ff2 | pbrook | for (j = 0; j < 8; j++) { |
725 | a41b2ff2 | pbrook | carry = ((crc & 0x80000000L) ? 1 : 0) ^ (b & 0x01); |
726 | a41b2ff2 | pbrook | crc <<= 1;
|
727 | a41b2ff2 | pbrook | b >>= 1;
|
728 | a41b2ff2 | pbrook | if (carry)
|
729 | a41b2ff2 | pbrook | crc = ((crc ^ POLYNOMIAL) | carry); |
730 | a41b2ff2 | pbrook | } |
731 | a41b2ff2 | pbrook | } |
732 | a41b2ff2 | pbrook | return (crc >> 26); |
733 | a41b2ff2 | pbrook | } |
734 | a41b2ff2 | pbrook | |
735 | a41b2ff2 | pbrook | static int rtl8139_RxWrap(RTL8139State *s) |
736 | a41b2ff2 | pbrook | { |
737 | a41b2ff2 | pbrook | /* wrapping enabled; assume 1.5k more buffer space if size < 65536 */
|
738 | a41b2ff2 | pbrook | return (s->RxConfig & (1 << 7)); |
739 | a41b2ff2 | pbrook | } |
740 | a41b2ff2 | pbrook | |
741 | a41b2ff2 | pbrook | static int rtl8139_receiver_enabled(RTL8139State *s) |
742 | a41b2ff2 | pbrook | { |
743 | a41b2ff2 | pbrook | return s->bChipCmdState & CmdRxEnb;
|
744 | a41b2ff2 | pbrook | } |
745 | a41b2ff2 | pbrook | |
746 | a41b2ff2 | pbrook | static int rtl8139_transmitter_enabled(RTL8139State *s) |
747 | a41b2ff2 | pbrook | { |
748 | a41b2ff2 | pbrook | return s->bChipCmdState & CmdTxEnb;
|
749 | a41b2ff2 | pbrook | } |
750 | a41b2ff2 | pbrook | |
751 | a41b2ff2 | pbrook | static int rtl8139_cp_receiver_enabled(RTL8139State *s) |
752 | a41b2ff2 | pbrook | { |
753 | a41b2ff2 | pbrook | return s->CpCmd & CPlusRxEnb;
|
754 | a41b2ff2 | pbrook | } |
755 | a41b2ff2 | pbrook | |
756 | a41b2ff2 | pbrook | static int rtl8139_cp_transmitter_enabled(RTL8139State *s) |
757 | a41b2ff2 | pbrook | { |
758 | a41b2ff2 | pbrook | return s->CpCmd & CPlusTxEnb;
|
759 | a41b2ff2 | pbrook | } |
760 | a41b2ff2 | pbrook | |
761 | a41b2ff2 | pbrook | static void rtl8139_write_buffer(RTL8139State *s, const void *buf, int size) |
762 | a41b2ff2 | pbrook | { |
763 | a41b2ff2 | pbrook | if (s->RxBufAddr + size > s->RxBufferSize)
|
764 | a41b2ff2 | pbrook | { |
765 | a41b2ff2 | pbrook | int wrapped = MOD2(s->RxBufAddr + size, s->RxBufferSize);
|
766 | a41b2ff2 | pbrook | |
767 | a41b2ff2 | pbrook | /* write packet data */
|
768 | ccf1d14a | ths | if (wrapped && !(s->RxBufferSize < 65536 && rtl8139_RxWrap(s))) |
769 | a41b2ff2 | pbrook | { |
770 | 7cdeb319 | Benjamin Poirier | DPRINTF(">>> rx packet wrapped in buffer at %d\n", size - wrapped);
|
771 | a41b2ff2 | pbrook | |
772 | a41b2ff2 | pbrook | if (size > wrapped)
|
773 | a41b2ff2 | pbrook | { |
774 | a41b2ff2 | pbrook | cpu_physical_memory_write( s->RxBuf + s->RxBufAddr, |
775 | a41b2ff2 | pbrook | buf, size-wrapped ); |
776 | a41b2ff2 | pbrook | } |
777 | a41b2ff2 | pbrook | |
778 | a41b2ff2 | pbrook | /* reset buffer pointer */
|
779 | a41b2ff2 | pbrook | s->RxBufAddr = 0;
|
780 | a41b2ff2 | pbrook | |
781 | a41b2ff2 | pbrook | cpu_physical_memory_write( s->RxBuf + s->RxBufAddr, |
782 | a41b2ff2 | pbrook | buf + (size-wrapped), wrapped ); |
783 | a41b2ff2 | pbrook | |
784 | a41b2ff2 | pbrook | s->RxBufAddr = wrapped; |
785 | a41b2ff2 | pbrook | |
786 | a41b2ff2 | pbrook | return;
|
787 | a41b2ff2 | pbrook | } |
788 | a41b2ff2 | pbrook | } |
789 | a41b2ff2 | pbrook | |
790 | a41b2ff2 | pbrook | /* non-wrapping path or overwrapping enabled */
|
791 | a41b2ff2 | pbrook | cpu_physical_memory_write( s->RxBuf + s->RxBufAddr, buf, size ); |
792 | a41b2ff2 | pbrook | |
793 | a41b2ff2 | pbrook | s->RxBufAddr += size; |
794 | a41b2ff2 | pbrook | } |
795 | a41b2ff2 | pbrook | |
796 | a41b2ff2 | pbrook | #define MIN_BUF_SIZE 60 |
797 | c227f099 | Anthony Liguori | static inline target_phys_addr_t rtl8139_addr64(uint32_t low, uint32_t high) |
798 | a41b2ff2 | pbrook | { |
799 | a41b2ff2 | pbrook | #if TARGET_PHYS_ADDR_BITS > 32 |
800 | c227f099 | Anthony Liguori | return low | ((target_phys_addr_t)high << 32); |
801 | a41b2ff2 | pbrook | #else
|
802 | a41b2ff2 | pbrook | return low;
|
803 | a41b2ff2 | pbrook | #endif
|
804 | a41b2ff2 | pbrook | } |
805 | a41b2ff2 | pbrook | |
806 | 1673ad51 | Mark McLoughlin | static int rtl8139_can_receive(VLANClientState *nc) |
807 | a41b2ff2 | pbrook | { |
808 | 1673ad51 | Mark McLoughlin | RTL8139State *s = DO_UPCAST(NICState, nc, nc)->opaque; |
809 | a41b2ff2 | pbrook | int avail;
|
810 | a41b2ff2 | pbrook | |
811 | aa1f17c1 | ths | /* Receive (drop) packets if card is disabled. */
|
812 | a41b2ff2 | pbrook | if (!s->clock_enabled)
|
813 | a41b2ff2 | pbrook | return 1; |
814 | a41b2ff2 | pbrook | if (!rtl8139_receiver_enabled(s))
|
815 | a41b2ff2 | pbrook | return 1; |
816 | a41b2ff2 | pbrook | |
817 | a41b2ff2 | pbrook | if (rtl8139_cp_receiver_enabled(s)) {
|
818 | a41b2ff2 | pbrook | /* ??? Flow control not implemented in c+ mode.
|
819 | a41b2ff2 | pbrook | This is a hack to work around slirp deficiencies anyway. */
|
820 | a41b2ff2 | pbrook | return 1; |
821 | a41b2ff2 | pbrook | } else {
|
822 | a41b2ff2 | pbrook | avail = MOD2(s->RxBufferSize + s->RxBufPtr - s->RxBufAddr, |
823 | a41b2ff2 | pbrook | s->RxBufferSize); |
824 | a41b2ff2 | pbrook | return (avail == 0 || avail >= 1514); |
825 | a41b2ff2 | pbrook | } |
826 | a41b2ff2 | pbrook | } |
827 | a41b2ff2 | pbrook | |
828 | 1673ad51 | Mark McLoughlin | static ssize_t rtl8139_do_receive(VLANClientState *nc, const uint8_t *buf, size_t size_, int do_interrupt) |
829 | a41b2ff2 | pbrook | { |
830 | 1673ad51 | Mark McLoughlin | RTL8139State *s = DO_UPCAST(NICState, nc, nc)->opaque; |
831 | 18dabfd1 | Benjamin Poirier | /* size is the length of the buffer passed to the driver */
|
832 | 4f1c942b | Mark McLoughlin | int size = size_;
|
833 | 18dabfd1 | Benjamin Poirier | const uint8_t *dot1q_buf = NULL; |
834 | a41b2ff2 | pbrook | |
835 | a41b2ff2 | pbrook | uint32_t packet_header = 0;
|
836 | a41b2ff2 | pbrook | |
837 | 18dabfd1 | Benjamin Poirier | uint8_t buf1[MIN_BUF_SIZE + VLAN_HLEN]; |
838 | 5fafdf24 | ths | static const uint8_t broadcast_macaddr[6] = |
839 | a41b2ff2 | pbrook | { 0xff, 0xff, 0xff, 0xff, 0xff, 0xff }; |
840 | a41b2ff2 | pbrook | |
841 | 7cdeb319 | Benjamin Poirier | DPRINTF(">>> received len=%d\n", size);
|
842 | a41b2ff2 | pbrook | |
843 | a41b2ff2 | pbrook | /* test if board clock is stopped */
|
844 | a41b2ff2 | pbrook | if (!s->clock_enabled)
|
845 | a41b2ff2 | pbrook | { |
846 | 7cdeb319 | Benjamin Poirier | DPRINTF("stopped ==========================\n");
|
847 | 4f1c942b | Mark McLoughlin | return -1; |
848 | a41b2ff2 | pbrook | } |
849 | a41b2ff2 | pbrook | |
850 | a41b2ff2 | pbrook | /* first check if receiver is enabled */
|
851 | a41b2ff2 | pbrook | |
852 | a41b2ff2 | pbrook | if (!rtl8139_receiver_enabled(s))
|
853 | a41b2ff2 | pbrook | { |
854 | 7cdeb319 | Benjamin Poirier | DPRINTF("receiver disabled ================\n");
|
855 | 4f1c942b | Mark McLoughlin | return -1; |
856 | a41b2ff2 | pbrook | } |
857 | a41b2ff2 | pbrook | |
858 | a41b2ff2 | pbrook | /* XXX: check this */
|
859 | a41b2ff2 | pbrook | if (s->RxConfig & AcceptAllPhys) {
|
860 | a41b2ff2 | pbrook | /* promiscuous: receive all */
|
861 | 7cdeb319 | Benjamin Poirier | DPRINTF(">>> packet received in promiscuous mode\n");
|
862 | a41b2ff2 | pbrook | |
863 | a41b2ff2 | pbrook | } else {
|
864 | a41b2ff2 | pbrook | if (!memcmp(buf, broadcast_macaddr, 6)) { |
865 | a41b2ff2 | pbrook | /* broadcast address */
|
866 | a41b2ff2 | pbrook | if (!(s->RxConfig & AcceptBroadcast))
|
867 | a41b2ff2 | pbrook | { |
868 | 7cdeb319 | Benjamin Poirier | DPRINTF(">>> broadcast packet rejected\n");
|
869 | 6cadb320 | bellard | |
870 | 6cadb320 | bellard | /* update tally counter */
|
871 | 6cadb320 | bellard | ++s->tally_counters.RxERR; |
872 | 6cadb320 | bellard | |
873 | 4f1c942b | Mark McLoughlin | return size;
|
874 | a41b2ff2 | pbrook | } |
875 | a41b2ff2 | pbrook | |
876 | a41b2ff2 | pbrook | packet_header |= RxBroadcast; |
877 | a41b2ff2 | pbrook | |
878 | 7cdeb319 | Benjamin Poirier | DPRINTF(">>> broadcast packet received\n");
|
879 | 6cadb320 | bellard | |
880 | 6cadb320 | bellard | /* update tally counter */
|
881 | 6cadb320 | bellard | ++s->tally_counters.RxOkBrd; |
882 | 6cadb320 | bellard | |
883 | a41b2ff2 | pbrook | } else if (buf[0] & 0x01) { |
884 | a41b2ff2 | pbrook | /* multicast */
|
885 | a41b2ff2 | pbrook | if (!(s->RxConfig & AcceptMulticast))
|
886 | a41b2ff2 | pbrook | { |
887 | 7cdeb319 | Benjamin Poirier | DPRINTF(">>> multicast packet rejected\n");
|
888 | 6cadb320 | bellard | |
889 | 6cadb320 | bellard | /* update tally counter */
|
890 | 6cadb320 | bellard | ++s->tally_counters.RxERR; |
891 | 6cadb320 | bellard | |
892 | 4f1c942b | Mark McLoughlin | return size;
|
893 | a41b2ff2 | pbrook | } |
894 | a41b2ff2 | pbrook | |
895 | a41b2ff2 | pbrook | int mcast_idx = compute_mcast_idx(buf);
|
896 | a41b2ff2 | pbrook | |
897 | a41b2ff2 | pbrook | if (!(s->mult[mcast_idx >> 3] & (1 << (mcast_idx & 7)))) |
898 | a41b2ff2 | pbrook | { |
899 | 7cdeb319 | Benjamin Poirier | DPRINTF(">>> multicast address mismatch\n");
|
900 | 6cadb320 | bellard | |
901 | 6cadb320 | bellard | /* update tally counter */
|
902 | 6cadb320 | bellard | ++s->tally_counters.RxERR; |
903 | 6cadb320 | bellard | |
904 | 4f1c942b | Mark McLoughlin | return size;
|
905 | a41b2ff2 | pbrook | } |
906 | a41b2ff2 | pbrook | |
907 | a41b2ff2 | pbrook | packet_header |= RxMulticast; |
908 | a41b2ff2 | pbrook | |
909 | 7cdeb319 | Benjamin Poirier | DPRINTF(">>> multicast packet received\n");
|
910 | 6cadb320 | bellard | |
911 | 6cadb320 | bellard | /* update tally counter */
|
912 | 6cadb320 | bellard | ++s->tally_counters.RxOkMul; |
913 | 6cadb320 | bellard | |
914 | a41b2ff2 | pbrook | } else if (s->phys[0] == buf[0] && |
915 | 3b46e624 | ths | s->phys[1] == buf[1] && |
916 | 3b46e624 | ths | s->phys[2] == buf[2] && |
917 | 3b46e624 | ths | s->phys[3] == buf[3] && |
918 | 3b46e624 | ths | s->phys[4] == buf[4] && |
919 | a41b2ff2 | pbrook | s->phys[5] == buf[5]) { |
920 | a41b2ff2 | pbrook | /* match */
|
921 | a41b2ff2 | pbrook | if (!(s->RxConfig & AcceptMyPhys))
|
922 | a41b2ff2 | pbrook | { |
923 | 7cdeb319 | Benjamin Poirier | DPRINTF(">>> rejecting physical address matching packet\n");
|
924 | 6cadb320 | bellard | |
925 | 6cadb320 | bellard | /* update tally counter */
|
926 | 6cadb320 | bellard | ++s->tally_counters.RxERR; |
927 | 6cadb320 | bellard | |
928 | 4f1c942b | Mark McLoughlin | return size;
|
929 | a41b2ff2 | pbrook | } |
930 | a41b2ff2 | pbrook | |
931 | a41b2ff2 | pbrook | packet_header |= RxPhysical; |
932 | a41b2ff2 | pbrook | |
933 | 7cdeb319 | Benjamin Poirier | DPRINTF(">>> physical address matching packet received\n");
|
934 | 6cadb320 | bellard | |
935 | 6cadb320 | bellard | /* update tally counter */
|
936 | 6cadb320 | bellard | ++s->tally_counters.RxOkPhy; |
937 | a41b2ff2 | pbrook | |
938 | a41b2ff2 | pbrook | } else {
|
939 | a41b2ff2 | pbrook | |
940 | 7cdeb319 | Benjamin Poirier | DPRINTF(">>> unknown packet\n");
|
941 | 6cadb320 | bellard | |
942 | 6cadb320 | bellard | /* update tally counter */
|
943 | 6cadb320 | bellard | ++s->tally_counters.RxERR; |
944 | 6cadb320 | bellard | |
945 | 4f1c942b | Mark McLoughlin | return size;
|
946 | a41b2ff2 | pbrook | } |
947 | a41b2ff2 | pbrook | } |
948 | a41b2ff2 | pbrook | |
949 | 18dabfd1 | Benjamin Poirier | /* if too small buffer, then expand it
|
950 | 18dabfd1 | Benjamin Poirier | * Include some tailroom in case a vlan tag is later removed. */
|
951 | 18dabfd1 | Benjamin Poirier | if (size < MIN_BUF_SIZE + VLAN_HLEN) {
|
952 | a41b2ff2 | pbrook | memcpy(buf1, buf, size); |
953 | 18dabfd1 | Benjamin Poirier | memset(buf1 + size, 0, MIN_BUF_SIZE + VLAN_HLEN - size);
|
954 | a41b2ff2 | pbrook | buf = buf1; |
955 | 18dabfd1 | Benjamin Poirier | if (size < MIN_BUF_SIZE) {
|
956 | 18dabfd1 | Benjamin Poirier | size = MIN_BUF_SIZE; |
957 | 18dabfd1 | Benjamin Poirier | } |
958 | a41b2ff2 | pbrook | } |
959 | a41b2ff2 | pbrook | |
960 | a41b2ff2 | pbrook | if (rtl8139_cp_receiver_enabled(s))
|
961 | a41b2ff2 | pbrook | { |
962 | 7cdeb319 | Benjamin Poirier | DPRINTF("in C+ Rx mode ================\n");
|
963 | a41b2ff2 | pbrook | |
964 | a41b2ff2 | pbrook | /* begin C+ receiver mode */
|
965 | a41b2ff2 | pbrook | |
966 | a41b2ff2 | pbrook | /* w0 ownership flag */
|
967 | a41b2ff2 | pbrook | #define CP_RX_OWN (1<<31) |
968 | a41b2ff2 | pbrook | /* w0 end of ring flag */
|
969 | a41b2ff2 | pbrook | #define CP_RX_EOR (1<<30) |
970 | a41b2ff2 | pbrook | /* w0 bits 0...12 : buffer size */
|
971 | a41b2ff2 | pbrook | #define CP_RX_BUFFER_SIZE_MASK ((1<<13) - 1) |
972 | a41b2ff2 | pbrook | /* w1 tag available flag */
|
973 | a41b2ff2 | pbrook | #define CP_RX_TAVA (1<<16) |
974 | a41b2ff2 | pbrook | /* w1 bits 0...15 : VLAN tag */
|
975 | a41b2ff2 | pbrook | #define CP_RX_VLAN_TAG_MASK ((1<<16) - 1) |
976 | a41b2ff2 | pbrook | /* w2 low 32bit of Rx buffer ptr */
|
977 | a41b2ff2 | pbrook | /* w3 high 32bit of Rx buffer ptr */
|
978 | a41b2ff2 | pbrook | |
979 | a41b2ff2 | pbrook | int descriptor = s->currCPlusRxDesc;
|
980 | c227f099 | Anthony Liguori | target_phys_addr_t cplus_rx_ring_desc; |
981 | a41b2ff2 | pbrook | |
982 | a41b2ff2 | pbrook | cplus_rx_ring_desc = rtl8139_addr64(s->RxRingAddrLO, s->RxRingAddrHI); |
983 | a41b2ff2 | pbrook | cplus_rx_ring_desc += 16 * descriptor;
|
984 | a41b2ff2 | pbrook | |
985 | 7cdeb319 | Benjamin Poirier | DPRINTF("+++ C+ mode reading RX descriptor %d from host memory at "
|
986 | 7cdeb319 | Benjamin Poirier | "%08x %08x = "TARGET_FMT_plx"\n", descriptor, s->RxRingAddrHI, |
987 | 7cdeb319 | Benjamin Poirier | s->RxRingAddrLO, cplus_rx_ring_desc); |
988 | a41b2ff2 | pbrook | |
989 | a41b2ff2 | pbrook | uint32_t val, rxdw0,rxdw1,rxbufLO,rxbufHI; |
990 | a41b2ff2 | pbrook | |
991 | a41b2ff2 | pbrook | cpu_physical_memory_read(cplus_rx_ring_desc, (uint8_t *)&val, 4);
|
992 | a41b2ff2 | pbrook | rxdw0 = le32_to_cpu(val); |
993 | a41b2ff2 | pbrook | cpu_physical_memory_read(cplus_rx_ring_desc+4, (uint8_t *)&val, 4); |
994 | a41b2ff2 | pbrook | rxdw1 = le32_to_cpu(val); |
995 | a41b2ff2 | pbrook | cpu_physical_memory_read(cplus_rx_ring_desc+8, (uint8_t *)&val, 4); |
996 | a41b2ff2 | pbrook | rxbufLO = le32_to_cpu(val); |
997 | a41b2ff2 | pbrook | cpu_physical_memory_read(cplus_rx_ring_desc+12, (uint8_t *)&val, 4); |
998 | a41b2ff2 | pbrook | rxbufHI = le32_to_cpu(val); |
999 | a41b2ff2 | pbrook | |
1000 | 7cdeb319 | Benjamin Poirier | DPRINTF("+++ C+ mode RX descriptor %d %08x %08x %08x %08x\n",
|
1001 | 7cdeb319 | Benjamin Poirier | descriptor, rxdw0, rxdw1, rxbufLO, rxbufHI); |
1002 | a41b2ff2 | pbrook | |
1003 | a41b2ff2 | pbrook | if (!(rxdw0 & CP_RX_OWN))
|
1004 | a41b2ff2 | pbrook | { |
1005 | 7cdeb319 | Benjamin Poirier | DPRINTF("C+ Rx mode : descriptor %d is owned by host\n",
|
1006 | 7cdeb319 | Benjamin Poirier | descriptor); |
1007 | 6cadb320 | bellard | |
1008 | a41b2ff2 | pbrook | s->IntrStatus |= RxOverflow; |
1009 | a41b2ff2 | pbrook | ++s->RxMissed; |
1010 | 6cadb320 | bellard | |
1011 | 6cadb320 | bellard | /* update tally counter */
|
1012 | 6cadb320 | bellard | ++s->tally_counters.RxERR; |
1013 | 6cadb320 | bellard | ++s->tally_counters.MissPkt; |
1014 | 6cadb320 | bellard | |
1015 | a41b2ff2 | pbrook | rtl8139_update_irq(s); |
1016 | 4f1c942b | Mark McLoughlin | return size_;
|
1017 | a41b2ff2 | pbrook | } |
1018 | a41b2ff2 | pbrook | |
1019 | a41b2ff2 | pbrook | uint32_t rx_space = rxdw0 & CP_RX_BUFFER_SIZE_MASK; |
1020 | a41b2ff2 | pbrook | |
1021 | 18dabfd1 | Benjamin Poirier | /* write VLAN info to descriptor variables. */
|
1022 | 18dabfd1 | Benjamin Poirier | if (s->CpCmd & CPlusRxVLAN && be16_to_cpup((uint16_t *)
|
1023 | 18dabfd1 | Benjamin Poirier | &buf[ETHER_ADDR_LEN * 2]) == ETH_P_8021Q) {
|
1024 | 18dabfd1 | Benjamin Poirier | dot1q_buf = &buf[ETHER_ADDR_LEN * 2];
|
1025 | 18dabfd1 | Benjamin Poirier | size -= VLAN_HLEN; |
1026 | 18dabfd1 | Benjamin Poirier | /* if too small buffer, use the tailroom added duing expansion */
|
1027 | 18dabfd1 | Benjamin Poirier | if (size < MIN_BUF_SIZE) {
|
1028 | 18dabfd1 | Benjamin Poirier | size = MIN_BUF_SIZE; |
1029 | 18dabfd1 | Benjamin Poirier | } |
1030 | 18dabfd1 | Benjamin Poirier | |
1031 | 18dabfd1 | Benjamin Poirier | rxdw1 &= ~CP_RX_VLAN_TAG_MASK; |
1032 | 18dabfd1 | Benjamin Poirier | /* BE + ~le_to_cpu()~ + cpu_to_le() = BE */
|
1033 | 18dabfd1 | Benjamin Poirier | rxdw1 |= CP_RX_TAVA | le16_to_cpup((uint16_t *) |
1034 | 18dabfd1 | Benjamin Poirier | &dot1q_buf[ETHER_TYPE_LEN]); |
1035 | 18dabfd1 | Benjamin Poirier | |
1036 | 7cdeb319 | Benjamin Poirier | DPRINTF("C+ Rx mode : extracted vlan tag with tci: ""%u\n", |
1037 | 7cdeb319 | Benjamin Poirier | be16_to_cpup((uint16_t *)&dot1q_buf[ETHER_TYPE_LEN])); |
1038 | 18dabfd1 | Benjamin Poirier | } else {
|
1039 | 18dabfd1 | Benjamin Poirier | /* reset VLAN tag flag */
|
1040 | 18dabfd1 | Benjamin Poirier | rxdw1 &= ~CP_RX_TAVA; |
1041 | 18dabfd1 | Benjamin Poirier | } |
1042 | 18dabfd1 | Benjamin Poirier | |
1043 | 6cadb320 | bellard | /* TODO: scatter the packet over available receive ring descriptors space */
|
1044 | 6cadb320 | bellard | |
1045 | a41b2ff2 | pbrook | if (size+4 > rx_space) |
1046 | a41b2ff2 | pbrook | { |
1047 | 7cdeb319 | Benjamin Poirier | DPRINTF("C+ Rx mode : descriptor %d size %d received %d + 4\n",
|
1048 | 7cdeb319 | Benjamin Poirier | descriptor, rx_space, size); |
1049 | 6cadb320 | bellard | |
1050 | a41b2ff2 | pbrook | s->IntrStatus |= RxOverflow; |
1051 | a41b2ff2 | pbrook | ++s->RxMissed; |
1052 | 6cadb320 | bellard | |
1053 | 6cadb320 | bellard | /* update tally counter */
|
1054 | 6cadb320 | bellard | ++s->tally_counters.RxERR; |
1055 | 6cadb320 | bellard | ++s->tally_counters.MissPkt; |
1056 | 6cadb320 | bellard | |
1057 | a41b2ff2 | pbrook | rtl8139_update_irq(s); |
1058 | 4f1c942b | Mark McLoughlin | return size_;
|
1059 | a41b2ff2 | pbrook | } |
1060 | a41b2ff2 | pbrook | |
1061 | c227f099 | Anthony Liguori | target_phys_addr_t rx_addr = rtl8139_addr64(rxbufLO, rxbufHI); |
1062 | a41b2ff2 | pbrook | |
1063 | a41b2ff2 | pbrook | /* receive/copy to target memory */
|
1064 | 18dabfd1 | Benjamin Poirier | if (dot1q_buf) {
|
1065 | 18dabfd1 | Benjamin Poirier | cpu_physical_memory_write(rx_addr, buf, 2 * ETHER_ADDR_LEN);
|
1066 | 18dabfd1 | Benjamin Poirier | cpu_physical_memory_write(rx_addr + 2 * ETHER_ADDR_LEN,
|
1067 | 18dabfd1 | Benjamin Poirier | buf + 2 * ETHER_ADDR_LEN + VLAN_HLEN,
|
1068 | 18dabfd1 | Benjamin Poirier | size - 2 * ETHER_ADDR_LEN);
|
1069 | 18dabfd1 | Benjamin Poirier | } else {
|
1070 | 18dabfd1 | Benjamin Poirier | cpu_physical_memory_write(rx_addr, buf, size); |
1071 | 18dabfd1 | Benjamin Poirier | } |
1072 | a41b2ff2 | pbrook | |
1073 | 6cadb320 | bellard | if (s->CpCmd & CPlusRxChkSum)
|
1074 | 6cadb320 | bellard | { |
1075 | 6cadb320 | bellard | /* do some packet checksumming */
|
1076 | 6cadb320 | bellard | } |
1077 | 6cadb320 | bellard | |
1078 | a41b2ff2 | pbrook | /* write checksum */
|
1079 | 18dabfd1 | Benjamin Poirier | val = cpu_to_le32(crc32(0, buf, size_));
|
1080 | a41b2ff2 | pbrook | cpu_physical_memory_write( rx_addr+size, (uint8_t *)&val, 4);
|
1081 | a41b2ff2 | pbrook | |
1082 | a41b2ff2 | pbrook | /* first segment of received packet flag */
|
1083 | a41b2ff2 | pbrook | #define CP_RX_STATUS_FS (1<<29) |
1084 | a41b2ff2 | pbrook | /* last segment of received packet flag */
|
1085 | a41b2ff2 | pbrook | #define CP_RX_STATUS_LS (1<<28) |
1086 | a41b2ff2 | pbrook | /* multicast packet flag */
|
1087 | a41b2ff2 | pbrook | #define CP_RX_STATUS_MAR (1<<26) |
1088 | a41b2ff2 | pbrook | /* physical-matching packet flag */
|
1089 | a41b2ff2 | pbrook | #define CP_RX_STATUS_PAM (1<<25) |
1090 | a41b2ff2 | pbrook | /* broadcast packet flag */
|
1091 | a41b2ff2 | pbrook | #define CP_RX_STATUS_BAR (1<<24) |
1092 | a41b2ff2 | pbrook | /* runt packet flag */
|
1093 | a41b2ff2 | pbrook | #define CP_RX_STATUS_RUNT (1<<19) |
1094 | a41b2ff2 | pbrook | /* crc error flag */
|
1095 | a41b2ff2 | pbrook | #define CP_RX_STATUS_CRC (1<<18) |
1096 | a41b2ff2 | pbrook | /* IP checksum error flag */
|
1097 | a41b2ff2 | pbrook | #define CP_RX_STATUS_IPF (1<<15) |
1098 | a41b2ff2 | pbrook | /* UDP checksum error flag */
|
1099 | a41b2ff2 | pbrook | #define CP_RX_STATUS_UDPF (1<<14) |
1100 | a41b2ff2 | pbrook | /* TCP checksum error flag */
|
1101 | a41b2ff2 | pbrook | #define CP_RX_STATUS_TCPF (1<<13) |
1102 | a41b2ff2 | pbrook | |
1103 | a41b2ff2 | pbrook | /* transfer ownership to target */
|
1104 | a41b2ff2 | pbrook | rxdw0 &= ~CP_RX_OWN; |
1105 | a41b2ff2 | pbrook | |
1106 | a41b2ff2 | pbrook | /* set first segment bit */
|
1107 | a41b2ff2 | pbrook | rxdw0 |= CP_RX_STATUS_FS; |
1108 | a41b2ff2 | pbrook | |
1109 | a41b2ff2 | pbrook | /* set last segment bit */
|
1110 | a41b2ff2 | pbrook | rxdw0 |= CP_RX_STATUS_LS; |
1111 | a41b2ff2 | pbrook | |
1112 | a41b2ff2 | pbrook | /* set received packet type flags */
|
1113 | a41b2ff2 | pbrook | if (packet_header & RxBroadcast)
|
1114 | a41b2ff2 | pbrook | rxdw0 |= CP_RX_STATUS_BAR; |
1115 | a41b2ff2 | pbrook | if (packet_header & RxMulticast)
|
1116 | a41b2ff2 | pbrook | rxdw0 |= CP_RX_STATUS_MAR; |
1117 | a41b2ff2 | pbrook | if (packet_header & RxPhysical)
|
1118 | a41b2ff2 | pbrook | rxdw0 |= CP_RX_STATUS_PAM; |
1119 | a41b2ff2 | pbrook | |
1120 | a41b2ff2 | pbrook | /* set received size */
|
1121 | a41b2ff2 | pbrook | rxdw0 &= ~CP_RX_BUFFER_SIZE_MASK; |
1122 | a41b2ff2 | pbrook | rxdw0 |= (size+4);
|
1123 | a41b2ff2 | pbrook | |
1124 | a41b2ff2 | pbrook | /* update ring data */
|
1125 | a41b2ff2 | pbrook | val = cpu_to_le32(rxdw0); |
1126 | a41b2ff2 | pbrook | cpu_physical_memory_write(cplus_rx_ring_desc, (uint8_t *)&val, 4);
|
1127 | a41b2ff2 | pbrook | val = cpu_to_le32(rxdw1); |
1128 | a41b2ff2 | pbrook | cpu_physical_memory_write(cplus_rx_ring_desc+4, (uint8_t *)&val, 4); |
1129 | a41b2ff2 | pbrook | |
1130 | 6cadb320 | bellard | /* update tally counter */
|
1131 | 6cadb320 | bellard | ++s->tally_counters.RxOk; |
1132 | 6cadb320 | bellard | |
1133 | a41b2ff2 | pbrook | /* seek to next Rx descriptor */
|
1134 | a41b2ff2 | pbrook | if (rxdw0 & CP_RX_EOR)
|
1135 | a41b2ff2 | pbrook | { |
1136 | a41b2ff2 | pbrook | s->currCPlusRxDesc = 0;
|
1137 | a41b2ff2 | pbrook | } |
1138 | a41b2ff2 | pbrook | else
|
1139 | a41b2ff2 | pbrook | { |
1140 | a41b2ff2 | pbrook | ++s->currCPlusRxDesc; |
1141 | a41b2ff2 | pbrook | } |
1142 | a41b2ff2 | pbrook | |
1143 | 7cdeb319 | Benjamin Poirier | DPRINTF("done C+ Rx mode ----------------\n");
|
1144 | a41b2ff2 | pbrook | |
1145 | a41b2ff2 | pbrook | } |
1146 | a41b2ff2 | pbrook | else
|
1147 | a41b2ff2 | pbrook | { |
1148 | 7cdeb319 | Benjamin Poirier | DPRINTF("in ring Rx mode ================\n");
|
1149 | 6cadb320 | bellard | |
1150 | a41b2ff2 | pbrook | /* begin ring receiver mode */
|
1151 | a41b2ff2 | pbrook | int avail = MOD2(s->RxBufferSize + s->RxBufPtr - s->RxBufAddr, s->RxBufferSize);
|
1152 | a41b2ff2 | pbrook | |
1153 | a41b2ff2 | pbrook | /* if receiver buffer is empty then avail == 0 */
|
1154 | a41b2ff2 | pbrook | |
1155 | a41b2ff2 | pbrook | if (avail != 0 && size + 8 >= avail) |
1156 | a41b2ff2 | pbrook | { |
1157 | 7cdeb319 | Benjamin Poirier | DPRINTF("rx overflow: rx buffer length %d head 0x%04x "
|
1158 | 7cdeb319 | Benjamin Poirier | "read 0x%04x === available 0x%04x need 0x%04x\n",
|
1159 | 7cdeb319 | Benjamin Poirier | s->RxBufferSize, s->RxBufAddr, s->RxBufPtr, avail, size + 8);
|
1160 | 6cadb320 | bellard | |
1161 | a41b2ff2 | pbrook | s->IntrStatus |= RxOverflow; |
1162 | a41b2ff2 | pbrook | ++s->RxMissed; |
1163 | a41b2ff2 | pbrook | rtl8139_update_irq(s); |
1164 | 4f1c942b | Mark McLoughlin | return size_;
|
1165 | a41b2ff2 | pbrook | } |
1166 | a41b2ff2 | pbrook | |
1167 | a41b2ff2 | pbrook | packet_header |= RxStatusOK; |
1168 | a41b2ff2 | pbrook | |
1169 | a41b2ff2 | pbrook | packet_header |= (((size+4) << 16) & 0xffff0000); |
1170 | a41b2ff2 | pbrook | |
1171 | a41b2ff2 | pbrook | /* write header */
|
1172 | a41b2ff2 | pbrook | uint32_t val = cpu_to_le32(packet_header); |
1173 | a41b2ff2 | pbrook | |
1174 | a41b2ff2 | pbrook | rtl8139_write_buffer(s, (uint8_t *)&val, 4);
|
1175 | a41b2ff2 | pbrook | |
1176 | a41b2ff2 | pbrook | rtl8139_write_buffer(s, buf, size); |
1177 | a41b2ff2 | pbrook | |
1178 | a41b2ff2 | pbrook | /* write checksum */
|
1179 | ccf1d14a | ths | val = cpu_to_le32(crc32(0, buf, size));
|
1180 | a41b2ff2 | pbrook | rtl8139_write_buffer(s, (uint8_t *)&val, 4);
|
1181 | a41b2ff2 | pbrook | |
1182 | a41b2ff2 | pbrook | /* correct buffer write pointer */
|
1183 | a41b2ff2 | pbrook | s->RxBufAddr = MOD2((s->RxBufAddr + 3) & ~0x3, s->RxBufferSize); |
1184 | a41b2ff2 | pbrook | |
1185 | a41b2ff2 | pbrook | /* now we can signal we have received something */
|
1186 | a41b2ff2 | pbrook | |
1187 | 7cdeb319 | Benjamin Poirier | DPRINTF("received: rx buffer length %d head 0x%04x read 0x%04x\n",
|
1188 | 7cdeb319 | Benjamin Poirier | s->RxBufferSize, s->RxBufAddr, s->RxBufPtr); |
1189 | a41b2ff2 | pbrook | } |
1190 | a41b2ff2 | pbrook | |
1191 | a41b2ff2 | pbrook | s->IntrStatus |= RxOK; |
1192 | 6cadb320 | bellard | |
1193 | 6cadb320 | bellard | if (do_interrupt)
|
1194 | 6cadb320 | bellard | { |
1195 | 6cadb320 | bellard | rtl8139_update_irq(s); |
1196 | 6cadb320 | bellard | } |
1197 | 4f1c942b | Mark McLoughlin | |
1198 | 4f1c942b | Mark McLoughlin | return size_;
|
1199 | 6cadb320 | bellard | } |
1200 | 6cadb320 | bellard | |
1201 | 1673ad51 | Mark McLoughlin | static ssize_t rtl8139_receive(VLANClientState *nc, const uint8_t *buf, size_t size) |
1202 | 6cadb320 | bellard | { |
1203 | 1673ad51 | Mark McLoughlin | return rtl8139_do_receive(nc, buf, size, 1); |
1204 | a41b2ff2 | pbrook | } |
1205 | a41b2ff2 | pbrook | |
1206 | a41b2ff2 | pbrook | static void rtl8139_reset_rxring(RTL8139State *s, uint32_t bufferSize) |
1207 | a41b2ff2 | pbrook | { |
1208 | a41b2ff2 | pbrook | s->RxBufferSize = bufferSize; |
1209 | a41b2ff2 | pbrook | s->RxBufPtr = 0;
|
1210 | a41b2ff2 | pbrook | s->RxBufAddr = 0;
|
1211 | a41b2ff2 | pbrook | } |
1212 | a41b2ff2 | pbrook | |
1213 | 7f23f812 | Michael S. Tsirkin | static void rtl8139_reset(DeviceState *d) |
1214 | a41b2ff2 | pbrook | { |
1215 | 7f23f812 | Michael S. Tsirkin | RTL8139State *s = container_of(d, RTL8139State, dev.qdev); |
1216 | a41b2ff2 | pbrook | int i;
|
1217 | a41b2ff2 | pbrook | |
1218 | a41b2ff2 | pbrook | /* restore MAC address */
|
1219 | 254111ec | Gerd Hoffmann | memcpy(s->phys, s->conf.macaddr.a, 6);
|
1220 | a41b2ff2 | pbrook | |
1221 | a41b2ff2 | pbrook | /* reset interrupt mask */
|
1222 | a41b2ff2 | pbrook | s->IntrStatus = 0;
|
1223 | a41b2ff2 | pbrook | s->IntrMask = 0;
|
1224 | a41b2ff2 | pbrook | |
1225 | a41b2ff2 | pbrook | rtl8139_update_irq(s); |
1226 | a41b2ff2 | pbrook | |
1227 | a41b2ff2 | pbrook | /* mark all status registers as owned by host */
|
1228 | a41b2ff2 | pbrook | for (i = 0; i < 4; ++i) |
1229 | a41b2ff2 | pbrook | { |
1230 | a41b2ff2 | pbrook | s->TxStatus[i] = TxHostOwns; |
1231 | a41b2ff2 | pbrook | } |
1232 | a41b2ff2 | pbrook | |
1233 | a41b2ff2 | pbrook | s->currTxDesc = 0;
|
1234 | a41b2ff2 | pbrook | s->currCPlusRxDesc = 0;
|
1235 | a41b2ff2 | pbrook | s->currCPlusTxDesc = 0;
|
1236 | a41b2ff2 | pbrook | |
1237 | a41b2ff2 | pbrook | s->RxRingAddrLO = 0;
|
1238 | a41b2ff2 | pbrook | s->RxRingAddrHI = 0;
|
1239 | a41b2ff2 | pbrook | |
1240 | a41b2ff2 | pbrook | s->RxBuf = 0;
|
1241 | a41b2ff2 | pbrook | |
1242 | a41b2ff2 | pbrook | rtl8139_reset_rxring(s, 8192);
|
1243 | a41b2ff2 | pbrook | |
1244 | a41b2ff2 | pbrook | /* ACK the reset */
|
1245 | a41b2ff2 | pbrook | s->TxConfig = 0;
|
1246 | a41b2ff2 | pbrook | |
1247 | a41b2ff2 | pbrook | #if 0
|
1248 | a41b2ff2 | pbrook | // s->TxConfig |= HW_REVID(1, 0, 0, 0, 0, 0, 0); // RTL-8139 HasHltClk
|
1249 | a41b2ff2 | pbrook | s->clock_enabled = 0;
|
1250 | a41b2ff2 | pbrook | #else
|
1251 | 6cadb320 | bellard | s->TxConfig |= HW_REVID(1, 1, 1, 0, 1, 1, 0); // RTL-8139C+ HasLWake |
1252 | a41b2ff2 | pbrook | s->clock_enabled = 1;
|
1253 | a41b2ff2 | pbrook | #endif
|
1254 | a41b2ff2 | pbrook | |
1255 | a41b2ff2 | pbrook | s->bChipCmdState = CmdReset; /* RxBufEmpty bit is calculated on read from ChipCmd */;
|
1256 | a41b2ff2 | pbrook | |
1257 | a41b2ff2 | pbrook | /* set initial state data */
|
1258 | a41b2ff2 | pbrook | s->Config0 = 0x0; /* No boot ROM */ |
1259 | a41b2ff2 | pbrook | s->Config1 = 0xC; /* IO mapped and MEM mapped registers available */ |
1260 | a41b2ff2 | pbrook | s->Config3 = 0x1; /* fast back-to-back compatible */ |
1261 | a41b2ff2 | pbrook | s->Config5 = 0x0;
|
1262 | a41b2ff2 | pbrook | |
1263 | 5fafdf24 | ths | s->CSCR = CSCR_F_LINK_100 | CSCR_HEART_BIT | CSCR_LD; |
1264 | a41b2ff2 | pbrook | |
1265 | a41b2ff2 | pbrook | s->CpCmd = 0x0; /* reset C+ mode */ |
1266 | 2c3891ab | aliguori | s->cplus_enabled = 0;
|
1267 | 2c3891ab | aliguori | |
1268 | a41b2ff2 | pbrook | |
1269 | a41b2ff2 | pbrook | // s->BasicModeCtrl = 0x3100; // 100Mbps, full duplex, autonegotiation
|
1270 | a41b2ff2 | pbrook | // s->BasicModeCtrl = 0x2100; // 100Mbps, full duplex
|
1271 | a41b2ff2 | pbrook | s->BasicModeCtrl = 0x1000; // autonegotiation |
1272 | a41b2ff2 | pbrook | |
1273 | a41b2ff2 | pbrook | s->BasicModeStatus = 0x7809;
|
1274 | a41b2ff2 | pbrook | //s->BasicModeStatus |= 0x0040; /* UTP medium */
|
1275 | a41b2ff2 | pbrook | s->BasicModeStatus |= 0x0020; /* autonegotiation completed */ |
1276 | a41b2ff2 | pbrook | s->BasicModeStatus |= 0x0004; /* link is up */ |
1277 | a41b2ff2 | pbrook | |
1278 | a41b2ff2 | pbrook | s->NWayAdvert = 0x05e1; /* all modes, full duplex */ |
1279 | a41b2ff2 | pbrook | s->NWayLPAR = 0x05e1; /* all modes, full duplex */ |
1280 | a41b2ff2 | pbrook | s->NWayExpansion = 0x0001; /* autonegotiation supported */ |
1281 | 6cadb320 | bellard | |
1282 | 6cadb320 | bellard | /* also reset timer and disable timer interrupt */
|
1283 | 6cadb320 | bellard | s->TCTR = 0;
|
1284 | 6cadb320 | bellard | s->TimerInt = 0;
|
1285 | 6cadb320 | bellard | s->TCTR_base = 0;
|
1286 | 6cadb320 | bellard | |
1287 | 6cadb320 | bellard | /* reset tally counters */
|
1288 | 6cadb320 | bellard | RTL8139TallyCounters_clear(&s->tally_counters); |
1289 | 6cadb320 | bellard | } |
1290 | 6cadb320 | bellard | |
1291 | b1d8e52e | blueswir1 | static void RTL8139TallyCounters_clear(RTL8139TallyCounters* counters) |
1292 | 6cadb320 | bellard | { |
1293 | 6cadb320 | bellard | counters->TxOk = 0;
|
1294 | 6cadb320 | bellard | counters->RxOk = 0;
|
1295 | 6cadb320 | bellard | counters->TxERR = 0;
|
1296 | 6cadb320 | bellard | counters->RxERR = 0;
|
1297 | 6cadb320 | bellard | counters->MissPkt = 0;
|
1298 | 6cadb320 | bellard | counters->FAE = 0;
|
1299 | 6cadb320 | bellard | counters->Tx1Col = 0;
|
1300 | 6cadb320 | bellard | counters->TxMCol = 0;
|
1301 | 6cadb320 | bellard | counters->RxOkPhy = 0;
|
1302 | 6cadb320 | bellard | counters->RxOkBrd = 0;
|
1303 | 6cadb320 | bellard | counters->RxOkMul = 0;
|
1304 | 6cadb320 | bellard | counters->TxAbt = 0;
|
1305 | 6cadb320 | bellard | counters->TxUndrn = 0;
|
1306 | 6cadb320 | bellard | } |
1307 | 6cadb320 | bellard | |
1308 | c227f099 | Anthony Liguori | static void RTL8139TallyCounters_physical_memory_write(target_phys_addr_t tc_addr, RTL8139TallyCounters* tally_counters) |
1309 | 6cadb320 | bellard | { |
1310 | 6cadb320 | bellard | uint16_t val16; |
1311 | 6cadb320 | bellard | uint32_t val32; |
1312 | 6cadb320 | bellard | uint64_t val64; |
1313 | 6cadb320 | bellard | |
1314 | 6cadb320 | bellard | val64 = cpu_to_le64(tally_counters->TxOk); |
1315 | 6cadb320 | bellard | cpu_physical_memory_write(tc_addr + 0, (uint8_t *)&val64, 8); |
1316 | 6cadb320 | bellard | |
1317 | 6cadb320 | bellard | val64 = cpu_to_le64(tally_counters->RxOk); |
1318 | 6cadb320 | bellard | cpu_physical_memory_write(tc_addr + 8, (uint8_t *)&val64, 8); |
1319 | 6cadb320 | bellard | |
1320 | 6cadb320 | bellard | val64 = cpu_to_le64(tally_counters->TxERR); |
1321 | 6cadb320 | bellard | cpu_physical_memory_write(tc_addr + 16, (uint8_t *)&val64, 8); |
1322 | 6cadb320 | bellard | |
1323 | 6cadb320 | bellard | val32 = cpu_to_le32(tally_counters->RxERR); |
1324 | 6cadb320 | bellard | cpu_physical_memory_write(tc_addr + 24, (uint8_t *)&val32, 4); |
1325 | 6cadb320 | bellard | |
1326 | 6cadb320 | bellard | val16 = cpu_to_le16(tally_counters->MissPkt); |
1327 | 6cadb320 | bellard | cpu_physical_memory_write(tc_addr + 28, (uint8_t *)&val16, 2); |
1328 | 6cadb320 | bellard | |
1329 | 6cadb320 | bellard | val16 = cpu_to_le16(tally_counters->FAE); |
1330 | 6cadb320 | bellard | cpu_physical_memory_write(tc_addr + 30, (uint8_t *)&val16, 2); |
1331 | 6cadb320 | bellard | |
1332 | 6cadb320 | bellard | val32 = cpu_to_le32(tally_counters->Tx1Col); |
1333 | 6cadb320 | bellard | cpu_physical_memory_write(tc_addr + 32, (uint8_t *)&val32, 4); |
1334 | 6cadb320 | bellard | |
1335 | 6cadb320 | bellard | val32 = cpu_to_le32(tally_counters->TxMCol); |
1336 | 6cadb320 | bellard | cpu_physical_memory_write(tc_addr + 36, (uint8_t *)&val32, 4); |
1337 | 6cadb320 | bellard | |
1338 | 6cadb320 | bellard | val64 = cpu_to_le64(tally_counters->RxOkPhy); |
1339 | 6cadb320 | bellard | cpu_physical_memory_write(tc_addr + 40, (uint8_t *)&val64, 8); |
1340 | 6cadb320 | bellard | |
1341 | 6cadb320 | bellard | val64 = cpu_to_le64(tally_counters->RxOkBrd); |
1342 | 6cadb320 | bellard | cpu_physical_memory_write(tc_addr + 48, (uint8_t *)&val64, 8); |
1343 | 6cadb320 | bellard | |
1344 | 6cadb320 | bellard | val32 = cpu_to_le32(tally_counters->RxOkMul); |
1345 | 6cadb320 | bellard | cpu_physical_memory_write(tc_addr + 56, (uint8_t *)&val32, 4); |
1346 | 6cadb320 | bellard | |
1347 | 6cadb320 | bellard | val16 = cpu_to_le16(tally_counters->TxAbt); |
1348 | 6cadb320 | bellard | cpu_physical_memory_write(tc_addr + 60, (uint8_t *)&val16, 2); |
1349 | 6cadb320 | bellard | |
1350 | 6cadb320 | bellard | val16 = cpu_to_le16(tally_counters->TxUndrn); |
1351 | 6cadb320 | bellard | cpu_physical_memory_write(tc_addr + 62, (uint8_t *)&val16, 2); |
1352 | 6cadb320 | bellard | } |
1353 | 6cadb320 | bellard | |
1354 | 6cadb320 | bellard | /* Loads values of tally counters from VM state file */
|
1355 | 9d29cdea | Juan Quintela | |
1356 | 9d29cdea | Juan Quintela | static const VMStateDescription vmstate_tally_counters = { |
1357 | 9d29cdea | Juan Quintela | .name = "tally_counters",
|
1358 | 9d29cdea | Juan Quintela | .version_id = 1,
|
1359 | 9d29cdea | Juan Quintela | .minimum_version_id = 1,
|
1360 | 9d29cdea | Juan Quintela | .minimum_version_id_old = 1,
|
1361 | 9d29cdea | Juan Quintela | .fields = (VMStateField []) { |
1362 | 9d29cdea | Juan Quintela | VMSTATE_UINT64(TxOk, RTL8139TallyCounters), |
1363 | 9d29cdea | Juan Quintela | VMSTATE_UINT64(RxOk, RTL8139TallyCounters), |
1364 | 9d29cdea | Juan Quintela | VMSTATE_UINT64(TxERR, RTL8139TallyCounters), |
1365 | 9d29cdea | Juan Quintela | VMSTATE_UINT32(RxERR, RTL8139TallyCounters), |
1366 | 9d29cdea | Juan Quintela | VMSTATE_UINT16(MissPkt, RTL8139TallyCounters), |
1367 | 9d29cdea | Juan Quintela | VMSTATE_UINT16(FAE, RTL8139TallyCounters), |
1368 | 9d29cdea | Juan Quintela | VMSTATE_UINT32(Tx1Col, RTL8139TallyCounters), |
1369 | 9d29cdea | Juan Quintela | VMSTATE_UINT32(TxMCol, RTL8139TallyCounters), |
1370 | 9d29cdea | Juan Quintela | VMSTATE_UINT64(RxOkPhy, RTL8139TallyCounters), |
1371 | 9d29cdea | Juan Quintela | VMSTATE_UINT64(RxOkBrd, RTL8139TallyCounters), |
1372 | 9d29cdea | Juan Quintela | VMSTATE_UINT16(TxAbt, RTL8139TallyCounters), |
1373 | 9d29cdea | Juan Quintela | VMSTATE_UINT16(TxUndrn, RTL8139TallyCounters), |
1374 | 9d29cdea | Juan Quintela | VMSTATE_END_OF_LIST() |
1375 | 9d29cdea | Juan Quintela | } |
1376 | 9d29cdea | Juan Quintela | }; |
1377 | a41b2ff2 | pbrook | |
1378 | a41b2ff2 | pbrook | static void rtl8139_ChipCmd_write(RTL8139State *s, uint32_t val) |
1379 | a41b2ff2 | pbrook | { |
1380 | a41b2ff2 | pbrook | val &= 0xff;
|
1381 | a41b2ff2 | pbrook | |
1382 | 7cdeb319 | Benjamin Poirier | DPRINTF("ChipCmd write val=0x%08x\n", val);
|
1383 | a41b2ff2 | pbrook | |
1384 | a41b2ff2 | pbrook | if (val & CmdReset)
|
1385 | a41b2ff2 | pbrook | { |
1386 | 7cdeb319 | Benjamin Poirier | DPRINTF("ChipCmd reset\n");
|
1387 | 7f23f812 | Michael S. Tsirkin | rtl8139_reset(&s->dev.qdev); |
1388 | a41b2ff2 | pbrook | } |
1389 | a41b2ff2 | pbrook | if (val & CmdRxEnb)
|
1390 | a41b2ff2 | pbrook | { |
1391 | 7cdeb319 | Benjamin Poirier | DPRINTF("ChipCmd enable receiver\n");
|
1392 | 718da2b9 | bellard | |
1393 | 718da2b9 | bellard | s->currCPlusRxDesc = 0;
|
1394 | a41b2ff2 | pbrook | } |
1395 | a41b2ff2 | pbrook | if (val & CmdTxEnb)
|
1396 | a41b2ff2 | pbrook | { |
1397 | 7cdeb319 | Benjamin Poirier | DPRINTF("ChipCmd enable transmitter\n");
|
1398 | 718da2b9 | bellard | |
1399 | 718da2b9 | bellard | s->currCPlusTxDesc = 0;
|
1400 | a41b2ff2 | pbrook | } |
1401 | a41b2ff2 | pbrook | |
1402 | a41b2ff2 | pbrook | /* mask unwriteable bits */
|
1403 | a41b2ff2 | pbrook | val = SET_MASKED(val, 0xe3, s->bChipCmdState);
|
1404 | a41b2ff2 | pbrook | |
1405 | a41b2ff2 | pbrook | /* Deassert reset pin before next read */
|
1406 | a41b2ff2 | pbrook | val &= ~CmdReset; |
1407 | a41b2ff2 | pbrook | |
1408 | a41b2ff2 | pbrook | s->bChipCmdState = val; |
1409 | a41b2ff2 | pbrook | } |
1410 | a41b2ff2 | pbrook | |
1411 | a41b2ff2 | pbrook | static int rtl8139_RxBufferEmpty(RTL8139State *s) |
1412 | a41b2ff2 | pbrook | { |
1413 | a41b2ff2 | pbrook | int unread = MOD2(s->RxBufferSize + s->RxBufAddr - s->RxBufPtr, s->RxBufferSize);
|
1414 | a41b2ff2 | pbrook | |
1415 | a41b2ff2 | pbrook | if (unread != 0) |
1416 | a41b2ff2 | pbrook | { |
1417 | 7cdeb319 | Benjamin Poirier | DPRINTF("receiver buffer data available 0x%04x\n", unread);
|
1418 | a41b2ff2 | pbrook | return 0; |
1419 | a41b2ff2 | pbrook | } |
1420 | a41b2ff2 | pbrook | |
1421 | 7cdeb319 | Benjamin Poirier | DPRINTF("receiver buffer is empty\n");
|
1422 | a41b2ff2 | pbrook | |
1423 | a41b2ff2 | pbrook | return 1; |
1424 | a41b2ff2 | pbrook | } |
1425 | a41b2ff2 | pbrook | |
1426 | a41b2ff2 | pbrook | static uint32_t rtl8139_ChipCmd_read(RTL8139State *s)
|
1427 | a41b2ff2 | pbrook | { |
1428 | a41b2ff2 | pbrook | uint32_t ret = s->bChipCmdState; |
1429 | a41b2ff2 | pbrook | |
1430 | a41b2ff2 | pbrook | if (rtl8139_RxBufferEmpty(s))
|
1431 | a41b2ff2 | pbrook | ret |= RxBufEmpty; |
1432 | a41b2ff2 | pbrook | |
1433 | 7cdeb319 | Benjamin Poirier | DPRINTF("ChipCmd read val=0x%04x\n", ret);
|
1434 | a41b2ff2 | pbrook | |
1435 | a41b2ff2 | pbrook | return ret;
|
1436 | a41b2ff2 | pbrook | } |
1437 | a41b2ff2 | pbrook | |
1438 | a41b2ff2 | pbrook | static void rtl8139_CpCmd_write(RTL8139State *s, uint32_t val) |
1439 | a41b2ff2 | pbrook | { |
1440 | a41b2ff2 | pbrook | val &= 0xffff;
|
1441 | a41b2ff2 | pbrook | |
1442 | 7cdeb319 | Benjamin Poirier | DPRINTF("C+ command register write(w) val=0x%04x\n", val);
|
1443 | a41b2ff2 | pbrook | |
1444 | 2c3891ab | aliguori | s->cplus_enabled = 1;
|
1445 | 2c3891ab | aliguori | |
1446 | a41b2ff2 | pbrook | /* mask unwriteable bits */
|
1447 | a41b2ff2 | pbrook | val = SET_MASKED(val, 0xff84, s->CpCmd);
|
1448 | a41b2ff2 | pbrook | |
1449 | a41b2ff2 | pbrook | s->CpCmd = val; |
1450 | a41b2ff2 | pbrook | } |
1451 | a41b2ff2 | pbrook | |
1452 | a41b2ff2 | pbrook | static uint32_t rtl8139_CpCmd_read(RTL8139State *s)
|
1453 | a41b2ff2 | pbrook | { |
1454 | a41b2ff2 | pbrook | uint32_t ret = s->CpCmd; |
1455 | a41b2ff2 | pbrook | |
1456 | 7cdeb319 | Benjamin Poirier | DPRINTF("C+ command register read(w) val=0x%04x\n", ret);
|
1457 | 6cadb320 | bellard | |
1458 | 6cadb320 | bellard | return ret;
|
1459 | 6cadb320 | bellard | } |
1460 | 6cadb320 | bellard | |
1461 | 6cadb320 | bellard | static void rtl8139_IntrMitigate_write(RTL8139State *s, uint32_t val) |
1462 | 6cadb320 | bellard | { |
1463 | 7cdeb319 | Benjamin Poirier | DPRINTF("C+ IntrMitigate register write(w) val=0x%04x\n", val);
|
1464 | 6cadb320 | bellard | } |
1465 | 6cadb320 | bellard | |
1466 | 6cadb320 | bellard | static uint32_t rtl8139_IntrMitigate_read(RTL8139State *s)
|
1467 | 6cadb320 | bellard | { |
1468 | 6cadb320 | bellard | uint32_t ret = 0;
|
1469 | 6cadb320 | bellard | |
1470 | 7cdeb319 | Benjamin Poirier | DPRINTF("C+ IntrMitigate register read(w) val=0x%04x\n", ret);
|
1471 | a41b2ff2 | pbrook | |
1472 | a41b2ff2 | pbrook | return ret;
|
1473 | a41b2ff2 | pbrook | } |
1474 | a41b2ff2 | pbrook | |
1475 | 9596ebb7 | pbrook | static int rtl8139_config_writeable(RTL8139State *s) |
1476 | a41b2ff2 | pbrook | { |
1477 | a41b2ff2 | pbrook | if (s->Cfg9346 & Cfg9346_Unlock)
|
1478 | a41b2ff2 | pbrook | { |
1479 | a41b2ff2 | pbrook | return 1; |
1480 | a41b2ff2 | pbrook | } |
1481 | a41b2ff2 | pbrook | |
1482 | 7cdeb319 | Benjamin Poirier | DPRINTF("Configuration registers are write-protected\n");
|
1483 | a41b2ff2 | pbrook | |
1484 | a41b2ff2 | pbrook | return 0; |
1485 | a41b2ff2 | pbrook | } |
1486 | a41b2ff2 | pbrook | |
1487 | a41b2ff2 | pbrook | static void rtl8139_BasicModeCtrl_write(RTL8139State *s, uint32_t val) |
1488 | a41b2ff2 | pbrook | { |
1489 | a41b2ff2 | pbrook | val &= 0xffff;
|
1490 | a41b2ff2 | pbrook | |
1491 | 7cdeb319 | Benjamin Poirier | DPRINTF("BasicModeCtrl register write(w) val=0x%04x\n", val);
|
1492 | a41b2ff2 | pbrook | |
1493 | a41b2ff2 | pbrook | /* mask unwriteable bits */
|
1494 | e3d7e843 | ths | uint32_t mask = 0x4cff;
|
1495 | a41b2ff2 | pbrook | |
1496 | a41b2ff2 | pbrook | if (1 || !rtl8139_config_writeable(s)) |
1497 | a41b2ff2 | pbrook | { |
1498 | a41b2ff2 | pbrook | /* Speed setting and autonegotiation enable bits are read-only */
|
1499 | a41b2ff2 | pbrook | mask |= 0x3000;
|
1500 | a41b2ff2 | pbrook | /* Duplex mode setting is read-only */
|
1501 | a41b2ff2 | pbrook | mask |= 0x0100;
|
1502 | a41b2ff2 | pbrook | } |
1503 | a41b2ff2 | pbrook | |
1504 | a41b2ff2 | pbrook | val = SET_MASKED(val, mask, s->BasicModeCtrl); |
1505 | a41b2ff2 | pbrook | |
1506 | a41b2ff2 | pbrook | s->BasicModeCtrl = val; |
1507 | a41b2ff2 | pbrook | } |
1508 | a41b2ff2 | pbrook | |
1509 | a41b2ff2 | pbrook | static uint32_t rtl8139_BasicModeCtrl_read(RTL8139State *s)
|
1510 | a41b2ff2 | pbrook | { |
1511 | a41b2ff2 | pbrook | uint32_t ret = s->BasicModeCtrl; |
1512 | a41b2ff2 | pbrook | |
1513 | 7cdeb319 | Benjamin Poirier | DPRINTF("BasicModeCtrl register read(w) val=0x%04x\n", ret);
|
1514 | a41b2ff2 | pbrook | |
1515 | a41b2ff2 | pbrook | return ret;
|
1516 | a41b2ff2 | pbrook | } |
1517 | a41b2ff2 | pbrook | |
1518 | a41b2ff2 | pbrook | static void rtl8139_BasicModeStatus_write(RTL8139State *s, uint32_t val) |
1519 | a41b2ff2 | pbrook | { |
1520 | a41b2ff2 | pbrook | val &= 0xffff;
|
1521 | a41b2ff2 | pbrook | |
1522 | 7cdeb319 | Benjamin Poirier | DPRINTF("BasicModeStatus register write(w) val=0x%04x\n", val);
|
1523 | a41b2ff2 | pbrook | |
1524 | a41b2ff2 | pbrook | /* mask unwriteable bits */
|
1525 | a41b2ff2 | pbrook | val = SET_MASKED(val, 0xff3f, s->BasicModeStatus);
|
1526 | a41b2ff2 | pbrook | |
1527 | a41b2ff2 | pbrook | s->BasicModeStatus = val; |
1528 | a41b2ff2 | pbrook | } |
1529 | a41b2ff2 | pbrook | |
1530 | a41b2ff2 | pbrook | static uint32_t rtl8139_BasicModeStatus_read(RTL8139State *s)
|
1531 | a41b2ff2 | pbrook | { |
1532 | a41b2ff2 | pbrook | uint32_t ret = s->BasicModeStatus; |
1533 | a41b2ff2 | pbrook | |
1534 | 7cdeb319 | Benjamin Poirier | DPRINTF("BasicModeStatus register read(w) val=0x%04x\n", ret);
|
1535 | a41b2ff2 | pbrook | |
1536 | a41b2ff2 | pbrook | return ret;
|
1537 | a41b2ff2 | pbrook | } |
1538 | a41b2ff2 | pbrook | |
1539 | a41b2ff2 | pbrook | static void rtl8139_Cfg9346_write(RTL8139State *s, uint32_t val) |
1540 | a41b2ff2 | pbrook | { |
1541 | a41b2ff2 | pbrook | val &= 0xff;
|
1542 | a41b2ff2 | pbrook | |
1543 | 7cdeb319 | Benjamin Poirier | DPRINTF("Cfg9346 write val=0x%02x\n", val);
|
1544 | a41b2ff2 | pbrook | |
1545 | a41b2ff2 | pbrook | /* mask unwriteable bits */
|
1546 | a41b2ff2 | pbrook | val = SET_MASKED(val, 0x31, s->Cfg9346);
|
1547 | a41b2ff2 | pbrook | |
1548 | a41b2ff2 | pbrook | uint32_t opmode = val & 0xc0;
|
1549 | a41b2ff2 | pbrook | uint32_t eeprom_val = val & 0xf;
|
1550 | a41b2ff2 | pbrook | |
1551 | a41b2ff2 | pbrook | if (opmode == 0x80) { |
1552 | a41b2ff2 | pbrook | /* eeprom access */
|
1553 | a41b2ff2 | pbrook | int eecs = (eeprom_val & 0x08)?1:0; |
1554 | a41b2ff2 | pbrook | int eesk = (eeprom_val & 0x04)?1:0; |
1555 | a41b2ff2 | pbrook | int eedi = (eeprom_val & 0x02)?1:0; |
1556 | a41b2ff2 | pbrook | prom9346_set_wire(s, eecs, eesk, eedi); |
1557 | a41b2ff2 | pbrook | } else if (opmode == 0x40) { |
1558 | a41b2ff2 | pbrook | /* Reset. */
|
1559 | a41b2ff2 | pbrook | val = 0;
|
1560 | 7f23f812 | Michael S. Tsirkin | rtl8139_reset(&s->dev.qdev); |
1561 | a41b2ff2 | pbrook | } |
1562 | a41b2ff2 | pbrook | |
1563 | a41b2ff2 | pbrook | s->Cfg9346 = val; |
1564 | a41b2ff2 | pbrook | } |
1565 | a41b2ff2 | pbrook | |
1566 | a41b2ff2 | pbrook | static uint32_t rtl8139_Cfg9346_read(RTL8139State *s)
|
1567 | a41b2ff2 | pbrook | { |
1568 | a41b2ff2 | pbrook | uint32_t ret = s->Cfg9346; |
1569 | a41b2ff2 | pbrook | |
1570 | a41b2ff2 | pbrook | uint32_t opmode = ret & 0xc0;
|
1571 | a41b2ff2 | pbrook | |
1572 | a41b2ff2 | pbrook | if (opmode == 0x80) |
1573 | a41b2ff2 | pbrook | { |
1574 | a41b2ff2 | pbrook | /* eeprom access */
|
1575 | a41b2ff2 | pbrook | int eedo = prom9346_get_wire(s);
|
1576 | a41b2ff2 | pbrook | if (eedo)
|
1577 | a41b2ff2 | pbrook | { |
1578 | a41b2ff2 | pbrook | ret |= 0x01;
|
1579 | a41b2ff2 | pbrook | } |
1580 | a41b2ff2 | pbrook | else
|
1581 | a41b2ff2 | pbrook | { |
1582 | a41b2ff2 | pbrook | ret &= ~0x01;
|
1583 | a41b2ff2 | pbrook | } |
1584 | a41b2ff2 | pbrook | } |
1585 | a41b2ff2 | pbrook | |
1586 | 7cdeb319 | Benjamin Poirier | DPRINTF("Cfg9346 read val=0x%02x\n", ret);
|
1587 | a41b2ff2 | pbrook | |
1588 | a41b2ff2 | pbrook | return ret;
|
1589 | a41b2ff2 | pbrook | } |
1590 | a41b2ff2 | pbrook | |
1591 | a41b2ff2 | pbrook | static void rtl8139_Config0_write(RTL8139State *s, uint32_t val) |
1592 | a41b2ff2 | pbrook | { |
1593 | a41b2ff2 | pbrook | val &= 0xff;
|
1594 | a41b2ff2 | pbrook | |
1595 | 7cdeb319 | Benjamin Poirier | DPRINTF("Config0 write val=0x%02x\n", val);
|
1596 | a41b2ff2 | pbrook | |
1597 | a41b2ff2 | pbrook | if (!rtl8139_config_writeable(s))
|
1598 | a41b2ff2 | pbrook | return;
|
1599 | a41b2ff2 | pbrook | |
1600 | a41b2ff2 | pbrook | /* mask unwriteable bits */
|
1601 | a41b2ff2 | pbrook | val = SET_MASKED(val, 0xf8, s->Config0);
|
1602 | a41b2ff2 | pbrook | |
1603 | a41b2ff2 | pbrook | s->Config0 = val; |
1604 | a41b2ff2 | pbrook | } |
1605 | a41b2ff2 | pbrook | |
1606 | a41b2ff2 | pbrook | static uint32_t rtl8139_Config0_read(RTL8139State *s)
|
1607 | a41b2ff2 | pbrook | { |
1608 | a41b2ff2 | pbrook | uint32_t ret = s->Config0; |
1609 | a41b2ff2 | pbrook | |
1610 | 7cdeb319 | Benjamin Poirier | DPRINTF("Config0 read val=0x%02x\n", ret);
|
1611 | a41b2ff2 | pbrook | |
1612 | a41b2ff2 | pbrook | return ret;
|
1613 | a41b2ff2 | pbrook | } |
1614 | a41b2ff2 | pbrook | |
1615 | a41b2ff2 | pbrook | static void rtl8139_Config1_write(RTL8139State *s, uint32_t val) |
1616 | a41b2ff2 | pbrook | { |
1617 | a41b2ff2 | pbrook | val &= 0xff;
|
1618 | a41b2ff2 | pbrook | |
1619 | 7cdeb319 | Benjamin Poirier | DPRINTF("Config1 write val=0x%02x\n", val);
|
1620 | a41b2ff2 | pbrook | |
1621 | a41b2ff2 | pbrook | if (!rtl8139_config_writeable(s))
|
1622 | a41b2ff2 | pbrook | return;
|
1623 | a41b2ff2 | pbrook | |
1624 | a41b2ff2 | pbrook | /* mask unwriteable bits */
|
1625 | a41b2ff2 | pbrook | val = SET_MASKED(val, 0xC, s->Config1);
|
1626 | a41b2ff2 | pbrook | |
1627 | a41b2ff2 | pbrook | s->Config1 = val; |
1628 | a41b2ff2 | pbrook | } |
1629 | a41b2ff2 | pbrook | |
1630 | a41b2ff2 | pbrook | static uint32_t rtl8139_Config1_read(RTL8139State *s)
|
1631 | a41b2ff2 | pbrook | { |
1632 | a41b2ff2 | pbrook | uint32_t ret = s->Config1; |
1633 | a41b2ff2 | pbrook | |
1634 | 7cdeb319 | Benjamin Poirier | DPRINTF("Config1 read val=0x%02x\n", ret);
|
1635 | a41b2ff2 | pbrook | |
1636 | a41b2ff2 | pbrook | return ret;
|
1637 | a41b2ff2 | pbrook | } |
1638 | a41b2ff2 | pbrook | |
1639 | a41b2ff2 | pbrook | static void rtl8139_Config3_write(RTL8139State *s, uint32_t val) |
1640 | a41b2ff2 | pbrook | { |
1641 | a41b2ff2 | pbrook | val &= 0xff;
|
1642 | a41b2ff2 | pbrook | |
1643 | 7cdeb319 | Benjamin Poirier | DPRINTF("Config3 write val=0x%02x\n", val);
|
1644 | a41b2ff2 | pbrook | |
1645 | a41b2ff2 | pbrook | if (!rtl8139_config_writeable(s))
|
1646 | a41b2ff2 | pbrook | return;
|
1647 | a41b2ff2 | pbrook | |
1648 | a41b2ff2 | pbrook | /* mask unwriteable bits */
|
1649 | a41b2ff2 | pbrook | val = SET_MASKED(val, 0x8F, s->Config3);
|
1650 | a41b2ff2 | pbrook | |
1651 | a41b2ff2 | pbrook | s->Config3 = val; |
1652 | a41b2ff2 | pbrook | } |
1653 | a41b2ff2 | pbrook | |
1654 | a41b2ff2 | pbrook | static uint32_t rtl8139_Config3_read(RTL8139State *s)
|
1655 | a41b2ff2 | pbrook | { |
1656 | a41b2ff2 | pbrook | uint32_t ret = s->Config3; |
1657 | a41b2ff2 | pbrook | |
1658 | 7cdeb319 | Benjamin Poirier | DPRINTF("Config3 read val=0x%02x\n", ret);
|
1659 | a41b2ff2 | pbrook | |
1660 | a41b2ff2 | pbrook | return ret;
|
1661 | a41b2ff2 | pbrook | } |
1662 | a41b2ff2 | pbrook | |
1663 | a41b2ff2 | pbrook | static void rtl8139_Config4_write(RTL8139State *s, uint32_t val) |
1664 | a41b2ff2 | pbrook | { |
1665 | a41b2ff2 | pbrook | val &= 0xff;
|
1666 | a41b2ff2 | pbrook | |
1667 | 7cdeb319 | Benjamin Poirier | DPRINTF("Config4 write val=0x%02x\n", val);
|
1668 | a41b2ff2 | pbrook | |
1669 | a41b2ff2 | pbrook | if (!rtl8139_config_writeable(s))
|
1670 | a41b2ff2 | pbrook | return;
|
1671 | a41b2ff2 | pbrook | |
1672 | a41b2ff2 | pbrook | /* mask unwriteable bits */
|
1673 | a41b2ff2 | pbrook | val = SET_MASKED(val, 0x0a, s->Config4);
|
1674 | a41b2ff2 | pbrook | |
1675 | a41b2ff2 | pbrook | s->Config4 = val; |
1676 | a41b2ff2 | pbrook | } |
1677 | a41b2ff2 | pbrook | |
1678 | a41b2ff2 | pbrook | static uint32_t rtl8139_Config4_read(RTL8139State *s)
|
1679 | a41b2ff2 | pbrook | { |
1680 | a41b2ff2 | pbrook | uint32_t ret = s->Config4; |
1681 | a41b2ff2 | pbrook | |
1682 | 7cdeb319 | Benjamin Poirier | DPRINTF("Config4 read val=0x%02x\n", ret);
|
1683 | a41b2ff2 | pbrook | |
1684 | a41b2ff2 | pbrook | return ret;
|
1685 | a41b2ff2 | pbrook | } |
1686 | a41b2ff2 | pbrook | |
1687 | a41b2ff2 | pbrook | static void rtl8139_Config5_write(RTL8139State *s, uint32_t val) |
1688 | a41b2ff2 | pbrook | { |
1689 | a41b2ff2 | pbrook | val &= 0xff;
|
1690 | a41b2ff2 | pbrook | |
1691 | 7cdeb319 | Benjamin Poirier | DPRINTF("Config5 write val=0x%02x\n", val);
|
1692 | a41b2ff2 | pbrook | |
1693 | a41b2ff2 | pbrook | /* mask unwriteable bits */
|
1694 | a41b2ff2 | pbrook | val = SET_MASKED(val, 0x80, s->Config5);
|
1695 | a41b2ff2 | pbrook | |
1696 | a41b2ff2 | pbrook | s->Config5 = val; |
1697 | a41b2ff2 | pbrook | } |
1698 | a41b2ff2 | pbrook | |
1699 | a41b2ff2 | pbrook | static uint32_t rtl8139_Config5_read(RTL8139State *s)
|
1700 | a41b2ff2 | pbrook | { |
1701 | a41b2ff2 | pbrook | uint32_t ret = s->Config5; |
1702 | a41b2ff2 | pbrook | |
1703 | 7cdeb319 | Benjamin Poirier | DPRINTF("Config5 read val=0x%02x\n", ret);
|
1704 | a41b2ff2 | pbrook | |
1705 | a41b2ff2 | pbrook | return ret;
|
1706 | a41b2ff2 | pbrook | } |
1707 | a41b2ff2 | pbrook | |
1708 | a41b2ff2 | pbrook | static void rtl8139_TxConfig_write(RTL8139State *s, uint32_t val) |
1709 | a41b2ff2 | pbrook | { |
1710 | a41b2ff2 | pbrook | if (!rtl8139_transmitter_enabled(s))
|
1711 | a41b2ff2 | pbrook | { |
1712 | 7cdeb319 | Benjamin Poirier | DPRINTF("transmitter disabled; no TxConfig write val=0x%08x\n", val);
|
1713 | a41b2ff2 | pbrook | return;
|
1714 | a41b2ff2 | pbrook | } |
1715 | a41b2ff2 | pbrook | |
1716 | 7cdeb319 | Benjamin Poirier | DPRINTF("TxConfig write val=0x%08x\n", val);
|
1717 | a41b2ff2 | pbrook | |
1718 | a41b2ff2 | pbrook | val = SET_MASKED(val, TxVersionMask | 0x8070f80f, s->TxConfig);
|
1719 | a41b2ff2 | pbrook | |
1720 | a41b2ff2 | pbrook | s->TxConfig = val; |
1721 | a41b2ff2 | pbrook | } |
1722 | a41b2ff2 | pbrook | |
1723 | a41b2ff2 | pbrook | static void rtl8139_TxConfig_writeb(RTL8139State *s, uint32_t val) |
1724 | a41b2ff2 | pbrook | { |
1725 | 7cdeb319 | Benjamin Poirier | DPRINTF("RTL8139C TxConfig via write(b) val=0x%02x\n", val);
|
1726 | 6cadb320 | bellard | |
1727 | 6cadb320 | bellard | uint32_t tc = s->TxConfig; |
1728 | 6cadb320 | bellard | tc &= 0xFFFFFF00;
|
1729 | 6cadb320 | bellard | tc |= (val & 0x000000FF);
|
1730 | 6cadb320 | bellard | rtl8139_TxConfig_write(s, tc); |
1731 | a41b2ff2 | pbrook | } |
1732 | a41b2ff2 | pbrook | |
1733 | a41b2ff2 | pbrook | static uint32_t rtl8139_TxConfig_read(RTL8139State *s)
|
1734 | a41b2ff2 | pbrook | { |
1735 | a41b2ff2 | pbrook | uint32_t ret = s->TxConfig; |
1736 | a41b2ff2 | pbrook | |
1737 | 7cdeb319 | Benjamin Poirier | DPRINTF("TxConfig read val=0x%04x\n", ret);
|
1738 | a41b2ff2 | pbrook | |
1739 | a41b2ff2 | pbrook | return ret;
|
1740 | a41b2ff2 | pbrook | } |
1741 | a41b2ff2 | pbrook | |
1742 | a41b2ff2 | pbrook | static void rtl8139_RxConfig_write(RTL8139State *s, uint32_t val) |
1743 | a41b2ff2 | pbrook | { |
1744 | 7cdeb319 | Benjamin Poirier | DPRINTF("RxConfig write val=0x%08x\n", val);
|
1745 | a41b2ff2 | pbrook | |
1746 | a41b2ff2 | pbrook | /* mask unwriteable bits */
|
1747 | a41b2ff2 | pbrook | val = SET_MASKED(val, 0xf0fc0040, s->RxConfig);
|
1748 | a41b2ff2 | pbrook | |
1749 | a41b2ff2 | pbrook | s->RxConfig = val; |
1750 | a41b2ff2 | pbrook | |
1751 | a41b2ff2 | pbrook | /* reset buffer size and read/write pointers */
|
1752 | a41b2ff2 | pbrook | rtl8139_reset_rxring(s, 8192 << ((s->RxConfig >> 11) & 0x3)); |
1753 | a41b2ff2 | pbrook | |
1754 | 7cdeb319 | Benjamin Poirier | DPRINTF("RxConfig write reset buffer size to %d\n", s->RxBufferSize);
|
1755 | a41b2ff2 | pbrook | } |
1756 | a41b2ff2 | pbrook | |
1757 | a41b2ff2 | pbrook | static uint32_t rtl8139_RxConfig_read(RTL8139State *s)
|
1758 | a41b2ff2 | pbrook | { |
1759 | a41b2ff2 | pbrook | uint32_t ret = s->RxConfig; |
1760 | a41b2ff2 | pbrook | |
1761 | 7cdeb319 | Benjamin Poirier | DPRINTF("RxConfig read val=0x%08x\n", ret);
|
1762 | a41b2ff2 | pbrook | |
1763 | a41b2ff2 | pbrook | return ret;
|
1764 | a41b2ff2 | pbrook | } |
1765 | a41b2ff2 | pbrook | |
1766 | bf6b87a8 | Benjamin Poirier | static void rtl8139_transfer_frame(RTL8139State *s, uint8_t *buf, int size, |
1767 | bf6b87a8 | Benjamin Poirier | int do_interrupt, const uint8_t *dot1q_buf) |
1768 | 718da2b9 | bellard | { |
1769 | bf6b87a8 | Benjamin Poirier | struct iovec *iov = NULL; |
1770 | bf6b87a8 | Benjamin Poirier | |
1771 | 718da2b9 | bellard | if (!size)
|
1772 | 718da2b9 | bellard | { |
1773 | 7cdeb319 | Benjamin Poirier | DPRINTF("+++ empty ethernet frame\n");
|
1774 | 718da2b9 | bellard | return;
|
1775 | 718da2b9 | bellard | } |
1776 | 718da2b9 | bellard | |
1777 | bf6b87a8 | Benjamin Poirier | if (dot1q_buf && size >= ETHER_ADDR_LEN * 2) { |
1778 | bf6b87a8 | Benjamin Poirier | iov = (struct iovec[3]) { |
1779 | bf6b87a8 | Benjamin Poirier | { .iov_base = buf, .iov_len = ETHER_ADDR_LEN * 2 },
|
1780 | bf6b87a8 | Benjamin Poirier | { .iov_base = (void *) dot1q_buf, .iov_len = VLAN_HLEN },
|
1781 | bf6b87a8 | Benjamin Poirier | { .iov_base = buf + ETHER_ADDR_LEN * 2,
|
1782 | bf6b87a8 | Benjamin Poirier | .iov_len = size - ETHER_ADDR_LEN * 2 },
|
1783 | bf6b87a8 | Benjamin Poirier | }; |
1784 | bf6b87a8 | Benjamin Poirier | } |
1785 | bf6b87a8 | Benjamin Poirier | |
1786 | 718da2b9 | bellard | if (TxLoopBack == (s->TxConfig & TxLoopBack))
|
1787 | 718da2b9 | bellard | { |
1788 | bf6b87a8 | Benjamin Poirier | size_t buf2_size; |
1789 | bf6b87a8 | Benjamin Poirier | uint8_t *buf2; |
1790 | bf6b87a8 | Benjamin Poirier | |
1791 | bf6b87a8 | Benjamin Poirier | if (iov) {
|
1792 | bf6b87a8 | Benjamin Poirier | buf2_size = iov_size(iov, 3);
|
1793 | bf6b87a8 | Benjamin Poirier | buf2 = qemu_malloc(buf2_size); |
1794 | bf6b87a8 | Benjamin Poirier | iov_to_buf(iov, 3, buf2, 0, buf2_size); |
1795 | bf6b87a8 | Benjamin Poirier | buf = buf2; |
1796 | bf6b87a8 | Benjamin Poirier | } |
1797 | bf6b87a8 | Benjamin Poirier | |
1798 | 7cdeb319 | Benjamin Poirier | DPRINTF("+++ transmit loopback mode\n");
|
1799 | 1673ad51 | Mark McLoughlin | rtl8139_do_receive(&s->nic->nc, buf, size, do_interrupt); |
1800 | bf6b87a8 | Benjamin Poirier | |
1801 | bf6b87a8 | Benjamin Poirier | if (iov) {
|
1802 | bf6b87a8 | Benjamin Poirier | qemu_free(buf2); |
1803 | bf6b87a8 | Benjamin Poirier | } |
1804 | 718da2b9 | bellard | } |
1805 | 718da2b9 | bellard | else
|
1806 | 718da2b9 | bellard | { |
1807 | bf6b87a8 | Benjamin Poirier | if (iov) {
|
1808 | bf6b87a8 | Benjamin Poirier | qemu_sendv_packet(&s->nic->nc, iov, 3);
|
1809 | bf6b87a8 | Benjamin Poirier | } else {
|
1810 | bf6b87a8 | Benjamin Poirier | qemu_send_packet(&s->nic->nc, buf, size); |
1811 | bf6b87a8 | Benjamin Poirier | } |
1812 | 718da2b9 | bellard | } |
1813 | 718da2b9 | bellard | } |
1814 | 718da2b9 | bellard | |
1815 | a41b2ff2 | pbrook | static int rtl8139_transmit_one(RTL8139State *s, int descriptor) |
1816 | a41b2ff2 | pbrook | { |
1817 | a41b2ff2 | pbrook | if (!rtl8139_transmitter_enabled(s))
|
1818 | a41b2ff2 | pbrook | { |
1819 | 7cdeb319 | Benjamin Poirier | DPRINTF("+++ cannot transmit from descriptor %d: transmitter "
|
1820 | 7cdeb319 | Benjamin Poirier | "disabled\n", descriptor);
|
1821 | a41b2ff2 | pbrook | return 0; |
1822 | a41b2ff2 | pbrook | } |
1823 | a41b2ff2 | pbrook | |
1824 | a41b2ff2 | pbrook | if (s->TxStatus[descriptor] & TxHostOwns)
|
1825 | a41b2ff2 | pbrook | { |
1826 | 7cdeb319 | Benjamin Poirier | DPRINTF("+++ cannot transmit from descriptor %d: owned by host "
|
1827 | 7cdeb319 | Benjamin Poirier | "(%08x)\n", descriptor, s->TxStatus[descriptor]);
|
1828 | a41b2ff2 | pbrook | return 0; |
1829 | a41b2ff2 | pbrook | } |
1830 | a41b2ff2 | pbrook | |
1831 | 7cdeb319 | Benjamin Poirier | DPRINTF("+++ transmitting from descriptor %d\n", descriptor);
|
1832 | a41b2ff2 | pbrook | |
1833 | a41b2ff2 | pbrook | int txsize = s->TxStatus[descriptor] & 0x1fff; |
1834 | a41b2ff2 | pbrook | uint8_t txbuffer[0x2000];
|
1835 | a41b2ff2 | pbrook | |
1836 | 7cdeb319 | Benjamin Poirier | DPRINTF("+++ transmit reading %d bytes from host memory at 0x%08x\n",
|
1837 | 7cdeb319 | Benjamin Poirier | txsize, s->TxAddr[descriptor]); |
1838 | a41b2ff2 | pbrook | |
1839 | 6cadb320 | bellard | cpu_physical_memory_read(s->TxAddr[descriptor], txbuffer, txsize); |
1840 | a41b2ff2 | pbrook | |
1841 | a41b2ff2 | pbrook | /* Mark descriptor as transferred */
|
1842 | a41b2ff2 | pbrook | s->TxStatus[descriptor] |= TxHostOwns; |
1843 | a41b2ff2 | pbrook | s->TxStatus[descriptor] |= TxStatOK; |
1844 | a41b2ff2 | pbrook | |
1845 | bf6b87a8 | Benjamin Poirier | rtl8139_transfer_frame(s, txbuffer, txsize, 0, NULL); |
1846 | 6cadb320 | bellard | |
1847 | 7cdeb319 | Benjamin Poirier | DPRINTF("+++ transmitted %d bytes from descriptor %d\n", txsize,
|
1848 | 7cdeb319 | Benjamin Poirier | descriptor); |
1849 | a41b2ff2 | pbrook | |
1850 | a41b2ff2 | pbrook | /* update interrupt */
|
1851 | a41b2ff2 | pbrook | s->IntrStatus |= TxOK; |
1852 | a41b2ff2 | pbrook | rtl8139_update_irq(s); |
1853 | a41b2ff2 | pbrook | |
1854 | a41b2ff2 | pbrook | return 1; |
1855 | a41b2ff2 | pbrook | } |
1856 | a41b2ff2 | pbrook | |
1857 | 718da2b9 | bellard | /* structures and macros for task offloading */
|
1858 | 718da2b9 | bellard | typedef struct ip_header |
1859 | 718da2b9 | bellard | { |
1860 | 718da2b9 | bellard | uint8_t ip_ver_len; /* version and header length */
|
1861 | 718da2b9 | bellard | uint8_t ip_tos; /* type of service */
|
1862 | 718da2b9 | bellard | uint16_t ip_len; /* total length */
|
1863 | 718da2b9 | bellard | uint16_t ip_id; /* identification */
|
1864 | 718da2b9 | bellard | uint16_t ip_off; /* fragment offset field */
|
1865 | 718da2b9 | bellard | uint8_t ip_ttl; /* time to live */
|
1866 | 718da2b9 | bellard | uint8_t ip_p; /* protocol */
|
1867 | 718da2b9 | bellard | uint16_t ip_sum; /* checksum */
|
1868 | 718da2b9 | bellard | uint32_t ip_src,ip_dst; /* source and dest address */
|
1869 | 718da2b9 | bellard | } ip_header; |
1870 | 718da2b9 | bellard | |
1871 | 718da2b9 | bellard | #define IP_HEADER_VERSION_4 4 |
1872 | 718da2b9 | bellard | #define IP_HEADER_VERSION(ip) ((ip->ip_ver_len >> 4)&0xf) |
1873 | 718da2b9 | bellard | #define IP_HEADER_LENGTH(ip) (((ip->ip_ver_len)&0xf) << 2) |
1874 | 718da2b9 | bellard | |
1875 | 718da2b9 | bellard | typedef struct tcp_header |
1876 | 718da2b9 | bellard | { |
1877 | 718da2b9 | bellard | uint16_t th_sport; /* source port */
|
1878 | 718da2b9 | bellard | uint16_t th_dport; /* destination port */
|
1879 | 718da2b9 | bellard | uint32_t th_seq; /* sequence number */
|
1880 | 718da2b9 | bellard | uint32_t th_ack; /* acknowledgement number */
|
1881 | 718da2b9 | bellard | uint16_t th_offset_flags; /* data offset, reserved 6 bits, TCP protocol flags */
|
1882 | 718da2b9 | bellard | uint16_t th_win; /* window */
|
1883 | 718da2b9 | bellard | uint16_t th_sum; /* checksum */
|
1884 | 718da2b9 | bellard | uint16_t th_urp; /* urgent pointer */
|
1885 | 718da2b9 | bellard | } tcp_header; |
1886 | 718da2b9 | bellard | |
1887 | 718da2b9 | bellard | typedef struct udp_header |
1888 | 718da2b9 | bellard | { |
1889 | 718da2b9 | bellard | uint16_t uh_sport; /* source port */
|
1890 | 718da2b9 | bellard | uint16_t uh_dport; /* destination port */
|
1891 | 718da2b9 | bellard | uint16_t uh_ulen; /* udp length */
|
1892 | 718da2b9 | bellard | uint16_t uh_sum; /* udp checksum */
|
1893 | 718da2b9 | bellard | } udp_header; |
1894 | 718da2b9 | bellard | |
1895 | 718da2b9 | bellard | typedef struct ip_pseudo_header |
1896 | 718da2b9 | bellard | { |
1897 | 718da2b9 | bellard | uint32_t ip_src; |
1898 | 718da2b9 | bellard | uint32_t ip_dst; |
1899 | 718da2b9 | bellard | uint8_t zeros; |
1900 | 718da2b9 | bellard | uint8_t ip_proto; |
1901 | 718da2b9 | bellard | uint16_t ip_payload; |
1902 | 718da2b9 | bellard | } ip_pseudo_header; |
1903 | 718da2b9 | bellard | |
1904 | 718da2b9 | bellard | #define IP_PROTO_TCP 6 |
1905 | 718da2b9 | bellard | #define IP_PROTO_UDP 17 |
1906 | 718da2b9 | bellard | |
1907 | 718da2b9 | bellard | #define TCP_HEADER_DATA_OFFSET(tcp) (((be16_to_cpu(tcp->th_offset_flags) >> 12)&0xf) << 2) |
1908 | 718da2b9 | bellard | #define TCP_FLAGS_ONLY(flags) ((flags)&0x3f) |
1909 | 718da2b9 | bellard | #define TCP_HEADER_FLAGS(tcp) TCP_FLAGS_ONLY(be16_to_cpu(tcp->th_offset_flags))
|
1910 | 718da2b9 | bellard | |
1911 | 718da2b9 | bellard | #define TCP_HEADER_CLEAR_FLAGS(tcp, off) ((tcp)->th_offset_flags &= cpu_to_be16(~TCP_FLAGS_ONLY(off)))
|
1912 | 718da2b9 | bellard | |
1913 | 718da2b9 | bellard | #define TCP_FLAG_FIN 0x01 |
1914 | 718da2b9 | bellard | #define TCP_FLAG_PUSH 0x08 |
1915 | 718da2b9 | bellard | |
1916 | 718da2b9 | bellard | /* produces ones' complement sum of data */
|
1917 | 718da2b9 | bellard | static uint16_t ones_complement_sum(uint8_t *data, size_t len)
|
1918 | 718da2b9 | bellard | { |
1919 | 718da2b9 | bellard | uint32_t result = 0;
|
1920 | 718da2b9 | bellard | |
1921 | 718da2b9 | bellard | for (; len > 1; data+=2, len-=2) |
1922 | 718da2b9 | bellard | { |
1923 | 718da2b9 | bellard | result += *(uint16_t*)data; |
1924 | 718da2b9 | bellard | } |
1925 | 718da2b9 | bellard | |
1926 | 718da2b9 | bellard | /* add the remainder byte */
|
1927 | 718da2b9 | bellard | if (len)
|
1928 | 718da2b9 | bellard | { |
1929 | 718da2b9 | bellard | uint8_t odd[2] = {*data, 0}; |
1930 | 718da2b9 | bellard | result += *(uint16_t*)odd; |
1931 | 718da2b9 | bellard | } |
1932 | 718da2b9 | bellard | |
1933 | 718da2b9 | bellard | while (result>>16) |
1934 | 718da2b9 | bellard | result = (result & 0xffff) + (result >> 16); |
1935 | 718da2b9 | bellard | |
1936 | 718da2b9 | bellard | return result;
|
1937 | 718da2b9 | bellard | } |
1938 | 718da2b9 | bellard | |
1939 | 718da2b9 | bellard | static uint16_t ip_checksum(void *data, size_t len) |
1940 | 718da2b9 | bellard | { |
1941 | 718da2b9 | bellard | return ~ones_complement_sum((uint8_t*)data, len);
|
1942 | 718da2b9 | bellard | } |
1943 | 718da2b9 | bellard | |
1944 | a41b2ff2 | pbrook | static int rtl8139_cplus_transmit_one(RTL8139State *s) |
1945 | a41b2ff2 | pbrook | { |
1946 | a41b2ff2 | pbrook | if (!rtl8139_transmitter_enabled(s))
|
1947 | a41b2ff2 | pbrook | { |
1948 | 7cdeb319 | Benjamin Poirier | DPRINTF("+++ C+ mode: transmitter disabled\n");
|
1949 | a41b2ff2 | pbrook | return 0; |
1950 | a41b2ff2 | pbrook | } |
1951 | a41b2ff2 | pbrook | |
1952 | a41b2ff2 | pbrook | if (!rtl8139_cp_transmitter_enabled(s))
|
1953 | a41b2ff2 | pbrook | { |
1954 | 7cdeb319 | Benjamin Poirier | DPRINTF("+++ C+ mode: C+ transmitter disabled\n");
|
1955 | a41b2ff2 | pbrook | return 0 ; |
1956 | a41b2ff2 | pbrook | } |
1957 | a41b2ff2 | pbrook | |
1958 | a41b2ff2 | pbrook | int descriptor = s->currCPlusTxDesc;
|
1959 | a41b2ff2 | pbrook | |
1960 | c227f099 | Anthony Liguori | target_phys_addr_t cplus_tx_ring_desc = |
1961 | a41b2ff2 | pbrook | rtl8139_addr64(s->TxAddr[0], s->TxAddr[1]); |
1962 | a41b2ff2 | pbrook | |
1963 | a41b2ff2 | pbrook | /* Normal priority ring */
|
1964 | a41b2ff2 | pbrook | cplus_tx_ring_desc += 16 * descriptor;
|
1965 | a41b2ff2 | pbrook | |
1966 | 7cdeb319 | Benjamin Poirier | DPRINTF("+++ C+ mode reading TX descriptor %d from host memory at "
|
1967 | 7cdeb319 | Benjamin Poirier | "%08x0x%08x = 0x"TARGET_FMT_plx"\n", descriptor, s->TxAddr[1], |
1968 | 7cdeb319 | Benjamin Poirier | s->TxAddr[0], cplus_tx_ring_desc);
|
1969 | a41b2ff2 | pbrook | |
1970 | a41b2ff2 | pbrook | uint32_t val, txdw0,txdw1,txbufLO,txbufHI; |
1971 | a41b2ff2 | pbrook | |
1972 | a41b2ff2 | pbrook | cpu_physical_memory_read(cplus_tx_ring_desc, (uint8_t *)&val, 4);
|
1973 | a41b2ff2 | pbrook | txdw0 = le32_to_cpu(val); |
1974 | a41b2ff2 | pbrook | cpu_physical_memory_read(cplus_tx_ring_desc+4, (uint8_t *)&val, 4); |
1975 | a41b2ff2 | pbrook | txdw1 = le32_to_cpu(val); |
1976 | a41b2ff2 | pbrook | cpu_physical_memory_read(cplus_tx_ring_desc+8, (uint8_t *)&val, 4); |
1977 | a41b2ff2 | pbrook | txbufLO = le32_to_cpu(val); |
1978 | a41b2ff2 | pbrook | cpu_physical_memory_read(cplus_tx_ring_desc+12, (uint8_t *)&val, 4); |
1979 | a41b2ff2 | pbrook | txbufHI = le32_to_cpu(val); |
1980 | a41b2ff2 | pbrook | |
1981 | 7cdeb319 | Benjamin Poirier | DPRINTF("+++ C+ mode TX descriptor %d %08x %08x %08x %08x\n", descriptor,
|
1982 | 7cdeb319 | Benjamin Poirier | txdw0, txdw1, txbufLO, txbufHI); |
1983 | a41b2ff2 | pbrook | |
1984 | a41b2ff2 | pbrook | /* w0 ownership flag */
|
1985 | a41b2ff2 | pbrook | #define CP_TX_OWN (1<<31) |
1986 | a41b2ff2 | pbrook | /* w0 end of ring flag */
|
1987 | a41b2ff2 | pbrook | #define CP_TX_EOR (1<<30) |
1988 | a41b2ff2 | pbrook | /* first segment of received packet flag */
|
1989 | a41b2ff2 | pbrook | #define CP_TX_FS (1<<29) |
1990 | a41b2ff2 | pbrook | /* last segment of received packet flag */
|
1991 | a41b2ff2 | pbrook | #define CP_TX_LS (1<<28) |
1992 | a41b2ff2 | pbrook | /* large send packet flag */
|
1993 | a41b2ff2 | pbrook | #define CP_TX_LGSEN (1<<27) |
1994 | 718da2b9 | bellard | /* large send MSS mask, bits 16...25 */
|
1995 | 718da2b9 | bellard | #define CP_TC_LGSEN_MSS_MASK ((1 << 12) - 1) |
1996 | 718da2b9 | bellard | |
1997 | a41b2ff2 | pbrook | /* IP checksum offload flag */
|
1998 | a41b2ff2 | pbrook | #define CP_TX_IPCS (1<<18) |
1999 | a41b2ff2 | pbrook | /* UDP checksum offload flag */
|
2000 | a41b2ff2 | pbrook | #define CP_TX_UDPCS (1<<17) |
2001 | a41b2ff2 | pbrook | /* TCP checksum offload flag */
|
2002 | a41b2ff2 | pbrook | #define CP_TX_TCPCS (1<<16) |
2003 | a41b2ff2 | pbrook | |
2004 | a41b2ff2 | pbrook | /* w0 bits 0...15 : buffer size */
|
2005 | a41b2ff2 | pbrook | #define CP_TX_BUFFER_SIZE (1<<16) |
2006 | a41b2ff2 | pbrook | #define CP_TX_BUFFER_SIZE_MASK (CP_TX_BUFFER_SIZE - 1) |
2007 | bf6b87a8 | Benjamin Poirier | /* w1 add tag flag */
|
2008 | bf6b87a8 | Benjamin Poirier | #define CP_TX_TAGC (1<<17) |
2009 | bf6b87a8 | Benjamin Poirier | /* w1 bits 0...15 : VLAN tag (big endian) */
|
2010 | a41b2ff2 | pbrook | #define CP_TX_VLAN_TAG_MASK ((1<<16) - 1) |
2011 | a41b2ff2 | pbrook | /* w2 low 32bit of Rx buffer ptr */
|
2012 | a41b2ff2 | pbrook | /* w3 high 32bit of Rx buffer ptr */
|
2013 | a41b2ff2 | pbrook | |
2014 | a41b2ff2 | pbrook | /* set after transmission */
|
2015 | a41b2ff2 | pbrook | /* FIFO underrun flag */
|
2016 | a41b2ff2 | pbrook | #define CP_TX_STATUS_UNF (1<<25) |
2017 | a41b2ff2 | pbrook | /* transmit error summary flag, valid if set any of three below */
|
2018 | a41b2ff2 | pbrook | #define CP_TX_STATUS_TES (1<<23) |
2019 | a41b2ff2 | pbrook | /* out-of-window collision flag */
|
2020 | a41b2ff2 | pbrook | #define CP_TX_STATUS_OWC (1<<22) |
2021 | a41b2ff2 | pbrook | /* link failure flag */
|
2022 | a41b2ff2 | pbrook | #define CP_TX_STATUS_LNKF (1<<21) |
2023 | a41b2ff2 | pbrook | /* excessive collisions flag */
|
2024 | a41b2ff2 | pbrook | #define CP_TX_STATUS_EXC (1<<20) |
2025 | a41b2ff2 | pbrook | |
2026 | a41b2ff2 | pbrook | if (!(txdw0 & CP_TX_OWN))
|
2027 | a41b2ff2 | pbrook | { |
2028 | 7cdeb319 | Benjamin Poirier | DPRINTF("C+ Tx mode : descriptor %d is owned by host\n", descriptor);
|
2029 | a41b2ff2 | pbrook | return 0 ; |
2030 | a41b2ff2 | pbrook | } |
2031 | a41b2ff2 | pbrook | |
2032 | 7cdeb319 | Benjamin Poirier | DPRINTF("+++ C+ Tx mode : transmitting from descriptor %d\n", descriptor);
|
2033 | 6cadb320 | bellard | |
2034 | 6cadb320 | bellard | if (txdw0 & CP_TX_FS)
|
2035 | 6cadb320 | bellard | { |
2036 | 7cdeb319 | Benjamin Poirier | DPRINTF("+++ C+ Tx mode : descriptor %d is first segment "
|
2037 | 7cdeb319 | Benjamin Poirier | "descriptor\n", descriptor);
|
2038 | 6cadb320 | bellard | |
2039 | 6cadb320 | bellard | /* reset internal buffer offset */
|
2040 | 6cadb320 | bellard | s->cplus_txbuffer_offset = 0;
|
2041 | 6cadb320 | bellard | } |
2042 | a41b2ff2 | pbrook | |
2043 | a41b2ff2 | pbrook | int txsize = txdw0 & CP_TX_BUFFER_SIZE_MASK;
|
2044 | c227f099 | Anthony Liguori | target_phys_addr_t tx_addr = rtl8139_addr64(txbufLO, txbufHI); |
2045 | a41b2ff2 | pbrook | |
2046 | 6cadb320 | bellard | /* make sure we have enough space to assemble the packet */
|
2047 | 6cadb320 | bellard | if (!s->cplus_txbuffer)
|
2048 | 6cadb320 | bellard | { |
2049 | 6cadb320 | bellard | s->cplus_txbuffer_len = CP_TX_BUFFER_SIZE; |
2050 | 2bc6f59b | Jean-Christophe DUBOIS | s->cplus_txbuffer = qemu_malloc(s->cplus_txbuffer_len); |
2051 | 6cadb320 | bellard | s->cplus_txbuffer_offset = 0;
|
2052 | 718da2b9 | bellard | |
2053 | 7cdeb319 | Benjamin Poirier | DPRINTF("+++ C+ mode transmission buffer allocated space %d\n",
|
2054 | 7cdeb319 | Benjamin Poirier | s->cplus_txbuffer_len); |
2055 | 6cadb320 | bellard | } |
2056 | 6cadb320 | bellard | |
2057 | 6cadb320 | bellard | while (s->cplus_txbuffer && s->cplus_txbuffer_offset + txsize >= s->cplus_txbuffer_len)
|
2058 | 6cadb320 | bellard | { |
2059 | 6cadb320 | bellard | s->cplus_txbuffer_len += CP_TX_BUFFER_SIZE; |
2060 | 2137b4cc | ths | s->cplus_txbuffer = qemu_realloc(s->cplus_txbuffer, s->cplus_txbuffer_len); |
2061 | a41b2ff2 | pbrook | |
2062 | 7cdeb319 | Benjamin Poirier | DPRINTF("+++ C+ mode transmission buffer space changed to %d\n",
|
2063 | 7cdeb319 | Benjamin Poirier | s->cplus_txbuffer_len); |
2064 | 6cadb320 | bellard | } |
2065 | 6cadb320 | bellard | |
2066 | 6cadb320 | bellard | if (!s->cplus_txbuffer)
|
2067 | 6cadb320 | bellard | { |
2068 | 6cadb320 | bellard | /* out of memory */
|
2069 | a41b2ff2 | pbrook | |
2070 | 7cdeb319 | Benjamin Poirier | DPRINTF("+++ C+ mode transmiter failed to reallocate %d bytes\n",
|
2071 | 7cdeb319 | Benjamin Poirier | s->cplus_txbuffer_len); |
2072 | 6cadb320 | bellard | |
2073 | 6cadb320 | bellard | /* update tally counter */
|
2074 | 6cadb320 | bellard | ++s->tally_counters.TxERR; |
2075 | 6cadb320 | bellard | ++s->tally_counters.TxAbt; |
2076 | 6cadb320 | bellard | |
2077 | 6cadb320 | bellard | return 0; |
2078 | 6cadb320 | bellard | } |
2079 | 6cadb320 | bellard | |
2080 | 6cadb320 | bellard | /* append more data to the packet */
|
2081 | 6cadb320 | bellard | |
2082 | 7cdeb319 | Benjamin Poirier | DPRINTF("+++ C+ mode transmit reading %d bytes from host memory at "
|
2083 | 7cdeb319 | Benjamin Poirier | TARGET_FMT_plx" to offset %d\n", txsize, tx_addr,
|
2084 | 7cdeb319 | Benjamin Poirier | s->cplus_txbuffer_offset); |
2085 | 6cadb320 | bellard | |
2086 | 6cadb320 | bellard | cpu_physical_memory_read(tx_addr, s->cplus_txbuffer + s->cplus_txbuffer_offset, txsize); |
2087 | 6cadb320 | bellard | s->cplus_txbuffer_offset += txsize; |
2088 | 6cadb320 | bellard | |
2089 | 6cadb320 | bellard | /* seek to next Rx descriptor */
|
2090 | 6cadb320 | bellard | if (txdw0 & CP_TX_EOR)
|
2091 | 6cadb320 | bellard | { |
2092 | 6cadb320 | bellard | s->currCPlusTxDesc = 0;
|
2093 | 6cadb320 | bellard | } |
2094 | 6cadb320 | bellard | else
|
2095 | 6cadb320 | bellard | { |
2096 | 6cadb320 | bellard | ++s->currCPlusTxDesc; |
2097 | 6cadb320 | bellard | if (s->currCPlusTxDesc >= 64) |
2098 | 6cadb320 | bellard | s->currCPlusTxDesc = 0;
|
2099 | 6cadb320 | bellard | } |
2100 | a41b2ff2 | pbrook | |
2101 | a41b2ff2 | pbrook | /* transfer ownership to target */
|
2102 | a41b2ff2 | pbrook | txdw0 &= ~CP_RX_OWN; |
2103 | a41b2ff2 | pbrook | |
2104 | a41b2ff2 | pbrook | /* reset error indicator bits */
|
2105 | a41b2ff2 | pbrook | txdw0 &= ~CP_TX_STATUS_UNF; |
2106 | a41b2ff2 | pbrook | txdw0 &= ~CP_TX_STATUS_TES; |
2107 | a41b2ff2 | pbrook | txdw0 &= ~CP_TX_STATUS_OWC; |
2108 | a41b2ff2 | pbrook | txdw0 &= ~CP_TX_STATUS_LNKF; |
2109 | a41b2ff2 | pbrook | txdw0 &= ~CP_TX_STATUS_EXC; |
2110 | a41b2ff2 | pbrook | |
2111 | a41b2ff2 | pbrook | /* update ring data */
|
2112 | a41b2ff2 | pbrook | val = cpu_to_le32(txdw0); |
2113 | a41b2ff2 | pbrook | cpu_physical_memory_write(cplus_tx_ring_desc, (uint8_t *)&val, 4);
|
2114 | a41b2ff2 | pbrook | |
2115 | 6cadb320 | bellard | /* Now decide if descriptor being processed is holding the last segment of packet */
|
2116 | 6cadb320 | bellard | if (txdw0 & CP_TX_LS)
|
2117 | a41b2ff2 | pbrook | { |
2118 | bf6b87a8 | Benjamin Poirier | uint8_t dot1q_buffer_space[VLAN_HLEN]; |
2119 | bf6b87a8 | Benjamin Poirier | uint16_t *dot1q_buffer; |
2120 | bf6b87a8 | Benjamin Poirier | |
2121 | 7cdeb319 | Benjamin Poirier | DPRINTF("+++ C+ Tx mode : descriptor %d is last segment descriptor\n",
|
2122 | 7cdeb319 | Benjamin Poirier | descriptor); |
2123 | 6cadb320 | bellard | |
2124 | 6cadb320 | bellard | /* can transfer fully assembled packet */
|
2125 | 6cadb320 | bellard | |
2126 | 6cadb320 | bellard | uint8_t *saved_buffer = s->cplus_txbuffer; |
2127 | 6cadb320 | bellard | int saved_size = s->cplus_txbuffer_offset;
|
2128 | 6cadb320 | bellard | int saved_buffer_len = s->cplus_txbuffer_len;
|
2129 | 6cadb320 | bellard | |
2130 | bf6b87a8 | Benjamin Poirier | /* create vlan tag */
|
2131 | bf6b87a8 | Benjamin Poirier | if (txdw1 & CP_TX_TAGC) {
|
2132 | bf6b87a8 | Benjamin Poirier | /* the vlan tag is in BE byte order in the descriptor
|
2133 | bf6b87a8 | Benjamin Poirier | * BE + le_to_cpu() + ~swap()~ = cpu */
|
2134 | 7cdeb319 | Benjamin Poirier | DPRINTF("+++ C+ Tx mode : inserting vlan tag with ""tci: %u\n", |
2135 | 7cdeb319 | Benjamin Poirier | bswap16(txdw1 & CP_TX_VLAN_TAG_MASK)); |
2136 | bf6b87a8 | Benjamin Poirier | |
2137 | bf6b87a8 | Benjamin Poirier | dot1q_buffer = (uint16_t *) dot1q_buffer_space; |
2138 | bf6b87a8 | Benjamin Poirier | dot1q_buffer[0] = cpu_to_be16(ETH_P_8021Q);
|
2139 | bf6b87a8 | Benjamin Poirier | /* BE + le_to_cpu() + ~cpu_to_le()~ = BE */
|
2140 | bf6b87a8 | Benjamin Poirier | dot1q_buffer[1] = cpu_to_le16(txdw1 & CP_TX_VLAN_TAG_MASK);
|
2141 | bf6b87a8 | Benjamin Poirier | } else {
|
2142 | bf6b87a8 | Benjamin Poirier | dot1q_buffer = NULL;
|
2143 | bf6b87a8 | Benjamin Poirier | } |
2144 | bf6b87a8 | Benjamin Poirier | |
2145 | 6cadb320 | bellard | /* reset the card space to protect from recursive call */
|
2146 | 6cadb320 | bellard | s->cplus_txbuffer = NULL;
|
2147 | 6cadb320 | bellard | s->cplus_txbuffer_offset = 0;
|
2148 | 6cadb320 | bellard | s->cplus_txbuffer_len = 0;
|
2149 | 6cadb320 | bellard | |
2150 | 718da2b9 | bellard | if (txdw0 & (CP_TX_IPCS | CP_TX_UDPCS | CP_TX_TCPCS | CP_TX_LGSEN))
|
2151 | 6cadb320 | bellard | { |
2152 | 7cdeb319 | Benjamin Poirier | DPRINTF("+++ C+ mode offloaded task checksum\n");
|
2153 | 6cadb320 | bellard | |
2154 | 6cadb320 | bellard | /* ip packet header */
|
2155 | 660f11be | Blue Swirl | ip_header *ip = NULL;
|
2156 | 6cadb320 | bellard | int hlen = 0; |
2157 | 718da2b9 | bellard | uint8_t ip_protocol = 0;
|
2158 | 718da2b9 | bellard | uint16_t ip_data_len = 0;
|
2159 | 6cadb320 | bellard | |
2160 | 660f11be | Blue Swirl | uint8_t *eth_payload_data = NULL;
|
2161 | 718da2b9 | bellard | size_t eth_payload_len = 0;
|
2162 | 6cadb320 | bellard | |
2163 | 718da2b9 | bellard | int proto = be16_to_cpu(*(uint16_t *)(saved_buffer + 12)); |
2164 | 6cadb320 | bellard | if (proto == ETH_P_IP)
|
2165 | 6cadb320 | bellard | { |
2166 | 7cdeb319 | Benjamin Poirier | DPRINTF("+++ C+ mode has IP packet\n");
|
2167 | 6cadb320 | bellard | |
2168 | 6cadb320 | bellard | /* not aligned */
|
2169 | 718da2b9 | bellard | eth_payload_data = saved_buffer + ETH_HLEN; |
2170 | 718da2b9 | bellard | eth_payload_len = saved_size - ETH_HLEN; |
2171 | 6cadb320 | bellard | |
2172 | 718da2b9 | bellard | ip = (ip_header*)eth_payload_data; |
2173 | 6cadb320 | bellard | |
2174 | 718da2b9 | bellard | if (IP_HEADER_VERSION(ip) != IP_HEADER_VERSION_4) {
|
2175 | 7cdeb319 | Benjamin Poirier | DPRINTF("+++ C+ mode packet has bad IP version %d "
|
2176 | 7cdeb319 | Benjamin Poirier | "expected %d\n", IP_HEADER_VERSION(ip),
|
2177 | 7cdeb319 | Benjamin Poirier | IP_HEADER_VERSION_4); |
2178 | 6cadb320 | bellard | ip = NULL;
|
2179 | 6cadb320 | bellard | } else {
|
2180 | 718da2b9 | bellard | hlen = IP_HEADER_LENGTH(ip); |
2181 | 718da2b9 | bellard | ip_protocol = ip->ip_p; |
2182 | 718da2b9 | bellard | ip_data_len = be16_to_cpu(ip->ip_len) - hlen; |
2183 | 6cadb320 | bellard | } |
2184 | 6cadb320 | bellard | } |
2185 | 6cadb320 | bellard | |
2186 | 6cadb320 | bellard | if (ip)
|
2187 | 6cadb320 | bellard | { |
2188 | 6cadb320 | bellard | if (txdw0 & CP_TX_IPCS)
|
2189 | 6cadb320 | bellard | { |
2190 | 7cdeb319 | Benjamin Poirier | DPRINTF("+++ C+ mode need IP checksum\n");
|
2191 | 6cadb320 | bellard | |
2192 | 718da2b9 | bellard | if (hlen<sizeof(ip_header) || hlen>eth_payload_len) {/* min header length */ |
2193 | 6cadb320 | bellard | /* bad packet header len */
|
2194 | 6cadb320 | bellard | /* or packet too short */
|
2195 | 6cadb320 | bellard | } |
2196 | 6cadb320 | bellard | else
|
2197 | 6cadb320 | bellard | { |
2198 | 6cadb320 | bellard | ip->ip_sum = 0;
|
2199 | 718da2b9 | bellard | ip->ip_sum = ip_checksum(ip, hlen); |
2200 | 7cdeb319 | Benjamin Poirier | DPRINTF("+++ C+ mode IP header len=%d checksum=%04x\n",
|
2201 | 7cdeb319 | Benjamin Poirier | hlen, ip->ip_sum); |
2202 | 6cadb320 | bellard | } |
2203 | 6cadb320 | bellard | } |
2204 | 6cadb320 | bellard | |
2205 | 718da2b9 | bellard | if ((txdw0 & CP_TX_LGSEN) && ip_protocol == IP_PROTO_TCP)
|
2206 | 6cadb320 | bellard | { |
2207 | 718da2b9 | bellard | int large_send_mss = (txdw0 >> 16) & CP_TC_LGSEN_MSS_MASK; |
2208 | ec48c774 | Benjamin Poirier | |
2209 | 7cdeb319 | Benjamin Poirier | DPRINTF("+++ C+ mode offloaded task TSO MTU=%d IP data %d "
|
2210 | 7cdeb319 | Benjamin Poirier | "frame data %d specified MSS=%d\n", ETH_MTU,
|
2211 | 7cdeb319 | Benjamin Poirier | ip_data_len, saved_size - ETH_HLEN, large_send_mss); |
2212 | 6cadb320 | bellard | |
2213 | 718da2b9 | bellard | int tcp_send_offset = 0; |
2214 | 718da2b9 | bellard | int send_count = 0; |
2215 | 6cadb320 | bellard | |
2216 | 6cadb320 | bellard | /* maximum IP header length is 60 bytes */
|
2217 | 6cadb320 | bellard | uint8_t saved_ip_header[60];
|
2218 | 6cadb320 | bellard | |
2219 | 718da2b9 | bellard | /* save IP header template; data area is used in tcp checksum calculation */
|
2220 | 718da2b9 | bellard | memcpy(saved_ip_header, eth_payload_data, hlen); |
2221 | 718da2b9 | bellard | |
2222 | 718da2b9 | bellard | /* a placeholder for checksum calculation routine in tcp case */
|
2223 | 718da2b9 | bellard | uint8_t *data_to_checksum = eth_payload_data + hlen - 12;
|
2224 | 718da2b9 | bellard | // size_t data_to_checksum_len = eth_payload_len - hlen + 12;
|
2225 | 718da2b9 | bellard | |
2226 | 718da2b9 | bellard | /* pointer to TCP header */
|
2227 | 718da2b9 | bellard | tcp_header *p_tcp_hdr = (tcp_header*)(eth_payload_data + hlen); |
2228 | 718da2b9 | bellard | |
2229 | 718da2b9 | bellard | int tcp_hlen = TCP_HEADER_DATA_OFFSET(p_tcp_hdr);
|
2230 | 718da2b9 | bellard | |
2231 | 718da2b9 | bellard | /* ETH_MTU = ip header len + tcp header len + payload */
|
2232 | 718da2b9 | bellard | int tcp_data_len = ip_data_len - tcp_hlen;
|
2233 | 718da2b9 | bellard | int tcp_chunk_size = ETH_MTU - hlen - tcp_hlen;
|
2234 | 718da2b9 | bellard | |
2235 | 7cdeb319 | Benjamin Poirier | DPRINTF("+++ C+ mode TSO IP data len %d TCP hlen %d TCP "
|
2236 | 7cdeb319 | Benjamin Poirier | "data len %d TCP chunk size %d\n", ip_data_len,
|
2237 | 7cdeb319 | Benjamin Poirier | tcp_hlen, tcp_data_len, tcp_chunk_size); |
2238 | 718da2b9 | bellard | |
2239 | 718da2b9 | bellard | /* note the cycle below overwrites IP header data,
|
2240 | 718da2b9 | bellard | but restores it from saved_ip_header before sending packet */
|
2241 | 718da2b9 | bellard | |
2242 | 718da2b9 | bellard | int is_last_frame = 0; |
2243 | 718da2b9 | bellard | |
2244 | 718da2b9 | bellard | for (tcp_send_offset = 0; tcp_send_offset < tcp_data_len; tcp_send_offset += tcp_chunk_size) |
2245 | 718da2b9 | bellard | { |
2246 | 718da2b9 | bellard | uint16_t chunk_size = tcp_chunk_size; |
2247 | 718da2b9 | bellard | |
2248 | 718da2b9 | bellard | /* check if this is the last frame */
|
2249 | 718da2b9 | bellard | if (tcp_send_offset + tcp_chunk_size >= tcp_data_len)
|
2250 | 718da2b9 | bellard | { |
2251 | 718da2b9 | bellard | is_last_frame = 1;
|
2252 | 718da2b9 | bellard | chunk_size = tcp_data_len - tcp_send_offset; |
2253 | 718da2b9 | bellard | } |
2254 | 718da2b9 | bellard | |
2255 | 7cdeb319 | Benjamin Poirier | DPRINTF("+++ C+ mode TSO TCP seqno %08x\n",
|
2256 | 7cdeb319 | Benjamin Poirier | be32_to_cpu(p_tcp_hdr->th_seq)); |
2257 | 718da2b9 | bellard | |
2258 | 718da2b9 | bellard | /* add 4 TCP pseudoheader fields */
|
2259 | 718da2b9 | bellard | /* copy IP source and destination fields */
|
2260 | 718da2b9 | bellard | memcpy(data_to_checksum, saved_ip_header + 12, 8); |
2261 | 718da2b9 | bellard | |
2262 | 7cdeb319 | Benjamin Poirier | DPRINTF("+++ C+ mode TSO calculating TCP checksum for "
|
2263 | 7cdeb319 | Benjamin Poirier | "packet with %d bytes data\n", tcp_hlen +
|
2264 | 7cdeb319 | Benjamin Poirier | chunk_size); |
2265 | 718da2b9 | bellard | |
2266 | 718da2b9 | bellard | if (tcp_send_offset)
|
2267 | 718da2b9 | bellard | { |
2268 | 718da2b9 | bellard | memcpy((uint8_t*)p_tcp_hdr + tcp_hlen, (uint8_t*)p_tcp_hdr + tcp_hlen + tcp_send_offset, chunk_size); |
2269 | 718da2b9 | bellard | } |
2270 | 718da2b9 | bellard | |
2271 | 718da2b9 | bellard | /* keep PUSH and FIN flags only for the last frame */
|
2272 | 718da2b9 | bellard | if (!is_last_frame)
|
2273 | 718da2b9 | bellard | { |
2274 | 718da2b9 | bellard | TCP_HEADER_CLEAR_FLAGS(p_tcp_hdr, TCP_FLAG_PUSH|TCP_FLAG_FIN); |
2275 | 718da2b9 | bellard | } |
2276 | 6cadb320 | bellard | |
2277 | 718da2b9 | bellard | /* recalculate TCP checksum */
|
2278 | 718da2b9 | bellard | ip_pseudo_header *p_tcpip_hdr = (ip_pseudo_header *)data_to_checksum; |
2279 | 718da2b9 | bellard | p_tcpip_hdr->zeros = 0;
|
2280 | 718da2b9 | bellard | p_tcpip_hdr->ip_proto = IP_PROTO_TCP; |
2281 | 718da2b9 | bellard | p_tcpip_hdr->ip_payload = cpu_to_be16(tcp_hlen + chunk_size); |
2282 | 718da2b9 | bellard | |
2283 | 718da2b9 | bellard | p_tcp_hdr->th_sum = 0;
|
2284 | 718da2b9 | bellard | |
2285 | 718da2b9 | bellard | int tcp_checksum = ip_checksum(data_to_checksum, tcp_hlen + chunk_size + 12); |
2286 | 7cdeb319 | Benjamin Poirier | DPRINTF("+++ C+ mode TSO TCP checksum %04x\n",
|
2287 | 7cdeb319 | Benjamin Poirier | tcp_checksum); |
2288 | 718da2b9 | bellard | |
2289 | 718da2b9 | bellard | p_tcp_hdr->th_sum = tcp_checksum; |
2290 | 718da2b9 | bellard | |
2291 | 718da2b9 | bellard | /* restore IP header */
|
2292 | 718da2b9 | bellard | memcpy(eth_payload_data, saved_ip_header, hlen); |
2293 | 718da2b9 | bellard | |
2294 | 718da2b9 | bellard | /* set IP data length and recalculate IP checksum */
|
2295 | 718da2b9 | bellard | ip->ip_len = cpu_to_be16(hlen + tcp_hlen + chunk_size); |
2296 | 718da2b9 | bellard | |
2297 | 718da2b9 | bellard | /* increment IP id for subsequent frames */
|
2298 | 718da2b9 | bellard | ip->ip_id = cpu_to_be16(tcp_send_offset/tcp_chunk_size + be16_to_cpu(ip->ip_id)); |
2299 | 718da2b9 | bellard | |
2300 | 718da2b9 | bellard | ip->ip_sum = 0;
|
2301 | 718da2b9 | bellard | ip->ip_sum = ip_checksum(eth_payload_data, hlen); |
2302 | 7cdeb319 | Benjamin Poirier | DPRINTF("+++ C+ mode TSO IP header len=%d "
|
2303 | 7cdeb319 | Benjamin Poirier | "checksum=%04x\n", hlen, ip->ip_sum);
|
2304 | 718da2b9 | bellard | |
2305 | 718da2b9 | bellard | int tso_send_size = ETH_HLEN + hlen + tcp_hlen + chunk_size;
|
2306 | 7cdeb319 | Benjamin Poirier | DPRINTF("+++ C+ mode TSO transferring packet size "
|
2307 | 7cdeb319 | Benjamin Poirier | "%d\n", tso_send_size);
|
2308 | bf6b87a8 | Benjamin Poirier | rtl8139_transfer_frame(s, saved_buffer, tso_send_size, |
2309 | bf6b87a8 | Benjamin Poirier | 0, (uint8_t *) dot1q_buffer);
|
2310 | 718da2b9 | bellard | |
2311 | 718da2b9 | bellard | /* add transferred count to TCP sequence number */
|
2312 | 718da2b9 | bellard | p_tcp_hdr->th_seq = cpu_to_be32(chunk_size + be32_to_cpu(p_tcp_hdr->th_seq)); |
2313 | 718da2b9 | bellard | ++send_count; |
2314 | 718da2b9 | bellard | } |
2315 | 718da2b9 | bellard | |
2316 | 718da2b9 | bellard | /* Stop sending this frame */
|
2317 | 718da2b9 | bellard | saved_size = 0;
|
2318 | 718da2b9 | bellard | } |
2319 | 718da2b9 | bellard | else if (txdw0 & (CP_TX_TCPCS|CP_TX_UDPCS)) |
2320 | 718da2b9 | bellard | { |
2321 | 7cdeb319 | Benjamin Poirier | DPRINTF("+++ C+ mode need TCP or UDP checksum\n");
|
2322 | 718da2b9 | bellard | |
2323 | 718da2b9 | bellard | /* maximum IP header length is 60 bytes */
|
2324 | 718da2b9 | bellard | uint8_t saved_ip_header[60];
|
2325 | 718da2b9 | bellard | memcpy(saved_ip_header, eth_payload_data, hlen); |
2326 | 718da2b9 | bellard | |
2327 | 718da2b9 | bellard | uint8_t *data_to_checksum = eth_payload_data + hlen - 12;
|
2328 | 718da2b9 | bellard | // size_t data_to_checksum_len = eth_payload_len - hlen + 12;
|
2329 | 6cadb320 | bellard | |
2330 | 6cadb320 | bellard | /* add 4 TCP pseudoheader fields */
|
2331 | 6cadb320 | bellard | /* copy IP source and destination fields */
|
2332 | 718da2b9 | bellard | memcpy(data_to_checksum, saved_ip_header + 12, 8); |
2333 | 6cadb320 | bellard | |
2334 | 718da2b9 | bellard | if ((txdw0 & CP_TX_TCPCS) && ip_protocol == IP_PROTO_TCP)
|
2335 | 6cadb320 | bellard | { |
2336 | 7cdeb319 | Benjamin Poirier | DPRINTF("+++ C+ mode calculating TCP checksum for "
|
2337 | 7cdeb319 | Benjamin Poirier | "packet with %d bytes data\n", ip_data_len);
|
2338 | 6cadb320 | bellard | |
2339 | 718da2b9 | bellard | ip_pseudo_header *p_tcpip_hdr = (ip_pseudo_header *)data_to_checksum; |
2340 | 718da2b9 | bellard | p_tcpip_hdr->zeros = 0;
|
2341 | 718da2b9 | bellard | p_tcpip_hdr->ip_proto = IP_PROTO_TCP; |
2342 | 718da2b9 | bellard | p_tcpip_hdr->ip_payload = cpu_to_be16(ip_data_len); |
2343 | 6cadb320 | bellard | |
2344 | 718da2b9 | bellard | tcp_header* p_tcp_hdr = (tcp_header *) (data_to_checksum+12);
|
2345 | 6cadb320 | bellard | |
2346 | 6cadb320 | bellard | p_tcp_hdr->th_sum = 0;
|
2347 | 6cadb320 | bellard | |
2348 | 718da2b9 | bellard | int tcp_checksum = ip_checksum(data_to_checksum, ip_data_len + 12); |
2349 | 7cdeb319 | Benjamin Poirier | DPRINTF("+++ C+ mode TCP checksum %04x\n",
|
2350 | 7cdeb319 | Benjamin Poirier | tcp_checksum); |
2351 | 6cadb320 | bellard | |
2352 | 6cadb320 | bellard | p_tcp_hdr->th_sum = tcp_checksum; |
2353 | 6cadb320 | bellard | } |
2354 | 718da2b9 | bellard | else if ((txdw0 & CP_TX_UDPCS) && ip_protocol == IP_PROTO_UDP) |
2355 | 6cadb320 | bellard | { |
2356 | 7cdeb319 | Benjamin Poirier | DPRINTF("+++ C+ mode calculating UDP checksum for "
|
2357 | 7cdeb319 | Benjamin Poirier | "packet with %d bytes data\n", ip_data_len);
|
2358 | 6cadb320 | bellard | |
2359 | 718da2b9 | bellard | ip_pseudo_header *p_udpip_hdr = (ip_pseudo_header *)data_to_checksum; |
2360 | 718da2b9 | bellard | p_udpip_hdr->zeros = 0;
|
2361 | 718da2b9 | bellard | p_udpip_hdr->ip_proto = IP_PROTO_UDP; |
2362 | 718da2b9 | bellard | p_udpip_hdr->ip_payload = cpu_to_be16(ip_data_len); |
2363 | 6cadb320 | bellard | |
2364 | 718da2b9 | bellard | udp_header *p_udp_hdr = (udp_header *) (data_to_checksum+12);
|
2365 | 6cadb320 | bellard | |
2366 | 6cadb320 | bellard | p_udp_hdr->uh_sum = 0;
|
2367 | 6cadb320 | bellard | |
2368 | 718da2b9 | bellard | int udp_checksum = ip_checksum(data_to_checksum, ip_data_len + 12); |
2369 | 7cdeb319 | Benjamin Poirier | DPRINTF("+++ C+ mode UDP checksum %04x\n",
|
2370 | 7cdeb319 | Benjamin Poirier | udp_checksum); |
2371 | 6cadb320 | bellard | |
2372 | 6cadb320 | bellard | p_udp_hdr->uh_sum = udp_checksum; |
2373 | 6cadb320 | bellard | } |
2374 | 6cadb320 | bellard | |
2375 | 6cadb320 | bellard | /* restore IP header */
|
2376 | 718da2b9 | bellard | memcpy(eth_payload_data, saved_ip_header, hlen); |
2377 | 6cadb320 | bellard | } |
2378 | 6cadb320 | bellard | } |
2379 | 6cadb320 | bellard | } |
2380 | 6cadb320 | bellard | |
2381 | 6cadb320 | bellard | /* update tally counter */
|
2382 | 6cadb320 | bellard | ++s->tally_counters.TxOk; |
2383 | 6cadb320 | bellard | |
2384 | 7cdeb319 | Benjamin Poirier | DPRINTF("+++ C+ mode transmitting %d bytes packet\n", saved_size);
|
2385 | 6cadb320 | bellard | |
2386 | bf6b87a8 | Benjamin Poirier | rtl8139_transfer_frame(s, saved_buffer, saved_size, 1,
|
2387 | bf6b87a8 | Benjamin Poirier | (uint8_t *) dot1q_buffer); |
2388 | 6cadb320 | bellard | |
2389 | 6cadb320 | bellard | /* restore card space if there was no recursion and reset offset */
|
2390 | 6cadb320 | bellard | if (!s->cplus_txbuffer)
|
2391 | 6cadb320 | bellard | { |
2392 | 6cadb320 | bellard | s->cplus_txbuffer = saved_buffer; |
2393 | 6cadb320 | bellard | s->cplus_txbuffer_len = saved_buffer_len; |
2394 | 6cadb320 | bellard | s->cplus_txbuffer_offset = 0;
|
2395 | 6cadb320 | bellard | } |
2396 | 6cadb320 | bellard | else
|
2397 | 6cadb320 | bellard | { |
2398 | 2bc6f59b | Jean-Christophe DUBOIS | qemu_free(saved_buffer); |
2399 | 6cadb320 | bellard | } |
2400 | a41b2ff2 | pbrook | } |
2401 | a41b2ff2 | pbrook | else
|
2402 | a41b2ff2 | pbrook | { |
2403 | 7cdeb319 | Benjamin Poirier | DPRINTF("+++ C+ mode transmission continue to next descriptor\n");
|
2404 | a41b2ff2 | pbrook | } |
2405 | a41b2ff2 | pbrook | |
2406 | a41b2ff2 | pbrook | return 1; |
2407 | a41b2ff2 | pbrook | } |
2408 | a41b2ff2 | pbrook | |
2409 | a41b2ff2 | pbrook | static void rtl8139_cplus_transmit(RTL8139State *s) |
2410 | a41b2ff2 | pbrook | { |
2411 | a41b2ff2 | pbrook | int txcount = 0; |
2412 | a41b2ff2 | pbrook | |
2413 | a41b2ff2 | pbrook | while (rtl8139_cplus_transmit_one(s))
|
2414 | a41b2ff2 | pbrook | { |
2415 | a41b2ff2 | pbrook | ++txcount; |
2416 | a41b2ff2 | pbrook | } |
2417 | a41b2ff2 | pbrook | |
2418 | a41b2ff2 | pbrook | /* Mark transfer completed */
|
2419 | a41b2ff2 | pbrook | if (!txcount)
|
2420 | a41b2ff2 | pbrook | { |
2421 | 7cdeb319 | Benjamin Poirier | DPRINTF("C+ mode : transmitter queue stalled, current TxDesc = %d\n",
|
2422 | 7cdeb319 | Benjamin Poirier | s->currCPlusTxDesc); |
2423 | a41b2ff2 | pbrook | } |
2424 | a41b2ff2 | pbrook | else
|
2425 | a41b2ff2 | pbrook | { |
2426 | a41b2ff2 | pbrook | /* update interrupt status */
|
2427 | a41b2ff2 | pbrook | s->IntrStatus |= TxOK; |
2428 | a41b2ff2 | pbrook | rtl8139_update_irq(s); |
2429 | a41b2ff2 | pbrook | } |
2430 | a41b2ff2 | pbrook | } |
2431 | a41b2ff2 | pbrook | |
2432 | a41b2ff2 | pbrook | static void rtl8139_transmit(RTL8139State *s) |
2433 | a41b2ff2 | pbrook | { |
2434 | a41b2ff2 | pbrook | int descriptor = s->currTxDesc, txcount = 0; |
2435 | a41b2ff2 | pbrook | |
2436 | a41b2ff2 | pbrook | /*while*/
|
2437 | a41b2ff2 | pbrook | if (rtl8139_transmit_one(s, descriptor))
|
2438 | a41b2ff2 | pbrook | { |
2439 | a41b2ff2 | pbrook | ++s->currTxDesc; |
2440 | a41b2ff2 | pbrook | s->currTxDesc %= 4;
|
2441 | a41b2ff2 | pbrook | ++txcount; |
2442 | a41b2ff2 | pbrook | } |
2443 | a41b2ff2 | pbrook | |
2444 | a41b2ff2 | pbrook | /* Mark transfer completed */
|
2445 | a41b2ff2 | pbrook | if (!txcount)
|
2446 | a41b2ff2 | pbrook | { |
2447 | 7cdeb319 | Benjamin Poirier | DPRINTF("transmitter queue stalled, current TxDesc = %d\n",
|
2448 | 7cdeb319 | Benjamin Poirier | s->currTxDesc); |
2449 | a41b2ff2 | pbrook | } |
2450 | a41b2ff2 | pbrook | } |
2451 | a41b2ff2 | pbrook | |
2452 | a41b2ff2 | pbrook | static void rtl8139_TxStatus_write(RTL8139State *s, uint32_t txRegOffset, uint32_t val) |
2453 | a41b2ff2 | pbrook | { |
2454 | a41b2ff2 | pbrook | |
2455 | a41b2ff2 | pbrook | int descriptor = txRegOffset/4; |
2456 | 6cadb320 | bellard | |
2457 | 6cadb320 | bellard | /* handle C+ transmit mode register configuration */
|
2458 | 6cadb320 | bellard | |
2459 | 2c3891ab | aliguori | if (s->cplus_enabled)
|
2460 | 6cadb320 | bellard | { |
2461 | 7cdeb319 | Benjamin Poirier | DPRINTF("RTL8139C+ DTCCR write offset=0x%x val=0x%08x "
|
2462 | 7cdeb319 | Benjamin Poirier | "descriptor=%d\n", txRegOffset, val, descriptor);
|
2463 | 6cadb320 | bellard | |
2464 | 6cadb320 | bellard | /* handle Dump Tally Counters command */
|
2465 | 6cadb320 | bellard | s->TxStatus[descriptor] = val; |
2466 | 6cadb320 | bellard | |
2467 | 6cadb320 | bellard | if (descriptor == 0 && (val & 0x8)) |
2468 | 6cadb320 | bellard | { |
2469 | c227f099 | Anthony Liguori | target_phys_addr_t tc_addr = rtl8139_addr64(s->TxStatus[0] & ~0x3f, s->TxStatus[1]); |
2470 | 6cadb320 | bellard | |
2471 | 6cadb320 | bellard | /* dump tally counters to specified memory location */
|
2472 | 6cadb320 | bellard | RTL8139TallyCounters_physical_memory_write( tc_addr, &s->tally_counters); |
2473 | 6cadb320 | bellard | |
2474 | 6cadb320 | bellard | /* mark dump completed */
|
2475 | 6cadb320 | bellard | s->TxStatus[0] &= ~0x8; |
2476 | 6cadb320 | bellard | } |
2477 | 6cadb320 | bellard | |
2478 | 6cadb320 | bellard | return;
|
2479 | 6cadb320 | bellard | } |
2480 | 6cadb320 | bellard | |
2481 | 7cdeb319 | Benjamin Poirier | DPRINTF("TxStatus write offset=0x%x val=0x%08x descriptor=%d\n",
|
2482 | 7cdeb319 | Benjamin Poirier | txRegOffset, val, descriptor); |
2483 | a41b2ff2 | pbrook | |
2484 | a41b2ff2 | pbrook | /* mask only reserved bits */
|
2485 | a41b2ff2 | pbrook | val &= ~0xff00c000; /* these bits are reset on write */ |
2486 | a41b2ff2 | pbrook | val = SET_MASKED(val, 0x00c00000, s->TxStatus[descriptor]);
|
2487 | a41b2ff2 | pbrook | |
2488 | a41b2ff2 | pbrook | s->TxStatus[descriptor] = val; |
2489 | a41b2ff2 | pbrook | |
2490 | a41b2ff2 | pbrook | /* attempt to start transmission */
|
2491 | a41b2ff2 | pbrook | rtl8139_transmit(s); |
2492 | a41b2ff2 | pbrook | } |
2493 | a41b2ff2 | pbrook | |
2494 | a41b2ff2 | pbrook | static uint32_t rtl8139_TxStatus_read(RTL8139State *s, uint32_t txRegOffset)
|
2495 | a41b2ff2 | pbrook | { |
2496 | a41b2ff2 | pbrook | uint32_t ret = s->TxStatus[txRegOffset/4];
|
2497 | a41b2ff2 | pbrook | |
2498 | 7cdeb319 | Benjamin Poirier | DPRINTF("TxStatus read offset=0x%x val=0x%08x\n", txRegOffset, ret);
|
2499 | a41b2ff2 | pbrook | |
2500 | a41b2ff2 | pbrook | return ret;
|
2501 | a41b2ff2 | pbrook | } |
2502 | a41b2ff2 | pbrook | |
2503 | a41b2ff2 | pbrook | static uint16_t rtl8139_TSAD_read(RTL8139State *s)
|
2504 | a41b2ff2 | pbrook | { |
2505 | a41b2ff2 | pbrook | uint16_t ret = 0;
|
2506 | a41b2ff2 | pbrook | |
2507 | a41b2ff2 | pbrook | /* Simulate TSAD, it is read only anyway */
|
2508 | a41b2ff2 | pbrook | |
2509 | a41b2ff2 | pbrook | ret = ((s->TxStatus[3] & TxStatOK )?TSAD_TOK3:0) |
2510 | a41b2ff2 | pbrook | |((s->TxStatus[2] & TxStatOK )?TSAD_TOK2:0) |
2511 | a41b2ff2 | pbrook | |((s->TxStatus[1] & TxStatOK )?TSAD_TOK1:0) |
2512 | a41b2ff2 | pbrook | |((s->TxStatus[0] & TxStatOK )?TSAD_TOK0:0) |
2513 | a41b2ff2 | pbrook | |
2514 | a41b2ff2 | pbrook | |((s->TxStatus[3] & TxUnderrun)?TSAD_TUN3:0) |
2515 | a41b2ff2 | pbrook | |((s->TxStatus[2] & TxUnderrun)?TSAD_TUN2:0) |
2516 | a41b2ff2 | pbrook | |((s->TxStatus[1] & TxUnderrun)?TSAD_TUN1:0) |
2517 | a41b2ff2 | pbrook | |((s->TxStatus[0] & TxUnderrun)?TSAD_TUN0:0) |
2518 | 3b46e624 | ths | |
2519 | a41b2ff2 | pbrook | |((s->TxStatus[3] & TxAborted )?TSAD_TABT3:0) |
2520 | a41b2ff2 | pbrook | |((s->TxStatus[2] & TxAborted )?TSAD_TABT2:0) |
2521 | a41b2ff2 | pbrook | |((s->TxStatus[1] & TxAborted )?TSAD_TABT1:0) |
2522 | a41b2ff2 | pbrook | |((s->TxStatus[0] & TxAborted )?TSAD_TABT0:0) |
2523 | 3b46e624 | ths | |
2524 | a41b2ff2 | pbrook | |((s->TxStatus[3] & TxHostOwns )?TSAD_OWN3:0) |
2525 | a41b2ff2 | pbrook | |((s->TxStatus[2] & TxHostOwns )?TSAD_OWN2:0) |
2526 | a41b2ff2 | pbrook | |((s->TxStatus[1] & TxHostOwns )?TSAD_OWN1:0) |
2527 | a41b2ff2 | pbrook | |((s->TxStatus[0] & TxHostOwns )?TSAD_OWN0:0) ; |
2528 | 3b46e624 | ths | |
2529 | a41b2ff2 | pbrook | |
2530 | 7cdeb319 | Benjamin Poirier | DPRINTF("TSAD read val=0x%04x\n", ret);
|
2531 | a41b2ff2 | pbrook | |
2532 | a41b2ff2 | pbrook | return ret;
|
2533 | a41b2ff2 | pbrook | } |
2534 | a41b2ff2 | pbrook | |
2535 | a41b2ff2 | pbrook | static uint16_t rtl8139_CSCR_read(RTL8139State *s)
|
2536 | a41b2ff2 | pbrook | { |
2537 | a41b2ff2 | pbrook | uint16_t ret = s->CSCR; |
2538 | a41b2ff2 | pbrook | |
2539 | 7cdeb319 | Benjamin Poirier | DPRINTF("CSCR read val=0x%04x\n", ret);
|
2540 | a41b2ff2 | pbrook | |
2541 | a41b2ff2 | pbrook | return ret;
|
2542 | a41b2ff2 | pbrook | } |
2543 | a41b2ff2 | pbrook | |
2544 | a41b2ff2 | pbrook | static void rtl8139_TxAddr_write(RTL8139State *s, uint32_t txAddrOffset, uint32_t val) |
2545 | a41b2ff2 | pbrook | { |
2546 | 7cdeb319 | Benjamin Poirier | DPRINTF("TxAddr write offset=0x%x val=0x%08x\n", txAddrOffset, val);
|
2547 | a41b2ff2 | pbrook | |
2548 | 290a0933 | ths | s->TxAddr[txAddrOffset/4] = val;
|
2549 | a41b2ff2 | pbrook | } |
2550 | a41b2ff2 | pbrook | |
2551 | a41b2ff2 | pbrook | static uint32_t rtl8139_TxAddr_read(RTL8139State *s, uint32_t txAddrOffset)
|
2552 | a41b2ff2 | pbrook | { |
2553 | 290a0933 | ths | uint32_t ret = s->TxAddr[txAddrOffset/4];
|
2554 | a41b2ff2 | pbrook | |
2555 | 7cdeb319 | Benjamin Poirier | DPRINTF("TxAddr read offset=0x%x val=0x%08x\n", txAddrOffset, ret);
|
2556 | a41b2ff2 | pbrook | |
2557 | a41b2ff2 | pbrook | return ret;
|
2558 | a41b2ff2 | pbrook | } |
2559 | a41b2ff2 | pbrook | |
2560 | a41b2ff2 | pbrook | static void rtl8139_RxBufPtr_write(RTL8139State *s, uint32_t val) |
2561 | a41b2ff2 | pbrook | { |
2562 | 7cdeb319 | Benjamin Poirier | DPRINTF("RxBufPtr write val=0x%04x\n", val);
|
2563 | a41b2ff2 | pbrook | |
2564 | a41b2ff2 | pbrook | /* this value is off by 16 */
|
2565 | a41b2ff2 | pbrook | s->RxBufPtr = MOD2(val + 0x10, s->RxBufferSize);
|
2566 | a41b2ff2 | pbrook | |
2567 | 7cdeb319 | Benjamin Poirier | DPRINTF(" CAPR write: rx buffer length %d head 0x%04x read 0x%04x\n",
|
2568 | 7cdeb319 | Benjamin Poirier | s->RxBufferSize, s->RxBufAddr, s->RxBufPtr); |
2569 | a41b2ff2 | pbrook | } |
2570 | a41b2ff2 | pbrook | |
2571 | a41b2ff2 | pbrook | static uint32_t rtl8139_RxBufPtr_read(RTL8139State *s)
|
2572 | a41b2ff2 | pbrook | { |
2573 | a41b2ff2 | pbrook | /* this value is off by 16 */
|
2574 | a41b2ff2 | pbrook | uint32_t ret = s->RxBufPtr - 0x10;
|
2575 | a41b2ff2 | pbrook | |
2576 | 7cdeb319 | Benjamin Poirier | DPRINTF("RxBufPtr read val=0x%04x\n", ret);
|
2577 | 6cadb320 | bellard | |
2578 | 6cadb320 | bellard | return ret;
|
2579 | 6cadb320 | bellard | } |
2580 | 6cadb320 | bellard | |
2581 | 6cadb320 | bellard | static uint32_t rtl8139_RxBufAddr_read(RTL8139State *s)
|
2582 | 6cadb320 | bellard | { |
2583 | 6cadb320 | bellard | /* this value is NOT off by 16 */
|
2584 | 6cadb320 | bellard | uint32_t ret = s->RxBufAddr; |
2585 | 6cadb320 | bellard | |
2586 | 7cdeb319 | Benjamin Poirier | DPRINTF("RxBufAddr read val=0x%04x\n", ret);
|
2587 | a41b2ff2 | pbrook | |
2588 | a41b2ff2 | pbrook | return ret;
|
2589 | a41b2ff2 | pbrook | } |
2590 | a41b2ff2 | pbrook | |
2591 | a41b2ff2 | pbrook | static void rtl8139_RxBuf_write(RTL8139State *s, uint32_t val) |
2592 | a41b2ff2 | pbrook | { |
2593 | 7cdeb319 | Benjamin Poirier | DPRINTF("RxBuf write val=0x%08x\n", val);
|
2594 | a41b2ff2 | pbrook | |
2595 | a41b2ff2 | pbrook | s->RxBuf = val; |
2596 | a41b2ff2 | pbrook | |
2597 | a41b2ff2 | pbrook | /* may need to reset rxring here */
|
2598 | a41b2ff2 | pbrook | } |
2599 | a41b2ff2 | pbrook | |
2600 | a41b2ff2 | pbrook | static uint32_t rtl8139_RxBuf_read(RTL8139State *s)
|
2601 | a41b2ff2 | pbrook | { |
2602 | a41b2ff2 | pbrook | uint32_t ret = s->RxBuf; |
2603 | a41b2ff2 | pbrook | |
2604 | 7cdeb319 | Benjamin Poirier | DPRINTF("RxBuf read val=0x%08x\n", ret);
|
2605 | a41b2ff2 | pbrook | |
2606 | a41b2ff2 | pbrook | return ret;
|
2607 | a41b2ff2 | pbrook | } |
2608 | a41b2ff2 | pbrook | |
2609 | a41b2ff2 | pbrook | static void rtl8139_IntrMask_write(RTL8139State *s, uint32_t val) |
2610 | a41b2ff2 | pbrook | { |
2611 | 7cdeb319 | Benjamin Poirier | DPRINTF("IntrMask write(w) val=0x%04x\n", val);
|
2612 | a41b2ff2 | pbrook | |
2613 | a41b2ff2 | pbrook | /* mask unwriteable bits */
|
2614 | a41b2ff2 | pbrook | val = SET_MASKED(val, 0x1e00, s->IntrMask);
|
2615 | a41b2ff2 | pbrook | |
2616 | a41b2ff2 | pbrook | s->IntrMask = val; |
2617 | a41b2ff2 | pbrook | |
2618 | 74475455 | Paolo Bonzini | rtl8139_set_next_tctr_time(s, qemu_get_clock_ns(vm_clock)); |
2619 | a41b2ff2 | pbrook | rtl8139_update_irq(s); |
2620 | 05447803 | Frediano Ziglio | |
2621 | a41b2ff2 | pbrook | } |
2622 | a41b2ff2 | pbrook | |
2623 | a41b2ff2 | pbrook | static uint32_t rtl8139_IntrMask_read(RTL8139State *s)
|
2624 | a41b2ff2 | pbrook | { |
2625 | a41b2ff2 | pbrook | uint32_t ret = s->IntrMask; |
2626 | a41b2ff2 | pbrook | |
2627 | 7cdeb319 | Benjamin Poirier | DPRINTF("IntrMask read(w) val=0x%04x\n", ret);
|
2628 | a41b2ff2 | pbrook | |
2629 | a41b2ff2 | pbrook | return ret;
|
2630 | a41b2ff2 | pbrook | } |
2631 | a41b2ff2 | pbrook | |
2632 | a41b2ff2 | pbrook | static void rtl8139_IntrStatus_write(RTL8139State *s, uint32_t val) |
2633 | a41b2ff2 | pbrook | { |
2634 | 7cdeb319 | Benjamin Poirier | DPRINTF("IntrStatus write(w) val=0x%04x\n", val);
|
2635 | a41b2ff2 | pbrook | |
2636 | a41b2ff2 | pbrook | #if 0
|
2637 | a41b2ff2 | pbrook | |
2638 | a41b2ff2 | pbrook | /* writing to ISR has no effect */
|
2639 | a41b2ff2 | pbrook | |
2640 | a41b2ff2 | pbrook | return;
|
2641 | a41b2ff2 | pbrook | |
2642 | a41b2ff2 | pbrook | #else
|
2643 | a41b2ff2 | pbrook | uint16_t newStatus = s->IntrStatus & ~val; |
2644 | a41b2ff2 | pbrook | |
2645 | a41b2ff2 | pbrook | /* mask unwriteable bits */
|
2646 | a41b2ff2 | pbrook | newStatus = SET_MASKED(newStatus, 0x1e00, s->IntrStatus);
|
2647 | a41b2ff2 | pbrook | |
2648 | a41b2ff2 | pbrook | /* writing 1 to interrupt status register bit clears it */
|
2649 | a41b2ff2 | pbrook | s->IntrStatus = 0;
|
2650 | a41b2ff2 | pbrook | rtl8139_update_irq(s); |
2651 | a41b2ff2 | pbrook | |
2652 | a41b2ff2 | pbrook | s->IntrStatus = newStatus; |
2653 | 05447803 | Frediano Ziglio | /*
|
2654 | 05447803 | Frediano Ziglio | * Computing if we miss an interrupt here is not that correct but
|
2655 | 05447803 | Frediano Ziglio | * considered that we should have had already an interrupt
|
2656 | 05447803 | Frediano Ziglio | * and probably emulated is slower is better to assume this resetting was
|
2657 | 05447803 | Frediano Ziglio | * done before testing on previous rtl8139_update_irq lead to IRQ loosing
|
2658 | 05447803 | Frediano Ziglio | */
|
2659 | 74475455 | Paolo Bonzini | rtl8139_set_next_tctr_time(s, qemu_get_clock_ns(vm_clock)); |
2660 | a41b2ff2 | pbrook | rtl8139_update_irq(s); |
2661 | 05447803 | Frediano Ziglio | |
2662 | a41b2ff2 | pbrook | #endif
|
2663 | a41b2ff2 | pbrook | } |
2664 | a41b2ff2 | pbrook | |
2665 | a41b2ff2 | pbrook | static uint32_t rtl8139_IntrStatus_read(RTL8139State *s)
|
2666 | a41b2ff2 | pbrook | { |
2667 | 74475455 | Paolo Bonzini | rtl8139_set_next_tctr_time(s, qemu_get_clock_ns(vm_clock)); |
2668 | 05447803 | Frediano Ziglio | |
2669 | a41b2ff2 | pbrook | uint32_t ret = s->IntrStatus; |
2670 | a41b2ff2 | pbrook | |
2671 | 7cdeb319 | Benjamin Poirier | DPRINTF("IntrStatus read(w) val=0x%04x\n", ret);
|
2672 | a41b2ff2 | pbrook | |
2673 | a41b2ff2 | pbrook | #if 0
|
2674 | a41b2ff2 | pbrook | |
2675 | a41b2ff2 | pbrook | /* reading ISR clears all interrupts */
|
2676 | a41b2ff2 | pbrook | s->IntrStatus = 0;
|
2677 | a41b2ff2 | pbrook | |
2678 | a41b2ff2 | pbrook | rtl8139_update_irq(s);
|
2679 | a41b2ff2 | pbrook | |
2680 | a41b2ff2 | pbrook | #endif
|
2681 | a41b2ff2 | pbrook | |
2682 | a41b2ff2 | pbrook | return ret;
|
2683 | a41b2ff2 | pbrook | } |
2684 | a41b2ff2 | pbrook | |
2685 | a41b2ff2 | pbrook | static void rtl8139_MultiIntr_write(RTL8139State *s, uint32_t val) |
2686 | a41b2ff2 | pbrook | { |
2687 | 7cdeb319 | Benjamin Poirier | DPRINTF("MultiIntr write(w) val=0x%04x\n", val);
|
2688 | a41b2ff2 | pbrook | |
2689 | a41b2ff2 | pbrook | /* mask unwriteable bits */
|
2690 | a41b2ff2 | pbrook | val = SET_MASKED(val, 0xf000, s->MultiIntr);
|
2691 | a41b2ff2 | pbrook | |
2692 | a41b2ff2 | pbrook | s->MultiIntr = val; |
2693 | a41b2ff2 | pbrook | } |
2694 | a41b2ff2 | pbrook | |
2695 | a41b2ff2 | pbrook | static uint32_t rtl8139_MultiIntr_read(RTL8139State *s)
|
2696 | a41b2ff2 | pbrook | { |
2697 | a41b2ff2 | pbrook | uint32_t ret = s->MultiIntr; |
2698 | a41b2ff2 | pbrook | |
2699 | 7cdeb319 | Benjamin Poirier | DPRINTF("MultiIntr read(w) val=0x%04x\n", ret);
|
2700 | a41b2ff2 | pbrook | |
2701 | a41b2ff2 | pbrook | return ret;
|
2702 | a41b2ff2 | pbrook | } |
2703 | a41b2ff2 | pbrook | |
2704 | a41b2ff2 | pbrook | static void rtl8139_io_writeb(void *opaque, uint8_t addr, uint32_t val) |
2705 | a41b2ff2 | pbrook | { |
2706 | a41b2ff2 | pbrook | RTL8139State *s = opaque; |
2707 | a41b2ff2 | pbrook | |
2708 | a41b2ff2 | pbrook | addr &= 0xff;
|
2709 | a41b2ff2 | pbrook | |
2710 | a41b2ff2 | pbrook | switch (addr)
|
2711 | a41b2ff2 | pbrook | { |
2712 | a41b2ff2 | pbrook | case MAC0 ... MAC0+5: |
2713 | a41b2ff2 | pbrook | s->phys[addr - MAC0] = val; |
2714 | a41b2ff2 | pbrook | break;
|
2715 | a41b2ff2 | pbrook | case MAC0+6 ... MAC0+7: |
2716 | a41b2ff2 | pbrook | /* reserved */
|
2717 | a41b2ff2 | pbrook | break;
|
2718 | a41b2ff2 | pbrook | case MAR0 ... MAR0+7: |
2719 | a41b2ff2 | pbrook | s->mult[addr - MAR0] = val; |
2720 | a41b2ff2 | pbrook | break;
|
2721 | a41b2ff2 | pbrook | case ChipCmd:
|
2722 | a41b2ff2 | pbrook | rtl8139_ChipCmd_write(s, val); |
2723 | a41b2ff2 | pbrook | break;
|
2724 | a41b2ff2 | pbrook | case Cfg9346:
|
2725 | a41b2ff2 | pbrook | rtl8139_Cfg9346_write(s, val); |
2726 | a41b2ff2 | pbrook | break;
|
2727 | a41b2ff2 | pbrook | case TxConfig: /* windows driver sometimes writes using byte-lenth call */ |
2728 | a41b2ff2 | pbrook | rtl8139_TxConfig_writeb(s, val); |
2729 | a41b2ff2 | pbrook | break;
|
2730 | a41b2ff2 | pbrook | case Config0:
|
2731 | a41b2ff2 | pbrook | rtl8139_Config0_write(s, val); |
2732 | a41b2ff2 | pbrook | break;
|
2733 | a41b2ff2 | pbrook | case Config1:
|
2734 | a41b2ff2 | pbrook | rtl8139_Config1_write(s, val); |
2735 | a41b2ff2 | pbrook | break;
|
2736 | a41b2ff2 | pbrook | case Config3:
|
2737 | a41b2ff2 | pbrook | rtl8139_Config3_write(s, val); |
2738 | a41b2ff2 | pbrook | break;
|
2739 | a41b2ff2 | pbrook | case Config4:
|
2740 | a41b2ff2 | pbrook | rtl8139_Config4_write(s, val); |
2741 | a41b2ff2 | pbrook | break;
|
2742 | a41b2ff2 | pbrook | case Config5:
|
2743 | a41b2ff2 | pbrook | rtl8139_Config5_write(s, val); |
2744 | a41b2ff2 | pbrook | break;
|
2745 | a41b2ff2 | pbrook | case MediaStatus:
|
2746 | a41b2ff2 | pbrook | /* ignore */
|
2747 | 7cdeb319 | Benjamin Poirier | DPRINTF("not implemented write(b) to MediaStatus val=0x%02x\n",
|
2748 | 7cdeb319 | Benjamin Poirier | val); |
2749 | a41b2ff2 | pbrook | break;
|
2750 | a41b2ff2 | pbrook | |
2751 | a41b2ff2 | pbrook | case HltClk:
|
2752 | 7cdeb319 | Benjamin Poirier | DPRINTF("HltClk write val=0x%08x\n", val);
|
2753 | a41b2ff2 | pbrook | if (val == 'R') |
2754 | a41b2ff2 | pbrook | { |
2755 | a41b2ff2 | pbrook | s->clock_enabled = 1;
|
2756 | a41b2ff2 | pbrook | } |
2757 | a41b2ff2 | pbrook | else if (val == 'H') |
2758 | a41b2ff2 | pbrook | { |
2759 | a41b2ff2 | pbrook | s->clock_enabled = 0;
|
2760 | a41b2ff2 | pbrook | } |
2761 | a41b2ff2 | pbrook | break;
|
2762 | a41b2ff2 | pbrook | |
2763 | a41b2ff2 | pbrook | case TxThresh:
|
2764 | 7cdeb319 | Benjamin Poirier | DPRINTF("C+ TxThresh write(b) val=0x%02x\n", val);
|
2765 | a41b2ff2 | pbrook | s->TxThresh = val; |
2766 | a41b2ff2 | pbrook | break;
|
2767 | a41b2ff2 | pbrook | |
2768 | a41b2ff2 | pbrook | case TxPoll:
|
2769 | 7cdeb319 | Benjamin Poirier | DPRINTF("C+ TxPoll write(b) val=0x%02x\n", val);
|
2770 | a41b2ff2 | pbrook | if (val & (1 << 7)) |
2771 | a41b2ff2 | pbrook | { |
2772 | 7cdeb319 | Benjamin Poirier | DPRINTF("C+ TxPoll high priority transmission (not "
|
2773 | 7cdeb319 | Benjamin Poirier | "implemented)\n");
|
2774 | a41b2ff2 | pbrook | //rtl8139_cplus_transmit(s);
|
2775 | a41b2ff2 | pbrook | } |
2776 | a41b2ff2 | pbrook | if (val & (1 << 6)) |
2777 | a41b2ff2 | pbrook | { |
2778 | 7cdeb319 | Benjamin Poirier | DPRINTF("C+ TxPoll normal priority transmission\n");
|
2779 | a41b2ff2 | pbrook | rtl8139_cplus_transmit(s); |
2780 | a41b2ff2 | pbrook | } |
2781 | a41b2ff2 | pbrook | |
2782 | a41b2ff2 | pbrook | break;
|
2783 | a41b2ff2 | pbrook | |
2784 | a41b2ff2 | pbrook | default:
|
2785 | 7cdeb319 | Benjamin Poirier | DPRINTF("not implemented write(b) addr=0x%x val=0x%02x\n", addr,
|
2786 | 7cdeb319 | Benjamin Poirier | val); |
2787 | a41b2ff2 | pbrook | break;
|
2788 | a41b2ff2 | pbrook | } |
2789 | a41b2ff2 | pbrook | } |
2790 | a41b2ff2 | pbrook | |
2791 | a41b2ff2 | pbrook | static void rtl8139_io_writew(void *opaque, uint8_t addr, uint32_t val) |
2792 | a41b2ff2 | pbrook | { |
2793 | a41b2ff2 | pbrook | RTL8139State *s = opaque; |
2794 | a41b2ff2 | pbrook | |
2795 | a41b2ff2 | pbrook | addr &= 0xfe;
|
2796 | a41b2ff2 | pbrook | |
2797 | a41b2ff2 | pbrook | switch (addr)
|
2798 | a41b2ff2 | pbrook | { |
2799 | a41b2ff2 | pbrook | case IntrMask:
|
2800 | a41b2ff2 | pbrook | rtl8139_IntrMask_write(s, val); |
2801 | a41b2ff2 | pbrook | break;
|
2802 | a41b2ff2 | pbrook | |
2803 | a41b2ff2 | pbrook | case IntrStatus:
|
2804 | a41b2ff2 | pbrook | rtl8139_IntrStatus_write(s, val); |
2805 | a41b2ff2 | pbrook | break;
|
2806 | a41b2ff2 | pbrook | |
2807 | a41b2ff2 | pbrook | case MultiIntr:
|
2808 | a41b2ff2 | pbrook | rtl8139_MultiIntr_write(s, val); |
2809 | a41b2ff2 | pbrook | break;
|
2810 | a41b2ff2 | pbrook | |
2811 | a41b2ff2 | pbrook | case RxBufPtr:
|
2812 | a41b2ff2 | pbrook | rtl8139_RxBufPtr_write(s, val); |
2813 | a41b2ff2 | pbrook | break;
|
2814 | a41b2ff2 | pbrook | |
2815 | a41b2ff2 | pbrook | case BasicModeCtrl:
|
2816 | a41b2ff2 | pbrook | rtl8139_BasicModeCtrl_write(s, val); |
2817 | a41b2ff2 | pbrook | break;
|
2818 | a41b2ff2 | pbrook | case BasicModeStatus:
|
2819 | a41b2ff2 | pbrook | rtl8139_BasicModeStatus_write(s, val); |
2820 | a41b2ff2 | pbrook | break;
|
2821 | a41b2ff2 | pbrook | case NWayAdvert:
|
2822 | 7cdeb319 | Benjamin Poirier | DPRINTF("NWayAdvert write(w) val=0x%04x\n", val);
|
2823 | a41b2ff2 | pbrook | s->NWayAdvert = val; |
2824 | a41b2ff2 | pbrook | break;
|
2825 | a41b2ff2 | pbrook | case NWayLPAR:
|
2826 | 7cdeb319 | Benjamin Poirier | DPRINTF("forbidden NWayLPAR write(w) val=0x%04x\n", val);
|
2827 | a41b2ff2 | pbrook | break;
|
2828 | a41b2ff2 | pbrook | case NWayExpansion:
|
2829 | 7cdeb319 | Benjamin Poirier | DPRINTF("NWayExpansion write(w) val=0x%04x\n", val);
|
2830 | a41b2ff2 | pbrook | s->NWayExpansion = val; |
2831 | a41b2ff2 | pbrook | break;
|
2832 | a41b2ff2 | pbrook | |
2833 | a41b2ff2 | pbrook | case CpCmd:
|
2834 | a41b2ff2 | pbrook | rtl8139_CpCmd_write(s, val); |
2835 | a41b2ff2 | pbrook | break;
|
2836 | a41b2ff2 | pbrook | |
2837 | 6cadb320 | bellard | case IntrMitigate:
|
2838 | 6cadb320 | bellard | rtl8139_IntrMitigate_write(s, val); |
2839 | 6cadb320 | bellard | break;
|
2840 | 6cadb320 | bellard | |
2841 | a41b2ff2 | pbrook | default:
|
2842 | 7cdeb319 | Benjamin Poirier | DPRINTF("ioport write(w) addr=0x%x val=0x%04x via write(b)\n",
|
2843 | 7cdeb319 | Benjamin Poirier | addr, val); |
2844 | a41b2ff2 | pbrook | |
2845 | a41b2ff2 | pbrook | rtl8139_io_writeb(opaque, addr, val & 0xff);
|
2846 | a41b2ff2 | pbrook | rtl8139_io_writeb(opaque, addr + 1, (val >> 8) & 0xff); |
2847 | a41b2ff2 | pbrook | break;
|
2848 | a41b2ff2 | pbrook | } |
2849 | a41b2ff2 | pbrook | } |
2850 | a41b2ff2 | pbrook | |
2851 | 05447803 | Frediano Ziglio | static void rtl8139_set_next_tctr_time(RTL8139State *s, int64_t current_time) |
2852 | 05447803 | Frediano Ziglio | { |
2853 | 05447803 | Frediano Ziglio | int64_t pci_time, next_time; |
2854 | 05447803 | Frediano Ziglio | uint32_t low_pci; |
2855 | 05447803 | Frediano Ziglio | |
2856 | 7cdeb319 | Benjamin Poirier | DPRINTF("entered rtl8139_set_next_tctr_time\n");
|
2857 | 05447803 | Frediano Ziglio | |
2858 | 05447803 | Frediano Ziglio | if (s->TimerExpire && current_time >= s->TimerExpire) {
|
2859 | 05447803 | Frediano Ziglio | s->IntrStatus |= PCSTimeout; |
2860 | 05447803 | Frediano Ziglio | rtl8139_update_irq(s); |
2861 | 05447803 | Frediano Ziglio | } |
2862 | 05447803 | Frediano Ziglio | |
2863 | 05447803 | Frediano Ziglio | /* Set QEMU timer only if needed that is
|
2864 | 05447803 | Frediano Ziglio | * - TimerInt <> 0 (we have a timer)
|
2865 | 05447803 | Frediano Ziglio | * - mask = 1 (we want an interrupt timer)
|
2866 | 05447803 | Frediano Ziglio | * - irq = 0 (irq is not already active)
|
2867 | 05447803 | Frediano Ziglio | * If any of above change we need to compute timer again
|
2868 | 05447803 | Frediano Ziglio | * Also we must check if timer is passed without QEMU timer
|
2869 | 05447803 | Frediano Ziglio | */
|
2870 | 05447803 | Frediano Ziglio | s->TimerExpire = 0;
|
2871 | 05447803 | Frediano Ziglio | if (!s->TimerInt) {
|
2872 | 05447803 | Frediano Ziglio | return;
|
2873 | 05447803 | Frediano Ziglio | } |
2874 | 05447803 | Frediano Ziglio | |
2875 | 05447803 | Frediano Ziglio | pci_time = muldiv64(current_time - s->TCTR_base, PCI_FREQUENCY, |
2876 | 05447803 | Frediano Ziglio | get_ticks_per_sec()); |
2877 | 05447803 | Frediano Ziglio | low_pci = pci_time & 0xffffffff;
|
2878 | 05447803 | Frediano Ziglio | pci_time = pci_time - low_pci + s->TimerInt; |
2879 | 05447803 | Frediano Ziglio | if (low_pci >= s->TimerInt) {
|
2880 | 05447803 | Frediano Ziglio | pci_time += 0x100000000LL;
|
2881 | 05447803 | Frediano Ziglio | } |
2882 | 05447803 | Frediano Ziglio | next_time = s->TCTR_base + muldiv64(pci_time, get_ticks_per_sec(), |
2883 | 05447803 | Frediano Ziglio | PCI_FREQUENCY); |
2884 | 05447803 | Frediano Ziglio | s->TimerExpire = next_time; |
2885 | 05447803 | Frediano Ziglio | |
2886 | 05447803 | Frediano Ziglio | if ((s->IntrMask & PCSTimeout) != 0 && (s->IntrStatus & PCSTimeout) == 0) { |
2887 | 05447803 | Frediano Ziglio | qemu_mod_timer(s->timer, next_time); |
2888 | 05447803 | Frediano Ziglio | } |
2889 | 05447803 | Frediano Ziglio | } |
2890 | 05447803 | Frediano Ziglio | |
2891 | a41b2ff2 | pbrook | static void rtl8139_io_writel(void *opaque, uint8_t addr, uint32_t val) |
2892 | a41b2ff2 | pbrook | { |
2893 | a41b2ff2 | pbrook | RTL8139State *s = opaque; |
2894 | a41b2ff2 | pbrook | |
2895 | a41b2ff2 | pbrook | addr &= 0xfc;
|
2896 | a41b2ff2 | pbrook | |
2897 | a41b2ff2 | pbrook | switch (addr)
|
2898 | a41b2ff2 | pbrook | { |
2899 | a41b2ff2 | pbrook | case RxMissed:
|
2900 | 7cdeb319 | Benjamin Poirier | DPRINTF("RxMissed clearing on write\n");
|
2901 | a41b2ff2 | pbrook | s->RxMissed = 0;
|
2902 | a41b2ff2 | pbrook | break;
|
2903 | a41b2ff2 | pbrook | |
2904 | a41b2ff2 | pbrook | case TxConfig:
|
2905 | a41b2ff2 | pbrook | rtl8139_TxConfig_write(s, val); |
2906 | a41b2ff2 | pbrook | break;
|
2907 | a41b2ff2 | pbrook | |
2908 | a41b2ff2 | pbrook | case RxConfig:
|
2909 | a41b2ff2 | pbrook | rtl8139_RxConfig_write(s, val); |
2910 | a41b2ff2 | pbrook | break;
|
2911 | a41b2ff2 | pbrook | |
2912 | a41b2ff2 | pbrook | case TxStatus0 ... TxStatus0+4*4-1: |
2913 | a41b2ff2 | pbrook | rtl8139_TxStatus_write(s, addr-TxStatus0, val); |
2914 | a41b2ff2 | pbrook | break;
|
2915 | a41b2ff2 | pbrook | |
2916 | a41b2ff2 | pbrook | case TxAddr0 ... TxAddr0+4*4-1: |
2917 | a41b2ff2 | pbrook | rtl8139_TxAddr_write(s, addr-TxAddr0, val); |
2918 | a41b2ff2 | pbrook | break;
|
2919 | a41b2ff2 | pbrook | |
2920 | a41b2ff2 | pbrook | case RxBuf:
|
2921 | a41b2ff2 | pbrook | rtl8139_RxBuf_write(s, val); |
2922 | a41b2ff2 | pbrook | break;
|
2923 | a41b2ff2 | pbrook | |
2924 | a41b2ff2 | pbrook | case RxRingAddrLO:
|
2925 | 7cdeb319 | Benjamin Poirier | DPRINTF("C+ RxRing low bits write val=0x%08x\n", val);
|
2926 | a41b2ff2 | pbrook | s->RxRingAddrLO = val; |
2927 | a41b2ff2 | pbrook | break;
|
2928 | a41b2ff2 | pbrook | |
2929 | a41b2ff2 | pbrook | case RxRingAddrHI:
|
2930 | 7cdeb319 | Benjamin Poirier | DPRINTF("C+ RxRing high bits write val=0x%08x\n", val);
|
2931 | a41b2ff2 | pbrook | s->RxRingAddrHI = val; |
2932 | a41b2ff2 | pbrook | break;
|
2933 | a41b2ff2 | pbrook | |
2934 | 6cadb320 | bellard | case Timer:
|
2935 | 7cdeb319 | Benjamin Poirier | DPRINTF("TCTR Timer reset on write\n");
|
2936 | 74475455 | Paolo Bonzini | s->TCTR_base = qemu_get_clock_ns(vm_clock); |
2937 | 05447803 | Frediano Ziglio | rtl8139_set_next_tctr_time(s, s->TCTR_base); |
2938 | 6cadb320 | bellard | break;
|
2939 | 6cadb320 | bellard | |
2940 | 6cadb320 | bellard | case FlashReg:
|
2941 | 7cdeb319 | Benjamin Poirier | DPRINTF("FlashReg TimerInt write val=0x%08x\n", val);
|
2942 | 05447803 | Frediano Ziglio | if (s->TimerInt != val) {
|
2943 | 05447803 | Frediano Ziglio | s->TimerInt = val; |
2944 | 74475455 | Paolo Bonzini | rtl8139_set_next_tctr_time(s, qemu_get_clock_ns(vm_clock)); |
2945 | 05447803 | Frediano Ziglio | } |
2946 | 6cadb320 | bellard | break;
|
2947 | 6cadb320 | bellard | |
2948 | a41b2ff2 | pbrook | default:
|
2949 | 7cdeb319 | Benjamin Poirier | DPRINTF("ioport write(l) addr=0x%x val=0x%08x via write(b)\n",
|
2950 | 7cdeb319 | Benjamin Poirier | addr, val); |
2951 | a41b2ff2 | pbrook | rtl8139_io_writeb(opaque, addr, val & 0xff);
|
2952 | a41b2ff2 | pbrook | rtl8139_io_writeb(opaque, addr + 1, (val >> 8) & 0xff); |
2953 | a41b2ff2 | pbrook | rtl8139_io_writeb(opaque, addr + 2, (val >> 16) & 0xff); |
2954 | a41b2ff2 | pbrook | rtl8139_io_writeb(opaque, addr + 3, (val >> 24) & 0xff); |
2955 | a41b2ff2 | pbrook | break;
|
2956 | a41b2ff2 | pbrook | } |
2957 | a41b2ff2 | pbrook | } |
2958 | a41b2ff2 | pbrook | |
2959 | a41b2ff2 | pbrook | static uint32_t rtl8139_io_readb(void *opaque, uint8_t addr) |
2960 | a41b2ff2 | pbrook | { |
2961 | a41b2ff2 | pbrook | RTL8139State *s = opaque; |
2962 | a41b2ff2 | pbrook | int ret;
|
2963 | a41b2ff2 | pbrook | |
2964 | a41b2ff2 | pbrook | addr &= 0xff;
|
2965 | a41b2ff2 | pbrook | |
2966 | a41b2ff2 | pbrook | switch (addr)
|
2967 | a41b2ff2 | pbrook | { |
2968 | a41b2ff2 | pbrook | case MAC0 ... MAC0+5: |
2969 | a41b2ff2 | pbrook | ret = s->phys[addr - MAC0]; |
2970 | a41b2ff2 | pbrook | break;
|
2971 | a41b2ff2 | pbrook | case MAC0+6 ... MAC0+7: |
2972 | a41b2ff2 | pbrook | ret = 0;
|
2973 | a41b2ff2 | pbrook | break;
|
2974 | a41b2ff2 | pbrook | case MAR0 ... MAR0+7: |
2975 | a41b2ff2 | pbrook | ret = s->mult[addr - MAR0]; |
2976 | a41b2ff2 | pbrook | break;
|
2977 | a41b2ff2 | pbrook | case ChipCmd:
|
2978 | a41b2ff2 | pbrook | ret = rtl8139_ChipCmd_read(s); |
2979 | a41b2ff2 | pbrook | break;
|
2980 | a41b2ff2 | pbrook | case Cfg9346:
|
2981 | a41b2ff2 | pbrook | ret = rtl8139_Cfg9346_read(s); |
2982 | a41b2ff2 | pbrook | break;
|
2983 | a41b2ff2 | pbrook | case Config0:
|
2984 | a41b2ff2 | pbrook | ret = rtl8139_Config0_read(s); |
2985 | a41b2ff2 | pbrook | break;
|
2986 | a41b2ff2 | pbrook | case Config1:
|
2987 | a41b2ff2 | pbrook | ret = rtl8139_Config1_read(s); |
2988 | a41b2ff2 | pbrook | break;
|
2989 | a41b2ff2 | pbrook | case Config3:
|
2990 | a41b2ff2 | pbrook | ret = rtl8139_Config3_read(s); |
2991 | a41b2ff2 | pbrook | break;
|
2992 | a41b2ff2 | pbrook | case Config4:
|
2993 | a41b2ff2 | pbrook | ret = rtl8139_Config4_read(s); |
2994 | a41b2ff2 | pbrook | break;
|
2995 | a41b2ff2 | pbrook | case Config5:
|
2996 | a41b2ff2 | pbrook | ret = rtl8139_Config5_read(s); |
2997 | a41b2ff2 | pbrook | break;
|
2998 | a41b2ff2 | pbrook | |
2999 | a41b2ff2 | pbrook | case MediaStatus:
|
3000 | a41b2ff2 | pbrook | ret = 0xd0;
|
3001 | 7cdeb319 | Benjamin Poirier | DPRINTF("MediaStatus read 0x%x\n", ret);
|
3002 | a41b2ff2 | pbrook | break;
|
3003 | a41b2ff2 | pbrook | |
3004 | a41b2ff2 | pbrook | case HltClk:
|
3005 | a41b2ff2 | pbrook | ret = s->clock_enabled; |
3006 | 7cdeb319 | Benjamin Poirier | DPRINTF("HltClk read 0x%x\n", ret);
|
3007 | a41b2ff2 | pbrook | break;
|
3008 | a41b2ff2 | pbrook | |
3009 | a41b2ff2 | pbrook | case PCIRevisionID:
|
3010 | 6cadb320 | bellard | ret = RTL8139_PCI_REVID; |
3011 | 7cdeb319 | Benjamin Poirier | DPRINTF("PCI Revision ID read 0x%x\n", ret);
|
3012 | a41b2ff2 | pbrook | break;
|
3013 | a41b2ff2 | pbrook | |
3014 | a41b2ff2 | pbrook | case TxThresh:
|
3015 | a41b2ff2 | pbrook | ret = s->TxThresh; |
3016 | 7cdeb319 | Benjamin Poirier | DPRINTF("C+ TxThresh read(b) val=0x%02x\n", ret);
|
3017 | a41b2ff2 | pbrook | break;
|
3018 | a41b2ff2 | pbrook | |
3019 | a41b2ff2 | pbrook | case 0x43: /* Part of TxConfig register. Windows driver tries to read it */ |
3020 | a41b2ff2 | pbrook | ret = s->TxConfig >> 24;
|
3021 | 7cdeb319 | Benjamin Poirier | DPRINTF("RTL8139C TxConfig at 0x43 read(b) val=0x%02x\n", ret);
|
3022 | a41b2ff2 | pbrook | break;
|
3023 | a41b2ff2 | pbrook | |
3024 | a41b2ff2 | pbrook | default:
|
3025 | 7cdeb319 | Benjamin Poirier | DPRINTF("not implemented read(b) addr=0x%x\n", addr);
|
3026 | a41b2ff2 | pbrook | ret = 0;
|
3027 | a41b2ff2 | pbrook | break;
|
3028 | a41b2ff2 | pbrook | } |
3029 | a41b2ff2 | pbrook | |
3030 | a41b2ff2 | pbrook | return ret;
|
3031 | a41b2ff2 | pbrook | } |
3032 | a41b2ff2 | pbrook | |
3033 | a41b2ff2 | pbrook | static uint32_t rtl8139_io_readw(void *opaque, uint8_t addr) |
3034 | a41b2ff2 | pbrook | { |
3035 | a41b2ff2 | pbrook | RTL8139State *s = opaque; |
3036 | a41b2ff2 | pbrook | uint32_t ret; |
3037 | a41b2ff2 | pbrook | |
3038 | a41b2ff2 | pbrook | addr &= 0xfe; /* mask lower bit */ |
3039 | a41b2ff2 | pbrook | |
3040 | a41b2ff2 | pbrook | switch (addr)
|
3041 | a41b2ff2 | pbrook | { |
3042 | a41b2ff2 | pbrook | case IntrMask:
|
3043 | a41b2ff2 | pbrook | ret = rtl8139_IntrMask_read(s); |
3044 | a41b2ff2 | pbrook | break;
|
3045 | a41b2ff2 | pbrook | |
3046 | a41b2ff2 | pbrook | case IntrStatus:
|
3047 | a41b2ff2 | pbrook | ret = rtl8139_IntrStatus_read(s); |
3048 | a41b2ff2 | pbrook | break;
|
3049 | a41b2ff2 | pbrook | |
3050 | a41b2ff2 | pbrook | case MultiIntr:
|
3051 | a41b2ff2 | pbrook | ret = rtl8139_MultiIntr_read(s); |
3052 | a41b2ff2 | pbrook | break;
|
3053 | a41b2ff2 | pbrook | |
3054 | a41b2ff2 | pbrook | case RxBufPtr:
|
3055 | a41b2ff2 | pbrook | ret = rtl8139_RxBufPtr_read(s); |
3056 | a41b2ff2 | pbrook | break;
|
3057 | a41b2ff2 | pbrook | |
3058 | 6cadb320 | bellard | case RxBufAddr:
|
3059 | 6cadb320 | bellard | ret = rtl8139_RxBufAddr_read(s); |
3060 | 6cadb320 | bellard | break;
|
3061 | 6cadb320 | bellard | |
3062 | a41b2ff2 | pbrook | case BasicModeCtrl:
|
3063 | a41b2ff2 | pbrook | ret = rtl8139_BasicModeCtrl_read(s); |
3064 | a41b2ff2 | pbrook | break;
|
3065 | a41b2ff2 | pbrook | case BasicModeStatus:
|
3066 | a41b2ff2 | pbrook | ret = rtl8139_BasicModeStatus_read(s); |
3067 | a41b2ff2 | pbrook | break;
|
3068 | a41b2ff2 | pbrook | case NWayAdvert:
|
3069 | a41b2ff2 | pbrook | ret = s->NWayAdvert; |
3070 | 7cdeb319 | Benjamin Poirier | DPRINTF("NWayAdvert read(w) val=0x%04x\n", ret);
|
3071 | a41b2ff2 | pbrook | break;
|
3072 | a41b2ff2 | pbrook | case NWayLPAR:
|
3073 | a41b2ff2 | pbrook | ret = s->NWayLPAR; |
3074 | 7cdeb319 | Benjamin Poirier | DPRINTF("NWayLPAR read(w) val=0x%04x\n", ret);
|
3075 | a41b2ff2 | pbrook | break;
|
3076 | a41b2ff2 | pbrook | case NWayExpansion:
|
3077 | a41b2ff2 | pbrook | ret = s->NWayExpansion; |
3078 | 7cdeb319 | Benjamin Poirier | DPRINTF("NWayExpansion read(w) val=0x%04x\n", ret);
|
3079 | a41b2ff2 | pbrook | break;
|
3080 | a41b2ff2 | pbrook | |
3081 | a41b2ff2 | pbrook | case CpCmd:
|
3082 | a41b2ff2 | pbrook | ret = rtl8139_CpCmd_read(s); |
3083 | a41b2ff2 | pbrook | break;
|
3084 | a41b2ff2 | pbrook | |
3085 | 6cadb320 | bellard | case IntrMitigate:
|
3086 | 6cadb320 | bellard | ret = rtl8139_IntrMitigate_read(s); |
3087 | 6cadb320 | bellard | break;
|
3088 | 6cadb320 | bellard | |
3089 | a41b2ff2 | pbrook | case TxSummary:
|
3090 | a41b2ff2 | pbrook | ret = rtl8139_TSAD_read(s); |
3091 | a41b2ff2 | pbrook | break;
|
3092 | a41b2ff2 | pbrook | |
3093 | a41b2ff2 | pbrook | case CSCR:
|
3094 | a41b2ff2 | pbrook | ret = rtl8139_CSCR_read(s); |
3095 | a41b2ff2 | pbrook | break;
|
3096 | a41b2ff2 | pbrook | |
3097 | a41b2ff2 | pbrook | default:
|
3098 | 7cdeb319 | Benjamin Poirier | DPRINTF("ioport read(w) addr=0x%x via read(b)\n", addr);
|
3099 | a41b2ff2 | pbrook | |
3100 | a41b2ff2 | pbrook | ret = rtl8139_io_readb(opaque, addr); |
3101 | a41b2ff2 | pbrook | ret |= rtl8139_io_readb(opaque, addr + 1) << 8; |
3102 | a41b2ff2 | pbrook | |
3103 | 7cdeb319 | Benjamin Poirier | DPRINTF("ioport read(w) addr=0x%x val=0x%04x\n", addr, ret);
|
3104 | a41b2ff2 | pbrook | break;
|
3105 | a41b2ff2 | pbrook | } |
3106 | a41b2ff2 | pbrook | |
3107 | a41b2ff2 | pbrook | return ret;
|
3108 | a41b2ff2 | pbrook | } |
3109 | a41b2ff2 | pbrook | |
3110 | a41b2ff2 | pbrook | static uint32_t rtl8139_io_readl(void *opaque, uint8_t addr) |
3111 | a41b2ff2 | pbrook | { |
3112 | a41b2ff2 | pbrook | RTL8139State *s = opaque; |
3113 | a41b2ff2 | pbrook | uint32_t ret; |
3114 | a41b2ff2 | pbrook | |
3115 | a41b2ff2 | pbrook | addr &= 0xfc; /* also mask low 2 bits */ |
3116 | a41b2ff2 | pbrook | |
3117 | a41b2ff2 | pbrook | switch (addr)
|
3118 | a41b2ff2 | pbrook | { |
3119 | a41b2ff2 | pbrook | case RxMissed:
|
3120 | a41b2ff2 | pbrook | ret = s->RxMissed; |
3121 | a41b2ff2 | pbrook | |
3122 | 7cdeb319 | Benjamin Poirier | DPRINTF("RxMissed read val=0x%08x\n", ret);
|
3123 | a41b2ff2 | pbrook | break;
|
3124 | a41b2ff2 | pbrook | |
3125 | a41b2ff2 | pbrook | case TxConfig:
|
3126 | a41b2ff2 | pbrook | ret = rtl8139_TxConfig_read(s); |
3127 | a41b2ff2 | pbrook | break;
|
3128 | a41b2ff2 | pbrook | |
3129 | a41b2ff2 | pbrook | case RxConfig:
|
3130 | a41b2ff2 | pbrook | ret = rtl8139_RxConfig_read(s); |
3131 | a41b2ff2 | pbrook | break;
|
3132 | a41b2ff2 | pbrook | |
3133 | a41b2ff2 | pbrook | case TxStatus0 ... TxStatus0+4*4-1: |
3134 | a41b2ff2 | pbrook | ret = rtl8139_TxStatus_read(s, addr-TxStatus0); |
3135 | a41b2ff2 | pbrook | break;
|
3136 | a41b2ff2 | pbrook | |
3137 | a41b2ff2 | pbrook | case TxAddr0 ... TxAddr0+4*4-1: |
3138 | a41b2ff2 | pbrook | ret = rtl8139_TxAddr_read(s, addr-TxAddr0); |
3139 | a41b2ff2 | pbrook | break;
|
3140 | a41b2ff2 | pbrook | |
3141 | a41b2ff2 | pbrook | case RxBuf:
|
3142 | a41b2ff2 | pbrook | ret = rtl8139_RxBuf_read(s); |
3143 | a41b2ff2 | pbrook | break;
|
3144 | a41b2ff2 | pbrook | |
3145 | a41b2ff2 | pbrook | case RxRingAddrLO:
|
3146 | a41b2ff2 | pbrook | ret = s->RxRingAddrLO; |
3147 | 7cdeb319 | Benjamin Poirier | DPRINTF("C+ RxRing low bits read val=0x%08x\n", ret);
|
3148 | a41b2ff2 | pbrook | break;
|
3149 | a41b2ff2 | pbrook | |
3150 | a41b2ff2 | pbrook | case RxRingAddrHI:
|
3151 | a41b2ff2 | pbrook | ret = s->RxRingAddrHI; |
3152 | 7cdeb319 | Benjamin Poirier | DPRINTF("C+ RxRing high bits read val=0x%08x\n", ret);
|
3153 | 6cadb320 | bellard | break;
|
3154 | 6cadb320 | bellard | |
3155 | 6cadb320 | bellard | case Timer:
|
3156 | 74475455 | Paolo Bonzini | ret = muldiv64(qemu_get_clock_ns(vm_clock) - s->TCTR_base, |
3157 | 05447803 | Frediano Ziglio | PCI_FREQUENCY, get_ticks_per_sec()); |
3158 | 7cdeb319 | Benjamin Poirier | DPRINTF("TCTR Timer read val=0x%08x\n", ret);
|
3159 | 6cadb320 | bellard | break;
|
3160 | 6cadb320 | bellard | |
3161 | 6cadb320 | bellard | case FlashReg:
|
3162 | 6cadb320 | bellard | ret = s->TimerInt; |
3163 | 7cdeb319 | Benjamin Poirier | DPRINTF("FlashReg TimerInt read val=0x%08x\n", ret);
|
3164 | a41b2ff2 | pbrook | break;
|
3165 | a41b2ff2 | pbrook | |
3166 | a41b2ff2 | pbrook | default:
|
3167 | 7cdeb319 | Benjamin Poirier | DPRINTF("ioport read(l) addr=0x%x via read(b)\n", addr);
|
3168 | a41b2ff2 | pbrook | |
3169 | a41b2ff2 | pbrook | ret = rtl8139_io_readb(opaque, addr); |
3170 | a41b2ff2 | pbrook | ret |= rtl8139_io_readb(opaque, addr + 1) << 8; |
3171 | a41b2ff2 | pbrook | ret |= rtl8139_io_readb(opaque, addr + 2) << 16; |
3172 | a41b2ff2 | pbrook | ret |= rtl8139_io_readb(opaque, addr + 3) << 24; |
3173 | a41b2ff2 | pbrook | |
3174 | 7cdeb319 | Benjamin Poirier | DPRINTF("read(l) addr=0x%x val=%08x\n", addr, ret);
|
3175 | a41b2ff2 | pbrook | break;
|
3176 | a41b2ff2 | pbrook | } |
3177 | a41b2ff2 | pbrook | |
3178 | a41b2ff2 | pbrook | return ret;
|
3179 | a41b2ff2 | pbrook | } |
3180 | a41b2ff2 | pbrook | |
3181 | a41b2ff2 | pbrook | /* */
|
3182 | a41b2ff2 | pbrook | |
3183 | a41b2ff2 | pbrook | static void rtl8139_ioport_writeb(void *opaque, uint32_t addr, uint32_t val) |
3184 | a41b2ff2 | pbrook | { |
3185 | a41b2ff2 | pbrook | rtl8139_io_writeb(opaque, addr & 0xFF, val);
|
3186 | a41b2ff2 | pbrook | } |
3187 | a41b2ff2 | pbrook | |
3188 | a41b2ff2 | pbrook | static void rtl8139_ioport_writew(void *opaque, uint32_t addr, uint32_t val) |
3189 | a41b2ff2 | pbrook | { |
3190 | a41b2ff2 | pbrook | rtl8139_io_writew(opaque, addr & 0xFF, val);
|
3191 | a41b2ff2 | pbrook | } |
3192 | a41b2ff2 | pbrook | |
3193 | a41b2ff2 | pbrook | static void rtl8139_ioport_writel(void *opaque, uint32_t addr, uint32_t val) |
3194 | a41b2ff2 | pbrook | { |
3195 | a41b2ff2 | pbrook | rtl8139_io_writel(opaque, addr & 0xFF, val);
|
3196 | a41b2ff2 | pbrook | } |
3197 | a41b2ff2 | pbrook | |
3198 | a41b2ff2 | pbrook | static uint32_t rtl8139_ioport_readb(void *opaque, uint32_t addr) |
3199 | a41b2ff2 | pbrook | { |
3200 | a41b2ff2 | pbrook | return rtl8139_io_readb(opaque, addr & 0xFF); |
3201 | a41b2ff2 | pbrook | } |
3202 | a41b2ff2 | pbrook | |
3203 | a41b2ff2 | pbrook | static uint32_t rtl8139_ioport_readw(void *opaque, uint32_t addr) |
3204 | a41b2ff2 | pbrook | { |
3205 | a41b2ff2 | pbrook | return rtl8139_io_readw(opaque, addr & 0xFF); |
3206 | a41b2ff2 | pbrook | } |
3207 | a41b2ff2 | pbrook | |
3208 | a41b2ff2 | pbrook | static uint32_t rtl8139_ioport_readl(void *opaque, uint32_t addr) |
3209 | a41b2ff2 | pbrook | { |
3210 | a41b2ff2 | pbrook | return rtl8139_io_readl(opaque, addr & 0xFF); |
3211 | a41b2ff2 | pbrook | } |
3212 | a41b2ff2 | pbrook | |
3213 | a41b2ff2 | pbrook | /* */
|
3214 | a41b2ff2 | pbrook | |
3215 | c227f099 | Anthony Liguori | static void rtl8139_mmio_writeb(void *opaque, target_phys_addr_t addr, uint32_t val) |
3216 | a41b2ff2 | pbrook | { |
3217 | a41b2ff2 | pbrook | rtl8139_io_writeb(opaque, addr & 0xFF, val);
|
3218 | a41b2ff2 | pbrook | } |
3219 | a41b2ff2 | pbrook | |
3220 | c227f099 | Anthony Liguori | static void rtl8139_mmio_writew(void *opaque, target_phys_addr_t addr, uint32_t val) |
3221 | a41b2ff2 | pbrook | { |
3222 | a41b2ff2 | pbrook | rtl8139_io_writew(opaque, addr & 0xFF, val);
|
3223 | a41b2ff2 | pbrook | } |
3224 | a41b2ff2 | pbrook | |
3225 | c227f099 | Anthony Liguori | static void rtl8139_mmio_writel(void *opaque, target_phys_addr_t addr, uint32_t val) |
3226 | a41b2ff2 | pbrook | { |
3227 | a41b2ff2 | pbrook | rtl8139_io_writel(opaque, addr & 0xFF, val);
|
3228 | a41b2ff2 | pbrook | } |
3229 | a41b2ff2 | pbrook | |
3230 | c227f099 | Anthony Liguori | static uint32_t rtl8139_mmio_readb(void *opaque, target_phys_addr_t addr) |
3231 | a41b2ff2 | pbrook | { |
3232 | a41b2ff2 | pbrook | return rtl8139_io_readb(opaque, addr & 0xFF); |
3233 | a41b2ff2 | pbrook | } |
3234 | a41b2ff2 | pbrook | |
3235 | c227f099 | Anthony Liguori | static uint32_t rtl8139_mmio_readw(void *opaque, target_phys_addr_t addr) |
3236 | a41b2ff2 | pbrook | { |
3237 | 5fedc612 | aurel32 | uint32_t val = rtl8139_io_readw(opaque, addr & 0xFF);
|
3238 | 5fedc612 | aurel32 | return val;
|
3239 | a41b2ff2 | pbrook | } |
3240 | a41b2ff2 | pbrook | |
3241 | c227f099 | Anthony Liguori | static uint32_t rtl8139_mmio_readl(void *opaque, target_phys_addr_t addr) |
3242 | a41b2ff2 | pbrook | { |
3243 | 5fedc612 | aurel32 | uint32_t val = rtl8139_io_readl(opaque, addr & 0xFF);
|
3244 | 5fedc612 | aurel32 | return val;
|
3245 | a41b2ff2 | pbrook | } |
3246 | a41b2ff2 | pbrook | |
3247 | 060110c3 | Juan Quintela | static int rtl8139_post_load(void *opaque, int version_id) |
3248 | a41b2ff2 | pbrook | { |
3249 | 6597ebbb | Juan Quintela | RTL8139State* s = opaque; |
3250 | 74475455 | Paolo Bonzini | rtl8139_set_next_tctr_time(s, qemu_get_clock_ns(vm_clock)); |
3251 | 060110c3 | Juan Quintela | if (version_id < 4) { |
3252 | 2c3891ab | aliguori | s->cplus_enabled = s->CpCmd != 0;
|
3253 | 2c3891ab | aliguori | } |
3254 | 2c3891ab | aliguori | |
3255 | a41b2ff2 | pbrook | return 0; |
3256 | a41b2ff2 | pbrook | } |
3257 | a41b2ff2 | pbrook | |
3258 | c574ba5a | Alex Williamson | static bool rtl8139_hotplug_ready_needed(void *opaque) |
3259 | c574ba5a | Alex Williamson | { |
3260 | c574ba5a | Alex Williamson | return qdev_machine_modified();
|
3261 | c574ba5a | Alex Williamson | } |
3262 | c574ba5a | Alex Williamson | |
3263 | c574ba5a | Alex Williamson | static const VMStateDescription vmstate_rtl8139_hotplug_ready ={ |
3264 | c574ba5a | Alex Williamson | .name = "rtl8139/hotplug_ready",
|
3265 | c574ba5a | Alex Williamson | .version_id = 1,
|
3266 | c574ba5a | Alex Williamson | .minimum_version_id = 1,
|
3267 | c574ba5a | Alex Williamson | .minimum_version_id_old = 1,
|
3268 | c574ba5a | Alex Williamson | .fields = (VMStateField []) { |
3269 | c574ba5a | Alex Williamson | VMSTATE_END_OF_LIST() |
3270 | c574ba5a | Alex Williamson | } |
3271 | c574ba5a | Alex Williamson | }; |
3272 | c574ba5a | Alex Williamson | |
3273 | 05447803 | Frediano Ziglio | static void rtl8139_pre_save(void *opaque) |
3274 | 05447803 | Frediano Ziglio | { |
3275 | 05447803 | Frediano Ziglio | RTL8139State* s = opaque; |
3276 | 74475455 | Paolo Bonzini | int64_t current_time = qemu_get_clock_ns(vm_clock); |
3277 | 05447803 | Frediano Ziglio | |
3278 | 05447803 | Frediano Ziglio | /* set IntrStatus correctly */
|
3279 | 05447803 | Frediano Ziglio | rtl8139_set_next_tctr_time(s, current_time); |
3280 | 05447803 | Frediano Ziglio | s->TCTR = muldiv64(current_time - s->TCTR_base, PCI_FREQUENCY, |
3281 | 05447803 | Frediano Ziglio | get_ticks_per_sec()); |
3282 | c574ba5a | Alex Williamson | s->rtl8139_mmio_io_addr_dummy = s->rtl8139_mmio_io_addr; |
3283 | 05447803 | Frediano Ziglio | } |
3284 | 05447803 | Frediano Ziglio | |
3285 | 060110c3 | Juan Quintela | static const VMStateDescription vmstate_rtl8139 = { |
3286 | 060110c3 | Juan Quintela | .name = "rtl8139",
|
3287 | 060110c3 | Juan Quintela | .version_id = 4,
|
3288 | 060110c3 | Juan Quintela | .minimum_version_id = 3,
|
3289 | 060110c3 | Juan Quintela | .minimum_version_id_old = 3,
|
3290 | 060110c3 | Juan Quintela | .post_load = rtl8139_post_load, |
3291 | 05447803 | Frediano Ziglio | .pre_save = rtl8139_pre_save, |
3292 | 060110c3 | Juan Quintela | .fields = (VMStateField []) { |
3293 | 060110c3 | Juan Quintela | VMSTATE_PCI_DEVICE(dev, RTL8139State), |
3294 | 060110c3 | Juan Quintela | VMSTATE_PARTIAL_BUFFER(phys, RTL8139State, 6),
|
3295 | 060110c3 | Juan Quintela | VMSTATE_BUFFER(mult, RTL8139State), |
3296 | 060110c3 | Juan Quintela | VMSTATE_UINT32_ARRAY(TxStatus, RTL8139State, 4),
|
3297 | 060110c3 | Juan Quintela | VMSTATE_UINT32_ARRAY(TxAddr, RTL8139State, 4),
|
3298 | 060110c3 | Juan Quintela | |
3299 | 060110c3 | Juan Quintela | VMSTATE_UINT32(RxBuf, RTL8139State), |
3300 | 060110c3 | Juan Quintela | VMSTATE_UINT32(RxBufferSize, RTL8139State), |
3301 | 060110c3 | Juan Quintela | VMSTATE_UINT32(RxBufPtr, RTL8139State), |
3302 | 060110c3 | Juan Quintela | VMSTATE_UINT32(RxBufAddr, RTL8139State), |
3303 | 060110c3 | Juan Quintela | |
3304 | 060110c3 | Juan Quintela | VMSTATE_UINT16(IntrStatus, RTL8139State), |
3305 | 060110c3 | Juan Quintela | VMSTATE_UINT16(IntrMask, RTL8139State), |
3306 | 060110c3 | Juan Quintela | |
3307 | 060110c3 | Juan Quintela | VMSTATE_UINT32(TxConfig, RTL8139State), |
3308 | 060110c3 | Juan Quintela | VMSTATE_UINT32(RxConfig, RTL8139State), |
3309 | 060110c3 | Juan Quintela | VMSTATE_UINT32(RxMissed, RTL8139State), |
3310 | 060110c3 | Juan Quintela | VMSTATE_UINT16(CSCR, RTL8139State), |
3311 | 060110c3 | Juan Quintela | |
3312 | 060110c3 | Juan Quintela | VMSTATE_UINT8(Cfg9346, RTL8139State), |
3313 | 060110c3 | Juan Quintela | VMSTATE_UINT8(Config0, RTL8139State), |
3314 | 060110c3 | Juan Quintela | VMSTATE_UINT8(Config1, RTL8139State), |
3315 | 060110c3 | Juan Quintela | VMSTATE_UINT8(Config3, RTL8139State), |
3316 | 060110c3 | Juan Quintela | VMSTATE_UINT8(Config4, RTL8139State), |
3317 | 060110c3 | Juan Quintela | VMSTATE_UINT8(Config5, RTL8139State), |
3318 | 060110c3 | Juan Quintela | |
3319 | 060110c3 | Juan Quintela | VMSTATE_UINT8(clock_enabled, RTL8139State), |
3320 | 060110c3 | Juan Quintela | VMSTATE_UINT8(bChipCmdState, RTL8139State), |
3321 | 060110c3 | Juan Quintela | |
3322 | 060110c3 | Juan Quintela | VMSTATE_UINT16(MultiIntr, RTL8139State), |
3323 | 060110c3 | Juan Quintela | |
3324 | 060110c3 | Juan Quintela | VMSTATE_UINT16(BasicModeCtrl, RTL8139State), |
3325 | 060110c3 | Juan Quintela | VMSTATE_UINT16(BasicModeStatus, RTL8139State), |
3326 | 060110c3 | Juan Quintela | VMSTATE_UINT16(NWayAdvert, RTL8139State), |
3327 | 060110c3 | Juan Quintela | VMSTATE_UINT16(NWayLPAR, RTL8139State), |
3328 | 060110c3 | Juan Quintela | VMSTATE_UINT16(NWayExpansion, RTL8139State), |
3329 | 060110c3 | Juan Quintela | |
3330 | 060110c3 | Juan Quintela | VMSTATE_UINT16(CpCmd, RTL8139State), |
3331 | 060110c3 | Juan Quintela | VMSTATE_UINT8(TxThresh, RTL8139State), |
3332 | 060110c3 | Juan Quintela | |
3333 | 060110c3 | Juan Quintela | VMSTATE_UNUSED(4),
|
3334 | 060110c3 | Juan Quintela | VMSTATE_MACADDR(conf.macaddr, RTL8139State), |
3335 | c574ba5a | Alex Williamson | VMSTATE_INT32(rtl8139_mmio_io_addr_dummy, RTL8139State), |
3336 | 060110c3 | Juan Quintela | |
3337 | 060110c3 | Juan Quintela | VMSTATE_UINT32(currTxDesc, RTL8139State), |
3338 | 060110c3 | Juan Quintela | VMSTATE_UINT32(currCPlusRxDesc, RTL8139State), |
3339 | 060110c3 | Juan Quintela | VMSTATE_UINT32(currCPlusTxDesc, RTL8139State), |
3340 | 060110c3 | Juan Quintela | VMSTATE_UINT32(RxRingAddrLO, RTL8139State), |
3341 | 060110c3 | Juan Quintela | VMSTATE_UINT32(RxRingAddrHI, RTL8139State), |
3342 | 060110c3 | Juan Quintela | |
3343 | 060110c3 | Juan Quintela | VMSTATE_UINT16_ARRAY(eeprom.contents, RTL8139State, EEPROM_9346_SIZE), |
3344 | 060110c3 | Juan Quintela | VMSTATE_INT32(eeprom.mode, RTL8139State), |
3345 | 060110c3 | Juan Quintela | VMSTATE_UINT32(eeprom.tick, RTL8139State), |
3346 | 060110c3 | Juan Quintela | VMSTATE_UINT8(eeprom.address, RTL8139State), |
3347 | 060110c3 | Juan Quintela | VMSTATE_UINT16(eeprom.input, RTL8139State), |
3348 | 060110c3 | Juan Quintela | VMSTATE_UINT16(eeprom.output, RTL8139State), |
3349 | 060110c3 | Juan Quintela | |
3350 | 060110c3 | Juan Quintela | VMSTATE_UINT8(eeprom.eecs, RTL8139State), |
3351 | 060110c3 | Juan Quintela | VMSTATE_UINT8(eeprom.eesk, RTL8139State), |
3352 | 060110c3 | Juan Quintela | VMSTATE_UINT8(eeprom.eedi, RTL8139State), |
3353 | 060110c3 | Juan Quintela | VMSTATE_UINT8(eeprom.eedo, RTL8139State), |
3354 | 060110c3 | Juan Quintela | |
3355 | 060110c3 | Juan Quintela | VMSTATE_UINT32(TCTR, RTL8139State), |
3356 | 060110c3 | Juan Quintela | VMSTATE_UINT32(TimerInt, RTL8139State), |
3357 | 060110c3 | Juan Quintela | VMSTATE_INT64(TCTR_base, RTL8139State), |
3358 | 060110c3 | Juan Quintela | |
3359 | 060110c3 | Juan Quintela | VMSTATE_STRUCT(tally_counters, RTL8139State, 0,
|
3360 | 060110c3 | Juan Quintela | vmstate_tally_counters, RTL8139TallyCounters), |
3361 | 060110c3 | Juan Quintela | |
3362 | 060110c3 | Juan Quintela | VMSTATE_UINT32_V(cplus_enabled, RTL8139State, 4),
|
3363 | 060110c3 | Juan Quintela | VMSTATE_END_OF_LIST() |
3364 | c574ba5a | Alex Williamson | }, |
3365 | c574ba5a | Alex Williamson | .subsections = (VMStateSubsection []) { |
3366 | c574ba5a | Alex Williamson | { |
3367 | c574ba5a | Alex Williamson | .vmsd = &vmstate_rtl8139_hotplug_ready, |
3368 | c574ba5a | Alex Williamson | .needed = rtl8139_hotplug_ready_needed, |
3369 | c574ba5a | Alex Williamson | }, { |
3370 | c574ba5a | Alex Williamson | /* empty */
|
3371 | c574ba5a | Alex Williamson | } |
3372 | 060110c3 | Juan Quintela | } |
3373 | 060110c3 | Juan Quintela | }; |
3374 | 060110c3 | Juan Quintela | |
3375 | a41b2ff2 | pbrook | /***********************************************************/
|
3376 | a41b2ff2 | pbrook | /* PCI RTL8139 definitions */
|
3377 | a41b2ff2 | pbrook | |
3378 | 5fafdf24 | ths | static void rtl8139_ioport_map(PCIDevice *pci_dev, int region_num, |
3379 | 6e355d90 | Isaku Yamahata | pcibus_t addr, pcibus_t size, int type)
|
3380 | a41b2ff2 | pbrook | { |
3381 | efd6dd45 | Juan Quintela | RTL8139State *s = DO_UPCAST(RTL8139State, dev, pci_dev); |
3382 | a41b2ff2 | pbrook | |
3383 | a41b2ff2 | pbrook | register_ioport_write(addr, 0x100, 1, rtl8139_ioport_writeb, s); |
3384 | a41b2ff2 | pbrook | register_ioport_read( addr, 0x100, 1, rtl8139_ioport_readb, s); |
3385 | a41b2ff2 | pbrook | |
3386 | a41b2ff2 | pbrook | register_ioport_write(addr, 0x100, 2, rtl8139_ioport_writew, s); |
3387 | a41b2ff2 | pbrook | register_ioport_read( addr, 0x100, 2, rtl8139_ioport_readw, s); |
3388 | a41b2ff2 | pbrook | |
3389 | a41b2ff2 | pbrook | register_ioport_write(addr, 0x100, 4, rtl8139_ioport_writel, s); |
3390 | a41b2ff2 | pbrook | register_ioport_read( addr, 0x100, 4, rtl8139_ioport_readl, s); |
3391 | a41b2ff2 | pbrook | } |
3392 | a41b2ff2 | pbrook | |
3393 | d60efc6b | Blue Swirl | static CPUReadMemoryFunc * const rtl8139_mmio_read[3] = { |
3394 | a41b2ff2 | pbrook | rtl8139_mmio_readb, |
3395 | a41b2ff2 | pbrook | rtl8139_mmio_readw, |
3396 | a41b2ff2 | pbrook | rtl8139_mmio_readl, |
3397 | a41b2ff2 | pbrook | }; |
3398 | a41b2ff2 | pbrook | |
3399 | d60efc6b | Blue Swirl | static CPUWriteMemoryFunc * const rtl8139_mmio_write[3] = { |
3400 | a41b2ff2 | pbrook | rtl8139_mmio_writeb, |
3401 | a41b2ff2 | pbrook | rtl8139_mmio_writew, |
3402 | a41b2ff2 | pbrook | rtl8139_mmio_writel, |
3403 | a41b2ff2 | pbrook | }; |
3404 | a41b2ff2 | pbrook | |
3405 | 6cadb320 | bellard | static void rtl8139_timer(void *opaque) |
3406 | 6cadb320 | bellard | { |
3407 | 6cadb320 | bellard | RTL8139State *s = opaque; |
3408 | 6cadb320 | bellard | |
3409 | 6cadb320 | bellard | if (!s->clock_enabled)
|
3410 | 6cadb320 | bellard | { |
3411 | 7cdeb319 | Benjamin Poirier | DPRINTF(">>> timer: clock is not running\n");
|
3412 | 6cadb320 | bellard | return;
|
3413 | 6cadb320 | bellard | } |
3414 | 6cadb320 | bellard | |
3415 | 05447803 | Frediano Ziglio | s->IntrStatus |= PCSTimeout; |
3416 | 05447803 | Frediano Ziglio | rtl8139_update_irq(s); |
3417 | 74475455 | Paolo Bonzini | rtl8139_set_next_tctr_time(s, qemu_get_clock_ns(vm_clock)); |
3418 | 6cadb320 | bellard | } |
3419 | 6cadb320 | bellard | |
3420 | 1673ad51 | Mark McLoughlin | static void rtl8139_cleanup(VLANClientState *nc) |
3421 | b946a153 | aliguori | { |
3422 | 1673ad51 | Mark McLoughlin | RTL8139State *s = DO_UPCAST(NICState, nc, nc)->opaque; |
3423 | b946a153 | aliguori | |
3424 | 1673ad51 | Mark McLoughlin | s->nic = NULL;
|
3425 | 254111ec | Gerd Hoffmann | } |
3426 | 254111ec | Gerd Hoffmann | |
3427 | 254111ec | Gerd Hoffmann | static int pci_rtl8139_uninit(PCIDevice *dev) |
3428 | 254111ec | Gerd Hoffmann | { |
3429 | 254111ec | Gerd Hoffmann | RTL8139State *s = DO_UPCAST(RTL8139State, dev, dev); |
3430 | 254111ec | Gerd Hoffmann | |
3431 | 254111ec | Gerd Hoffmann | cpu_unregister_io_memory(s->rtl8139_mmio_io_addr); |
3432 | b946a153 | aliguori | if (s->cplus_txbuffer) {
|
3433 | b946a153 | aliguori | qemu_free(s->cplus_txbuffer); |
3434 | b946a153 | aliguori | s->cplus_txbuffer = NULL;
|
3435 | b946a153 | aliguori | } |
3436 | b946a153 | aliguori | qemu_del_timer(s->timer); |
3437 | b946a153 | aliguori | qemu_free_timer(s->timer); |
3438 | 1673ad51 | Mark McLoughlin | qemu_del_vlan_client(&s->nic->nc); |
3439 | b946a153 | aliguori | return 0; |
3440 | b946a153 | aliguori | } |
3441 | b946a153 | aliguori | |
3442 | 1673ad51 | Mark McLoughlin | static NetClientInfo net_rtl8139_info = {
|
3443 | 1673ad51 | Mark McLoughlin | .type = NET_CLIENT_TYPE_NIC, |
3444 | 1673ad51 | Mark McLoughlin | .size = sizeof(NICState),
|
3445 | 1673ad51 | Mark McLoughlin | .can_receive = rtl8139_can_receive, |
3446 | 1673ad51 | Mark McLoughlin | .receive = rtl8139_receive, |
3447 | 1673ad51 | Mark McLoughlin | .cleanup = rtl8139_cleanup, |
3448 | 1673ad51 | Mark McLoughlin | }; |
3449 | 1673ad51 | Mark McLoughlin | |
3450 | 81a322d4 | Gerd Hoffmann | static int pci_rtl8139_init(PCIDevice *dev) |
3451 | a41b2ff2 | pbrook | { |
3452 | efd6dd45 | Juan Quintela | RTL8139State * s = DO_UPCAST(RTL8139State, dev, dev); |
3453 | a41b2ff2 | pbrook | uint8_t *pci_conf; |
3454 | 3b46e624 | ths | |
3455 | efd6dd45 | Juan Quintela | pci_conf = s->dev.config; |
3456 | 0b5b3547 | Michael S. Tsirkin | pci_conf[PCI_INTERRUPT_PIN] = 1; /* interrupt pin 0 */ |
3457 | 0b5b3547 | Michael S. Tsirkin | /* TODO: start of capability list, but no capability
|
3458 | 0b5b3547 | Michael S. Tsirkin | * list bit in status register, and offset 0xdc seems unused. */
|
3459 | 0b5b3547 | Michael S. Tsirkin | pci_conf[PCI_CAPABILITY_LIST] = 0xdc;
|
3460 | a41b2ff2 | pbrook | |
3461 | a41b2ff2 | pbrook | /* I/O handler for memory-mapped I/O */
|
3462 | a41b2ff2 | pbrook | s->rtl8139_mmio_io_addr = |
3463 | 2507c12a | Alexander Graf | cpu_register_io_memory(rtl8139_mmio_read, rtl8139_mmio_write, s, |
3464 | 5cf7a3ca | Alexander Graf | DEVICE_LITTLE_ENDIAN); |
3465 | a41b2ff2 | pbrook | |
3466 | efd6dd45 | Juan Quintela | pci_register_bar(&s->dev, 0, 0x100, |
3467 | 0392a017 | Isaku Yamahata | PCI_BASE_ADDRESS_SPACE_IO, rtl8139_ioport_map); |
3468 | a41b2ff2 | pbrook | |
3469 | f5de212c | Avi Kivity | pci_register_bar_simple(&s->dev, 1, 0x100, 0, s->rtl8139_mmio_io_addr); |
3470 | a41b2ff2 | pbrook | |
3471 | 254111ec | Gerd Hoffmann | qemu_macaddr_default_if_unset(&s->conf.macaddr); |
3472 | c1699988 | Glauber Costa | |
3473 | 7165448a | William Dauchy | /* prepare eeprom */
|
3474 | 7165448a | William Dauchy | s->eeprom.contents[0] = 0x8129; |
3475 | 7165448a | William Dauchy | #if 1 |
3476 | 7165448a | William Dauchy | /* PCI vendor and device ID should be mirrored here */
|
3477 | 7165448a | William Dauchy | s->eeprom.contents[1] = PCI_VENDOR_ID_REALTEK;
|
3478 | 7165448a | William Dauchy | s->eeprom.contents[2] = PCI_DEVICE_ID_REALTEK_8139;
|
3479 | 7165448a | William Dauchy | #endif
|
3480 | 7165448a | William Dauchy | s->eeprom.contents[7] = s->conf.macaddr.a[0] | s->conf.macaddr.a[1] << 8; |
3481 | 7165448a | William Dauchy | s->eeprom.contents[8] = s->conf.macaddr.a[2] | s->conf.macaddr.a[3] << 8; |
3482 | 7165448a | William Dauchy | s->eeprom.contents[9] = s->conf.macaddr.a[4] | s->conf.macaddr.a[5] << 8; |
3483 | 7165448a | William Dauchy | |
3484 | 1673ad51 | Mark McLoughlin | s->nic = qemu_new_nic(&net_rtl8139_info, &s->conf, |
3485 | 1673ad51 | Mark McLoughlin | dev->qdev.info->name, dev->qdev.id, s); |
3486 | 1673ad51 | Mark McLoughlin | qemu_format_nic_info_str(&s->nic->nc, s->conf.macaddr.a); |
3487 | 6cadb320 | bellard | |
3488 | 6cadb320 | bellard | s->cplus_txbuffer = NULL;
|
3489 | 6cadb320 | bellard | s->cplus_txbuffer_len = 0;
|
3490 | 6cadb320 | bellard | s->cplus_txbuffer_offset = 0;
|
3491 | 3b46e624 | ths | |
3492 | 05447803 | Frediano Ziglio | s->TimerExpire = 0;
|
3493 | 74475455 | Paolo Bonzini | s->timer = qemu_new_timer_ns(vm_clock, rtl8139_timer, s); |
3494 | 74475455 | Paolo Bonzini | rtl8139_set_next_tctr_time(s, qemu_get_clock_ns(vm_clock)); |
3495 | 1ca4d09a | Gleb Natapov | |
3496 | 1ca4d09a | Gleb Natapov | add_boot_device_path(s->conf.bootindex, &dev->qdev, "/ethernet-phy@0");
|
3497 | 1ca4d09a | Gleb Natapov | |
3498 | 81a322d4 | Gerd Hoffmann | return 0; |
3499 | a41b2ff2 | pbrook | } |
3500 | 9d07d757 | Paul Brook | |
3501 | 0aab0d3a | Gerd Hoffmann | static PCIDeviceInfo rtl8139_info = {
|
3502 | f82de8f0 | Gerd Hoffmann | .qdev.name = "rtl8139",
|
3503 | f82de8f0 | Gerd Hoffmann | .qdev.size = sizeof(RTL8139State),
|
3504 | f82de8f0 | Gerd Hoffmann | .qdev.reset = rtl8139_reset, |
3505 | be73cfe2 | Juan Quintela | .qdev.vmsd = &vmstate_rtl8139, |
3506 | f82de8f0 | Gerd Hoffmann | .init = pci_rtl8139_init, |
3507 | e3936fa5 | Gerd Hoffmann | .exit = pci_rtl8139_uninit, |
3508 | 5ee8ad71 | Alex Williamson | .romfile = "pxe-rtl8139.rom",
|
3509 | 7cba16a7 | Isaku Yamahata | .vendor_id = PCI_VENDOR_ID_REALTEK, |
3510 | 7cba16a7 | Isaku Yamahata | .device_id = PCI_DEVICE_ID_REALTEK_8139, |
3511 | 7cba16a7 | Isaku Yamahata | .revision = RTL8139_PCI_REVID, /* >=0x20 is for 8139C+ */
|
3512 | 7cba16a7 | Isaku Yamahata | .class_id = PCI_CLASS_NETWORK_ETHERNET, |
3513 | 254111ec | Gerd Hoffmann | .qdev.props = (Property[]) { |
3514 | 254111ec | Gerd Hoffmann | DEFINE_NIC_PROPERTIES(RTL8139State, conf), |
3515 | 254111ec | Gerd Hoffmann | DEFINE_PROP_END_OF_LIST(), |
3516 | 254111ec | Gerd Hoffmann | } |
3517 | 0aab0d3a | Gerd Hoffmann | }; |
3518 | 0aab0d3a | Gerd Hoffmann | |
3519 | 9d07d757 | Paul Brook | static void rtl8139_register_devices(void) |
3520 | 9d07d757 | Paul Brook | { |
3521 | 0aab0d3a | Gerd Hoffmann | pci_qdev_register(&rtl8139_info); |
3522 | 9d07d757 | Paul Brook | } |
3523 | 9d07d757 | Paul Brook | |
3524 | 9d07d757 | Paul Brook | device_init(rtl8139_register_devices) |