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1 | d4e8164f | bellard | /*
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2 | d4e8164f | bellard | * internal execution defines for qemu
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3 | d4e8164f | bellard | *
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4 | d4e8164f | bellard | * Copyright (c) 2003 Fabrice Bellard
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5 | d4e8164f | bellard | *
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6 | d4e8164f | bellard | * This library is free software; you can redistribute it and/or
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7 | d4e8164f | bellard | * modify it under the terms of the GNU Lesser General Public
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8 | d4e8164f | bellard | * License as published by the Free Software Foundation; either
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9 | d4e8164f | bellard | * version 2 of the License, or (at your option) any later version.
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10 | d4e8164f | bellard | *
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11 | d4e8164f | bellard | * This library is distributed in the hope that it will be useful,
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12 | d4e8164f | bellard | * but WITHOUT ANY WARRANTY; without even the implied warranty of
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13 | d4e8164f | bellard | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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14 | d4e8164f | bellard | * Lesser General Public License for more details.
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15 | d4e8164f | bellard | *
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16 | d4e8164f | bellard | * You should have received a copy of the GNU Lesser General Public
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17 | d4e8164f | bellard | * License along with this library; if not, write to the Free Software
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18 | d4e8164f | bellard | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
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19 | d4e8164f | bellard | */
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20 | d4e8164f | bellard | |
21 | b346ff46 | bellard | /* allow to see translation results - the slowdown should be negligible, so we leave it */
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22 | b346ff46 | bellard | #define DEBUG_DISAS
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23 | b346ff46 | bellard | |
24 | 33417e70 | bellard | #ifndef glue
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25 | 33417e70 | bellard | #define xglue(x, y) x ## y |
26 | 33417e70 | bellard | #define glue(x, y) xglue(x, y)
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27 | 33417e70 | bellard | #define stringify(s) tostring(s)
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28 | 33417e70 | bellard | #define tostring(s) #s |
29 | 33417e70 | bellard | #endif
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30 | 33417e70 | bellard | |
31 | 33417e70 | bellard | #if GCC_MAJOR < 3 |
32 | 33417e70 | bellard | #define __builtin_expect(x, n) (x)
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33 | 33417e70 | bellard | #endif
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34 | 33417e70 | bellard | |
35 | e2222c39 | bellard | #ifdef __i386__
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36 | e2222c39 | bellard | #define REGPARM(n) __attribute((regparm(n)))
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37 | e2222c39 | bellard | #else
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38 | e2222c39 | bellard | #define REGPARM(n)
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39 | e2222c39 | bellard | #endif
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40 | e2222c39 | bellard | |
41 | b346ff46 | bellard | /* is_jmp field values */
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42 | b346ff46 | bellard | #define DISAS_NEXT 0 /* next instruction can be analyzed */ |
43 | b346ff46 | bellard | #define DISAS_JUMP 1 /* only pc was modified dynamically */ |
44 | b346ff46 | bellard | #define DISAS_UPDATE 2 /* cpu state was modified dynamically */ |
45 | b346ff46 | bellard | #define DISAS_TB_JUMP 3 /* only pc was modified statically */ |
46 | b346ff46 | bellard | |
47 | b346ff46 | bellard | struct TranslationBlock;
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48 | b346ff46 | bellard | |
49 | b346ff46 | bellard | /* XXX: make safe guess about sizes */
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50 | b346ff46 | bellard | #define MAX_OP_PER_INSTR 32 |
51 | b346ff46 | bellard | #define OPC_BUF_SIZE 512 |
52 | b346ff46 | bellard | #define OPC_MAX_SIZE (OPC_BUF_SIZE - MAX_OP_PER_INSTR)
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53 | b346ff46 | bellard | |
54 | b346ff46 | bellard | #define OPPARAM_BUF_SIZE (OPC_BUF_SIZE * 3) |
55 | b346ff46 | bellard | |
56 | b346ff46 | bellard | extern uint16_t gen_opc_buf[OPC_BUF_SIZE];
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57 | b346ff46 | bellard | extern uint32_t gen_opparam_buf[OPPARAM_BUF_SIZE];
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58 | c27004ec | bellard | extern long gen_labels[OPC_BUF_SIZE]; |
59 | c27004ec | bellard | extern int nb_gen_labels; |
60 | c27004ec | bellard | extern target_ulong gen_opc_pc[OPC_BUF_SIZE];
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61 | c27004ec | bellard | extern target_ulong gen_opc_npc[OPC_BUF_SIZE];
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62 | 66e85a21 | bellard | extern uint8_t gen_opc_cc_op[OPC_BUF_SIZE];
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63 | b346ff46 | bellard | extern uint8_t gen_opc_instr_start[OPC_BUF_SIZE];
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64 | b346ff46 | bellard | |
65 | 9886cc16 | bellard | typedef void (GenOpFunc)(void); |
66 | 9886cc16 | bellard | typedef void (GenOpFunc1)(long); |
67 | 9886cc16 | bellard | typedef void (GenOpFunc2)(long, long); |
68 | 9886cc16 | bellard | typedef void (GenOpFunc3)(long, long, long); |
69 | 9886cc16 | bellard | |
70 | b346ff46 | bellard | #if defined(TARGET_I386)
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71 | b346ff46 | bellard | |
72 | 33417e70 | bellard | void optimize_flags_init(void); |
73 | d4e8164f | bellard | |
74 | b346ff46 | bellard | #endif
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75 | b346ff46 | bellard | |
76 | b346ff46 | bellard | extern FILE *logfile;
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77 | b346ff46 | bellard | extern int loglevel; |
78 | b346ff46 | bellard | |
79 | 4c3a88a2 | bellard | int gen_intermediate_code(CPUState *env, struct TranslationBlock *tb); |
80 | 4c3a88a2 | bellard | int gen_intermediate_code_pc(CPUState *env, struct TranslationBlock *tb); |
81 | b346ff46 | bellard | void dump_ops(const uint16_t *opc_buf, const uint32_t *opparam_buf); |
82 | 4c3a88a2 | bellard | int cpu_gen_code(CPUState *env, struct TranslationBlock *tb, |
83 | b346ff46 | bellard | int max_code_size, int *gen_code_size_ptr); |
84 | 66e85a21 | bellard | int cpu_restore_state(struct TranslationBlock *tb, |
85 | 58fe2f10 | bellard | CPUState *env, unsigned long searched_pc, |
86 | 58fe2f10 | bellard | void *puc);
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87 | 58fe2f10 | bellard | int cpu_gen_code_copy(CPUState *env, struct TranslationBlock *tb, |
88 | 58fe2f10 | bellard | int max_code_size, int *gen_code_size_ptr); |
89 | 58fe2f10 | bellard | int cpu_restore_state_copy(struct TranslationBlock *tb, |
90 | 58fe2f10 | bellard | CPUState *env, unsigned long searched_pc, |
91 | 58fe2f10 | bellard | void *puc);
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92 | 2e12669a | bellard | void cpu_resume_from_signal(CPUState *env1, void *puc); |
93 | b346ff46 | bellard | void cpu_exec_init(void); |
94 | 2e12669a | bellard | int page_unprotect(unsigned long address, unsigned long pc, void *puc); |
95 | 2e12669a | bellard | void tb_invalidate_phys_page_range(target_ulong start, target_ulong end,
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96 | 2e12669a | bellard | int is_cpu_write_access);
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97 | 4390df51 | bellard | void tb_invalidate_page_range(target_ulong start, target_ulong end);
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98 | 2e12669a | bellard | void tlb_flush_page(CPUState *env, target_ulong addr);
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99 | ee8b7021 | bellard | void tlb_flush(CPUState *env, int flush_global); |
100 | 2e12669a | bellard | int tlb_set_page(CPUState *env, target_ulong vaddr,
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101 | 2e12669a | bellard | target_phys_addr_t paddr, int prot,
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102 | 4390df51 | bellard | int is_user, int is_softmmu); |
103 | d4e8164f | bellard | |
104 | d4e8164f | bellard | #define CODE_GEN_MAX_SIZE 65536 |
105 | d4e8164f | bellard | #define CODE_GEN_ALIGN 16 /* must be >= of the size of a icache line */ |
106 | d4e8164f | bellard | |
107 | d4e8164f | bellard | #define CODE_GEN_HASH_BITS 15 |
108 | d4e8164f | bellard | #define CODE_GEN_HASH_SIZE (1 << CODE_GEN_HASH_BITS) |
109 | d4e8164f | bellard | |
110 | 4390df51 | bellard | #define CODE_GEN_PHYS_HASH_BITS 15 |
111 | 4390df51 | bellard | #define CODE_GEN_PHYS_HASH_SIZE (1 << CODE_GEN_PHYS_HASH_BITS) |
112 | 4390df51 | bellard | |
113 | d4e8164f | bellard | /* maximum total translate dcode allocated */
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114 | 4390df51 | bellard | |
115 | 4390df51 | bellard | /* NOTE: the translated code area cannot be too big because on some
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116 | c4c7e3e6 | bellard | archs the range of "fast" function calls is limited. Here is a
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117 | 4390df51 | bellard | summary of the ranges:
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118 | 4390df51 | bellard | |
119 | 4390df51 | bellard | i386 : signed 32 bits
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120 | 4390df51 | bellard | arm : signed 26 bits
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121 | 4390df51 | bellard | ppc : signed 24 bits
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122 | 4390df51 | bellard | sparc : signed 32 bits
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123 | 4390df51 | bellard | alpha : signed 23 bits
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124 | 4390df51 | bellard | */
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125 | 4390df51 | bellard | |
126 | 4390df51 | bellard | #if defined(__alpha__)
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127 | 4390df51 | bellard | #define CODE_GEN_BUFFER_SIZE (2 * 1024 * 1024) |
128 | 4390df51 | bellard | #elif defined(__powerpc__)
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129 | c4c7e3e6 | bellard | #define CODE_GEN_BUFFER_SIZE (6 * 1024 * 1024) |
130 | 4390df51 | bellard | #else
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131 | 4390df51 | bellard | #define CODE_GEN_BUFFER_SIZE (8 * 1024 * 1024) |
132 | 4390df51 | bellard | #endif
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133 | 4390df51 | bellard | |
134 | d4e8164f | bellard | //#define CODE_GEN_BUFFER_SIZE (128 * 1024)
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135 | d4e8164f | bellard | |
136 | 4390df51 | bellard | /* estimated block size for TB allocation */
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137 | 4390df51 | bellard | /* XXX: use a per code average code fragment size and modulate it
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138 | 4390df51 | bellard | according to the host CPU */
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139 | 4390df51 | bellard | #if defined(CONFIG_SOFTMMU)
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140 | 4390df51 | bellard | #define CODE_GEN_AVG_BLOCK_SIZE 128 |
141 | 4390df51 | bellard | #else
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142 | 4390df51 | bellard | #define CODE_GEN_AVG_BLOCK_SIZE 64 |
143 | 4390df51 | bellard | #endif
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144 | 4390df51 | bellard | |
145 | 4390df51 | bellard | #define CODE_GEN_MAX_BLOCKS (CODE_GEN_BUFFER_SIZE / CODE_GEN_AVG_BLOCK_SIZE)
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146 | 4390df51 | bellard | |
147 | 4390df51 | bellard | #if defined(__powerpc__)
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148 | 4390df51 | bellard | #define USE_DIRECT_JUMP
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149 | 4390df51 | bellard | #endif
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150 | 67b915a5 | bellard | #if defined(__i386__) && !defined(_WIN32)
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151 | d4e8164f | bellard | #define USE_DIRECT_JUMP
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152 | d4e8164f | bellard | #endif
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153 | d4e8164f | bellard | |
154 | d4e8164f | bellard | typedef struct TranslationBlock { |
155 | 2e12669a | bellard | target_ulong pc; /* simulated PC corresponding to this block (EIP + CS base) */
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156 | 2e12669a | bellard | target_ulong cs_base; /* CS base for this block */
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157 | d4e8164f | bellard | unsigned int flags; /* flags defining in which context the code was generated */ |
158 | d4e8164f | bellard | uint16_t size; /* size of target code for this block (1 <=
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159 | d4e8164f | bellard | size <= TARGET_PAGE_SIZE) */
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160 | 58fe2f10 | bellard | uint16_t cflags; /* compile flags */
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161 | bf088061 | bellard | #define CF_CODE_COPY 0x0001 /* block was generated in code copy mode */ |
162 | bf088061 | bellard | #define CF_TB_FP_USED 0x0002 /* fp ops are used in the TB */ |
163 | bf088061 | bellard | #define CF_FP_USED 0x0004 /* fp ops are used in the TB or in a chained TB */ |
164 | 2e12669a | bellard | #define CF_SINGLE_INSN 0x0008 /* compile only a single instruction */ |
165 | 58fe2f10 | bellard | |
166 | d4e8164f | bellard | uint8_t *tc_ptr; /* pointer to the translated code */
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167 | 4390df51 | bellard | struct TranslationBlock *hash_next; /* next matching tb for virtual address */ |
168 | 4390df51 | bellard | /* next matching tb for physical address. */
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169 | 4390df51 | bellard | struct TranslationBlock *phys_hash_next;
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170 | 4390df51 | bellard | /* first and second physical page containing code. The lower bit
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171 | 4390df51 | bellard | of the pointer tells the index in page_next[] */
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172 | 4390df51 | bellard | struct TranslationBlock *page_next[2]; |
173 | 4390df51 | bellard | target_ulong page_addr[2];
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174 | 4390df51 | bellard | |
175 | d4e8164f | bellard | /* the following data are used to directly call another TB from
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176 | d4e8164f | bellard | the code of this one. */
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177 | d4e8164f | bellard | uint16_t tb_next_offset[2]; /* offset of original jump target */ |
178 | d4e8164f | bellard | #ifdef USE_DIRECT_JUMP
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179 | 4cbb86e1 | bellard | uint16_t tb_jmp_offset[4]; /* offset of jump instruction */ |
180 | d4e8164f | bellard | #else
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181 | 95f7652d | bellard | uint32_t tb_next[2]; /* address of jump generated code */ |
182 | d4e8164f | bellard | #endif
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183 | d4e8164f | bellard | /* list of TBs jumping to this one. This is a circular list using
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184 | d4e8164f | bellard | the two least significant bits of the pointers to tell what is
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185 | d4e8164f | bellard | the next pointer: 0 = jmp_next[0], 1 = jmp_next[1], 2 =
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186 | d4e8164f | bellard | jmp_first */
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187 | d4e8164f | bellard | struct TranslationBlock *jmp_next[2]; |
188 | d4e8164f | bellard | struct TranslationBlock *jmp_first;
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189 | d4e8164f | bellard | } TranslationBlock; |
190 | d4e8164f | bellard | |
191 | c27004ec | bellard | static inline unsigned int tb_hash_func(target_ulong pc) |
192 | d4e8164f | bellard | { |
193 | d4e8164f | bellard | return pc & (CODE_GEN_HASH_SIZE - 1); |
194 | d4e8164f | bellard | } |
195 | d4e8164f | bellard | |
196 | 4390df51 | bellard | static inline unsigned int tb_phys_hash_func(unsigned long pc) |
197 | 4390df51 | bellard | { |
198 | 4390df51 | bellard | return pc & (CODE_GEN_PHYS_HASH_SIZE - 1); |
199 | 4390df51 | bellard | } |
200 | 4390df51 | bellard | |
201 | c27004ec | bellard | TranslationBlock *tb_alloc(target_ulong pc); |
202 | 0124311e | bellard | void tb_flush(CPUState *env);
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203 | d4e8164f | bellard | void tb_link(TranslationBlock *tb);
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204 | 4390df51 | bellard | void tb_link_phys(TranslationBlock *tb,
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205 | 4390df51 | bellard | target_ulong phys_pc, target_ulong phys_page2); |
206 | d4e8164f | bellard | |
207 | d4e8164f | bellard | extern TranslationBlock *tb_hash[CODE_GEN_HASH_SIZE];
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208 | 4390df51 | bellard | extern TranslationBlock *tb_phys_hash[CODE_GEN_PHYS_HASH_SIZE];
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209 | d4e8164f | bellard | |
210 | d4e8164f | bellard | extern uint8_t code_gen_buffer[CODE_GEN_BUFFER_SIZE];
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211 | d4e8164f | bellard | extern uint8_t *code_gen_ptr;
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212 | d4e8164f | bellard | |
213 | d4e8164f | bellard | /* find a translation block in the translation cache. If not found,
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214 | d4e8164f | bellard | return NULL and the pointer to the last element of the list in pptb */
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215 | d4e8164f | bellard | static inline TranslationBlock *tb_find(TranslationBlock ***pptb, |
216 | 2e12669a | bellard | target_ulong pc, |
217 | 2e12669a | bellard | target_ulong cs_base, |
218 | d4e8164f | bellard | unsigned int flags) |
219 | d4e8164f | bellard | { |
220 | d4e8164f | bellard | TranslationBlock **ptb, *tb; |
221 | d4e8164f | bellard | unsigned int h; |
222 | d4e8164f | bellard | |
223 | d4e8164f | bellard | h = tb_hash_func(pc); |
224 | d4e8164f | bellard | ptb = &tb_hash[h]; |
225 | d4e8164f | bellard | for(;;) {
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226 | d4e8164f | bellard | tb = *ptb; |
227 | d4e8164f | bellard | if (!tb)
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228 | d4e8164f | bellard | break;
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229 | d4e8164f | bellard | if (tb->pc == pc && tb->cs_base == cs_base && tb->flags == flags)
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230 | d4e8164f | bellard | return tb;
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231 | d4e8164f | bellard | ptb = &tb->hash_next; |
232 | d4e8164f | bellard | } |
233 | d4e8164f | bellard | *pptb = ptb; |
234 | d4e8164f | bellard | return NULL; |
235 | d4e8164f | bellard | } |
236 | d4e8164f | bellard | |
237 | d4e8164f | bellard | |
238 | 4390df51 | bellard | #if defined(USE_DIRECT_JUMP)
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239 | 4390df51 | bellard | |
240 | 4390df51 | bellard | #if defined(__powerpc__)
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241 | 4cbb86e1 | bellard | static inline void tb_set_jmp_target1(unsigned long jmp_addr, unsigned long addr) |
242 | d4e8164f | bellard | { |
243 | d4e8164f | bellard | uint32_t val, *ptr; |
244 | d4e8164f | bellard | |
245 | d4e8164f | bellard | /* patch the branch destination */
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246 | 4cbb86e1 | bellard | ptr = (uint32_t *)jmp_addr; |
247 | d4e8164f | bellard | val = *ptr; |
248 | 4cbb86e1 | bellard | val = (val & ~0x03fffffc) | ((addr - jmp_addr) & 0x03fffffc); |
249 | d4e8164f | bellard | *ptr = val; |
250 | d4e8164f | bellard | /* flush icache */
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251 | d4e8164f | bellard | asm volatile ("dcbst 0,%0" : : "r"(ptr) : "memory"); |
252 | d4e8164f | bellard | asm volatile ("sync" : : : "memory"); |
253 | d4e8164f | bellard | asm volatile ("icbi 0,%0" : : "r"(ptr) : "memory"); |
254 | d4e8164f | bellard | asm volatile ("sync" : : : "memory"); |
255 | d4e8164f | bellard | asm volatile ("isync" : : : "memory"); |
256 | d4e8164f | bellard | } |
257 | 4390df51 | bellard | #elif defined(__i386__)
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258 | 4390df51 | bellard | static inline void tb_set_jmp_target1(unsigned long jmp_addr, unsigned long addr) |
259 | 4390df51 | bellard | { |
260 | 4390df51 | bellard | /* patch the branch destination */
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261 | 4390df51 | bellard | *(uint32_t *)jmp_addr = addr - (jmp_addr + 4);
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262 | 4390df51 | bellard | /* no need to flush icache explicitely */
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263 | 4390df51 | bellard | } |
264 | 4390df51 | bellard | #endif
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265 | d4e8164f | bellard | |
266 | 4cbb86e1 | bellard | static inline void tb_set_jmp_target(TranslationBlock *tb, |
267 | 4cbb86e1 | bellard | int n, unsigned long addr) |
268 | 4cbb86e1 | bellard | { |
269 | 4cbb86e1 | bellard | unsigned long offset; |
270 | 4cbb86e1 | bellard | |
271 | 4cbb86e1 | bellard | offset = tb->tb_jmp_offset[n]; |
272 | 4cbb86e1 | bellard | tb_set_jmp_target1((unsigned long)(tb->tc_ptr + offset), addr); |
273 | 4cbb86e1 | bellard | offset = tb->tb_jmp_offset[n + 2];
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274 | 4cbb86e1 | bellard | if (offset != 0xffff) |
275 | 4cbb86e1 | bellard | tb_set_jmp_target1((unsigned long)(tb->tc_ptr + offset), addr); |
276 | 4cbb86e1 | bellard | } |
277 | 4cbb86e1 | bellard | |
278 | d4e8164f | bellard | #else
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279 | d4e8164f | bellard | |
280 | d4e8164f | bellard | /* set the jump target */
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281 | d4e8164f | bellard | static inline void tb_set_jmp_target(TranslationBlock *tb, |
282 | d4e8164f | bellard | int n, unsigned long addr) |
283 | d4e8164f | bellard | { |
284 | 95f7652d | bellard | tb->tb_next[n] = addr; |
285 | d4e8164f | bellard | } |
286 | d4e8164f | bellard | |
287 | d4e8164f | bellard | #endif
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288 | d4e8164f | bellard | |
289 | d4e8164f | bellard | static inline void tb_add_jump(TranslationBlock *tb, int n, |
290 | d4e8164f | bellard | TranslationBlock *tb_next) |
291 | d4e8164f | bellard | { |
292 | cf25629d | bellard | /* NOTE: this test is only needed for thread safety */
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293 | cf25629d | bellard | if (!tb->jmp_next[n]) {
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294 | cf25629d | bellard | /* patch the native jump address */
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295 | cf25629d | bellard | tb_set_jmp_target(tb, n, (unsigned long)tb_next->tc_ptr); |
296 | cf25629d | bellard | |
297 | cf25629d | bellard | /* add in TB jmp circular list */
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298 | cf25629d | bellard | tb->jmp_next[n] = tb_next->jmp_first; |
299 | cf25629d | bellard | tb_next->jmp_first = (TranslationBlock *)((long)(tb) | (n));
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300 | cf25629d | bellard | } |
301 | d4e8164f | bellard | } |
302 | d4e8164f | bellard | |
303 | a513fe19 | bellard | TranslationBlock *tb_find_pc(unsigned long pc_ptr); |
304 | a513fe19 | bellard | |
305 | d4e8164f | bellard | #ifndef offsetof
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306 | d4e8164f | bellard | #define offsetof(type, field) ((size_t) &((type *)0)->field) |
307 | d4e8164f | bellard | #endif
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308 | d4e8164f | bellard | |
309 | d549f7d9 | bellard | #if defined(_WIN32)
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310 | d549f7d9 | bellard | #define ASM_DATA_SECTION ".section \".data\"\n" |
311 | d549f7d9 | bellard | #define ASM_PREVIOUS_SECTION ".section .text\n" |
312 | d549f7d9 | bellard | #elif defined(__APPLE__)
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313 | d549f7d9 | bellard | #define ASM_DATA_SECTION ".data\n" |
314 | d549f7d9 | bellard | #define ASM_PREVIOUS_SECTION ".text\n" |
315 | d549f7d9 | bellard | #else
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316 | d549f7d9 | bellard | #define ASM_DATA_SECTION ".section \".data\"\n" |
317 | d549f7d9 | bellard | #define ASM_PREVIOUS_SECTION ".previous\n" |
318 | d549f7d9 | bellard | #endif
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319 | d549f7d9 | bellard | |
320 | b346ff46 | bellard | #if defined(__powerpc__)
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321 | b346ff46 | bellard | |
322 | 4390df51 | bellard | /* we patch the jump instruction directly */
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323 | ae063a68 | bellard | #define GOTO_TB(opname, tbparam, n)\
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324 | b346ff46 | bellard | do {\
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325 | d549f7d9 | bellard | asm volatile (ASM_DATA_SECTION\ |
326 | d549f7d9 | bellard | ASM_NAME(__op_label) #n "." ASM_NAME(opname) ":\n"\ |
327 | 9257a9e4 | bellard | ".long 1f\n"\
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328 | d549f7d9 | bellard | ASM_PREVIOUS_SECTION \ |
329 | d549f7d9 | bellard | "b " ASM_NAME(__op_jmp) #n "\n"\ |
330 | 9257a9e4 | bellard | "1:\n");\
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331 | 4390df51 | bellard | } while (0) |
332 | 4390df51 | bellard | |
333 | 4390df51 | bellard | #elif defined(__i386__) && defined(USE_DIRECT_JUMP)
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334 | 4390df51 | bellard | |
335 | 4390df51 | bellard | /* we patch the jump instruction directly */
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336 | ae063a68 | bellard | #define GOTO_TB(opname, tbparam, n)\
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337 | c27004ec | bellard | do {\
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338 | c27004ec | bellard | asm volatile (".section .data\n"\ |
339 | c27004ec | bellard | ASM_NAME(__op_label) #n "." ASM_NAME(opname) ":\n"\ |
340 | c27004ec | bellard | ".long 1f\n"\
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341 | c27004ec | bellard | ASM_PREVIOUS_SECTION \ |
342 | c27004ec | bellard | "jmp " ASM_NAME(__op_jmp) #n "\n"\ |
343 | c27004ec | bellard | "1:\n");\
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344 | c27004ec | bellard | } while (0) |
345 | c27004ec | bellard | |
346 | b346ff46 | bellard | #else
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347 | b346ff46 | bellard | |
348 | b346ff46 | bellard | /* jump to next block operations (more portable code, does not need
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349 | b346ff46 | bellard | cache flushing, but slower because of indirect jump) */
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350 | ae063a68 | bellard | #define GOTO_TB(opname, tbparam, n)\
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351 | b346ff46 | bellard | do {\
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352 | 2f62b397 | bellard | static void __attribute__((unused)) *dummy ## n = &&dummy_label ## n;\ |
353 | ae063a68 | bellard | static void __attribute__((unused)) *__op_label ## n = &&label ## n;\ |
354 | b346ff46 | bellard | goto *(void *)(((TranslationBlock *)tbparam)->tb_next[n]);\ |
355 | ae063a68 | bellard | label ## n: ;\ |
356 | ae063a68 | bellard | dummy_label ## n: ;\ |
357 | b346ff46 | bellard | } while (0) |
358 | b346ff46 | bellard | |
359 | ae063a68 | bellard | #endif
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360 | ae063a68 | bellard | |
361 | ae063a68 | bellard | /* XXX: will be suppressed */
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362 | ae063a68 | bellard | #define JUMP_TB(opname, tbparam, n, eip)\
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363 | 4cbb86e1 | bellard | do {\
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364 | ae063a68 | bellard | GOTO_TB(opname, tbparam, n);\ |
365 | ae063a68 | bellard | T0 = (long)(tbparam) + (n);\
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366 | ae063a68 | bellard | EIP = (int32_t)eip;\ |
367 | ae063a68 | bellard | EXIT_TB();\ |
368 | 4cbb86e1 | bellard | } while (0) |
369 | 4cbb86e1 | bellard | |
370 | 33417e70 | bellard | extern CPUWriteMemoryFunc *io_mem_write[IO_MEM_NB_ENTRIES][4]; |
371 | 33417e70 | bellard | extern CPUReadMemoryFunc *io_mem_read[IO_MEM_NB_ENTRIES][4]; |
372 | a4193c8a | bellard | extern void *io_mem_opaque[IO_MEM_NB_ENTRIES]; |
373 | 33417e70 | bellard | |
374 | d4e8164f | bellard | #ifdef __powerpc__
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375 | d4e8164f | bellard | static inline int testandset (int *p) |
376 | d4e8164f | bellard | { |
377 | d4e8164f | bellard | int ret;
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378 | d4e8164f | bellard | __asm__ __volatile__ ( |
379 | 02e1ec9b | bellard | "0: lwarx %0,0,%1\n"
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380 | 02e1ec9b | bellard | " xor. %0,%3,%0\n"
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381 | 02e1ec9b | bellard | " bne 1f\n"
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382 | 02e1ec9b | bellard | " stwcx. %2,0,%1\n"
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383 | 02e1ec9b | bellard | " bne- 0b\n"
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384 | d4e8164f | bellard | "1: "
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385 | d4e8164f | bellard | : "=&r" (ret)
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386 | d4e8164f | bellard | : "r" (p), "r" (1), "r" (0) |
387 | d4e8164f | bellard | : "cr0", "memory"); |
388 | d4e8164f | bellard | return ret;
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389 | d4e8164f | bellard | } |
390 | d4e8164f | bellard | #endif
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391 | d4e8164f | bellard | |
392 | d4e8164f | bellard | #ifdef __i386__
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393 | d4e8164f | bellard | static inline int testandset (int *p) |
394 | d4e8164f | bellard | { |
395 | d4e8164f | bellard | char ret;
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396 | d4e8164f | bellard | long int readval; |
397 | d4e8164f | bellard | |
398 | d4e8164f | bellard | __asm__ __volatile__ ("lock; cmpxchgl %3, %1; sete %0"
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399 | d4e8164f | bellard | : "=q" (ret), "=m" (*p), "=a" (readval) |
400 | d4e8164f | bellard | : "r" (1), "m" (*p), "a" (0) |
401 | d4e8164f | bellard | : "memory");
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402 | d4e8164f | bellard | return ret;
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403 | d4e8164f | bellard | } |
404 | d4e8164f | bellard | #endif
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405 | d4e8164f | bellard | |
406 | bc51c5c9 | bellard | #ifdef __x86_64__
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407 | bc51c5c9 | bellard | static inline int testandset (int *p) |
408 | bc51c5c9 | bellard | { |
409 | bc51c5c9 | bellard | char ret;
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410 | bc51c5c9 | bellard | int readval;
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411 | bc51c5c9 | bellard | |
412 | bc51c5c9 | bellard | __asm__ __volatile__ ("lock; cmpxchgl %3, %1; sete %0"
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413 | bc51c5c9 | bellard | : "=q" (ret), "=m" (*p), "=a" (readval) |
414 | bc51c5c9 | bellard | : "r" (1), "m" (*p), "a" (0) |
415 | bc51c5c9 | bellard | : "memory");
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416 | bc51c5c9 | bellard | return ret;
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417 | bc51c5c9 | bellard | } |
418 | bc51c5c9 | bellard | #endif
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419 | bc51c5c9 | bellard | |
420 | d4e8164f | bellard | #ifdef __s390__
|
421 | d4e8164f | bellard | static inline int testandset (int *p) |
422 | d4e8164f | bellard | { |
423 | d4e8164f | bellard | int ret;
|
424 | d4e8164f | bellard | |
425 | d4e8164f | bellard | __asm__ __volatile__ ("0: cs %0,%1,0(%2)\n"
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426 | d4e8164f | bellard | " jl 0b"
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427 | d4e8164f | bellard | : "=&d" (ret)
|
428 | d4e8164f | bellard | : "r" (1), "a" (p), "0" (*p) |
429 | d4e8164f | bellard | : "cc", "memory" ); |
430 | d4e8164f | bellard | return ret;
|
431 | d4e8164f | bellard | } |
432 | d4e8164f | bellard | #endif
|
433 | d4e8164f | bellard | |
434 | d4e8164f | bellard | #ifdef __alpha__
|
435 | 2f87c607 | bellard | static inline int testandset (int *p) |
436 | d4e8164f | bellard | { |
437 | d4e8164f | bellard | int ret;
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438 | d4e8164f | bellard | unsigned long one; |
439 | d4e8164f | bellard | |
440 | d4e8164f | bellard | __asm__ __volatile__ ("0: mov 1,%2\n"
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441 | d4e8164f | bellard | " ldl_l %0,%1\n"
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442 | d4e8164f | bellard | " stl_c %2,%1\n"
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443 | d4e8164f | bellard | " beq %2,1f\n"
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444 | d4e8164f | bellard | ".subsection 2\n"
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445 | d4e8164f | bellard | "1: br 0b\n"
|
446 | d4e8164f | bellard | ".previous"
|
447 | d4e8164f | bellard | : "=r" (ret), "=m" (*p), "=r" (one) |
448 | d4e8164f | bellard | : "m" (*p));
|
449 | d4e8164f | bellard | return ret;
|
450 | d4e8164f | bellard | } |
451 | d4e8164f | bellard | #endif
|
452 | d4e8164f | bellard | |
453 | d4e8164f | bellard | #ifdef __sparc__
|
454 | d4e8164f | bellard | static inline int testandset (int *p) |
455 | d4e8164f | bellard | { |
456 | d4e8164f | bellard | int ret;
|
457 | d4e8164f | bellard | |
458 | d4e8164f | bellard | __asm__ __volatile__("ldstub [%1], %0"
|
459 | d4e8164f | bellard | : "=r" (ret)
|
460 | d4e8164f | bellard | : "r" (p)
|
461 | d4e8164f | bellard | : "memory");
|
462 | d4e8164f | bellard | |
463 | d4e8164f | bellard | return (ret ? 1 : 0); |
464 | d4e8164f | bellard | } |
465 | d4e8164f | bellard | #endif
|
466 | d4e8164f | bellard | |
467 | a95c6790 | bellard | #ifdef __arm__
|
468 | a95c6790 | bellard | static inline int testandset (int *spinlock) |
469 | a95c6790 | bellard | { |
470 | a95c6790 | bellard | register unsigned int ret; |
471 | a95c6790 | bellard | __asm__ __volatile__("swp %0, %1, [%2]"
|
472 | a95c6790 | bellard | : "=r"(ret)
|
473 | a95c6790 | bellard | : "0"(1), "r"(spinlock)); |
474 | a95c6790 | bellard | |
475 | a95c6790 | bellard | return ret;
|
476 | a95c6790 | bellard | } |
477 | a95c6790 | bellard | #endif
|
478 | a95c6790 | bellard | |
479 | 38e584a0 | bellard | #ifdef __mc68000
|
480 | 38e584a0 | bellard | static inline int testandset (int *p) |
481 | 38e584a0 | bellard | { |
482 | 38e584a0 | bellard | char ret;
|
483 | 38e584a0 | bellard | __asm__ __volatile__("tas %1; sne %0"
|
484 | 38e584a0 | bellard | : "=r" (ret)
|
485 | 38e584a0 | bellard | : "m" (p)
|
486 | 38e584a0 | bellard | : "cc","memory"); |
487 | 38e584a0 | bellard | return ret == 0; |
488 | 38e584a0 | bellard | } |
489 | 38e584a0 | bellard | #endif
|
490 | 38e584a0 | bellard | |
491 | d4e8164f | bellard | typedef int spinlock_t; |
492 | d4e8164f | bellard | |
493 | d4e8164f | bellard | #define SPIN_LOCK_UNLOCKED 0 |
494 | d4e8164f | bellard | |
495 | aebcb60e | bellard | #if defined(CONFIG_USER_ONLY)
|
496 | d4e8164f | bellard | static inline void spin_lock(spinlock_t *lock) |
497 | d4e8164f | bellard | { |
498 | d4e8164f | bellard | while (testandset(lock));
|
499 | d4e8164f | bellard | } |
500 | d4e8164f | bellard | |
501 | d4e8164f | bellard | static inline void spin_unlock(spinlock_t *lock) |
502 | d4e8164f | bellard | { |
503 | d4e8164f | bellard | *lock = 0;
|
504 | d4e8164f | bellard | } |
505 | d4e8164f | bellard | |
506 | d4e8164f | bellard | static inline int spin_trylock(spinlock_t *lock) |
507 | d4e8164f | bellard | { |
508 | d4e8164f | bellard | return !testandset(lock);
|
509 | d4e8164f | bellard | } |
510 | 3c1cf9fa | bellard | #else
|
511 | 3c1cf9fa | bellard | static inline void spin_lock(spinlock_t *lock) |
512 | 3c1cf9fa | bellard | { |
513 | 3c1cf9fa | bellard | } |
514 | 3c1cf9fa | bellard | |
515 | 3c1cf9fa | bellard | static inline void spin_unlock(spinlock_t *lock) |
516 | 3c1cf9fa | bellard | { |
517 | 3c1cf9fa | bellard | } |
518 | 3c1cf9fa | bellard | |
519 | 3c1cf9fa | bellard | static inline int spin_trylock(spinlock_t *lock) |
520 | 3c1cf9fa | bellard | { |
521 | 3c1cf9fa | bellard | return 1; |
522 | 3c1cf9fa | bellard | } |
523 | 3c1cf9fa | bellard | #endif
|
524 | d4e8164f | bellard | |
525 | d4e8164f | bellard | extern spinlock_t tb_lock;
|
526 | d4e8164f | bellard | |
527 | 36bdbe54 | bellard | extern int tb_invalidated_flag; |
528 | 6e59c1db | bellard | |
529 | e95c8d51 | bellard | #if !defined(CONFIG_USER_ONLY)
|
530 | 6e59c1db | bellard | |
531 | c27004ec | bellard | void tlb_fill(target_ulong addr, int is_write, int is_user, |
532 | 6e59c1db | bellard | void *retaddr);
|
533 | 6e59c1db | bellard | |
534 | 6e59c1db | bellard | #define ACCESS_TYPE 3 |
535 | 6e59c1db | bellard | #define MEMSUFFIX _code
|
536 | 6e59c1db | bellard | #define env cpu_single_env
|
537 | 6e59c1db | bellard | |
538 | 6e59c1db | bellard | #define DATA_SIZE 1 |
539 | 6e59c1db | bellard | #include "softmmu_header.h" |
540 | 6e59c1db | bellard | |
541 | 6e59c1db | bellard | #define DATA_SIZE 2 |
542 | 6e59c1db | bellard | #include "softmmu_header.h" |
543 | 6e59c1db | bellard | |
544 | 6e59c1db | bellard | #define DATA_SIZE 4 |
545 | 6e59c1db | bellard | #include "softmmu_header.h" |
546 | 6e59c1db | bellard | |
547 | c27004ec | bellard | #define DATA_SIZE 8 |
548 | c27004ec | bellard | #include "softmmu_header.h" |
549 | c27004ec | bellard | |
550 | 6e59c1db | bellard | #undef ACCESS_TYPE
|
551 | 6e59c1db | bellard | #undef MEMSUFFIX
|
552 | 6e59c1db | bellard | #undef env
|
553 | 6e59c1db | bellard | |
554 | 6e59c1db | bellard | #endif
|
555 | 4390df51 | bellard | |
556 | 4390df51 | bellard | #if defined(CONFIG_USER_ONLY)
|
557 | 4390df51 | bellard | static inline target_ulong get_phys_addr_code(CPUState *env, target_ulong addr) |
558 | 4390df51 | bellard | { |
559 | 4390df51 | bellard | return addr;
|
560 | 4390df51 | bellard | } |
561 | 4390df51 | bellard | #else
|
562 | 4390df51 | bellard | /* NOTE: this function can trigger an exception */
|
563 | 1ccde1cb | bellard | /* NOTE2: the returned address is not exactly the physical address: it
|
564 | 1ccde1cb | bellard | is the offset relative to phys_ram_base */
|
565 | 4390df51 | bellard | /* XXX: i386 target specific */
|
566 | 4390df51 | bellard | static inline target_ulong get_phys_addr_code(CPUState *env, target_ulong addr) |
567 | 4390df51 | bellard | { |
568 | c27004ec | bellard | int is_user, index, pd;
|
569 | 4390df51 | bellard | |
570 | 4390df51 | bellard | index = (addr >> TARGET_PAGE_BITS) & (CPU_TLB_SIZE - 1);
|
571 | 3f5dcc34 | bellard | #if defined(TARGET_I386)
|
572 | 4390df51 | bellard | is_user = ((env->hflags & HF_CPL_MASK) == 3);
|
573 | 3f5dcc34 | bellard | #elif defined (TARGET_PPC)
|
574 | 3f5dcc34 | bellard | is_user = msr_pr; |
575 | e95c8d51 | bellard | #elif defined (TARGET_SPARC)
|
576 | e95c8d51 | bellard | is_user = (env->psrs == 0);
|
577 | 3f5dcc34 | bellard | #else
|
578 | 3f5dcc34 | bellard | #error "Unimplemented !" |
579 | 3f5dcc34 | bellard | #endif
|
580 | 4390df51 | bellard | if (__builtin_expect(env->tlb_read[is_user][index].address !=
|
581 | 4390df51 | bellard | (addr & TARGET_PAGE_MASK), 0)) {
|
582 | c27004ec | bellard | ldub_code(addr); |
583 | c27004ec | bellard | } |
584 | c27004ec | bellard | pd = env->tlb_read[is_user][index].address & ~TARGET_PAGE_MASK; |
585 | c27004ec | bellard | if (pd > IO_MEM_ROM) {
|
586 | c27004ec | bellard | cpu_abort(env, "Trying to execute code outside RAM or ROM at 0x%08lx\n", addr);
|
587 | 4390df51 | bellard | } |
588 | 4390df51 | bellard | return addr + env->tlb_read[is_user][index].addend - (unsigned long)phys_ram_base; |
589 | 4390df51 | bellard | } |
590 | 4390df51 | bellard | #endif |