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1 | a541f297 | bellard | /*
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2 | a541f297 | bellard | * QEMU generic PPC hardware System Emulator
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3 | a541f297 | bellard | *
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4 | a541f297 | bellard | * Copyright (c) 2003-2004 Jocelyn Mayer
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5 | a541f297 | bellard | *
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6 | a541f297 | bellard | * Permission is hereby granted, free of charge, to any person obtaining a copy
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7 | a541f297 | bellard | * of this software and associated documentation files (the "Software"), to deal
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8 | a541f297 | bellard | * in the Software without restriction, including without limitation the rights
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9 | a541f297 | bellard | * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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10 | a541f297 | bellard | * copies of the Software, and to permit persons to whom the Software is
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11 | a541f297 | bellard | * furnished to do so, subject to the following conditions:
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12 | a541f297 | bellard | *
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13 | a541f297 | bellard | * The above copyright notice and this permission notice shall be included in
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14 | a541f297 | bellard | * all copies or substantial portions of the Software.
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15 | a541f297 | bellard | *
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16 | a541f297 | bellard | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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17 | a541f297 | bellard | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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18 | a541f297 | bellard | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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19 | a541f297 | bellard | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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20 | a541f297 | bellard | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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21 | a541f297 | bellard | * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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22 | a541f297 | bellard | * THE SOFTWARE.
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23 | a541f297 | bellard | */
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24 | a541f297 | bellard | #include "vl.h" |
25 | fd0bbb12 | bellard | #include "m48t59.h" |
26 | a541f297 | bellard | |
27 | 9fddaa0c | bellard | /*****************************************************************************/
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28 | 9fddaa0c | bellard | /* PPC time base and decrementer emulation */
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29 | 9fddaa0c | bellard | //#define DEBUG_TB
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30 | 9fddaa0c | bellard | |
31 | 9fddaa0c | bellard | struct ppc_tb_t {
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32 | 9fddaa0c | bellard | /* Time base management */
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33 | 9fddaa0c | bellard | int64_t tb_offset; /* Compensation */
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34 | 9fddaa0c | bellard | uint32_t tb_freq; /* TB frequency */
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35 | 9fddaa0c | bellard | /* Decrementer management */
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36 | 9fddaa0c | bellard | uint64_t decr_next; /* Tick for next decr interrupt */
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37 | 9fddaa0c | bellard | struct QEMUTimer *decr_timer;
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38 | 9fddaa0c | bellard | }; |
39 | 9fddaa0c | bellard | |
40 | 9fddaa0c | bellard | static inline uint64_t cpu_ppc_get_tb (ppc_tb_t *tb_env) |
41 | 9fddaa0c | bellard | { |
42 | 9fddaa0c | bellard | /* TB time in tb periods */
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43 | 9fddaa0c | bellard | return muldiv64(qemu_get_clock(vm_clock) + tb_env->tb_offset,
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44 | 9fddaa0c | bellard | tb_env->tb_freq, ticks_per_sec); |
45 | 9fddaa0c | bellard | } |
46 | 9fddaa0c | bellard | |
47 | 9fddaa0c | bellard | uint32_t cpu_ppc_load_tbl (CPUState *env) |
48 | 9fddaa0c | bellard | { |
49 | 9fddaa0c | bellard | ppc_tb_t *tb_env = env->tb_env; |
50 | 9fddaa0c | bellard | uint64_t tb; |
51 | 9fddaa0c | bellard | |
52 | 9fddaa0c | bellard | tb = cpu_ppc_get_tb(tb_env); |
53 | 9fddaa0c | bellard | #ifdef DEBUG_TB
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54 | 9fddaa0c | bellard | { |
55 | 9fddaa0c | bellard | static int last_time; |
56 | 9fddaa0c | bellard | int now;
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57 | 9fddaa0c | bellard | now = time(NULL);
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58 | 9fddaa0c | bellard | if (last_time != now) {
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59 | 9fddaa0c | bellard | last_time = now; |
60 | 9fddaa0c | bellard | printf("%s: tb=0x%016lx %d %08lx\n",
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61 | 9fddaa0c | bellard | __func__, tb, now, tb_env->tb_offset); |
62 | 9fddaa0c | bellard | } |
63 | 9fddaa0c | bellard | } |
64 | 9fddaa0c | bellard | #endif
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65 | 9fddaa0c | bellard | |
66 | 9fddaa0c | bellard | return tb & 0xFFFFFFFF; |
67 | 9fddaa0c | bellard | } |
68 | 9fddaa0c | bellard | |
69 | 9fddaa0c | bellard | uint32_t cpu_ppc_load_tbu (CPUState *env) |
70 | 9fddaa0c | bellard | { |
71 | 9fddaa0c | bellard | ppc_tb_t *tb_env = env->tb_env; |
72 | 9fddaa0c | bellard | uint64_t tb; |
73 | 9fddaa0c | bellard | |
74 | 9fddaa0c | bellard | tb = cpu_ppc_get_tb(tb_env); |
75 | 9fddaa0c | bellard | #ifdef DEBUG_TB
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76 | 9fddaa0c | bellard | printf("%s: tb=0x%016lx\n", __func__, tb);
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77 | 9fddaa0c | bellard | #endif
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78 | 9fddaa0c | bellard | return tb >> 32; |
79 | 9fddaa0c | bellard | } |
80 | 9fddaa0c | bellard | |
81 | 9fddaa0c | bellard | static void cpu_ppc_store_tb (ppc_tb_t *tb_env, uint64_t value) |
82 | 9fddaa0c | bellard | { |
83 | 9fddaa0c | bellard | tb_env->tb_offset = muldiv64(value, ticks_per_sec, tb_env->tb_freq) |
84 | 9fddaa0c | bellard | - qemu_get_clock(vm_clock); |
85 | 9fddaa0c | bellard | #ifdef DEBUG_TB
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86 | 9fddaa0c | bellard | printf("%s: tb=0x%016lx offset=%08x\n", __func__, value);
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87 | 9fddaa0c | bellard | #endif
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88 | 9fddaa0c | bellard | } |
89 | 9fddaa0c | bellard | |
90 | 9fddaa0c | bellard | void cpu_ppc_store_tbu (CPUState *env, uint32_t value)
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91 | 9fddaa0c | bellard | { |
92 | 9fddaa0c | bellard | ppc_tb_t *tb_env = env->tb_env; |
93 | 9fddaa0c | bellard | |
94 | 9fddaa0c | bellard | cpu_ppc_store_tb(tb_env, |
95 | 9fddaa0c | bellard | ((uint64_t)value << 32) | cpu_ppc_load_tbl(env));
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96 | 9fddaa0c | bellard | } |
97 | 9fddaa0c | bellard | |
98 | 9fddaa0c | bellard | void cpu_ppc_store_tbl (CPUState *env, uint32_t value)
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99 | 9fddaa0c | bellard | { |
100 | 9fddaa0c | bellard | ppc_tb_t *tb_env = env->tb_env; |
101 | 9fddaa0c | bellard | |
102 | 9fddaa0c | bellard | cpu_ppc_store_tb(tb_env, |
103 | 9fddaa0c | bellard | ((uint64_t)cpu_ppc_load_tbu(env) << 32) | value);
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104 | 9fddaa0c | bellard | } |
105 | 9fddaa0c | bellard | |
106 | 9fddaa0c | bellard | uint32_t cpu_ppc_load_decr (CPUState *env) |
107 | 9fddaa0c | bellard | { |
108 | 9fddaa0c | bellard | ppc_tb_t *tb_env = env->tb_env; |
109 | 9fddaa0c | bellard | uint32_t decr; |
110 | 9fddaa0c | bellard | |
111 | 9fddaa0c | bellard | decr = muldiv64(tb_env->decr_next - qemu_get_clock(vm_clock), |
112 | 9fddaa0c | bellard | tb_env->tb_freq, ticks_per_sec); |
113 | fd0bbb12 | bellard | #if defined(DEBUG_TB)
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114 | 9fddaa0c | bellard | printf("%s: 0x%08x\n", __func__, decr);
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115 | 9fddaa0c | bellard | #endif
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116 | 9fddaa0c | bellard | |
117 | 9fddaa0c | bellard | return decr;
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118 | 9fddaa0c | bellard | } |
119 | 9fddaa0c | bellard | |
120 | 9fddaa0c | bellard | /* When decrementer expires,
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121 | 9fddaa0c | bellard | * all we need to do is generate or queue a CPU exception
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122 | 9fddaa0c | bellard | */
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123 | 9fddaa0c | bellard | static inline void cpu_ppc_decr_excp (CPUState *env) |
124 | 9fddaa0c | bellard | { |
125 | 9fddaa0c | bellard | /* Raise it */
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126 | 9fddaa0c | bellard | #ifdef DEBUG_TB
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127 | 9fddaa0c | bellard | printf("raise decrementer exception\n");
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128 | 9fddaa0c | bellard | #endif
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129 | 9fddaa0c | bellard | cpu_interrupt(env, CPU_INTERRUPT_TIMER); |
130 | 9fddaa0c | bellard | } |
131 | 9fddaa0c | bellard | |
132 | 9fddaa0c | bellard | static void _cpu_ppc_store_decr (CPUState *env, uint32_t decr, |
133 | 9fddaa0c | bellard | uint32_t value, int is_excp)
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134 | 9fddaa0c | bellard | { |
135 | 9fddaa0c | bellard | ppc_tb_t *tb_env = env->tb_env; |
136 | 9fddaa0c | bellard | uint64_t now, next; |
137 | 9fddaa0c | bellard | |
138 | 9fddaa0c | bellard | #ifdef DEBUG_TB
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139 | 9fddaa0c | bellard | printf("%s: 0x%08x => 0x%08x\n", __func__, decr, value);
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140 | 9fddaa0c | bellard | #endif
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141 | 9fddaa0c | bellard | now = qemu_get_clock(vm_clock); |
142 | 9fddaa0c | bellard | next = now + muldiv64(value, ticks_per_sec, tb_env->tb_freq); |
143 | 9fddaa0c | bellard | if (is_excp)
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144 | 9fddaa0c | bellard | next += tb_env->decr_next - now; |
145 | 9fddaa0c | bellard | if (next == now)
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146 | 9fddaa0c | bellard | next++; |
147 | 9fddaa0c | bellard | tb_env->decr_next = next; |
148 | 9fddaa0c | bellard | /* Adjust timer */
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149 | 9fddaa0c | bellard | qemu_mod_timer(tb_env->decr_timer, next); |
150 | 9fddaa0c | bellard | /* If we set a negative value and the decrementer was positive,
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151 | 9fddaa0c | bellard | * raise an exception.
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152 | 9fddaa0c | bellard | */
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153 | 9fddaa0c | bellard | if ((value & 0x80000000) && !(decr & 0x80000000)) |
154 | 9fddaa0c | bellard | cpu_ppc_decr_excp(env); |
155 | 9fddaa0c | bellard | } |
156 | 9fddaa0c | bellard | |
157 | 9fddaa0c | bellard | void cpu_ppc_store_decr (CPUState *env, uint32_t value)
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158 | 9fddaa0c | bellard | { |
159 | 9fddaa0c | bellard | _cpu_ppc_store_decr(env, cpu_ppc_load_decr(env), value, 0);
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160 | 9fddaa0c | bellard | } |
161 | 9fddaa0c | bellard | |
162 | 9fddaa0c | bellard | static void cpu_ppc_decr_cb (void *opaque) |
163 | 9fddaa0c | bellard | { |
164 | 9fddaa0c | bellard | _cpu_ppc_store_decr(opaque, 0x00000000, 0xFFFFFFFF, 1); |
165 | 9fddaa0c | bellard | } |
166 | 9fddaa0c | bellard | |
167 | 9fddaa0c | bellard | /* Set up (once) timebase frequency (in Hz) */
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168 | 9fddaa0c | bellard | ppc_tb_t *cpu_ppc_tb_init (CPUState *env, uint32_t freq) |
169 | 9fddaa0c | bellard | { |
170 | 9fddaa0c | bellard | ppc_tb_t *tb_env; |
171 | 9fddaa0c | bellard | |
172 | 9fddaa0c | bellard | tb_env = qemu_mallocz(sizeof(ppc_tb_t));
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173 | 9fddaa0c | bellard | if (tb_env == NULL) |
174 | 9fddaa0c | bellard | return NULL; |
175 | 9fddaa0c | bellard | env->tb_env = tb_env; |
176 | 9fddaa0c | bellard | if (tb_env->tb_freq == 0 || 1) { |
177 | 9fddaa0c | bellard | tb_env->tb_freq = freq; |
178 | 9fddaa0c | bellard | /* Create new timer */
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179 | 9fddaa0c | bellard | tb_env->decr_timer = |
180 | 9fddaa0c | bellard | qemu_new_timer(vm_clock, &cpu_ppc_decr_cb, env); |
181 | 9fddaa0c | bellard | /* There is a bug in 2.4 kernels:
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182 | 9fddaa0c | bellard | * if a decrementer exception is pending when it enables msr_ee,
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183 | 9fddaa0c | bellard | * it's not ready to handle it...
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184 | 9fddaa0c | bellard | */
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185 | 9fddaa0c | bellard | _cpu_ppc_store_decr(env, 0xFFFFFFFF, 0xFFFFFFFF, 0); |
186 | 9fddaa0c | bellard | } |
187 | 9fddaa0c | bellard | |
188 | 9fddaa0c | bellard | return tb_env;
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189 | 9fddaa0c | bellard | } |
190 | 9fddaa0c | bellard | |
191 | 9fddaa0c | bellard | #if 0
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192 | 9fddaa0c | bellard | /*****************************************************************************/
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193 | 9fddaa0c | bellard | /* Handle system reset (for now, just stop emulation) */
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194 | 9fddaa0c | bellard | void cpu_ppc_reset (CPUState *env)
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195 | 9fddaa0c | bellard | {
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196 | 9fddaa0c | bellard | printf("Reset asked... Stop emulation\n");
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197 | 9fddaa0c | bellard | abort();
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198 | 9fddaa0c | bellard | }
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199 | 9fddaa0c | bellard | #endif
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200 | 9fddaa0c | bellard | |
201 | a4193c8a | bellard | static void PPC_io_writeb (void *opaque, target_phys_addr_t addr, uint32_t value) |
202 | 64201201 | bellard | { |
203 | 64201201 | bellard | cpu_outb(NULL, addr & 0xffff, value); |
204 | 64201201 | bellard | } |
205 | 64201201 | bellard | |
206 | a4193c8a | bellard | static uint32_t PPC_io_readb (void *opaque, target_phys_addr_t addr) |
207 | 64201201 | bellard | { |
208 | 64201201 | bellard | uint32_t ret = cpu_inb(NULL, addr & 0xffff); |
209 | 64201201 | bellard | return ret;
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210 | 64201201 | bellard | } |
211 | 64201201 | bellard | |
212 | a4193c8a | bellard | static void PPC_io_writew (void *opaque, target_phys_addr_t addr, uint32_t value) |
213 | 64201201 | bellard | { |
214 | 64201201 | bellard | #ifdef TARGET_WORDS_BIGENDIAN
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215 | 64201201 | bellard | value = bswap16(value); |
216 | 64201201 | bellard | #endif
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217 | 64201201 | bellard | cpu_outw(NULL, addr & 0xffff, value); |
218 | 64201201 | bellard | } |
219 | 64201201 | bellard | |
220 | a4193c8a | bellard | static uint32_t PPC_io_readw (void *opaque, target_phys_addr_t addr) |
221 | 64201201 | bellard | { |
222 | 64201201 | bellard | uint32_t ret = cpu_inw(NULL, addr & 0xffff); |
223 | 64201201 | bellard | #ifdef TARGET_WORDS_BIGENDIAN
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224 | 64201201 | bellard | ret = bswap16(ret); |
225 | 64201201 | bellard | #endif
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226 | 64201201 | bellard | return ret;
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227 | 64201201 | bellard | } |
228 | 64201201 | bellard | |
229 | a4193c8a | bellard | static void PPC_io_writel (void *opaque, target_phys_addr_t addr, uint32_t value) |
230 | 64201201 | bellard | { |
231 | 64201201 | bellard | #ifdef TARGET_WORDS_BIGENDIAN
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232 | 64201201 | bellard | value = bswap32(value); |
233 | 64201201 | bellard | #endif
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234 | 64201201 | bellard | cpu_outl(NULL, addr & 0xffff, value); |
235 | 64201201 | bellard | } |
236 | 64201201 | bellard | |
237 | a4193c8a | bellard | static uint32_t PPC_io_readl (void *opaque, target_phys_addr_t addr) |
238 | 64201201 | bellard | { |
239 | 64201201 | bellard | uint32_t ret = cpu_inl(NULL, addr & 0xffff); |
240 | 64201201 | bellard | |
241 | 64201201 | bellard | #ifdef TARGET_WORDS_BIGENDIAN
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242 | 64201201 | bellard | ret = bswap32(ret); |
243 | 64201201 | bellard | #endif
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244 | 64201201 | bellard | return ret;
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245 | 64201201 | bellard | } |
246 | 64201201 | bellard | |
247 | 64201201 | bellard | CPUWriteMemoryFunc *PPC_io_write[] = { |
248 | 64201201 | bellard | &PPC_io_writeb, |
249 | 64201201 | bellard | &PPC_io_writew, |
250 | 64201201 | bellard | &PPC_io_writel, |
251 | 64201201 | bellard | }; |
252 | 64201201 | bellard | |
253 | 64201201 | bellard | CPUReadMemoryFunc *PPC_io_read[] = { |
254 | 64201201 | bellard | &PPC_io_readb, |
255 | 64201201 | bellard | &PPC_io_readw, |
256 | 64201201 | bellard | &PPC_io_readl, |
257 | 64201201 | bellard | }; |
258 | 64201201 | bellard | |
259 | 64201201 | bellard | /*****************************************************************************/
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260 | 64201201 | bellard | /* Debug port */
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261 | fd0bbb12 | bellard | void PPC_debug_write (void *opaque, uint32_t addr, uint32_t val) |
262 | 64201201 | bellard | { |
263 | 64201201 | bellard | addr &= 0xF;
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264 | 64201201 | bellard | switch (addr) {
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265 | 64201201 | bellard | case 0: |
266 | 64201201 | bellard | printf("%c", val);
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267 | 64201201 | bellard | break;
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268 | 64201201 | bellard | case 1: |
269 | 64201201 | bellard | printf("\n");
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270 | 64201201 | bellard | fflush(stdout); |
271 | 64201201 | bellard | break;
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272 | 64201201 | bellard | case 2: |
273 | 64201201 | bellard | printf("Set loglevel to %04x\n", val);
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274 | fd0bbb12 | bellard | cpu_set_log(val | 0x100);
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275 | 64201201 | bellard | break;
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276 | 64201201 | bellard | } |
277 | 64201201 | bellard | } |
278 | 64201201 | bellard | |
279 | 64201201 | bellard | /*****************************************************************************/
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280 | 64201201 | bellard | /* NVRAM helpers */
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281 | 64201201 | bellard | void NVRAM_set_byte (m48t59_t *nvram, uint32_t addr, uint8_t value)
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282 | 64201201 | bellard | { |
283 | 64201201 | bellard | m48t59_set_addr(nvram, addr); |
284 | 64201201 | bellard | m48t59_write(nvram, value); |
285 | 64201201 | bellard | } |
286 | 64201201 | bellard | |
287 | 64201201 | bellard | uint8_t NVRAM_get_byte (m48t59_t *nvram, uint32_t addr) |
288 | 64201201 | bellard | { |
289 | 64201201 | bellard | m48t59_set_addr(nvram, addr); |
290 | 64201201 | bellard | return m48t59_read(nvram);
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291 | 64201201 | bellard | } |
292 | 64201201 | bellard | |
293 | 64201201 | bellard | void NVRAM_set_word (m48t59_t *nvram, uint32_t addr, uint16_t value)
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294 | 64201201 | bellard | { |
295 | 64201201 | bellard | m48t59_set_addr(nvram, addr); |
296 | 64201201 | bellard | m48t59_write(nvram, value >> 8);
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297 | 64201201 | bellard | m48t59_set_addr(nvram, addr + 1);
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298 | 64201201 | bellard | m48t59_write(nvram, value & 0xFF);
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299 | 64201201 | bellard | } |
300 | 64201201 | bellard | |
301 | 64201201 | bellard | uint16_t NVRAM_get_word (m48t59_t *nvram, uint32_t addr) |
302 | 64201201 | bellard | { |
303 | 64201201 | bellard | uint16_t tmp; |
304 | 64201201 | bellard | |
305 | 64201201 | bellard | m48t59_set_addr(nvram, addr); |
306 | 64201201 | bellard | tmp = m48t59_read(nvram) << 8;
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307 | 64201201 | bellard | m48t59_set_addr(nvram, addr + 1);
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308 | 64201201 | bellard | tmp |= m48t59_read(nvram); |
309 | 64201201 | bellard | |
310 | 64201201 | bellard | return tmp;
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311 | 64201201 | bellard | } |
312 | 64201201 | bellard | |
313 | 64201201 | bellard | void NVRAM_set_lword (m48t59_t *nvram, uint32_t addr, uint32_t value)
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314 | 64201201 | bellard | { |
315 | 64201201 | bellard | m48t59_set_addr(nvram, addr); |
316 | 64201201 | bellard | m48t59_write(nvram, value >> 24);
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317 | 64201201 | bellard | m48t59_set_addr(nvram, addr + 1);
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318 | 64201201 | bellard | m48t59_write(nvram, (value >> 16) & 0xFF); |
319 | 64201201 | bellard | m48t59_set_addr(nvram, addr + 2);
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320 | 64201201 | bellard | m48t59_write(nvram, (value >> 8) & 0xFF); |
321 | 64201201 | bellard | m48t59_set_addr(nvram, addr + 3);
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322 | 64201201 | bellard | m48t59_write(nvram, value & 0xFF);
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323 | 64201201 | bellard | } |
324 | 64201201 | bellard | |
325 | 64201201 | bellard | uint32_t NVRAM_get_lword (m48t59_t *nvram, uint32_t addr) |
326 | 64201201 | bellard | { |
327 | 64201201 | bellard | uint32_t tmp; |
328 | 64201201 | bellard | |
329 | 64201201 | bellard | m48t59_set_addr(nvram, addr); |
330 | 64201201 | bellard | tmp = m48t59_read(nvram) << 24;
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331 | 64201201 | bellard | m48t59_set_addr(nvram, addr + 1);
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332 | 64201201 | bellard | tmp |= m48t59_read(nvram) << 16;
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333 | 64201201 | bellard | m48t59_set_addr(nvram, addr + 2);
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334 | 64201201 | bellard | tmp |= m48t59_read(nvram) << 8;
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335 | 64201201 | bellard | m48t59_set_addr(nvram, addr + 3);
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336 | 64201201 | bellard | tmp |= m48t59_read(nvram); |
337 | 64201201 | bellard | |
338 | 64201201 | bellard | return tmp;
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339 | 64201201 | bellard | } |
340 | 64201201 | bellard | |
341 | 64201201 | bellard | void NVRAM_set_string (m48t59_t *nvram, uint32_t addr,
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342 | 64201201 | bellard | const unsigned char *str, uint32_t max) |
343 | 64201201 | bellard | { |
344 | 64201201 | bellard | int i;
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345 | 64201201 | bellard | |
346 | 64201201 | bellard | for (i = 0; i < max && str[i] != '\0'; i++) { |
347 | 64201201 | bellard | m48t59_set_addr(nvram, addr + i); |
348 | 64201201 | bellard | m48t59_write(nvram, str[i]); |
349 | 64201201 | bellard | } |
350 | 64201201 | bellard | m48t59_set_addr(nvram, addr + max - 1);
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351 | 64201201 | bellard | m48t59_write(nvram, '\0');
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352 | 64201201 | bellard | } |
353 | 64201201 | bellard | |
354 | 64201201 | bellard | int NVRAM_get_string (m48t59_t *nvram, uint8_t *dst, uint16_t addr, int max) |
355 | 64201201 | bellard | { |
356 | 64201201 | bellard | int i;
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357 | 64201201 | bellard | |
358 | 64201201 | bellard | memset(dst, 0, max);
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359 | 64201201 | bellard | for (i = 0; i < max; i++) { |
360 | 64201201 | bellard | dst[i] = NVRAM_get_byte(nvram, addr + i); |
361 | 64201201 | bellard | if (dst[i] == '\0') |
362 | 64201201 | bellard | break;
|
363 | 64201201 | bellard | } |
364 | 64201201 | bellard | |
365 | 64201201 | bellard | return i;
|
366 | 64201201 | bellard | } |
367 | 64201201 | bellard | |
368 | 64201201 | bellard | static uint16_t NVRAM_crc_update (uint16_t prev, uint16_t value)
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369 | 64201201 | bellard | { |
370 | 64201201 | bellard | uint16_t tmp; |
371 | 64201201 | bellard | uint16_t pd, pd1, pd2; |
372 | 64201201 | bellard | |
373 | 64201201 | bellard | tmp = prev >> 8;
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374 | 64201201 | bellard | pd = prev ^ value; |
375 | 64201201 | bellard | pd1 = pd & 0x000F;
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376 | 64201201 | bellard | pd2 = ((pd >> 4) & 0x000F) ^ pd1; |
377 | 64201201 | bellard | tmp ^= (pd1 << 3) | (pd1 << 8); |
378 | 64201201 | bellard | tmp ^= pd2 | (pd2 << 7) | (pd2 << 12); |
379 | 64201201 | bellard | |
380 | 64201201 | bellard | return tmp;
|
381 | 64201201 | bellard | } |
382 | 64201201 | bellard | |
383 | 64201201 | bellard | uint16_t NVRAM_compute_crc (m48t59_t *nvram, uint32_t start, uint32_t count) |
384 | 64201201 | bellard | { |
385 | 64201201 | bellard | uint32_t i; |
386 | 64201201 | bellard | uint16_t crc = 0xFFFF;
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387 | 64201201 | bellard | int odd;
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388 | 64201201 | bellard | |
389 | 64201201 | bellard | odd = count & 1;
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390 | 64201201 | bellard | count &= ~1;
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391 | 64201201 | bellard | for (i = 0; i != count; i++) { |
392 | 64201201 | bellard | crc = NVRAM_crc_update(crc, NVRAM_get_word(nvram, start + i)); |
393 | 64201201 | bellard | } |
394 | 64201201 | bellard | if (odd) {
|
395 | 64201201 | bellard | crc = NVRAM_crc_update(crc, NVRAM_get_byte(nvram, start + i) << 8);
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396 | 64201201 | bellard | } |
397 | 64201201 | bellard | |
398 | 64201201 | bellard | return crc;
|
399 | 64201201 | bellard | } |
400 | 64201201 | bellard | |
401 | fd0bbb12 | bellard | #define CMDLINE_ADDR 0x017ff000 |
402 | fd0bbb12 | bellard | |
403 | 64201201 | bellard | int PPC_NVRAM_set_params (m48t59_t *nvram, uint16_t NVRAM_size,
|
404 | 64201201 | bellard | const unsigned char *arch, |
405 | 64201201 | bellard | uint32_t RAM_size, int boot_device,
|
406 | 64201201 | bellard | uint32_t kernel_image, uint32_t kernel_size, |
407 | fd0bbb12 | bellard | const char *cmdline, |
408 | 64201201 | bellard | uint32_t initrd_image, uint32_t initrd_size, |
409 | fd0bbb12 | bellard | uint32_t NVRAM_image, |
410 | fd0bbb12 | bellard | int width, int height, int depth) |
411 | 64201201 | bellard | { |
412 | 64201201 | bellard | uint16_t crc; |
413 | 64201201 | bellard | |
414 | 64201201 | bellard | /* Set parameters for Open Hack'Ware BIOS */
|
415 | 64201201 | bellard | NVRAM_set_string(nvram, 0x00, "QEMU_BIOS", 16); |
416 | 64201201 | bellard | NVRAM_set_lword(nvram, 0x10, 0x00000002); /* structure v2 */ |
417 | 64201201 | bellard | NVRAM_set_word(nvram, 0x14, NVRAM_size);
|
418 | 64201201 | bellard | NVRAM_set_string(nvram, 0x20, arch, 16); |
419 | 64201201 | bellard | NVRAM_set_lword(nvram, 0x30, RAM_size);
|
420 | 64201201 | bellard | NVRAM_set_byte(nvram, 0x34, boot_device);
|
421 | 64201201 | bellard | NVRAM_set_lword(nvram, 0x38, kernel_image);
|
422 | 64201201 | bellard | NVRAM_set_lword(nvram, 0x3C, kernel_size);
|
423 | fd0bbb12 | bellard | if (cmdline) {
|
424 | fd0bbb12 | bellard | /* XXX: put the cmdline in NVRAM too ? */
|
425 | fd0bbb12 | bellard | strcpy(phys_ram_base + CMDLINE_ADDR, cmdline); |
426 | fd0bbb12 | bellard | NVRAM_set_lword(nvram, 0x40, CMDLINE_ADDR);
|
427 | fd0bbb12 | bellard | NVRAM_set_lword(nvram, 0x44, strlen(cmdline));
|
428 | fd0bbb12 | bellard | } else {
|
429 | fd0bbb12 | bellard | NVRAM_set_lword(nvram, 0x40, 0); |
430 | fd0bbb12 | bellard | NVRAM_set_lword(nvram, 0x44, 0); |
431 | fd0bbb12 | bellard | } |
432 | 64201201 | bellard | NVRAM_set_lword(nvram, 0x48, initrd_image);
|
433 | 64201201 | bellard | NVRAM_set_lword(nvram, 0x4C, initrd_size);
|
434 | 64201201 | bellard | NVRAM_set_lword(nvram, 0x50, NVRAM_image);
|
435 | fd0bbb12 | bellard | |
436 | fd0bbb12 | bellard | NVRAM_set_word(nvram, 0x54, width);
|
437 | fd0bbb12 | bellard | NVRAM_set_word(nvram, 0x56, height);
|
438 | fd0bbb12 | bellard | NVRAM_set_word(nvram, 0x58, depth);
|
439 | fd0bbb12 | bellard | crc = NVRAM_compute_crc(nvram, 0x00, 0xF8); |
440 | fd0bbb12 | bellard | NVRAM_set_word(nvram, 0xFC, crc);
|
441 | 64201201 | bellard | |
442 | 64201201 | bellard | return 0; |
443 | 64201201 | bellard | } |
444 | 64201201 | bellard | |
445 | 9fddaa0c | bellard | /*****************************************************************************/
|
446 | a541f297 | bellard | void ppc_init (int ram_size, int vga_ram_size, int boot_device, |
447 | a541f297 | bellard | DisplayState *ds, const char **fd_filename, int snapshot, |
448 | a541f297 | bellard | const char *kernel_filename, const char *kernel_cmdline, |
449 | a541f297 | bellard | const char *initrd_filename) |
450 | a541f297 | bellard | { |
451 | 64201201 | bellard | if (prep_enabled) {
|
452 | 64201201 | bellard | ppc_prep_init(ram_size, vga_ram_size, boot_device, ds, fd_filename, |
453 | 64201201 | bellard | snapshot, kernel_filename, kernel_cmdline, |
454 | 64201201 | bellard | initrd_filename); |
455 | 64201201 | bellard | } else {
|
456 | 64201201 | bellard | ppc_chrp_init(ram_size, vga_ram_size, boot_device, ds, fd_filename, |
457 | 64201201 | bellard | snapshot, kernel_filename, kernel_cmdline, |
458 | 64201201 | bellard | initrd_filename); |
459 | 64201201 | bellard | } |
460 | fd0bbb12 | bellard | /* Special port to get debug messages from Open-Firmware */
|
461 | fd0bbb12 | bellard | register_ioport_write(0x0F00, 4, 1, &PPC_debug_write, NULL); |
462 | a541f297 | bellard | } |