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1 | 80cabfad | bellard | /*
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2 | 80cabfad | bellard | * QEMU 16450 UART emulation
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3 | 80cabfad | bellard | *
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4 | 80cabfad | bellard | * Copyright (c) 2003-2004 Fabrice Bellard
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5 | 80cabfad | bellard | *
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6 | 80cabfad | bellard | * Permission is hereby granted, free of charge, to any person obtaining a copy
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7 | 80cabfad | bellard | * of this software and associated documentation files (the "Software"), to deal
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8 | 80cabfad | bellard | * in the Software without restriction, including without limitation the rights
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9 | 80cabfad | bellard | * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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10 | 80cabfad | bellard | * copies of the Software, and to permit persons to whom the Software is
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11 | 80cabfad | bellard | * furnished to do so, subject to the following conditions:
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12 | 80cabfad | bellard | *
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13 | 80cabfad | bellard | * The above copyright notice and this permission notice shall be included in
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14 | 80cabfad | bellard | * all copies or substantial portions of the Software.
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15 | 80cabfad | bellard | *
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16 | 80cabfad | bellard | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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17 | 80cabfad | bellard | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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18 | 80cabfad | bellard | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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19 | 80cabfad | bellard | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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20 | 80cabfad | bellard | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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21 | 80cabfad | bellard | * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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22 | 80cabfad | bellard | * THE SOFTWARE.
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23 | 80cabfad | bellard | */
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24 | 80cabfad | bellard | #include "vl.h" |
25 | 80cabfad | bellard | |
26 | 80cabfad | bellard | //#define DEBUG_SERIAL
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27 | 80cabfad | bellard | |
28 | 80cabfad | bellard | #define UART_LCR_DLAB 0x80 /* Divisor latch access bit */ |
29 | 80cabfad | bellard | |
30 | 80cabfad | bellard | #define UART_IER_MSI 0x08 /* Enable Modem status interrupt */ |
31 | 80cabfad | bellard | #define UART_IER_RLSI 0x04 /* Enable receiver line status interrupt */ |
32 | 80cabfad | bellard | #define UART_IER_THRI 0x02 /* Enable Transmitter holding register int. */ |
33 | 80cabfad | bellard | #define UART_IER_RDI 0x01 /* Enable receiver data interrupt */ |
34 | 80cabfad | bellard | |
35 | 80cabfad | bellard | #define UART_IIR_NO_INT 0x01 /* No interrupts pending */ |
36 | 80cabfad | bellard | #define UART_IIR_ID 0x06 /* Mask for the interrupt ID */ |
37 | 80cabfad | bellard | |
38 | 80cabfad | bellard | #define UART_IIR_MSI 0x00 /* Modem status interrupt */ |
39 | 80cabfad | bellard | #define UART_IIR_THRI 0x02 /* Transmitter holding register empty */ |
40 | 80cabfad | bellard | #define UART_IIR_RDI 0x04 /* Receiver data interrupt */ |
41 | 80cabfad | bellard | #define UART_IIR_RLSI 0x06 /* Receiver line status interrupt */ |
42 | 80cabfad | bellard | |
43 | 80cabfad | bellard | /*
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44 | 80cabfad | bellard | * These are the definitions for the Modem Control Register
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45 | 80cabfad | bellard | */
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46 | 80cabfad | bellard | #define UART_MCR_LOOP 0x10 /* Enable loopback test mode */ |
47 | 80cabfad | bellard | #define UART_MCR_OUT2 0x08 /* Out2 complement */ |
48 | 80cabfad | bellard | #define UART_MCR_OUT1 0x04 /* Out1 complement */ |
49 | 80cabfad | bellard | #define UART_MCR_RTS 0x02 /* RTS complement */ |
50 | 80cabfad | bellard | #define UART_MCR_DTR 0x01 /* DTR complement */ |
51 | 80cabfad | bellard | |
52 | 80cabfad | bellard | /*
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53 | 80cabfad | bellard | * These are the definitions for the Modem Status Register
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54 | 80cabfad | bellard | */
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55 | 80cabfad | bellard | #define UART_MSR_DCD 0x80 /* Data Carrier Detect */ |
56 | 80cabfad | bellard | #define UART_MSR_RI 0x40 /* Ring Indicator */ |
57 | 80cabfad | bellard | #define UART_MSR_DSR 0x20 /* Data Set Ready */ |
58 | 80cabfad | bellard | #define UART_MSR_CTS 0x10 /* Clear to Send */ |
59 | 80cabfad | bellard | #define UART_MSR_DDCD 0x08 /* Delta DCD */ |
60 | 80cabfad | bellard | #define UART_MSR_TERI 0x04 /* Trailing edge ring indicator */ |
61 | 80cabfad | bellard | #define UART_MSR_DDSR 0x02 /* Delta DSR */ |
62 | 80cabfad | bellard | #define UART_MSR_DCTS 0x01 /* Delta CTS */ |
63 | 80cabfad | bellard | #define UART_MSR_ANY_DELTA 0x0F /* Any of the delta bits! */ |
64 | 80cabfad | bellard | |
65 | 80cabfad | bellard | #define UART_LSR_TEMT 0x40 /* Transmitter empty */ |
66 | 80cabfad | bellard | #define UART_LSR_THRE 0x20 /* Transmit-hold-register empty */ |
67 | 80cabfad | bellard | #define UART_LSR_BI 0x10 /* Break interrupt indicator */ |
68 | 80cabfad | bellard | #define UART_LSR_FE 0x08 /* Frame error indicator */ |
69 | 80cabfad | bellard | #define UART_LSR_PE 0x04 /* Parity error indicator */ |
70 | 80cabfad | bellard | #define UART_LSR_OE 0x02 /* Overrun error indicator */ |
71 | 80cabfad | bellard | #define UART_LSR_DR 0x01 /* Receiver data ready */ |
72 | 80cabfad | bellard | |
73 | b41a2cd1 | bellard | struct SerialState {
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74 | 80cabfad | bellard | uint8_t divider; |
75 | 80cabfad | bellard | uint8_t rbr; /* receive register */
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76 | 80cabfad | bellard | uint8_t ier; |
77 | 80cabfad | bellard | uint8_t iir; /* read only */
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78 | 80cabfad | bellard | uint8_t lcr; |
79 | 80cabfad | bellard | uint8_t mcr; |
80 | 80cabfad | bellard | uint8_t lsr; /* read only */
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81 | 80cabfad | bellard | uint8_t msr; |
82 | 80cabfad | bellard | uint8_t scr; |
83 | 80cabfad | bellard | /* NOTE: this hidden state is necessary for tx irq generation as
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84 | 80cabfad | bellard | it can be reset while reading iir */
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85 | 80cabfad | bellard | int thr_ipending;
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86 | 80cabfad | bellard | int irq;
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87 | 82c643ff | bellard | CharDriverState *chr; |
88 | b41a2cd1 | bellard | }; |
89 | 80cabfad | bellard | |
90 | b41a2cd1 | bellard | static void serial_update_irq(SerialState *s) |
91 | 80cabfad | bellard | { |
92 | 80cabfad | bellard | if ((s->lsr & UART_LSR_DR) && (s->ier & UART_IER_RDI)) {
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93 | 80cabfad | bellard | s->iir = UART_IIR_RDI; |
94 | 80cabfad | bellard | } else if (s->thr_ipending && (s->ier & UART_IER_THRI)) { |
95 | 80cabfad | bellard | s->iir = UART_IIR_THRI; |
96 | 80cabfad | bellard | } else {
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97 | 80cabfad | bellard | s->iir = UART_IIR_NO_INT; |
98 | 80cabfad | bellard | } |
99 | 80cabfad | bellard | if (s->iir != UART_IIR_NO_INT) {
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100 | 80cabfad | bellard | pic_set_irq(s->irq, 1);
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101 | 80cabfad | bellard | } else {
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102 | 80cabfad | bellard | pic_set_irq(s->irq, 0);
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103 | 80cabfad | bellard | } |
104 | 80cabfad | bellard | } |
105 | 80cabfad | bellard | |
106 | b41a2cd1 | bellard | static void serial_ioport_write(void *opaque, uint32_t addr, uint32_t val) |
107 | 80cabfad | bellard | { |
108 | b41a2cd1 | bellard | SerialState *s = opaque; |
109 | 80cabfad | bellard | unsigned char ch; |
110 | 80cabfad | bellard | |
111 | 80cabfad | bellard | addr &= 7;
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112 | 80cabfad | bellard | #ifdef DEBUG_SERIAL
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113 | 80cabfad | bellard | printf("serial: write addr=0x%02x val=0x%02x\n", addr, val);
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114 | 80cabfad | bellard | #endif
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115 | 80cabfad | bellard | switch(addr) {
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116 | 80cabfad | bellard | default:
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117 | 80cabfad | bellard | case 0: |
118 | 80cabfad | bellard | if (s->lcr & UART_LCR_DLAB) {
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119 | 80cabfad | bellard | s->divider = (s->divider & 0xff00) | val;
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120 | 80cabfad | bellard | } else {
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121 | 80cabfad | bellard | s->thr_ipending = 0;
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122 | 80cabfad | bellard | s->lsr &= ~UART_LSR_THRE; |
123 | b41a2cd1 | bellard | serial_update_irq(s); |
124 | 82c643ff | bellard | ch = val; |
125 | 82c643ff | bellard | qemu_chr_write(s->chr, &ch, 1);
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126 | 80cabfad | bellard | s->thr_ipending = 1;
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127 | 80cabfad | bellard | s->lsr |= UART_LSR_THRE; |
128 | 80cabfad | bellard | s->lsr |= UART_LSR_TEMT; |
129 | b41a2cd1 | bellard | serial_update_irq(s); |
130 | 80cabfad | bellard | } |
131 | 80cabfad | bellard | break;
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132 | 80cabfad | bellard | case 1: |
133 | 80cabfad | bellard | if (s->lcr & UART_LCR_DLAB) {
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134 | 80cabfad | bellard | s->divider = (s->divider & 0x00ff) | (val << 8); |
135 | 80cabfad | bellard | } else {
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136 | 60e336db | bellard | s->ier = val & 0x0f;
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137 | 60e336db | bellard | if (s->lsr & UART_LSR_THRE) {
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138 | 60e336db | bellard | s->thr_ipending = 1;
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139 | 60e336db | bellard | } |
140 | b41a2cd1 | bellard | serial_update_irq(s); |
141 | 80cabfad | bellard | } |
142 | 80cabfad | bellard | break;
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143 | 80cabfad | bellard | case 2: |
144 | 80cabfad | bellard | break;
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145 | 80cabfad | bellard | case 3: |
146 | 80cabfad | bellard | s->lcr = val; |
147 | 80cabfad | bellard | break;
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148 | 80cabfad | bellard | case 4: |
149 | 60e336db | bellard | s->mcr = val & 0x1f;
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150 | 80cabfad | bellard | break;
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151 | 80cabfad | bellard | case 5: |
152 | 80cabfad | bellard | break;
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153 | 80cabfad | bellard | case 6: |
154 | 80cabfad | bellard | s->msr = val; |
155 | 80cabfad | bellard | break;
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156 | 80cabfad | bellard | case 7: |
157 | 80cabfad | bellard | s->scr = val; |
158 | 80cabfad | bellard | break;
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159 | 80cabfad | bellard | } |
160 | 80cabfad | bellard | } |
161 | 80cabfad | bellard | |
162 | b41a2cd1 | bellard | static uint32_t serial_ioport_read(void *opaque, uint32_t addr) |
163 | 80cabfad | bellard | { |
164 | b41a2cd1 | bellard | SerialState *s = opaque; |
165 | 80cabfad | bellard | uint32_t ret; |
166 | 80cabfad | bellard | |
167 | 80cabfad | bellard | addr &= 7;
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168 | 80cabfad | bellard | switch(addr) {
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169 | 80cabfad | bellard | default:
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170 | 80cabfad | bellard | case 0: |
171 | 80cabfad | bellard | if (s->lcr & UART_LCR_DLAB) {
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172 | 80cabfad | bellard | ret = s->divider & 0xff;
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173 | 80cabfad | bellard | } else {
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174 | 80cabfad | bellard | ret = s->rbr; |
175 | 80cabfad | bellard | s->lsr &= ~(UART_LSR_DR | UART_LSR_BI); |
176 | b41a2cd1 | bellard | serial_update_irq(s); |
177 | 80cabfad | bellard | } |
178 | 80cabfad | bellard | break;
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179 | 80cabfad | bellard | case 1: |
180 | 80cabfad | bellard | if (s->lcr & UART_LCR_DLAB) {
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181 | 80cabfad | bellard | ret = (s->divider >> 8) & 0xff; |
182 | 80cabfad | bellard | } else {
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183 | 80cabfad | bellard | ret = s->ier; |
184 | 80cabfad | bellard | } |
185 | 80cabfad | bellard | break;
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186 | 80cabfad | bellard | case 2: |
187 | 80cabfad | bellard | ret = s->iir; |
188 | 80cabfad | bellard | /* reset THR pending bit */
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189 | 80cabfad | bellard | if ((ret & 0x7) == UART_IIR_THRI) |
190 | 80cabfad | bellard | s->thr_ipending = 0;
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191 | b41a2cd1 | bellard | serial_update_irq(s); |
192 | 80cabfad | bellard | break;
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193 | 80cabfad | bellard | case 3: |
194 | 80cabfad | bellard | ret = s->lcr; |
195 | 80cabfad | bellard | break;
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196 | 80cabfad | bellard | case 4: |
197 | 80cabfad | bellard | ret = s->mcr; |
198 | 80cabfad | bellard | break;
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199 | 80cabfad | bellard | case 5: |
200 | 80cabfad | bellard | ret = s->lsr; |
201 | 80cabfad | bellard | break;
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202 | 80cabfad | bellard | case 6: |
203 | 80cabfad | bellard | if (s->mcr & UART_MCR_LOOP) {
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204 | 80cabfad | bellard | /* in loopback, the modem output pins are connected to the
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205 | 80cabfad | bellard | inputs */
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206 | 80cabfad | bellard | ret = (s->mcr & 0x0c) << 4; |
207 | 80cabfad | bellard | ret |= (s->mcr & 0x02) << 3; |
208 | 80cabfad | bellard | ret |= (s->mcr & 0x01) << 5; |
209 | 80cabfad | bellard | } else {
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210 | 80cabfad | bellard | ret = s->msr; |
211 | 80cabfad | bellard | } |
212 | 80cabfad | bellard | break;
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213 | 80cabfad | bellard | case 7: |
214 | 80cabfad | bellard | ret = s->scr; |
215 | 80cabfad | bellard | break;
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216 | 80cabfad | bellard | } |
217 | 80cabfad | bellard | #ifdef DEBUG_SERIAL
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218 | 80cabfad | bellard | printf("serial: read addr=0x%02x val=0x%02x\n", addr, ret);
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219 | 80cabfad | bellard | #endif
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220 | 80cabfad | bellard | return ret;
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221 | 80cabfad | bellard | } |
222 | 80cabfad | bellard | |
223 | 82c643ff | bellard | static int serial_can_receive(SerialState *s) |
224 | 80cabfad | bellard | { |
225 | 80cabfad | bellard | return !(s->lsr & UART_LSR_DR);
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226 | 80cabfad | bellard | } |
227 | 80cabfad | bellard | |
228 | 82c643ff | bellard | static void serial_receive_byte(SerialState *s, int ch) |
229 | 80cabfad | bellard | { |
230 | 80cabfad | bellard | s->rbr = ch; |
231 | 80cabfad | bellard | s->lsr |= UART_LSR_DR; |
232 | b41a2cd1 | bellard | serial_update_irq(s); |
233 | 80cabfad | bellard | } |
234 | 80cabfad | bellard | |
235 | 82c643ff | bellard | static void serial_receive_break(SerialState *s) |
236 | 80cabfad | bellard | { |
237 | 80cabfad | bellard | s->rbr = 0;
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238 | 80cabfad | bellard | s->lsr |= UART_LSR_BI | UART_LSR_DR; |
239 | b41a2cd1 | bellard | serial_update_irq(s); |
240 | 80cabfad | bellard | } |
241 | 80cabfad | bellard | |
242 | b41a2cd1 | bellard | static int serial_can_receive1(void *opaque) |
243 | 80cabfad | bellard | { |
244 | b41a2cd1 | bellard | SerialState *s = opaque; |
245 | b41a2cd1 | bellard | return serial_can_receive(s);
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246 | b41a2cd1 | bellard | } |
247 | b41a2cd1 | bellard | |
248 | b41a2cd1 | bellard | static void serial_receive1(void *opaque, const uint8_t *buf, int size) |
249 | b41a2cd1 | bellard | { |
250 | b41a2cd1 | bellard | SerialState *s = opaque; |
251 | b41a2cd1 | bellard | serial_receive_byte(s, buf[0]);
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252 | b41a2cd1 | bellard | } |
253 | 80cabfad | bellard | |
254 | 82c643ff | bellard | static void serial_event(void *opaque, int event) |
255 | 82c643ff | bellard | { |
256 | 82c643ff | bellard | SerialState *s = opaque; |
257 | 82c643ff | bellard | if (event == CHR_EVENT_BREAK)
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258 | 82c643ff | bellard | serial_receive_break(s); |
259 | 82c643ff | bellard | } |
260 | 82c643ff | bellard | |
261 | b41a2cd1 | bellard | /* If fd is zero, it means that the serial device uses the console */
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262 | 82c643ff | bellard | SerialState *serial_init(int base, int irq, CharDriverState *chr) |
263 | b41a2cd1 | bellard | { |
264 | b41a2cd1 | bellard | SerialState *s; |
265 | b41a2cd1 | bellard | |
266 | b41a2cd1 | bellard | s = qemu_mallocz(sizeof(SerialState));
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267 | b41a2cd1 | bellard | if (!s)
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268 | b41a2cd1 | bellard | return NULL; |
269 | 80cabfad | bellard | s->irq = irq; |
270 | 80cabfad | bellard | s->lsr = UART_LSR_TEMT | UART_LSR_THRE; |
271 | 80cabfad | bellard | s->iir = UART_IIR_NO_INT; |
272 | b41a2cd1 | bellard | |
273 | b41a2cd1 | bellard | register_ioport_write(base, 8, 1, serial_ioport_write, s); |
274 | b41a2cd1 | bellard | register_ioport_read(base, 8, 1, serial_ioport_read, s); |
275 | 82c643ff | bellard | s->chr = chr; |
276 | 82c643ff | bellard | qemu_chr_add_read_handler(chr, serial_can_receive1, serial_receive1, s); |
277 | 82c643ff | bellard | qemu_chr_add_event_handler(chr, serial_event); |
278 | b41a2cd1 | bellard | return s;
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279 | 80cabfad | bellard | } |