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1 | 00406dff | bellard | /*
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2 | 00406dff | bellard | NetWinder Floating Point Emulator
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3 | 00406dff | bellard | (c) Rebel.com, 1998-1999
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4 | 00406dff | bellard | |
5 | 00406dff | bellard | Direct questions, comments to Scott Bambrough <scottb@netwinder.org>
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6 | 00406dff | bellard | |
7 | 00406dff | bellard | This program is free software; you can redistribute it and/or modify
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8 | 00406dff | bellard | it under the terms of the GNU General Public License as published by
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9 | 00406dff | bellard | the Free Software Foundation; either version 2 of the License, or
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10 | 00406dff | bellard | (at your option) any later version.
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11 | 00406dff | bellard | |
12 | 00406dff | bellard | This program is distributed in the hope that it will be useful,
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13 | 00406dff | bellard | but WITHOUT ANY WARRANTY; without even the implied warranty of
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14 | 00406dff | bellard | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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15 | 00406dff | bellard | GNU General Public License for more details.
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16 | 00406dff | bellard | |
17 | 00406dff | bellard | You should have received a copy of the GNU General Public License
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18 | 00406dff | bellard | along with this program; if not, write to the Free Software
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19 | 00406dff | bellard | Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
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20 | 00406dff | bellard | */
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21 | 00406dff | bellard | |
22 | 00406dff | bellard | #ifndef __FPSR_H__
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23 | 00406dff | bellard | #define __FPSR_H__
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24 | 00406dff | bellard | |
25 | 00406dff | bellard | /*
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26 | 00406dff | bellard | The FPSR is a 32 bit register consisting of 4 parts, each exactly
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27 | 00406dff | bellard | one byte.
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28 | 00406dff | bellard | |
29 | 00406dff | bellard | SYSTEM ID
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30 | 00406dff | bellard | EXCEPTION TRAP ENABLE BYTE
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31 | 00406dff | bellard | SYSTEM CONTROL BYTE
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32 | 00406dff | bellard | CUMULATIVE EXCEPTION FLAGS BYTE
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33 | 00406dff | bellard |
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34 | 00406dff | bellard | The FPCR is a 32 bit register consisting of bit flags.
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35 | 00406dff | bellard | */
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36 | 00406dff | bellard | |
37 | 00406dff | bellard | /* SYSTEM ID
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38 | 00406dff | bellard | ------------
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39 | 00406dff | bellard | Note: the system id byte is read only */
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40 | 00406dff | bellard | |
41 | 00406dff | bellard | typedef unsigned int FPSR; /* type for floating point status register */ |
42 | 00406dff | bellard | typedef unsigned int FPCR; /* type for floating point control register */ |
43 | 00406dff | bellard | |
44 | 00406dff | bellard | #define MASK_SYSID 0xff000000 |
45 | 00406dff | bellard | #define BIT_HARDWARE 0x80000000 |
46 | 00406dff | bellard | #define FP_EMULATOR 0x01000000 /* System ID for emulator */ |
47 | 00406dff | bellard | #define FP_ACCELERATOR 0x81000000 /* System ID for FPA11 */ |
48 | 00406dff | bellard | |
49 | 00406dff | bellard | /* EXCEPTION TRAP ENABLE BYTE
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50 | 00406dff | bellard | ----------------------------- */
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51 | 00406dff | bellard | |
52 | 00406dff | bellard | #define MASK_TRAP_ENABLE 0x00ff0000 |
53 | 00406dff | bellard | #define MASK_TRAP_ENABLE_STRICT 0x001f0000 |
54 | 00406dff | bellard | #define BIT_IXE 0x00100000 /* inexact exception enable */ |
55 | 00406dff | bellard | #define BIT_UFE 0x00080000 /* underflow exception enable */ |
56 | 00406dff | bellard | #define BIT_OFE 0x00040000 /* overflow exception enable */ |
57 | 00406dff | bellard | #define BIT_DZE 0x00020000 /* divide by zero exception enable */ |
58 | 00406dff | bellard | #define BIT_IOE 0x00010000 /* invalid operation exception enable */ |
59 | 00406dff | bellard | |
60 | 00406dff | bellard | /* SYSTEM CONTROL BYTE
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61 | 00406dff | bellard | ---------------------- */
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62 | 00406dff | bellard | |
63 | 00406dff | bellard | #define MASK_SYSTEM_CONTROL 0x0000ff00 |
64 | 00406dff | bellard | #define MASK_TRAP_STRICT 0x00001f00 |
65 | 00406dff | bellard | |
66 | 00406dff | bellard | #define BIT_AC 0x00001000 /* use alternative C-flag definition |
67 | 00406dff | bellard | for compares */
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68 | 00406dff | bellard | #define BIT_EP 0x00000800 /* use expanded packed decimal format */ |
69 | 00406dff | bellard | #define BIT_SO 0x00000400 /* select synchronous operation of FPA */ |
70 | 00406dff | bellard | #define BIT_NE 0x00000200 /* NaN exception bit */ |
71 | 00406dff | bellard | #define BIT_ND 0x00000100 /* no denormalized numbers bit */ |
72 | 00406dff | bellard | |
73 | 00406dff | bellard | /* CUMULATIVE EXCEPTION FLAGS BYTE
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74 | 00406dff | bellard | ---------------------------------- */
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75 | 00406dff | bellard | |
76 | 00406dff | bellard | #define MASK_EXCEPTION_FLAGS 0x000000ff |
77 | 00406dff | bellard | #define MASK_EXCEPTION_FLAGS_STRICT 0x0000001f |
78 | 00406dff | bellard | |
79 | 00406dff | bellard | #define BIT_IXC 0x00000010 /* inexact exception flag */ |
80 | 00406dff | bellard | #define BIT_UFC 0x00000008 /* underflow exception flag */ |
81 | 00406dff | bellard | #define BIT_OFC 0x00000004 /* overfloat exception flag */ |
82 | 00406dff | bellard | #define BIT_DZC 0x00000002 /* divide by zero exception flag */ |
83 | 00406dff | bellard | #define BIT_IOC 0x00000001 /* invalid operation exception flag */ |
84 | 00406dff | bellard | |
85 | 00406dff | bellard | /* Floating Point Control Register
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86 | 00406dff | bellard | ----------------------------------*/
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87 | 00406dff | bellard | |
88 | 00406dff | bellard | #define BIT_RU 0x80000000 /* rounded up bit */ |
89 | 00406dff | bellard | #define BIT_IE 0x10000000 /* inexact bit */ |
90 | 00406dff | bellard | #define BIT_MO 0x08000000 /* mantissa overflow bit */ |
91 | 00406dff | bellard | #define BIT_EO 0x04000000 /* exponent overflow bit */ |
92 | 00406dff | bellard | #define BIT_SB 0x00000800 /* store bounce */ |
93 | 00406dff | bellard | #define BIT_AB 0x00000400 /* arithmetic bounce */ |
94 | 00406dff | bellard | #define BIT_RE 0x00000200 /* rounding exception */ |
95 | 00406dff | bellard | #define BIT_DA 0x00000100 /* disable FPA */ |
96 | 00406dff | bellard | |
97 | 00406dff | bellard | #define MASK_OP 0x00f08010 /* AU operation code */ |
98 | 00406dff | bellard | #define MASK_PR 0x00080080 /* AU precision */ |
99 | 00406dff | bellard | #define MASK_S1 0x00070000 /* AU source register 1 */ |
100 | 00406dff | bellard | #define MASK_S2 0x00000007 /* AU source register 2 */ |
101 | 00406dff | bellard | #define MASK_DS 0x00007000 /* AU destination register */ |
102 | 00406dff | bellard | #define MASK_RM 0x00000060 /* AU rounding mode */ |
103 | 00406dff | bellard | #define MASK_ALU 0x9cfff2ff /* only ALU can write these bits */ |
104 | 00406dff | bellard | #define MASK_RESET 0x00000d00 /* bits set on reset, all others cleared */ |
105 | 00406dff | bellard | #define MASK_WFC MASK_RESET
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106 | 00406dff | bellard | #define MASK_RFC ~MASK_RESET
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107 | 00406dff | bellard | |
108 | 00406dff | bellard | #endif |