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1 | 2c0262af | bellard | /*
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2 | 2c0262af | bellard | * ARM translation
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3 | 2c0262af | bellard | *
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4 | 2c0262af | bellard | * Copyright (c) 2003 Fabrice Bellard
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5 | 2c0262af | bellard | *
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6 | 2c0262af | bellard | * This library is free software; you can redistribute it and/or
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7 | 2c0262af | bellard | * modify it under the terms of the GNU Lesser General Public
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8 | 2c0262af | bellard | * License as published by the Free Software Foundation; either
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9 | 2c0262af | bellard | * version 2 of the License, or (at your option) any later version.
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10 | 2c0262af | bellard | *
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11 | 2c0262af | bellard | * This library is distributed in the hope that it will be useful,
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12 | 2c0262af | bellard | * but WITHOUT ANY WARRANTY; without even the implied warranty of
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13 | 2c0262af | bellard | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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14 | 2c0262af | bellard | * Lesser General Public License for more details.
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15 | 2c0262af | bellard | *
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16 | 2c0262af | bellard | * You should have received a copy of the GNU Lesser General Public
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17 | 2c0262af | bellard | * License along with this library; if not, write to the Free Software
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18 | 2c0262af | bellard | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
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19 | 2c0262af | bellard | */
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20 | 2c0262af | bellard | #include <stdarg.h> |
21 | 2c0262af | bellard | #include <stdlib.h> |
22 | 2c0262af | bellard | #include <stdio.h> |
23 | 2c0262af | bellard | #include <string.h> |
24 | 2c0262af | bellard | #include <inttypes.h> |
25 | 2c0262af | bellard | |
26 | 2c0262af | bellard | #include "cpu.h" |
27 | 2c0262af | bellard | #include "exec-all.h" |
28 | 2c0262af | bellard | #include "disas.h" |
29 | 2c0262af | bellard | |
30 | 2c0262af | bellard | /* internal defines */
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31 | 2c0262af | bellard | typedef struct DisasContext { |
32 | 0fa85d43 | bellard | target_ulong pc; |
33 | 2c0262af | bellard | int is_jmp;
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34 | 2c0262af | bellard | struct TranslationBlock *tb;
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35 | 2c0262af | bellard | } DisasContext; |
36 | 2c0262af | bellard | |
37 | 2c0262af | bellard | #define DISAS_JUMP_NEXT 4 |
38 | 2c0262af | bellard | |
39 | 2c0262af | bellard | /* XXX: move that elsewhere */
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40 | 2c0262af | bellard | static uint16_t *gen_opc_ptr;
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41 | 2c0262af | bellard | static uint32_t *gen_opparam_ptr;
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42 | 2c0262af | bellard | extern FILE *logfile;
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43 | 2c0262af | bellard | extern int loglevel; |
44 | 2c0262af | bellard | |
45 | 2c0262af | bellard | enum {
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46 | 2c0262af | bellard | #define DEF(s, n, copy_size) INDEX_op_ ## s, |
47 | 2c0262af | bellard | #include "opc.h" |
48 | 2c0262af | bellard | #undef DEF
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49 | 2c0262af | bellard | NB_OPS, |
50 | 2c0262af | bellard | }; |
51 | 2c0262af | bellard | |
52 | 2c0262af | bellard | #include "gen-op.h" |
53 | 2c0262af | bellard | |
54 | 2c0262af | bellard | static GenOpFunc2 *gen_test_cc[14] = { |
55 | 2c0262af | bellard | gen_op_test_eq, |
56 | 2c0262af | bellard | gen_op_test_ne, |
57 | 2c0262af | bellard | gen_op_test_cs, |
58 | 2c0262af | bellard | gen_op_test_cc, |
59 | 2c0262af | bellard | gen_op_test_mi, |
60 | 2c0262af | bellard | gen_op_test_pl, |
61 | 2c0262af | bellard | gen_op_test_vs, |
62 | 2c0262af | bellard | gen_op_test_vc, |
63 | 2c0262af | bellard | gen_op_test_hi, |
64 | 2c0262af | bellard | gen_op_test_ls, |
65 | 2c0262af | bellard | gen_op_test_ge, |
66 | 2c0262af | bellard | gen_op_test_lt, |
67 | 2c0262af | bellard | gen_op_test_gt, |
68 | 2c0262af | bellard | gen_op_test_le, |
69 | 2c0262af | bellard | }; |
70 | 2c0262af | bellard | |
71 | 2c0262af | bellard | const uint8_t table_logic_cc[16] = { |
72 | 2c0262af | bellard | 1, /* and */ |
73 | 2c0262af | bellard | 1, /* xor */ |
74 | 2c0262af | bellard | 0, /* sub */ |
75 | 2c0262af | bellard | 0, /* rsb */ |
76 | 2c0262af | bellard | 0, /* add */ |
77 | 2c0262af | bellard | 0, /* adc */ |
78 | 2c0262af | bellard | 0, /* sbc */ |
79 | 2c0262af | bellard | 0, /* rsc */ |
80 | 2c0262af | bellard | 1, /* andl */ |
81 | 2c0262af | bellard | 1, /* xorl */ |
82 | 2c0262af | bellard | 0, /* cmp */ |
83 | 2c0262af | bellard | 0, /* cmn */ |
84 | 2c0262af | bellard | 1, /* orr */ |
85 | 2c0262af | bellard | 1, /* mov */ |
86 | 2c0262af | bellard | 1, /* bic */ |
87 | 2c0262af | bellard | 1, /* mvn */ |
88 | 2c0262af | bellard | }; |
89 | 2c0262af | bellard | |
90 | 2c0262af | bellard | static GenOpFunc1 *gen_shift_T1_im[4] = { |
91 | 2c0262af | bellard | gen_op_shll_T1_im, |
92 | 2c0262af | bellard | gen_op_shrl_T1_im, |
93 | 2c0262af | bellard | gen_op_sarl_T1_im, |
94 | 2c0262af | bellard | gen_op_rorl_T1_im, |
95 | 2c0262af | bellard | }; |
96 | 2c0262af | bellard | |
97 | 1e8d4eec | bellard | static GenOpFunc *gen_shift_T1_0[4] = { |
98 | 1e8d4eec | bellard | NULL,
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99 | 1e8d4eec | bellard | gen_op_shrl_T1_0, |
100 | 1e8d4eec | bellard | gen_op_sarl_T1_0, |
101 | 1e8d4eec | bellard | gen_op_rrxl_T1, |
102 | 1e8d4eec | bellard | }; |
103 | 1e8d4eec | bellard | |
104 | 2c0262af | bellard | static GenOpFunc1 *gen_shift_T2_im[4] = { |
105 | 2c0262af | bellard | gen_op_shll_T2_im, |
106 | 2c0262af | bellard | gen_op_shrl_T2_im, |
107 | 2c0262af | bellard | gen_op_sarl_T2_im, |
108 | 2c0262af | bellard | gen_op_rorl_T2_im, |
109 | 2c0262af | bellard | }; |
110 | 2c0262af | bellard | |
111 | 1e8d4eec | bellard | static GenOpFunc *gen_shift_T2_0[4] = { |
112 | 1e8d4eec | bellard | NULL,
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113 | 1e8d4eec | bellard | gen_op_shrl_T2_0, |
114 | 1e8d4eec | bellard | gen_op_sarl_T2_0, |
115 | 1e8d4eec | bellard | gen_op_rrxl_T2, |
116 | 1e8d4eec | bellard | }; |
117 | 1e8d4eec | bellard | |
118 | 2c0262af | bellard | static GenOpFunc1 *gen_shift_T1_im_cc[4] = { |
119 | 2c0262af | bellard | gen_op_shll_T1_im_cc, |
120 | 2c0262af | bellard | gen_op_shrl_T1_im_cc, |
121 | 2c0262af | bellard | gen_op_sarl_T1_im_cc, |
122 | 2c0262af | bellard | gen_op_rorl_T1_im_cc, |
123 | 2c0262af | bellard | }; |
124 | 2c0262af | bellard | |
125 | 1e8d4eec | bellard | static GenOpFunc *gen_shift_T1_0_cc[4] = { |
126 | 1e8d4eec | bellard | NULL,
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127 | 1e8d4eec | bellard | gen_op_shrl_T1_0_cc, |
128 | 1e8d4eec | bellard | gen_op_sarl_T1_0_cc, |
129 | 1e8d4eec | bellard | gen_op_rrxl_T1_cc, |
130 | 1e8d4eec | bellard | }; |
131 | 1e8d4eec | bellard | |
132 | 2c0262af | bellard | static GenOpFunc *gen_shift_T1_T0[4] = { |
133 | 2c0262af | bellard | gen_op_shll_T1_T0, |
134 | 2c0262af | bellard | gen_op_shrl_T1_T0, |
135 | 2c0262af | bellard | gen_op_sarl_T1_T0, |
136 | 2c0262af | bellard | gen_op_rorl_T1_T0, |
137 | 2c0262af | bellard | }; |
138 | 2c0262af | bellard | |
139 | 2c0262af | bellard | static GenOpFunc *gen_shift_T1_T0_cc[4] = { |
140 | 2c0262af | bellard | gen_op_shll_T1_T0_cc, |
141 | 2c0262af | bellard | gen_op_shrl_T1_T0_cc, |
142 | 2c0262af | bellard | gen_op_sarl_T1_T0_cc, |
143 | 2c0262af | bellard | gen_op_rorl_T1_T0_cc, |
144 | 2c0262af | bellard | }; |
145 | 2c0262af | bellard | |
146 | 2c0262af | bellard | static GenOpFunc *gen_op_movl_TN_reg[3][16] = { |
147 | 2c0262af | bellard | { |
148 | 2c0262af | bellard | gen_op_movl_T0_r0, |
149 | 2c0262af | bellard | gen_op_movl_T0_r1, |
150 | 2c0262af | bellard | gen_op_movl_T0_r2, |
151 | 2c0262af | bellard | gen_op_movl_T0_r3, |
152 | 2c0262af | bellard | gen_op_movl_T0_r4, |
153 | 2c0262af | bellard | gen_op_movl_T0_r5, |
154 | 2c0262af | bellard | gen_op_movl_T0_r6, |
155 | 2c0262af | bellard | gen_op_movl_T0_r7, |
156 | 2c0262af | bellard | gen_op_movl_T0_r8, |
157 | 2c0262af | bellard | gen_op_movl_T0_r9, |
158 | 2c0262af | bellard | gen_op_movl_T0_r10, |
159 | 2c0262af | bellard | gen_op_movl_T0_r11, |
160 | 2c0262af | bellard | gen_op_movl_T0_r12, |
161 | 2c0262af | bellard | gen_op_movl_T0_r13, |
162 | 2c0262af | bellard | gen_op_movl_T0_r14, |
163 | 2c0262af | bellard | gen_op_movl_T0_r15, |
164 | 2c0262af | bellard | }, |
165 | 2c0262af | bellard | { |
166 | 2c0262af | bellard | gen_op_movl_T1_r0, |
167 | 2c0262af | bellard | gen_op_movl_T1_r1, |
168 | 2c0262af | bellard | gen_op_movl_T1_r2, |
169 | 2c0262af | bellard | gen_op_movl_T1_r3, |
170 | 2c0262af | bellard | gen_op_movl_T1_r4, |
171 | 2c0262af | bellard | gen_op_movl_T1_r5, |
172 | 2c0262af | bellard | gen_op_movl_T1_r6, |
173 | 2c0262af | bellard | gen_op_movl_T1_r7, |
174 | 2c0262af | bellard | gen_op_movl_T1_r8, |
175 | 2c0262af | bellard | gen_op_movl_T1_r9, |
176 | 2c0262af | bellard | gen_op_movl_T1_r10, |
177 | 2c0262af | bellard | gen_op_movl_T1_r11, |
178 | 2c0262af | bellard | gen_op_movl_T1_r12, |
179 | 2c0262af | bellard | gen_op_movl_T1_r13, |
180 | 2c0262af | bellard | gen_op_movl_T1_r14, |
181 | 2c0262af | bellard | gen_op_movl_T1_r15, |
182 | 2c0262af | bellard | }, |
183 | 2c0262af | bellard | { |
184 | 2c0262af | bellard | gen_op_movl_T2_r0, |
185 | 2c0262af | bellard | gen_op_movl_T2_r1, |
186 | 2c0262af | bellard | gen_op_movl_T2_r2, |
187 | 2c0262af | bellard | gen_op_movl_T2_r3, |
188 | 2c0262af | bellard | gen_op_movl_T2_r4, |
189 | 2c0262af | bellard | gen_op_movl_T2_r5, |
190 | 2c0262af | bellard | gen_op_movl_T2_r6, |
191 | 2c0262af | bellard | gen_op_movl_T2_r7, |
192 | 2c0262af | bellard | gen_op_movl_T2_r8, |
193 | 2c0262af | bellard | gen_op_movl_T2_r9, |
194 | 2c0262af | bellard | gen_op_movl_T2_r10, |
195 | 2c0262af | bellard | gen_op_movl_T2_r11, |
196 | 2c0262af | bellard | gen_op_movl_T2_r12, |
197 | 2c0262af | bellard | gen_op_movl_T2_r13, |
198 | 2c0262af | bellard | gen_op_movl_T2_r14, |
199 | 2c0262af | bellard | gen_op_movl_T2_r15, |
200 | 2c0262af | bellard | }, |
201 | 2c0262af | bellard | }; |
202 | 2c0262af | bellard | |
203 | 2c0262af | bellard | static GenOpFunc *gen_op_movl_reg_TN[2][16] = { |
204 | 2c0262af | bellard | { |
205 | 2c0262af | bellard | gen_op_movl_r0_T0, |
206 | 2c0262af | bellard | gen_op_movl_r1_T0, |
207 | 2c0262af | bellard | gen_op_movl_r2_T0, |
208 | 2c0262af | bellard | gen_op_movl_r3_T0, |
209 | 2c0262af | bellard | gen_op_movl_r4_T0, |
210 | 2c0262af | bellard | gen_op_movl_r5_T0, |
211 | 2c0262af | bellard | gen_op_movl_r6_T0, |
212 | 2c0262af | bellard | gen_op_movl_r7_T0, |
213 | 2c0262af | bellard | gen_op_movl_r8_T0, |
214 | 2c0262af | bellard | gen_op_movl_r9_T0, |
215 | 2c0262af | bellard | gen_op_movl_r10_T0, |
216 | 2c0262af | bellard | gen_op_movl_r11_T0, |
217 | 2c0262af | bellard | gen_op_movl_r12_T0, |
218 | 2c0262af | bellard | gen_op_movl_r13_T0, |
219 | 2c0262af | bellard | gen_op_movl_r14_T0, |
220 | 2c0262af | bellard | gen_op_movl_r15_T0, |
221 | 2c0262af | bellard | }, |
222 | 2c0262af | bellard | { |
223 | 2c0262af | bellard | gen_op_movl_r0_T1, |
224 | 2c0262af | bellard | gen_op_movl_r1_T1, |
225 | 2c0262af | bellard | gen_op_movl_r2_T1, |
226 | 2c0262af | bellard | gen_op_movl_r3_T1, |
227 | 2c0262af | bellard | gen_op_movl_r4_T1, |
228 | 2c0262af | bellard | gen_op_movl_r5_T1, |
229 | 2c0262af | bellard | gen_op_movl_r6_T1, |
230 | 2c0262af | bellard | gen_op_movl_r7_T1, |
231 | 2c0262af | bellard | gen_op_movl_r8_T1, |
232 | 2c0262af | bellard | gen_op_movl_r9_T1, |
233 | 2c0262af | bellard | gen_op_movl_r10_T1, |
234 | 2c0262af | bellard | gen_op_movl_r11_T1, |
235 | 2c0262af | bellard | gen_op_movl_r12_T1, |
236 | 2c0262af | bellard | gen_op_movl_r13_T1, |
237 | 2c0262af | bellard | gen_op_movl_r14_T1, |
238 | 2c0262af | bellard | gen_op_movl_r15_T1, |
239 | 2c0262af | bellard | }, |
240 | 2c0262af | bellard | }; |
241 | 2c0262af | bellard | |
242 | 2c0262af | bellard | static GenOpFunc1 *gen_op_movl_TN_im[3] = { |
243 | 2c0262af | bellard | gen_op_movl_T0_im, |
244 | 2c0262af | bellard | gen_op_movl_T1_im, |
245 | 2c0262af | bellard | gen_op_movl_T2_im, |
246 | 2c0262af | bellard | }; |
247 | 2c0262af | bellard | |
248 | 2c0262af | bellard | static inline void gen_movl_TN_reg(DisasContext *s, int reg, int t) |
249 | 2c0262af | bellard | { |
250 | 2c0262af | bellard | int val;
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251 | 2c0262af | bellard | |
252 | 2c0262af | bellard | if (reg == 15) { |
253 | 2c0262af | bellard | /* normaly, since we updated PC, we need only to add 4 */
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254 | 2c0262af | bellard | val = (long)s->pc + 4; |
255 | 2c0262af | bellard | gen_op_movl_TN_im[t](val); |
256 | 2c0262af | bellard | } else {
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257 | 2c0262af | bellard | gen_op_movl_TN_reg[t][reg](); |
258 | 2c0262af | bellard | } |
259 | 2c0262af | bellard | } |
260 | 2c0262af | bellard | |
261 | 2c0262af | bellard | static inline void gen_movl_T0_reg(DisasContext *s, int reg) |
262 | 2c0262af | bellard | { |
263 | 2c0262af | bellard | gen_movl_TN_reg(s, reg, 0);
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264 | 2c0262af | bellard | } |
265 | 2c0262af | bellard | |
266 | 2c0262af | bellard | static inline void gen_movl_T1_reg(DisasContext *s, int reg) |
267 | 2c0262af | bellard | { |
268 | 2c0262af | bellard | gen_movl_TN_reg(s, reg, 1);
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269 | 2c0262af | bellard | } |
270 | 2c0262af | bellard | |
271 | 2c0262af | bellard | static inline void gen_movl_T2_reg(DisasContext *s, int reg) |
272 | 2c0262af | bellard | { |
273 | 2c0262af | bellard | gen_movl_TN_reg(s, reg, 2);
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274 | 2c0262af | bellard | } |
275 | 2c0262af | bellard | |
276 | 2c0262af | bellard | static inline void gen_movl_reg_TN(DisasContext *s, int reg, int t) |
277 | 2c0262af | bellard | { |
278 | 2c0262af | bellard | gen_op_movl_reg_TN[t][reg](); |
279 | 2c0262af | bellard | if (reg == 15) { |
280 | 2c0262af | bellard | s->is_jmp = DISAS_JUMP; |
281 | 2c0262af | bellard | } |
282 | 2c0262af | bellard | } |
283 | 2c0262af | bellard | |
284 | 2c0262af | bellard | static inline void gen_movl_reg_T0(DisasContext *s, int reg) |
285 | 2c0262af | bellard | { |
286 | 2c0262af | bellard | gen_movl_reg_TN(s, reg, 0);
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287 | 2c0262af | bellard | } |
288 | 2c0262af | bellard | |
289 | 2c0262af | bellard | static inline void gen_movl_reg_T1(DisasContext *s, int reg) |
290 | 2c0262af | bellard | { |
291 | 2c0262af | bellard | gen_movl_reg_TN(s, reg, 1);
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292 | 2c0262af | bellard | } |
293 | 2c0262af | bellard | |
294 | 2c0262af | bellard | static inline void gen_add_data_offset(DisasContext *s, unsigned int insn) |
295 | 2c0262af | bellard | { |
296 | 1e8d4eec | bellard | int val, rm, shift, shiftop;
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297 | 2c0262af | bellard | |
298 | 2c0262af | bellard | if (!(insn & (1 << 25))) { |
299 | 2c0262af | bellard | /* immediate */
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300 | 2c0262af | bellard | val = insn & 0xfff;
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301 | 2c0262af | bellard | if (!(insn & (1 << 23))) |
302 | 2c0262af | bellard | val = -val; |
303 | 537730b9 | bellard | if (val != 0) |
304 | 537730b9 | bellard | gen_op_addl_T1_im(val); |
305 | 2c0262af | bellard | } else {
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306 | 2c0262af | bellard | /* shift/register */
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307 | 2c0262af | bellard | rm = (insn) & 0xf;
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308 | 2c0262af | bellard | shift = (insn >> 7) & 0x1f; |
309 | 2c0262af | bellard | gen_movl_T2_reg(s, rm); |
310 | 1e8d4eec | bellard | shiftop = (insn >> 5) & 3; |
311 | 2c0262af | bellard | if (shift != 0) { |
312 | 1e8d4eec | bellard | gen_shift_T2_im[shiftop](shift); |
313 | 1e8d4eec | bellard | } else if (shiftop != 0) { |
314 | 1e8d4eec | bellard | gen_shift_T2_0[shiftop](); |
315 | 2c0262af | bellard | } |
316 | 2c0262af | bellard | if (!(insn & (1 << 23))) |
317 | 2c0262af | bellard | gen_op_subl_T1_T2(); |
318 | 2c0262af | bellard | else
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319 | 2c0262af | bellard | gen_op_addl_T1_T2(); |
320 | 2c0262af | bellard | } |
321 | 2c0262af | bellard | } |
322 | 2c0262af | bellard | |
323 | 2c0262af | bellard | static inline void gen_add_datah_offset(DisasContext *s, unsigned int insn) |
324 | 2c0262af | bellard | { |
325 | 2c0262af | bellard | int val, rm;
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326 | 2c0262af | bellard | |
327 | 2c0262af | bellard | if (insn & (1 << 22)) { |
328 | 2c0262af | bellard | /* immediate */
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329 | 2c0262af | bellard | val = (insn & 0xf) | ((insn >> 4) & 0xf0); |
330 | 2c0262af | bellard | if (!(insn & (1 << 23))) |
331 | 2c0262af | bellard | val = -val; |
332 | 537730b9 | bellard | if (val != 0) |
333 | 537730b9 | bellard | gen_op_addl_T1_im(val); |
334 | 2c0262af | bellard | } else {
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335 | 2c0262af | bellard | /* register */
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336 | 2c0262af | bellard | rm = (insn) & 0xf;
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337 | 2c0262af | bellard | gen_movl_T2_reg(s, rm); |
338 | 2c0262af | bellard | if (!(insn & (1 << 23))) |
339 | 2c0262af | bellard | gen_op_subl_T1_T2(); |
340 | 2c0262af | bellard | else
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341 | 2c0262af | bellard | gen_op_addl_T1_T2(); |
342 | 2c0262af | bellard | } |
343 | 2c0262af | bellard | } |
344 | 2c0262af | bellard | |
345 | 2c0262af | bellard | static void disas_arm_insn(DisasContext *s) |
346 | 2c0262af | bellard | { |
347 | 2c0262af | bellard | unsigned int cond, insn, val, op1, i, shift, rm, rs, rn, rd, sh; |
348 | 2c0262af | bellard | |
349 | 2c0262af | bellard | insn = ldl(s->pc); |
350 | 2c0262af | bellard | s->pc += 4;
|
351 | 2c0262af | bellard | |
352 | 2c0262af | bellard | cond = insn >> 28;
|
353 | 2c0262af | bellard | if (cond == 0xf) |
354 | 2c0262af | bellard | goto illegal_op;
|
355 | 2c0262af | bellard | if (cond != 0xe) { |
356 | 2c0262af | bellard | /* if not always execute, we generate a conditional jump to
|
357 | 2c0262af | bellard | next instruction */
|
358 | 2c0262af | bellard | gen_test_cc[cond ^ 1]((long)s->tb, (long)s->pc); |
359 | 2c0262af | bellard | s->is_jmp = DISAS_JUMP_NEXT; |
360 | 2c0262af | bellard | } |
361 | 2c0262af | bellard | if (((insn & 0x0e000000) == 0 && |
362 | 2c0262af | bellard | (insn & 0x00000090) != 0x90) || |
363 | 2c0262af | bellard | ((insn & 0x0e000000) == (1 << 25))) { |
364 | 2c0262af | bellard | int set_cc, logic_cc, shiftop;
|
365 | 2c0262af | bellard | |
366 | 2c0262af | bellard | op1 = (insn >> 21) & 0xf; |
367 | 2c0262af | bellard | set_cc = (insn >> 20) & 1; |
368 | 2c0262af | bellard | logic_cc = table_logic_cc[op1] & set_cc; |
369 | 2c0262af | bellard | |
370 | 2c0262af | bellard | /* data processing instruction */
|
371 | 2c0262af | bellard | if (insn & (1 << 25)) { |
372 | 2c0262af | bellard | /* immediate operand */
|
373 | 2c0262af | bellard | val = insn & 0xff;
|
374 | 2c0262af | bellard | shift = ((insn >> 8) & 0xf) * 2; |
375 | 2c0262af | bellard | if (shift)
|
376 | 2c0262af | bellard | val = (val >> shift) | (val << (32 - shift));
|
377 | 2c0262af | bellard | gen_op_movl_T1_im(val); |
378 | 2c0262af | bellard | /* XXX: is CF modified ? */
|
379 | 2c0262af | bellard | } else {
|
380 | 2c0262af | bellard | /* register */
|
381 | 2c0262af | bellard | rm = (insn) & 0xf;
|
382 | 2c0262af | bellard | gen_movl_T1_reg(s, rm); |
383 | 2c0262af | bellard | shiftop = (insn >> 5) & 3; |
384 | 2c0262af | bellard | if (!(insn & (1 << 4))) { |
385 | 2c0262af | bellard | shift = (insn >> 7) & 0x1f; |
386 | 2c0262af | bellard | if (shift != 0) { |
387 | 2c0262af | bellard | if (logic_cc) {
|
388 | 2c0262af | bellard | gen_shift_T1_im_cc[shiftop](shift); |
389 | 2c0262af | bellard | } else {
|
390 | 2c0262af | bellard | gen_shift_T1_im[shiftop](shift); |
391 | 2c0262af | bellard | } |
392 | 1e8d4eec | bellard | } else if (shiftop != 0) { |
393 | 1e8d4eec | bellard | if (logic_cc) {
|
394 | 1e8d4eec | bellard | gen_shift_T1_0_cc[shiftop](); |
395 | 1e8d4eec | bellard | } else {
|
396 | 1e8d4eec | bellard | gen_shift_T1_0[shiftop](); |
397 | 1e8d4eec | bellard | } |
398 | 2c0262af | bellard | } |
399 | 2c0262af | bellard | } else {
|
400 | 2c0262af | bellard | rs = (insn >> 8) & 0xf; |
401 | 2c0262af | bellard | gen_movl_T0_reg(s, rs); |
402 | 2c0262af | bellard | if (logic_cc) {
|
403 | 2c0262af | bellard | gen_shift_T1_T0_cc[shiftop](); |
404 | 2c0262af | bellard | } else {
|
405 | 2c0262af | bellard | gen_shift_T1_T0[shiftop](); |
406 | 2c0262af | bellard | } |
407 | 2c0262af | bellard | } |
408 | 2c0262af | bellard | } |
409 | 2c0262af | bellard | if (op1 != 0x0f && op1 != 0x0d) { |
410 | 2c0262af | bellard | rn = (insn >> 16) & 0xf; |
411 | 2c0262af | bellard | gen_movl_T0_reg(s, rn); |
412 | 2c0262af | bellard | } |
413 | 2c0262af | bellard | rd = (insn >> 12) & 0xf; |
414 | 2c0262af | bellard | switch(op1) {
|
415 | 2c0262af | bellard | case 0x00: |
416 | 2c0262af | bellard | gen_op_andl_T0_T1(); |
417 | 2c0262af | bellard | gen_movl_reg_T0(s, rd); |
418 | 2c0262af | bellard | if (logic_cc)
|
419 | 2c0262af | bellard | gen_op_logic_T0_cc(); |
420 | 2c0262af | bellard | break;
|
421 | 2c0262af | bellard | case 0x01: |
422 | 2c0262af | bellard | gen_op_xorl_T0_T1(); |
423 | 2c0262af | bellard | gen_movl_reg_T0(s, rd); |
424 | 2c0262af | bellard | if (logic_cc)
|
425 | 2c0262af | bellard | gen_op_logic_T0_cc(); |
426 | 2c0262af | bellard | break;
|
427 | 2c0262af | bellard | case 0x02: |
428 | 2c0262af | bellard | if (set_cc)
|
429 | 2c0262af | bellard | gen_op_subl_T0_T1_cc(); |
430 | 2c0262af | bellard | else
|
431 | 2c0262af | bellard | gen_op_subl_T0_T1(); |
432 | 2c0262af | bellard | gen_movl_reg_T0(s, rd); |
433 | 2c0262af | bellard | break;
|
434 | 2c0262af | bellard | case 0x03: |
435 | 2c0262af | bellard | if (set_cc)
|
436 | 2c0262af | bellard | gen_op_rsbl_T0_T1_cc(); |
437 | 2c0262af | bellard | else
|
438 | 2c0262af | bellard | gen_op_rsbl_T0_T1(); |
439 | 2c0262af | bellard | gen_movl_reg_T0(s, rd); |
440 | 2c0262af | bellard | break;
|
441 | 2c0262af | bellard | case 0x04: |
442 | 2c0262af | bellard | if (set_cc)
|
443 | 2c0262af | bellard | gen_op_addl_T0_T1_cc(); |
444 | 2c0262af | bellard | else
|
445 | 2c0262af | bellard | gen_op_addl_T0_T1(); |
446 | 2c0262af | bellard | gen_movl_reg_T0(s, rd); |
447 | 2c0262af | bellard | break;
|
448 | 2c0262af | bellard | case 0x05: |
449 | 2c0262af | bellard | if (set_cc)
|
450 | 2c0262af | bellard | gen_op_adcl_T0_T1_cc(); |
451 | 2c0262af | bellard | else
|
452 | 2c0262af | bellard | gen_op_adcl_T0_T1(); |
453 | 2c0262af | bellard | gen_movl_reg_T0(s, rd); |
454 | 2c0262af | bellard | break;
|
455 | 2c0262af | bellard | case 0x06: |
456 | 2c0262af | bellard | if (set_cc)
|
457 | 2c0262af | bellard | gen_op_sbcl_T0_T1_cc(); |
458 | 2c0262af | bellard | else
|
459 | 2c0262af | bellard | gen_op_sbcl_T0_T1(); |
460 | 2c0262af | bellard | gen_movl_reg_T0(s, rd); |
461 | 2c0262af | bellard | break;
|
462 | 2c0262af | bellard | case 0x07: |
463 | 2c0262af | bellard | if (set_cc)
|
464 | 2c0262af | bellard | gen_op_rscl_T0_T1_cc(); |
465 | 2c0262af | bellard | else
|
466 | 2c0262af | bellard | gen_op_rscl_T0_T1(); |
467 | 2c0262af | bellard | gen_movl_reg_T0(s, rd); |
468 | 2c0262af | bellard | break;
|
469 | 2c0262af | bellard | case 0x08: |
470 | 2c0262af | bellard | if (set_cc) {
|
471 | 2c0262af | bellard | gen_op_andl_T0_T1(); |
472 | 2c0262af | bellard | gen_op_logic_T0_cc(); |
473 | 2c0262af | bellard | } |
474 | 2c0262af | bellard | break;
|
475 | 2c0262af | bellard | case 0x09: |
476 | 2c0262af | bellard | if (set_cc) {
|
477 | 2c0262af | bellard | gen_op_xorl_T0_T1(); |
478 | 2c0262af | bellard | gen_op_logic_T0_cc(); |
479 | 2c0262af | bellard | } |
480 | 2c0262af | bellard | break;
|
481 | 2c0262af | bellard | case 0x0a: |
482 | 2c0262af | bellard | if (set_cc) {
|
483 | 2c0262af | bellard | gen_op_subl_T0_T1_cc(); |
484 | 2c0262af | bellard | } |
485 | 2c0262af | bellard | break;
|
486 | 2c0262af | bellard | case 0x0b: |
487 | 2c0262af | bellard | if (set_cc) {
|
488 | 2c0262af | bellard | gen_op_addl_T0_T1_cc(); |
489 | 2c0262af | bellard | } |
490 | 2c0262af | bellard | break;
|
491 | 2c0262af | bellard | case 0x0c: |
492 | 2c0262af | bellard | gen_op_orl_T0_T1(); |
493 | 2c0262af | bellard | gen_movl_reg_T0(s, rd); |
494 | 2c0262af | bellard | if (logic_cc)
|
495 | 2c0262af | bellard | gen_op_logic_T0_cc(); |
496 | 2c0262af | bellard | break;
|
497 | 2c0262af | bellard | case 0x0d: |
498 | 2c0262af | bellard | gen_movl_reg_T1(s, rd); |
499 | 2c0262af | bellard | if (logic_cc)
|
500 | 2c0262af | bellard | gen_op_logic_T1_cc(); |
501 | 2c0262af | bellard | break;
|
502 | 2c0262af | bellard | case 0x0e: |
503 | 2c0262af | bellard | gen_op_bicl_T0_T1(); |
504 | 2c0262af | bellard | gen_movl_reg_T0(s, rd); |
505 | 2c0262af | bellard | if (logic_cc)
|
506 | 2c0262af | bellard | gen_op_logic_T0_cc(); |
507 | 2c0262af | bellard | break;
|
508 | 2c0262af | bellard | default:
|
509 | 2c0262af | bellard | case 0x0f: |
510 | 2c0262af | bellard | gen_op_notl_T1(); |
511 | 2c0262af | bellard | gen_movl_reg_T1(s, rd); |
512 | 2c0262af | bellard | if (logic_cc)
|
513 | 2c0262af | bellard | gen_op_logic_T1_cc(); |
514 | 2c0262af | bellard | break;
|
515 | 2c0262af | bellard | } |
516 | 2c0262af | bellard | } else {
|
517 | 2c0262af | bellard | /* other instructions */
|
518 | 2c0262af | bellard | op1 = (insn >> 24) & 0xf; |
519 | 2c0262af | bellard | switch(op1) {
|
520 | 2c0262af | bellard | case 0x0: |
521 | 2c0262af | bellard | case 0x1: |
522 | 2c0262af | bellard | sh = (insn >> 5) & 3; |
523 | 2c0262af | bellard | if (sh == 0) { |
524 | 2c0262af | bellard | if (op1 == 0x0) { |
525 | 2c0262af | bellard | rd = (insn >> 16) & 0xf; |
526 | 2c0262af | bellard | rn = (insn >> 12) & 0xf; |
527 | 2c0262af | bellard | rs = (insn >> 8) & 0xf; |
528 | 2c0262af | bellard | rm = (insn) & 0xf;
|
529 | 2c0262af | bellard | if (!(insn & (1 << 23))) { |
530 | 2c0262af | bellard | /* 32 bit mul */
|
531 | 2c0262af | bellard | gen_movl_T0_reg(s, rs); |
532 | 2c0262af | bellard | gen_movl_T1_reg(s, rm); |
533 | 2c0262af | bellard | gen_op_mul_T0_T1(); |
534 | 2c0262af | bellard | if (insn & (1 << 21)) { |
535 | 2c0262af | bellard | gen_movl_T1_reg(s, rn); |
536 | 2c0262af | bellard | gen_op_addl_T0_T1(); |
537 | 2c0262af | bellard | } |
538 | 2c0262af | bellard | if (insn & (1 << 20)) |
539 | 2c0262af | bellard | gen_op_logic_T0_cc(); |
540 | 2c0262af | bellard | gen_movl_reg_T0(s, rd); |
541 | 2c0262af | bellard | } else {
|
542 | 2c0262af | bellard | /* 64 bit mul */
|
543 | 2c0262af | bellard | gen_movl_T0_reg(s, rs); |
544 | 2c0262af | bellard | gen_movl_T1_reg(s, rm); |
545 | 2c0262af | bellard | if (insn & (1 << 22)) |
546 | 2c0262af | bellard | gen_op_imull_T0_T1(); |
547 | 2e134c9c | bellard | else
|
548 | 2e134c9c | bellard | gen_op_mull_T0_T1(); |
549 | 2c0262af | bellard | if (insn & (1 << 21)) |
550 | 2c0262af | bellard | gen_op_addq_T0_T1(rn, rd); |
551 | 2c0262af | bellard | if (insn & (1 << 20)) |
552 | 2c0262af | bellard | gen_op_logicq_cc(); |
553 | 2c0262af | bellard | gen_movl_reg_T0(s, rn); |
554 | 2c0262af | bellard | gen_movl_reg_T1(s, rd); |
555 | 2c0262af | bellard | } |
556 | 2c0262af | bellard | } else {
|
557 | 2c0262af | bellard | /* SWP instruction */
|
558 | 2c0262af | bellard | rn = (insn >> 16) & 0xf; |
559 | 2c0262af | bellard | rd = (insn >> 12) & 0xf; |
560 | 2c0262af | bellard | rm = (insn) & 0xf;
|
561 | 2c0262af | bellard | |
562 | 2c0262af | bellard | gen_movl_T0_reg(s, rm); |
563 | 2c0262af | bellard | gen_movl_T1_reg(s, rn); |
564 | 2c0262af | bellard | if (insn & (1 << 22)) { |
565 | 2c0262af | bellard | gen_op_swpb_T0_T1(); |
566 | 2c0262af | bellard | } else {
|
567 | 2c0262af | bellard | gen_op_swpl_T0_T1(); |
568 | 2c0262af | bellard | } |
569 | 2c0262af | bellard | gen_movl_reg_T0(s, rd); |
570 | 2c0262af | bellard | } |
571 | 2c0262af | bellard | } else {
|
572 | 2c0262af | bellard | /* load/store half word */
|
573 | 2c0262af | bellard | rn = (insn >> 16) & 0xf; |
574 | 2c0262af | bellard | rd = (insn >> 12) & 0xf; |
575 | 2c0262af | bellard | gen_movl_T1_reg(s, rn); |
576 | beddab75 | bellard | if (insn & (1 << 24)) |
577 | beddab75 | bellard | gen_add_datah_offset(s, insn); |
578 | 2c0262af | bellard | if (insn & (1 << 20)) { |
579 | 2c0262af | bellard | /* load */
|
580 | 2c0262af | bellard | switch(sh) {
|
581 | 2c0262af | bellard | case 1: |
582 | 2c0262af | bellard | gen_op_lduw_T0_T1(); |
583 | 2c0262af | bellard | break;
|
584 | 2c0262af | bellard | case 2: |
585 | 2c0262af | bellard | gen_op_ldsb_T0_T1(); |
586 | 2c0262af | bellard | break;
|
587 | 2c0262af | bellard | default:
|
588 | 2c0262af | bellard | case 3: |
589 | 2c0262af | bellard | gen_op_ldsw_T0_T1(); |
590 | 2c0262af | bellard | break;
|
591 | 2c0262af | bellard | } |
592 | e748ba4f | bellard | gen_movl_reg_T0(s, rd); |
593 | 2c0262af | bellard | } else {
|
594 | 2c0262af | bellard | /* store */
|
595 | e748ba4f | bellard | gen_movl_T0_reg(s, rd); |
596 | 2c0262af | bellard | gen_op_stw_T0_T1(); |
597 | 2c0262af | bellard | } |
598 | 2c0262af | bellard | if (!(insn & (1 << 24))) { |
599 | 2c0262af | bellard | gen_add_datah_offset(s, insn); |
600 | 2c0262af | bellard | gen_movl_reg_T1(s, rn); |
601 | 2c0262af | bellard | } else if (insn & (1 << 21)) { |
602 | 2c0262af | bellard | gen_movl_reg_T1(s, rn); |
603 | 2c0262af | bellard | } |
604 | 2c0262af | bellard | } |
605 | 2c0262af | bellard | break;
|
606 | 2c0262af | bellard | case 0x4: |
607 | 2c0262af | bellard | case 0x5: |
608 | 2c0262af | bellard | case 0x6: |
609 | 2c0262af | bellard | case 0x7: |
610 | 2c0262af | bellard | /* load/store byte/word */
|
611 | 2c0262af | bellard | rn = (insn >> 16) & 0xf; |
612 | 2c0262af | bellard | rd = (insn >> 12) & 0xf; |
613 | 2c0262af | bellard | gen_movl_T1_reg(s, rn); |
614 | 2c0262af | bellard | if (insn & (1 << 24)) |
615 | 2c0262af | bellard | gen_add_data_offset(s, insn); |
616 | 2c0262af | bellard | if (insn & (1 << 20)) { |
617 | 2c0262af | bellard | /* load */
|
618 | 2c0262af | bellard | if (insn & (1 << 22)) |
619 | 2c0262af | bellard | gen_op_ldub_T0_T1(); |
620 | 2c0262af | bellard | else
|
621 | 2c0262af | bellard | gen_op_ldl_T0_T1(); |
622 | 2c0262af | bellard | gen_movl_reg_T0(s, rd); |
623 | 2c0262af | bellard | } else {
|
624 | 2c0262af | bellard | /* store */
|
625 | 2c0262af | bellard | gen_movl_T0_reg(s, rd); |
626 | 2c0262af | bellard | if (insn & (1 << 22)) |
627 | 2c0262af | bellard | gen_op_stb_T0_T1(); |
628 | 2c0262af | bellard | else
|
629 | 2c0262af | bellard | gen_op_stl_T0_T1(); |
630 | 2c0262af | bellard | } |
631 | 2c0262af | bellard | if (!(insn & (1 << 24))) { |
632 | 2c0262af | bellard | gen_add_data_offset(s, insn); |
633 | 2c0262af | bellard | gen_movl_reg_T1(s, rn); |
634 | 2c0262af | bellard | } else if (insn & (1 << 21)) |
635 | 2c0262af | bellard | gen_movl_reg_T1(s, rn); { |
636 | 2c0262af | bellard | } |
637 | 2c0262af | bellard | break;
|
638 | 2c0262af | bellard | case 0x08: |
639 | 2c0262af | bellard | case 0x09: |
640 | 2c0262af | bellard | { |
641 | 2c0262af | bellard | int j, n;
|
642 | 2c0262af | bellard | /* load/store multiple words */
|
643 | 2c0262af | bellard | /* XXX: store correct base if write back */
|
644 | 2c0262af | bellard | if (insn & (1 << 22)) |
645 | 2c0262af | bellard | goto illegal_op; /* only usable in supervisor mode */ |
646 | 2c0262af | bellard | rn = (insn >> 16) & 0xf; |
647 | 2c0262af | bellard | gen_movl_T1_reg(s, rn); |
648 | 2c0262af | bellard | |
649 | 2c0262af | bellard | /* compute total size */
|
650 | 2c0262af | bellard | n = 0;
|
651 | 2c0262af | bellard | for(i=0;i<16;i++) { |
652 | 2c0262af | bellard | if (insn & (1 << i)) |
653 | 2c0262af | bellard | n++; |
654 | 2c0262af | bellard | } |
655 | 2c0262af | bellard | /* XXX: test invalid n == 0 case ? */
|
656 | 2c0262af | bellard | if (insn & (1 << 23)) { |
657 | 2c0262af | bellard | if (insn & (1 << 24)) { |
658 | 2c0262af | bellard | /* pre increment */
|
659 | 2c0262af | bellard | gen_op_addl_T1_im(4);
|
660 | 2c0262af | bellard | } else {
|
661 | 2c0262af | bellard | /* post increment */
|
662 | 2c0262af | bellard | } |
663 | 2c0262af | bellard | } else {
|
664 | 2c0262af | bellard | if (insn & (1 << 24)) { |
665 | 2c0262af | bellard | /* pre decrement */
|
666 | 2c0262af | bellard | gen_op_addl_T1_im(-(n * 4));
|
667 | 2c0262af | bellard | } else {
|
668 | 2c0262af | bellard | /* post decrement */
|
669 | 2c0262af | bellard | if (n != 1) |
670 | 2c0262af | bellard | gen_op_addl_T1_im(-((n - 1) * 4)); |
671 | 2c0262af | bellard | } |
672 | 2c0262af | bellard | } |
673 | 2c0262af | bellard | j = 0;
|
674 | 2c0262af | bellard | for(i=0;i<16;i++) { |
675 | 2c0262af | bellard | if (insn & (1 << i)) { |
676 | 2c0262af | bellard | if (insn & (1 << 20)) { |
677 | 2c0262af | bellard | /* load */
|
678 | 2c0262af | bellard | gen_op_ldl_T0_T1(); |
679 | 2c0262af | bellard | gen_movl_reg_T0(s, i); |
680 | 2c0262af | bellard | } else {
|
681 | 2c0262af | bellard | /* store */
|
682 | 2c0262af | bellard | if (i == 15) { |
683 | 2c0262af | bellard | /* special case: r15 = PC + 12 */
|
684 | 2c0262af | bellard | val = (long)s->pc + 8; |
685 | 2c0262af | bellard | gen_op_movl_TN_im[0](val);
|
686 | 2c0262af | bellard | } else {
|
687 | 2c0262af | bellard | gen_movl_T0_reg(s, i); |
688 | 2c0262af | bellard | } |
689 | 2c0262af | bellard | gen_op_stl_T0_T1(); |
690 | 2c0262af | bellard | } |
691 | 2c0262af | bellard | j++; |
692 | 2c0262af | bellard | /* no need to add after the last transfer */
|
693 | 2c0262af | bellard | if (j != n)
|
694 | 2c0262af | bellard | gen_op_addl_T1_im(4);
|
695 | 2c0262af | bellard | } |
696 | 2c0262af | bellard | } |
697 | 2c0262af | bellard | if (insn & (1 << 21)) { |
698 | 2c0262af | bellard | /* write back */
|
699 | 2c0262af | bellard | if (insn & (1 << 23)) { |
700 | 2c0262af | bellard | if (insn & (1 << 24)) { |
701 | 2c0262af | bellard | /* pre increment */
|
702 | 2c0262af | bellard | } else {
|
703 | 2c0262af | bellard | /* post increment */
|
704 | 2c0262af | bellard | gen_op_addl_T1_im(4);
|
705 | 2c0262af | bellard | } |
706 | 2c0262af | bellard | } else {
|
707 | 2c0262af | bellard | if (insn & (1 << 24)) { |
708 | 2c0262af | bellard | /* pre decrement */
|
709 | 2c0262af | bellard | if (n != 1) |
710 | 2c0262af | bellard | gen_op_addl_T1_im(-((n - 1) * 4)); |
711 | 2c0262af | bellard | } else {
|
712 | 2c0262af | bellard | /* post decrement */
|
713 | 2c0262af | bellard | gen_op_addl_T1_im(-(n * 4));
|
714 | 2c0262af | bellard | } |
715 | 2c0262af | bellard | } |
716 | 2c0262af | bellard | gen_movl_reg_T1(s, rn); |
717 | 2c0262af | bellard | } |
718 | 2c0262af | bellard | } |
719 | 2c0262af | bellard | break;
|
720 | 2c0262af | bellard | case 0xa: |
721 | 2c0262af | bellard | case 0xb: |
722 | 2c0262af | bellard | { |
723 | 2c0262af | bellard | int offset;
|
724 | 2c0262af | bellard | |
725 | 2c0262af | bellard | /* branch (and link) */
|
726 | 2c0262af | bellard | val = (int)s->pc;
|
727 | 2c0262af | bellard | if (insn & (1 << 24)) { |
728 | 2c0262af | bellard | gen_op_movl_T0_im(val); |
729 | 2c0262af | bellard | gen_op_movl_reg_TN[0][14](); |
730 | 2c0262af | bellard | } |
731 | 2c0262af | bellard | offset = (((int)insn << 8) >> 8); |
732 | 2c0262af | bellard | val += (offset << 2) + 4; |
733 | 2c0262af | bellard | gen_op_jmp((long)s->tb, val);
|
734 | 2c0262af | bellard | s->is_jmp = DISAS_TB_JUMP; |
735 | 2c0262af | bellard | } |
736 | 2c0262af | bellard | break;
|
737 | 2c0262af | bellard | case 0xf: |
738 | 2c0262af | bellard | /* swi */
|
739 | 2c0262af | bellard | gen_op_movl_T0_im((long)s->pc);
|
740 | 2c0262af | bellard | gen_op_movl_reg_TN[0][15](); |
741 | 2c0262af | bellard | gen_op_swi(); |
742 | 2c0262af | bellard | s->is_jmp = DISAS_JUMP; |
743 | 2c0262af | bellard | break;
|
744 | 2c0262af | bellard | default:
|
745 | 2c0262af | bellard | illegal_op:
|
746 | 2c0262af | bellard | gen_op_movl_T0_im((long)s->pc - 4); |
747 | 2c0262af | bellard | gen_op_movl_reg_TN[0][15](); |
748 | 2c0262af | bellard | gen_op_undef_insn(); |
749 | 2c0262af | bellard | s->is_jmp = DISAS_JUMP; |
750 | 2c0262af | bellard | break;
|
751 | 2c0262af | bellard | } |
752 | 2c0262af | bellard | } |
753 | 2c0262af | bellard | } |
754 | 2c0262af | bellard | |
755 | 2c0262af | bellard | /* generate intermediate code in gen_opc_buf and gen_opparam_buf for
|
756 | 2c0262af | bellard | basic block 'tb'. If search_pc is TRUE, also generate PC
|
757 | 2c0262af | bellard | information for each intermediate instruction. */
|
758 | 2c0262af | bellard | static inline int gen_intermediate_code_internal(CPUState *env, |
759 | 2c0262af | bellard | TranslationBlock *tb, |
760 | 2c0262af | bellard | int search_pc)
|
761 | 2c0262af | bellard | { |
762 | 2c0262af | bellard | DisasContext dc1, *dc = &dc1; |
763 | 2c0262af | bellard | uint16_t *gen_opc_end; |
764 | 2c0262af | bellard | int j, lj;
|
765 | 0fa85d43 | bellard | target_ulong pc_start; |
766 | 2c0262af | bellard | |
767 | 2c0262af | bellard | /* generate intermediate code */
|
768 | 0fa85d43 | bellard | pc_start = tb->pc; |
769 | 2c0262af | bellard | |
770 | 2c0262af | bellard | dc->tb = tb; |
771 | 2c0262af | bellard | |
772 | 2c0262af | bellard | gen_opc_ptr = gen_opc_buf; |
773 | 2c0262af | bellard | gen_opc_end = gen_opc_buf + OPC_MAX_SIZE; |
774 | 2c0262af | bellard | gen_opparam_ptr = gen_opparam_buf; |
775 | 2c0262af | bellard | |
776 | 2c0262af | bellard | dc->is_jmp = DISAS_NEXT; |
777 | 2c0262af | bellard | dc->pc = pc_start; |
778 | 2c0262af | bellard | lj = -1;
|
779 | 2c0262af | bellard | do {
|
780 | 2c0262af | bellard | if (search_pc) {
|
781 | 2c0262af | bellard | j = gen_opc_ptr - gen_opc_buf; |
782 | 2c0262af | bellard | if (lj < j) {
|
783 | 2c0262af | bellard | lj++; |
784 | 2c0262af | bellard | while (lj < j)
|
785 | 2c0262af | bellard | gen_opc_instr_start[lj++] = 0;
|
786 | 2c0262af | bellard | } |
787 | 0fa85d43 | bellard | gen_opc_pc[lj] = dc->pc; |
788 | 2c0262af | bellard | gen_opc_instr_start[lj] = 1;
|
789 | 2c0262af | bellard | } |
790 | 2c0262af | bellard | disas_arm_insn(dc); |
791 | 2c0262af | bellard | } while (!dc->is_jmp && gen_opc_ptr < gen_opc_end &&
|
792 | 2c0262af | bellard | (dc->pc - pc_start) < (TARGET_PAGE_SIZE - 32));
|
793 | 2c0262af | bellard | switch(dc->is_jmp) {
|
794 | 2c0262af | bellard | case DISAS_JUMP_NEXT:
|
795 | 2c0262af | bellard | case DISAS_NEXT:
|
796 | 2c0262af | bellard | gen_op_jmp((long)dc->tb, (long)dc->pc); |
797 | 2c0262af | bellard | break;
|
798 | 2c0262af | bellard | default:
|
799 | 2c0262af | bellard | case DISAS_JUMP:
|
800 | 2c0262af | bellard | /* indicate that the hash table must be used to find the next TB */
|
801 | 2c0262af | bellard | gen_op_movl_T0_0(); |
802 | 2c0262af | bellard | gen_op_exit_tb(); |
803 | 2c0262af | bellard | break;
|
804 | 2c0262af | bellard | case DISAS_TB_JUMP:
|
805 | 2c0262af | bellard | /* nothing more to generate */
|
806 | 2c0262af | bellard | break;
|
807 | 2c0262af | bellard | } |
808 | 2c0262af | bellard | *gen_opc_ptr = INDEX_op_end; |
809 | 2c0262af | bellard | |
810 | 2c0262af | bellard | #ifdef DEBUG_DISAS
|
811 | e19e89a5 | bellard | if (loglevel & CPU_LOG_TB_IN_ASM) {
|
812 | 2c0262af | bellard | fprintf(logfile, "----------------\n");
|
813 | 2c0262af | bellard | fprintf(logfile, "IN: %s\n", lookup_symbol(pc_start));
|
814 | 0fa85d43 | bellard | target_disas(logfile, pc_start, dc->pc - pc_start, 0);
|
815 | 2c0262af | bellard | fprintf(logfile, "\n");
|
816 | e19e89a5 | bellard | if (loglevel & (CPU_LOG_TB_OP)) {
|
817 | e19e89a5 | bellard | fprintf(logfile, "OP:\n");
|
818 | e19e89a5 | bellard | dump_ops(gen_opc_buf, gen_opparam_buf); |
819 | e19e89a5 | bellard | fprintf(logfile, "\n");
|
820 | e19e89a5 | bellard | } |
821 | 2c0262af | bellard | } |
822 | 2c0262af | bellard | #endif
|
823 | 2c0262af | bellard | if (!search_pc)
|
824 | 2c0262af | bellard | tb->size = dc->pc - pc_start; |
825 | 2c0262af | bellard | return 0; |
826 | 2c0262af | bellard | } |
827 | 2c0262af | bellard | |
828 | 2c0262af | bellard | int gen_intermediate_code(CPUState *env, TranslationBlock *tb)
|
829 | 2c0262af | bellard | { |
830 | 2c0262af | bellard | return gen_intermediate_code_internal(env, tb, 0); |
831 | 2c0262af | bellard | } |
832 | 2c0262af | bellard | |
833 | 2c0262af | bellard | int gen_intermediate_code_pc(CPUState *env, TranslationBlock *tb)
|
834 | 2c0262af | bellard | { |
835 | 2c0262af | bellard | return gen_intermediate_code_internal(env, tb, 1); |
836 | 2c0262af | bellard | } |
837 | 2c0262af | bellard | |
838 | 2c0262af | bellard | CPUARMState *cpu_arm_init(void)
|
839 | 2c0262af | bellard | { |
840 | 2c0262af | bellard | CPUARMState *env; |
841 | 2c0262af | bellard | |
842 | 2c0262af | bellard | cpu_exec_init(); |
843 | 2c0262af | bellard | |
844 | 2c0262af | bellard | env = malloc(sizeof(CPUARMState));
|
845 | 2c0262af | bellard | if (!env)
|
846 | 2c0262af | bellard | return NULL; |
847 | 2c0262af | bellard | memset(env, 0, sizeof(CPUARMState)); |
848 | 7496f526 | bellard | cpu_single_env = env; |
849 | 2c0262af | bellard | return env;
|
850 | 2c0262af | bellard | } |
851 | 2c0262af | bellard | |
852 | 2c0262af | bellard | void cpu_arm_close(CPUARMState *env)
|
853 | 2c0262af | bellard | { |
854 | 2c0262af | bellard | free(env); |
855 | 2c0262af | bellard | } |
856 | 2c0262af | bellard | |
857 | 7fe48483 | bellard | void cpu_dump_state(CPUState *env, FILE *f,
|
858 | 7fe48483 | bellard | int (*cpu_fprintf)(FILE *f, const char *fmt, ...), |
859 | 7fe48483 | bellard | int flags)
|
860 | 2c0262af | bellard | { |
861 | 2c0262af | bellard | int i;
|
862 | 2c0262af | bellard | |
863 | 2c0262af | bellard | for(i=0;i<16;i++) { |
864 | 7fe48483 | bellard | cpu_fprintf(f, "R%02d=%08x", i, env->regs[i]);
|
865 | 2c0262af | bellard | if ((i % 4) == 3) |
866 | 7fe48483 | bellard | cpu_fprintf(f, "\n");
|
867 | 2c0262af | bellard | else
|
868 | 7fe48483 | bellard | cpu_fprintf(f, " ");
|
869 | 2c0262af | bellard | } |
870 | 7fe48483 | bellard | cpu_fprintf(f, "PSR=%08x %c%c%c%c\n",
|
871 | 2c0262af | bellard | env->cpsr, |
872 | 2c0262af | bellard | env->cpsr & (1 << 31) ? 'N' : '-', |
873 | 2c0262af | bellard | env->cpsr & (1 << 30) ? 'Z' : '-', |
874 | 2c0262af | bellard | env->cpsr & (1 << 29) ? 'C' : '-', |
875 | 2c0262af | bellard | env->cpsr & (1 << 28) ? 'V' : '-'); |
876 | 2c0262af | bellard | } |
877 | a6b025d3 | bellard | |
878 | a6b025d3 | bellard | target_ulong cpu_get_phys_page_debug(CPUState *env, target_ulong addr) |
879 | a6b025d3 | bellard | { |
880 | a6b025d3 | bellard | return addr;
|
881 | a6b025d3 | bellard | } |