root / target-sparc / cpu.h @ d3c61721
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1 | 7a3f1944 | bellard | #ifndef CPU_SPARC_H
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2 | 7a3f1944 | bellard | #define CPU_SPARC_H
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3 | 7a3f1944 | bellard | |
4 | 3cf1e035 | bellard | #define TARGET_LONG_BITS 32 |
5 | 3cf1e035 | bellard | |
6 | 7a3f1944 | bellard | #include "cpu-defs.h" |
7 | 7a3f1944 | bellard | |
8 | 7a3f1944 | bellard | /*#define EXCP_INTERRUPT 0x100*/
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9 | 7a3f1944 | bellard | |
10 | cf495bcf | bellard | /* trap definitions */
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11 | cf495bcf | bellard | #define TT_ILL_INSN 0x02 |
12 | e8af50a3 | bellard | #define TT_PRIV_INSN 0x03 |
13 | e80cfcfc | bellard | #define TT_NFPU_INSN 0x04 |
14 | cf495bcf | bellard | #define TT_WIN_OVF 0x05 |
15 | cf495bcf | bellard | #define TT_WIN_UNF 0x06 |
16 | e8af50a3 | bellard | #define TT_FP_EXCP 0x08 |
17 | cf495bcf | bellard | #define TT_DIV_ZERO 0x2a |
18 | cf495bcf | bellard | #define TT_TRAP 0x80 |
19 | e80cfcfc | bellard | #define TT_EXTINT 0x10 |
20 | 7a3f1944 | bellard | |
21 | 7a3f1944 | bellard | #define PSR_NEG (1<<23) |
22 | 7a3f1944 | bellard | #define PSR_ZERO (1<<22) |
23 | 7a3f1944 | bellard | #define PSR_OVF (1<<21) |
24 | 7a3f1944 | bellard | #define PSR_CARRY (1<<20) |
25 | e8af50a3 | bellard | #define PSR_ICC (PSR_NEG|PSR_ZERO|PSR_OVF|PSR_CARRY)
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26 | e80cfcfc | bellard | #define PSR_EF (1<<12) |
27 | e80cfcfc | bellard | #define PSR_PIL 0xf00 |
28 | e8af50a3 | bellard | #define PSR_S (1<<7) |
29 | e8af50a3 | bellard | #define PSR_PS (1<<6) |
30 | e8af50a3 | bellard | #define PSR_ET (1<<5) |
31 | e8af50a3 | bellard | #define PSR_CWP 0x1f |
32 | e8af50a3 | bellard | |
33 | e8af50a3 | bellard | /* Trap base register */
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34 | e8af50a3 | bellard | #define TBR_BASE_MASK 0xfffff000 |
35 | e8af50a3 | bellard | |
36 | e8af50a3 | bellard | /* Fcc */
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37 | e8af50a3 | bellard | #define FSR_RD1 (1<<31) |
38 | e8af50a3 | bellard | #define FSR_RD0 (1<<30) |
39 | e8af50a3 | bellard | #define FSR_RD_MASK (FSR_RD1 | FSR_RD0)
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40 | e8af50a3 | bellard | #define FSR_RD_NEAREST 0 |
41 | e8af50a3 | bellard | #define FSR_RD_ZERO FSR_RD0
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42 | e8af50a3 | bellard | #define FSR_RD_POS FSR_RD1
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43 | e8af50a3 | bellard | #define FSR_RD_NEG (FSR_RD1 | FSR_RD0)
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44 | e8af50a3 | bellard | |
45 | e8af50a3 | bellard | #define FSR_NVM (1<<27) |
46 | e8af50a3 | bellard | #define FSR_OFM (1<<26) |
47 | e8af50a3 | bellard | #define FSR_UFM (1<<25) |
48 | e8af50a3 | bellard | #define FSR_DZM (1<<24) |
49 | e8af50a3 | bellard | #define FSR_NXM (1<<23) |
50 | e8af50a3 | bellard | #define FSR_TEM_MASK (FSR_NVM | FSR_OFM | FSR_UFM | FSR_DZM | FSR_NXM)
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51 | e8af50a3 | bellard | |
52 | e8af50a3 | bellard | #define FSR_NVA (1<<9) |
53 | e8af50a3 | bellard | #define FSR_OFA (1<<8) |
54 | e8af50a3 | bellard | #define FSR_UFA (1<<7) |
55 | e8af50a3 | bellard | #define FSR_DZA (1<<6) |
56 | e8af50a3 | bellard | #define FSR_NXA (1<<5) |
57 | e8af50a3 | bellard | #define FSR_AEXC_MASK (FSR_NVA | FSR_OFA | FSR_UFA | FSR_DZA | FSR_NXA)
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58 | e8af50a3 | bellard | |
59 | e8af50a3 | bellard | #define FSR_NVC (1<<4) |
60 | e8af50a3 | bellard | #define FSR_OFC (1<<3) |
61 | e8af50a3 | bellard | #define FSR_UFC (1<<2) |
62 | e8af50a3 | bellard | #define FSR_DZC (1<<1) |
63 | e8af50a3 | bellard | #define FSR_NXC (1<<0) |
64 | e8af50a3 | bellard | #define FSR_CEXC_MASK (FSR_NVC | FSR_OFC | FSR_UFC | FSR_DZC | FSR_NXC)
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65 | e8af50a3 | bellard | |
66 | e8af50a3 | bellard | #define FSR_FTT2 (1<<16) |
67 | e8af50a3 | bellard | #define FSR_FTT1 (1<<15) |
68 | e8af50a3 | bellard | #define FSR_FTT0 (1<<14) |
69 | e8af50a3 | bellard | #define FSR_FTT_MASK (FSR_FTT2 | FSR_FTT1 | FSR_FTT0)
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70 | e80cfcfc | bellard | #define FSR_FTT_IEEE_EXCP (1 << 14) |
71 | e80cfcfc | bellard | #define FSR_FTT_UNIMPFPOP (3 << 14) |
72 | e80cfcfc | bellard | #define FSR_FTT_INVAL_FPR (6 << 14) |
73 | e8af50a3 | bellard | |
74 | e8af50a3 | bellard | #define FSR_FCC1 (1<<11) |
75 | e8af50a3 | bellard | #define FSR_FCC0 (1<<10) |
76 | e8af50a3 | bellard | |
77 | e8af50a3 | bellard | /* MMU */
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78 | e8af50a3 | bellard | #define MMU_E (1<<0) |
79 | e8af50a3 | bellard | #define MMU_NF (1<<1) |
80 | e8af50a3 | bellard | |
81 | e8af50a3 | bellard | #define PTE_ENTRYTYPE_MASK 3 |
82 | e8af50a3 | bellard | #define PTE_ACCESS_MASK 0x1c |
83 | e8af50a3 | bellard | #define PTE_ACCESS_SHIFT 2 |
84 | 8d5f07fa | bellard | #define PTE_PPN_SHIFT 7 |
85 | e8af50a3 | bellard | #define PTE_ADDR_MASK 0xffffff00 |
86 | e8af50a3 | bellard | |
87 | e8af50a3 | bellard | #define PG_ACCESSED_BIT 5 |
88 | e8af50a3 | bellard | #define PG_MODIFIED_BIT 6 |
89 | e8af50a3 | bellard | #define PG_CACHE_BIT 7 |
90 | e8af50a3 | bellard | |
91 | e8af50a3 | bellard | #define PG_ACCESSED_MASK (1 << PG_ACCESSED_BIT) |
92 | e8af50a3 | bellard | #define PG_MODIFIED_MASK (1 << PG_MODIFIED_BIT) |
93 | e8af50a3 | bellard | #define PG_CACHE_MASK (1 << PG_CACHE_BIT) |
94 | e8af50a3 | bellard | |
95 | cf495bcf | bellard | #define NWINDOWS 32 |
96 | cf495bcf | bellard | |
97 | 7a3f1944 | bellard | typedef struct CPUSPARCState { |
98 | cf495bcf | bellard | uint32_t gregs[8]; /* general registers */ |
99 | cf495bcf | bellard | uint32_t *regwptr; /* pointer to current register window */
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100 | e8af50a3 | bellard | float fpr[32]; /* floating point registers */ |
101 | cf495bcf | bellard | uint32_t pc; /* program counter */
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102 | cf495bcf | bellard | uint32_t npc; /* next program counter */
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103 | cf495bcf | bellard | uint32_t y; /* multiply/divide register */
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104 | cf495bcf | bellard | uint32_t psr; /* processor state register */
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105 | e8af50a3 | bellard | uint32_t fsr; /* FPU state register */
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106 | cf495bcf | bellard | uint32_t T2; |
107 | cf495bcf | bellard | uint32_t cwp; /* index of current register window (extracted
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108 | cf495bcf | bellard | from PSR) */
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109 | cf495bcf | bellard | uint32_t wim; /* window invalid mask */
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110 | e8af50a3 | bellard | uint32_t tbr; /* trap base register */
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111 | e8af50a3 | bellard | int psrs; /* supervisor mode (extracted from PSR) */ |
112 | e8af50a3 | bellard | int psrps; /* previous supervisor mode */ |
113 | e8af50a3 | bellard | int psret; /* enable traps */ |
114 | e80cfcfc | bellard | int psrpil; /* interrupt level */ |
115 | e80cfcfc | bellard | int psref; /* enable fpu */ |
116 | cf495bcf | bellard | jmp_buf jmp_env; |
117 | cf495bcf | bellard | int user_mode_only;
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118 | cf495bcf | bellard | int exception_index;
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119 | cf495bcf | bellard | int interrupt_index;
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120 | cf495bcf | bellard | int interrupt_request;
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121 | e8af50a3 | bellard | uint32_t exception_next_pc; |
122 | cf495bcf | bellard | struct TranslationBlock *current_tb;
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123 | cf495bcf | bellard | void *opaque;
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124 | cf495bcf | bellard | /* NOTE: we allow 8 more registers to handle wrapping */
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125 | cf495bcf | bellard | uint32_t regbase[NWINDOWS * 16 + 8]; |
126 | d720b93d | bellard | |
127 | d720b93d | bellard | /* in order to avoid passing too many arguments to the memory
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128 | d720b93d | bellard | write helpers, we store some rarely used information in the CPU
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129 | d720b93d | bellard | context) */
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130 | d720b93d | bellard | unsigned long mem_write_pc; /* host pc at which the memory was |
131 | d720b93d | bellard | written */
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132 | d720b93d | bellard | unsigned long mem_write_vaddr; /* target virtual addr at which the |
133 | d720b93d | bellard | memory was written */
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134 | e8af50a3 | bellard | /* 0 = kernel, 1 = user (may have 2 = kernel code, 3 = user code ?) */
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135 | e8af50a3 | bellard | CPUTLBEntry tlb_read[2][CPU_TLB_SIZE];
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136 | e8af50a3 | bellard | CPUTLBEntry tlb_write[2][CPU_TLB_SIZE];
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137 | e8af50a3 | bellard | int error_code;
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138 | e8af50a3 | bellard | /* MMU regs */
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139 | e8af50a3 | bellard | uint32_t mmuregs[16];
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140 | e8af50a3 | bellard | /* temporary float registers */
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141 | e8af50a3 | bellard | float ft0, ft1, ft2;
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142 | e8af50a3 | bellard | double dt0, dt1, dt2;
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143 | e8af50a3 | bellard | |
144 | e8af50a3 | bellard | /* ice debug support */
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145 | e8af50a3 | bellard | uint32_t breakpoints[MAX_BREAKPOINTS]; |
146 | e8af50a3 | bellard | int nb_breakpoints;
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147 | e8af50a3 | bellard | int singlestep_enabled; /* XXX: should use CPU single step mode instead */ |
148 | e8af50a3 | bellard | |
149 | 7a3f1944 | bellard | } CPUSPARCState; |
150 | 7a3f1944 | bellard | |
151 | 7a3f1944 | bellard | CPUSPARCState *cpu_sparc_init(void);
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152 | 7a3f1944 | bellard | int cpu_sparc_exec(CPUSPARCState *s);
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153 | 7a3f1944 | bellard | int cpu_sparc_close(CPUSPARCState *s);
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154 | e80cfcfc | bellard | void cpu_get_fp64(uint64_t *pmant, uint16_t *pexp, double f); |
155 | e80cfcfc | bellard | double cpu_put_fp64(uint64_t mant, uint16_t exp);
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156 | 7a3f1944 | bellard | |
157 | b4ff5987 | bellard | /* Fake impl 0, version 4 */
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158 | b4ff5987 | bellard | #define GET_PSR(env) ((0 << 28) | (4 << 24) | env->psr | \ |
159 | b4ff5987 | bellard | (env->psref? PSR_EF : 0) | \
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160 | b4ff5987 | bellard | (env->psrpil << 8) | \
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161 | b4ff5987 | bellard | (env->psrs? PSR_S : 0) | \
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162 | b4ff5987 | bellard | (env->psrs? PSR_PS : 0) | \
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163 | b4ff5987 | bellard | (env->psret? PSR_ET : 0) | env->cwp)
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164 | b4ff5987 | bellard | |
165 | b4ff5987 | bellard | #ifndef NO_CPU_IO_DEFS
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166 | b4ff5987 | bellard | void cpu_set_cwp(CPUSPARCState *env1, int new_cwp); |
167 | b4ff5987 | bellard | #endif
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168 | b4ff5987 | bellard | |
169 | b4ff5987 | bellard | #define PUT_PSR(env, val) do { int _tmp = val; \ |
170 | b4ff5987 | bellard | env->psr = _tmp & ~PSR_ICC; \ |
171 | b4ff5987 | bellard | env->psref = (_tmp & PSR_EF)? 1 : 0; \ |
172 | b4ff5987 | bellard | env->psrpil = (_tmp & PSR_PIL) >> 8; \
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173 | b4ff5987 | bellard | env->psrs = (_tmp & PSR_S)? 1 : 0; \ |
174 | b4ff5987 | bellard | env->psrps = (_tmp & PSR_PS)? 1 : 0; \ |
175 | b4ff5987 | bellard | env->psret = (_tmp & PSR_ET)? 1 : 0; \ |
176 | b4ff5987 | bellard | cpu_set_cwp(env, _tmp & PSR_CWP & (NWINDOWS - 1)); \
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177 | b4ff5987 | bellard | } while (0) |
178 | b4ff5987 | bellard | |
179 | 7a3f1944 | bellard | struct siginfo;
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180 | 7a3f1944 | bellard | int cpu_sparc_signal_handler(int hostsignum, struct siginfo *info, void *puc); |
181 | 7a3f1944 | bellard | |
182 | e8af50a3 | bellard | #define TARGET_PAGE_BITS 12 /* 4k */ |
183 | 7a3f1944 | bellard | #include "cpu-all.h" |
184 | 7a3f1944 | bellard | |
185 | 7a3f1944 | bellard | #endif |