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/*
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   SPARC micro operations
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   Copyright (C) 2003 Thomas M. Ogrisegg <tom@fnord.at>
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   This library is free software; you can redistribute it and/or
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   modify it under the terms of the GNU Lesser General Public
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   License as published by the Free Software Foundation; either
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   version 2 of the License, or (at your option) any later version.
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   This library is distributed in the hope that it will be useful,
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   but WITHOUT ANY WARRANTY; without even the implied warranty of
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   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
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   Lesser General Public License for more details.
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   You should have received a copy of the GNU Lesser General Public
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   License along with this library; if not, write to the Free Software
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   Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
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*/
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#include "exec.h"
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 /*XXX*/
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#define REGNAME g0
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#define REG (env->gregs[0])
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#include "op_template.h"
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#define REGNAME g1
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#define REG (env->gregs[1])
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#include "op_template.h"
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#define REGNAME g2
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#define REG (env->gregs[2])
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#include "op_template.h"
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#define REGNAME g3
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#define REG (env->gregs[3])
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#include "op_template.h"
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#define REGNAME g4
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#define REG (env->gregs[4])
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#include "op_template.h"
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#define REGNAME g5
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#define REG (env->gregs[5])
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#include "op_template.h"
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#define REGNAME g6
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#define REG (env->gregs[6])
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#include "op_template.h"
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#define REGNAME g7
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#define REG (env->gregs[7])
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#include "op_template.h"
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#define REGNAME i0
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#define REG (env->regwptr[16])
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#include "op_template.h"
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#define REGNAME i1
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#define REG (env->regwptr[17])
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#include "op_template.h"
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#define REGNAME i2
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#define REG (env->regwptr[18])
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#include "op_template.h"
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#define REGNAME i3
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#define REG (env->regwptr[19])
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#include "op_template.h"
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#define REGNAME i4
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#define REG (env->regwptr[20])
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#include "op_template.h"
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#define REGNAME i5
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#define REG (env->regwptr[21])
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#include "op_template.h"
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#define REGNAME i6
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#define REG (env->regwptr[22])
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#include "op_template.h"
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#define REGNAME i7
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#define REG (env->regwptr[23])
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#include "op_template.h"
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#define REGNAME l0
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#define REG (env->regwptr[8])
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#include "op_template.h"
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#define REGNAME l1
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#define REG (env->regwptr[9])
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#include "op_template.h"
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#define REGNAME l2
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#define REG (env->regwptr[10])
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#include "op_template.h"
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#define REGNAME l3
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#define REG (env->regwptr[11])
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#include "op_template.h"
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#define REGNAME l4
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#define REG (env->regwptr[12])
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#include "op_template.h"
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#define REGNAME l5
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#define REG (env->regwptr[13])
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#include "op_template.h"
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#define REGNAME l6
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#define REG (env->regwptr[14])
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#include "op_template.h"
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#define REGNAME l7
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#define REG (env->regwptr[15])
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#include "op_template.h"
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#define REGNAME o0
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#define REG (env->regwptr[0])
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#include "op_template.h"
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#define REGNAME o1
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#define REG (env->regwptr[1])
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#include "op_template.h"
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#define REGNAME o2
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#define REG (env->regwptr[2])
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#include "op_template.h"
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#define REGNAME o3
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#define REG (env->regwptr[3])
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#include "op_template.h"
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#define REGNAME o4
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#define REG (env->regwptr[4])
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#include "op_template.h"
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#define REGNAME o5
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#define REG (env->regwptr[5])
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#include "op_template.h"
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#define REGNAME o6
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#define REG (env->regwptr[6])
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#include "op_template.h"
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#define REGNAME o7
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#define REG (env->regwptr[7])
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#include "op_template.h"
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#define REGNAME f0
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#define REG (env->fpr[0])
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#include "fop_template.h"
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#define REGNAME f1
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#define REG (env->fpr[1])
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#include "fop_template.h"
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#define REGNAME f2
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#define REG (env->fpr[2])
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#include "fop_template.h"
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#define REGNAME f3
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#define REG (env->fpr[3])
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#include "fop_template.h"
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#define REGNAME f4
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#define REG (env->fpr[4])
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#include "fop_template.h"
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#define REGNAME f5
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#define REG (env->fpr[5])
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#include "fop_template.h"
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#define REGNAME f6
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#define REG (env->fpr[6])
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#include "fop_template.h"
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#define REGNAME f7
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#define REG (env->fpr[7])
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#include "fop_template.h"
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#define REGNAME f8
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#define REG (env->fpr[8])
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#include "fop_template.h"
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#define REGNAME f9
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#define REG (env->fpr[9])
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#include "fop_template.h"
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#define REGNAME f10
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#define REG (env->fpr[10])
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#include "fop_template.h"
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#define REGNAME f11
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#define REG (env->fpr[11])
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#include "fop_template.h"
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#define REGNAME f12
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#define REG (env->fpr[12])
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#include "fop_template.h"
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#define REGNAME f13
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#define REG (env->fpr[13])
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#include "fop_template.h"
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#define REGNAME f14
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#define REG (env->fpr[14])
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#include "fop_template.h"
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#define REGNAME f15
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#define REG (env->fpr[15])
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#include "fop_template.h"
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#define REGNAME f16
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#define REG (env->fpr[16])
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#include "fop_template.h"
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#define REGNAME f17
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#define REG (env->fpr[17])
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#include "fop_template.h"
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#define REGNAME f18
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#define REG (env->fpr[18])
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#include "fop_template.h"
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#define REGNAME f19
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#define REG (env->fpr[19])
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#include "fop_template.h"
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#define REGNAME f20
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#define REG (env->fpr[20])
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#include "fop_template.h"
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#define REGNAME f21
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#define REG (env->fpr[21])
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#include "fop_template.h"
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#define REGNAME f22
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#define REG (env->fpr[22])
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#include "fop_template.h"
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#define REGNAME f23
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#define REG (env->fpr[23])
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#include "fop_template.h"
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#define REGNAME f24
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#define REG (env->fpr[24])
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#include "fop_template.h"
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#define REGNAME f25
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#define REG (env->fpr[25])
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#include "fop_template.h"
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#define REGNAME f26
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#define REG (env->fpr[26])
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#include "fop_template.h"
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#define REGNAME f27
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#define REG (env->fpr[27])
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#include "fop_template.h"
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#define REGNAME f28
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#define REG (env->fpr[28])
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#include "fop_template.h"
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#define REGNAME f29
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#define REG (env->fpr[29])
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#include "fop_template.h"
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#define REGNAME f30
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#define REG (env->fpr[30])
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#include "fop_template.h"
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#define REGNAME f31
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#define REG (env->fpr[31])
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#include "fop_template.h"
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#define EIP (env->pc)
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#define FLAG_SET(x) (env->psr&x)?1:0
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#define FFLAG_SET(x) ((env->fsr&x)?1:0)
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void OPPROTO op_movl_T0_0(void)
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{
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    T0 = 0;
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}
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void OPPROTO op_movl_T0_1(void)
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{
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    T0 = 1;
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}
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void OPPROTO op_movl_T0_im(void)
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{
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    T0 = PARAM1;
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}
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void OPPROTO op_movl_T1_im(void)
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{
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    T1 = PARAM1;
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}
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void OPPROTO op_movl_T2_im(void)
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{
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    T2 = PARAM1;
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}
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void OPPROTO op_addl_T1_im(void)
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{
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    T1 += PARAM1;
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}
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void OPPROTO op_addl_T1_T2(void)
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{
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    T1 += T2;
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}
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void OPPROTO op_subl_T1_T2(void)
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{
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    T1 -= T2;
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}
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void OPPROTO op_add_T1_T0(void)
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{
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    T0 += T1;
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}
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void OPPROTO op_add_T1_T0_cc(void)
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{
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    unsigned int src1;
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    src1 = T0;
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    T0 += T1;
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    env->psr = 0;
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    if (!T0)
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        env->psr |= PSR_ZERO;
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    if ((int) T0 < 0)
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        env->psr |= PSR_NEG;
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    if (T0 < src1)
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        env->psr |= PSR_CARRY;
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    if (((src1 ^ T1 ^ -1) & (src1 ^ T0)) & (1 << 31))
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        env->psr |= PSR_OVF;
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    FORCE_RET();
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}
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void OPPROTO op_sub_T1_T0(void)
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{
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    T0 -= T1;
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}
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void OPPROTO op_sub_T1_T0_cc(void)
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{
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    unsigned int src1;
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    src1 = T0;
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    T0 -= T1;
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    env->psr = 0;
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    if (!T0)
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        env->psr |= PSR_ZERO;
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    if ((int) T0 < 0)
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        env->psr |= PSR_NEG;
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    if (src1 < T1)
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        env->psr |= PSR_CARRY;
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    if (((src1 ^ T1) & (src1 ^ T0)) & (1 << 31))
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        env->psr |= PSR_OVF;
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    FORCE_RET();
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}
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void OPPROTO op_and_T1_T0(void)
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{
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    T0 &= T1;
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}
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void OPPROTO op_or_T1_T0(void)
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{
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    T0 |= T1;
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}
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void OPPROTO op_xor_T1_T0(void)
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{
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    T0 ^= T1;
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}
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void OPPROTO op_andn_T1_T0(void)
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{
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    T0 &= ~T1;
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}
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void OPPROTO op_orn_T1_T0(void)
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{
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    T0 |= ~T1;
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}
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void OPPROTO op_xnor_T1_T0(void)
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{
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    T0 ^= ~T1;
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}
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void OPPROTO op_addx_T1_T0(void)
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{
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    T0 += T1 + ((env->psr & PSR_CARRY) ? 1 : 0);
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}
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void OPPROTO op_umul_T1_T0(void)
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{
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    uint64_t res;
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    res = (uint64_t) T0 *(uint64_t) T1;
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    T0 = res & 0xffffffff;
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    env->y = res >> 32;
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}
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void OPPROTO op_smul_T1_T0(void)
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{
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    uint64_t res;
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    res = (int64_t) ((int32_t) T0) * (int64_t) ((int32_t) T1);
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    T0 = res & 0xffffffff;
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    env->y = res >> 32;
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}
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void OPPROTO op_mulscc_T1_T0(void)
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{
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    unsigned int b1, N, V, b2, src1;
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    N = FLAG_SET(PSR_NEG);
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    V = FLAG_SET(PSR_OVF);
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    b1 = N ^ V;
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    b2 = T0 & 1;
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    T0 = (b1 << 31) | (T0 >> 1);
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    if (!(env->y & 1))
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        T1 = 0;
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    /* do addition and update flags */
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    src1 = T0;
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    T0 += T1;
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    env->psr = 0;
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    if (!T0)
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        env->psr |= PSR_ZERO;
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    if ((int) T0 < 0)
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        env->psr |= PSR_NEG;
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    if (T0 < src1)
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        env->psr |= PSR_CARRY;
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    if (((src1 ^ T1 ^ -1) & (src1 ^ T0)) & (1 << 31))
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        env->psr |= PSR_OVF;
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    env->y = (b2 << 31) | (env->y >> 1);
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    FORCE_RET();
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}
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void OPPROTO op_udiv_T1_T0(void)
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{
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    uint64_t x0;
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    uint32_t x1;
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    x0 = T0 | ((uint64_t) (env->y) << 32);
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    x1 = T1;
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    x0 = x0 / x1;
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    if (x0 > 0xffffffff) {
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        T0 = 0xffffffff;
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        T1 = 1;
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    } else {
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        T0 = x0;
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        T1 = 0;
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    }
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    FORCE_RET();
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}
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void OPPROTO op_sdiv_T1_T0(void)
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{
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    int64_t x0;
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    int32_t x1;
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    x0 = T0 | ((uint64_t) (env->y) << 32);
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    x1 = T1;
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    x0 = x0 / x1;
411 cf495bcf bellard
    if ((int32_t) x0 != x0) {
412 cf495bcf bellard
        T0 = x0 >> 63;
413 cf495bcf bellard
        T1 = 1;
414 cf495bcf bellard
    } else {
415 cf495bcf bellard
        T0 = x0;
416 cf495bcf bellard
        T1 = 0;
417 cf495bcf bellard
    }
418 cf495bcf bellard
    FORCE_RET();
419 7a3f1944 bellard
}
420 7a3f1944 bellard
421 cf495bcf bellard
void OPPROTO op_div_cc(void)
422 7a3f1944 bellard
{
423 cf495bcf bellard
    env->psr = 0;
424 cf495bcf bellard
    if (!T0)
425 cf495bcf bellard
        env->psr |= PSR_ZERO;
426 cf495bcf bellard
    if ((int) T0 < 0)
427 cf495bcf bellard
        env->psr |= PSR_NEG;
428 cf495bcf bellard
    if (T1)
429 cf495bcf bellard
        env->psr |= PSR_OVF;
430 cf495bcf bellard
    FORCE_RET();
431 7a3f1944 bellard
}
432 7a3f1944 bellard
433 cf495bcf bellard
void OPPROTO op_subx_T1_T0(void)
434 7a3f1944 bellard
{
435 cf495bcf bellard
    T0 -= T1 + ((env->psr & PSR_CARRY) ? 1 : 0);
436 7a3f1944 bellard
}
437 7a3f1944 bellard
438 cf495bcf bellard
void OPPROTO op_logic_T0_cc(void)
439 7a3f1944 bellard
{
440 cf495bcf bellard
    env->psr = 0;
441 cf495bcf bellard
    if (!T0)
442 cf495bcf bellard
        env->psr |= PSR_ZERO;
443 cf495bcf bellard
    if ((int) T0 < 0)
444 cf495bcf bellard
        env->psr |= PSR_NEG;
445 cf495bcf bellard
    FORCE_RET();
446 7a3f1944 bellard
}
447 7a3f1944 bellard
448 cf495bcf bellard
void OPPROTO op_set_flags(void)
449 7a3f1944 bellard
{
450 cf495bcf bellard
    env->psr = 0;
451 cf495bcf bellard
    if (!T0)
452 cf495bcf bellard
        env->psr |= PSR_ZERO;
453 cf495bcf bellard
    if ((unsigned int) T0 < (unsigned int) T1)
454 cf495bcf bellard
        env->psr |= PSR_CARRY;
455 cf495bcf bellard
    if ((int) T0 < (int) T1)
456 cf495bcf bellard
        env->psr |= PSR_OVF;
457 cf495bcf bellard
    if ((int) T0 < 0)
458 cf495bcf bellard
        env->psr |= PSR_NEG;
459 cf495bcf bellard
    FORCE_RET();
460 7a3f1944 bellard
}
461 7a3f1944 bellard
462 cf495bcf bellard
void OPPROTO op_sll(void)
463 7a3f1944 bellard
{
464 cf495bcf bellard
    T0 <<= T1;
465 7a3f1944 bellard
}
466 7a3f1944 bellard
467 cf495bcf bellard
void OPPROTO op_srl(void)
468 7a3f1944 bellard
{
469 cf495bcf bellard
    T0 >>= T1;
470 7a3f1944 bellard
}
471 7a3f1944 bellard
472 cf495bcf bellard
void OPPROTO op_sra(void)
473 7a3f1944 bellard
{
474 cf495bcf bellard
    T0 = ((int32_t) T0) >> T1;
475 7a3f1944 bellard
}
476 7a3f1944 bellard
477 e8af50a3 bellard
/* Load and store */
478 e8af50a3 bellard
#define MEMSUFFIX _raw
479 e8af50a3 bellard
#include "op_mem.h"
480 e8af50a3 bellard
#if !defined(CONFIG_USER_ONLY)
481 e8af50a3 bellard
#define MEMSUFFIX _user
482 e8af50a3 bellard
#include "op_mem.h"
483 e8af50a3 bellard
484 e8af50a3 bellard
#define MEMSUFFIX _kernel
485 e8af50a3 bellard
#include "op_mem.h"
486 e8af50a3 bellard
#endif
487 e8af50a3 bellard
488 e8af50a3 bellard
void OPPROTO op_ldfsr(void)
489 e8af50a3 bellard
{
490 e8af50a3 bellard
    env->fsr = *((uint32_t *) &FT0);
491 8d5f07fa bellard
    helper_ldfsr();
492 e8af50a3 bellard
}
493 e8af50a3 bellard
494 e8af50a3 bellard
void OPPROTO op_stfsr(void)
495 e8af50a3 bellard
{
496 e8af50a3 bellard
    *((uint32_t *) &FT0) = env->fsr;
497 e8af50a3 bellard
}
498 e8af50a3 bellard
499 cf495bcf bellard
void OPPROTO op_wry(void)
500 7a3f1944 bellard
{
501 cf495bcf bellard
    env->y = T0;
502 7a3f1944 bellard
}
503 7a3f1944 bellard
504 cf495bcf bellard
void OPPROTO op_rdy(void)
505 7a3f1944 bellard
{
506 cf495bcf bellard
    T0 = env->y;
507 7a3f1944 bellard
}
508 7a3f1944 bellard
509 e8af50a3 bellard
void OPPROTO op_rdwim(void)
510 cf495bcf bellard
{
511 e8af50a3 bellard
    T0 = env->wim;
512 e8af50a3 bellard
}
513 e8af50a3 bellard
514 e8af50a3 bellard
void OPPROTO op_wrwim(void)
515 e8af50a3 bellard
{
516 e8af50a3 bellard
    env->wim = T0;
517 e8af50a3 bellard
    FORCE_RET();
518 e8af50a3 bellard
}
519 e8af50a3 bellard
520 e8af50a3 bellard
void OPPROTO op_rdpsr(void)
521 e8af50a3 bellard
{
522 e8af50a3 bellard
    T0 = GET_PSR(env);
523 e8af50a3 bellard
}
524 e8af50a3 bellard
525 e8af50a3 bellard
void OPPROTO op_wrpsr(void)
526 e8af50a3 bellard
{
527 e80cfcfc bellard
    PUT_PSR(env,T0);
528 e8af50a3 bellard
    FORCE_RET();
529 e8af50a3 bellard
}
530 e8af50a3 bellard
531 e8af50a3 bellard
void OPPROTO op_rdtbr(void)
532 e8af50a3 bellard
{
533 e8af50a3 bellard
    T0 = env->tbr;
534 e8af50a3 bellard
}
535 cf495bcf bellard
536 e8af50a3 bellard
void OPPROTO op_wrtbr(void)
537 7a3f1944 bellard
{
538 e8af50a3 bellard
    env->tbr = T0;
539 e8af50a3 bellard
    FORCE_RET();
540 7a3f1944 bellard
}
541 7a3f1944 bellard
542 e8af50a3 bellard
void OPPROTO op_rett(void)
543 cf495bcf bellard
{
544 e8af50a3 bellard
    helper_rett();
545 e8af50a3 bellard
    FORCE_RET();
546 cf495bcf bellard
}
547 7a3f1944 bellard
548 e8af50a3 bellard
void raise_exception(int tt)
549 e8af50a3 bellard
{
550 e8af50a3 bellard
    env->exception_index = tt;
551 e8af50a3 bellard
    cpu_loop_exit();
552 e8af50a3 bellard
}   
553 e8af50a3 bellard
554 cf495bcf bellard
/* XXX: use another pointer for %iN registers to avoid slow wrapping
555 cf495bcf bellard
   handling ? */
556 cf495bcf bellard
void OPPROTO op_save(void)
557 7a3f1944 bellard
{
558 cf495bcf bellard
    int cwp;
559 cf495bcf bellard
    cwp = (env->cwp - 1) & (NWINDOWS - 1); 
560 cf495bcf bellard
    if (env->wim & (1 << cwp)) {
561 cf495bcf bellard
        raise_exception(TT_WIN_OVF);
562 cf495bcf bellard
    }
563 cf495bcf bellard
    set_cwp(cwp);
564 cf495bcf bellard
    FORCE_RET();
565 7a3f1944 bellard
}
566 7a3f1944 bellard
567 cf495bcf bellard
void OPPROTO op_restore(void)
568 7a3f1944 bellard
{
569 cf495bcf bellard
    int cwp;
570 cf495bcf bellard
    cwp = (env->cwp + 1) & (NWINDOWS - 1); 
571 cf495bcf bellard
    if (env->wim & (1 << cwp)) {
572 cf495bcf bellard
        raise_exception(TT_WIN_UNF);
573 cf495bcf bellard
    }
574 cf495bcf bellard
    set_cwp(cwp);
575 cf495bcf bellard
    FORCE_RET();
576 7a3f1944 bellard
}
577 7a3f1944 bellard
578 cf495bcf bellard
void OPPROTO op_exception(void)
579 7a3f1944 bellard
{
580 cf495bcf bellard
    env->exception_index = PARAM1;
581 cf495bcf bellard
    cpu_loop_exit();
582 7a3f1944 bellard
}
583 7a3f1944 bellard
584 cf495bcf bellard
void OPPROTO op_trap_T0(void)
585 7a3f1944 bellard
{
586 cf495bcf bellard
    env->exception_index = TT_TRAP + (T0 & 0x7f);
587 cf495bcf bellard
    cpu_loop_exit();
588 7a3f1944 bellard
}
589 7a3f1944 bellard
590 cf495bcf bellard
void OPPROTO op_trapcc_T0(void)
591 7a3f1944 bellard
{
592 cf495bcf bellard
    if (T2) {
593 cf495bcf bellard
        env->exception_index = TT_TRAP + (T0 & 0x7f);
594 cf495bcf bellard
        cpu_loop_exit();
595 cf495bcf bellard
    }
596 cf495bcf bellard
    FORCE_RET();
597 7a3f1944 bellard
}
598 7a3f1944 bellard
599 e80cfcfc bellard
void OPPROTO op_trap_ifnofpu(void)
600 e80cfcfc bellard
{
601 e80cfcfc bellard
    if (!env->psref) {
602 e80cfcfc bellard
        env->exception_index = TT_NFPU_INSN;
603 e80cfcfc bellard
        cpu_loop_exit();
604 e80cfcfc bellard
    }
605 e80cfcfc bellard
    FORCE_RET();
606 e80cfcfc bellard
}
607 e80cfcfc bellard
608 e80cfcfc bellard
void OPPROTO op_fpexception_im(void)
609 e8af50a3 bellard
{
610 e80cfcfc bellard
    env->exception_index = TT_FP_EXCP;
611 e80cfcfc bellard
    env->fsr &= ~FSR_FTT_MASK;
612 e80cfcfc bellard
    env->fsr |= PARAM1;
613 e8af50a3 bellard
    cpu_loop_exit();
614 e80cfcfc bellard
    FORCE_RET();
615 e80cfcfc bellard
}
616 e80cfcfc bellard
617 e80cfcfc bellard
void OPPROTO op_debug(void)
618 e80cfcfc bellard
{
619 e80cfcfc bellard
    helper_debug();
620 e8af50a3 bellard
}
621 e8af50a3 bellard
622 cf495bcf bellard
void OPPROTO op_exit_tb(void)
623 7a3f1944 bellard
{
624 cf495bcf bellard
    EXIT_TB();
625 7a3f1944 bellard
}
626 7a3f1944 bellard
627 cf495bcf bellard
void OPPROTO op_eval_be(void)
628 7a3f1944 bellard
{
629 cf495bcf bellard
    T2 = (env->psr & PSR_ZERO);
630 7a3f1944 bellard
}
631 7a3f1944 bellard
632 cf495bcf bellard
void OPPROTO op_eval_ble(void)
633 7a3f1944 bellard
{
634 612b477d bellard
    unsigned int Z = FLAG_SET(PSR_ZERO), N = FLAG_SET(PSR_NEG), V = FLAG_SET(PSR_OVF);
635 612b477d bellard
    
636 cf495bcf bellard
    T2 = Z | (N ^ V);
637 7a3f1944 bellard
}
638 7a3f1944 bellard
639 cf495bcf bellard
void OPPROTO op_eval_bl(void)
640 7a3f1944 bellard
{
641 612b477d bellard
    unsigned int N = FLAG_SET(PSR_NEG), V = FLAG_SET(PSR_OVF);
642 612b477d bellard
643 cf495bcf bellard
    T2 = N ^ V;
644 7a3f1944 bellard
}
645 7a3f1944 bellard
646 cf495bcf bellard
void OPPROTO op_eval_bleu(void)
647 7a3f1944 bellard
{
648 612b477d bellard
    unsigned int Z = FLAG_SET(PSR_ZERO), C = FLAG_SET(PSR_CARRY);
649 612b477d bellard
650 cf495bcf bellard
    T2 = C | Z;
651 7a3f1944 bellard
}
652 7a3f1944 bellard
653 cf495bcf bellard
void OPPROTO op_eval_bcs(void)
654 7a3f1944 bellard
{
655 cf495bcf bellard
    T2 = (env->psr & PSR_CARRY);
656 7a3f1944 bellard
}
657 7a3f1944 bellard
658 cf495bcf bellard
void OPPROTO op_eval_bvs(void)
659 7a3f1944 bellard
{
660 cf495bcf bellard
    T2 = (env->psr & PSR_OVF);
661 7a3f1944 bellard
}
662 7a3f1944 bellard
663 cf495bcf bellard
void OPPROTO op_eval_bneg(void)
664 7a3f1944 bellard
{
665 cf495bcf bellard
    T2 = (env->psr & PSR_NEG);
666 7a3f1944 bellard
}
667 7a3f1944 bellard
668 cf495bcf bellard
void OPPROTO op_eval_bne(void)
669 7a3f1944 bellard
{
670 cf495bcf bellard
    T2 = !(env->psr & PSR_ZERO);
671 7a3f1944 bellard
}
672 7a3f1944 bellard
673 cf495bcf bellard
void OPPROTO op_eval_bg(void)
674 7a3f1944 bellard
{
675 612b477d bellard
    unsigned int Z = FLAG_SET(PSR_ZERO), N = FLAG_SET(PSR_NEG), V = FLAG_SET(PSR_OVF);
676 612b477d bellard
677 cf495bcf bellard
    T2 = !(Z | (N ^ V));
678 7a3f1944 bellard
}
679 7a3f1944 bellard
680 cf495bcf bellard
void OPPROTO op_eval_bge(void)
681 7a3f1944 bellard
{
682 612b477d bellard
    unsigned int N = FLAG_SET(PSR_NEG), V = FLAG_SET(PSR_OVF);
683 612b477d bellard
684 cf495bcf bellard
    T2 = !(N ^ V);
685 7a3f1944 bellard
}
686 7a3f1944 bellard
687 cf495bcf bellard
void OPPROTO op_eval_bgu(void)
688 7a3f1944 bellard
{
689 612b477d bellard
    unsigned int Z = FLAG_SET(PSR_ZERO), C = FLAG_SET(PSR_CARRY);
690 612b477d bellard
691 cf495bcf bellard
    T2 = !(C | Z);
692 7a3f1944 bellard
}
693 7a3f1944 bellard
694 cf495bcf bellard
void OPPROTO op_eval_bcc(void)
695 7a3f1944 bellard
{
696 cf495bcf bellard
    T2 = !(env->psr & PSR_CARRY);
697 7a3f1944 bellard
}
698 7a3f1944 bellard
699 cf495bcf bellard
void OPPROTO op_eval_bpos(void)
700 cf495bcf bellard
{
701 cf495bcf bellard
    T2 = !(env->psr & PSR_NEG);
702 cf495bcf bellard
}
703 cf495bcf bellard
704 cf495bcf bellard
void OPPROTO op_eval_bvc(void)
705 cf495bcf bellard
{
706 cf495bcf bellard
    T2 = !(env->psr & PSR_OVF);
707 cf495bcf bellard
}
708 cf495bcf bellard
709 e8af50a3 bellard
/* FCC1:FCC0: 0 =, 1 <, 2 >, 3 u */
710 e8af50a3 bellard
711 e8af50a3 bellard
void OPPROTO op_eval_fbne(void)
712 e8af50a3 bellard
{
713 e8af50a3 bellard
// !0
714 e8af50a3 bellard
    T2 = (env->fsr & (FSR_FCC1 | FSR_FCC0)); /* L or G or U */
715 e8af50a3 bellard
}
716 e8af50a3 bellard
717 e8af50a3 bellard
void OPPROTO op_eval_fblg(void)
718 e8af50a3 bellard
{
719 e8af50a3 bellard
// 1 or 2
720 e8af50a3 bellard
    T2 = FFLAG_SET(FSR_FCC0) ^ FFLAG_SET(FSR_FCC1);
721 e8af50a3 bellard
}
722 e8af50a3 bellard
723 e8af50a3 bellard
void OPPROTO op_eval_fbul(void)
724 e8af50a3 bellard
{
725 e8af50a3 bellard
// 1 or 3
726 e8af50a3 bellard
    T2 = FFLAG_SET(FSR_FCC0);
727 e8af50a3 bellard
}
728 e8af50a3 bellard
729 e8af50a3 bellard
void OPPROTO op_eval_fbl(void)
730 e8af50a3 bellard
{
731 e8af50a3 bellard
// 1
732 e8af50a3 bellard
    T2 = FFLAG_SET(FSR_FCC0) & !FFLAG_SET(FSR_FCC1);
733 e8af50a3 bellard
}
734 e8af50a3 bellard
735 e8af50a3 bellard
void OPPROTO op_eval_fbug(void)
736 e8af50a3 bellard
{
737 e8af50a3 bellard
// 2 or 3
738 e8af50a3 bellard
    T2 = FFLAG_SET(FSR_FCC1);
739 e8af50a3 bellard
}
740 e8af50a3 bellard
741 e8af50a3 bellard
void OPPROTO op_eval_fbg(void)
742 e8af50a3 bellard
{
743 e8af50a3 bellard
// 2
744 e8af50a3 bellard
    T2 = !FFLAG_SET(FSR_FCC0) & FFLAG_SET(FSR_FCC1);
745 e8af50a3 bellard
}
746 e8af50a3 bellard
747 e8af50a3 bellard
void OPPROTO op_eval_fbu(void)
748 e8af50a3 bellard
{
749 e8af50a3 bellard
// 3
750 e8af50a3 bellard
    T2 = FFLAG_SET(FSR_FCC0) & FFLAG_SET(FSR_FCC1);
751 e8af50a3 bellard
}
752 e8af50a3 bellard
753 e8af50a3 bellard
void OPPROTO op_eval_fbe(void)
754 e8af50a3 bellard
{
755 e8af50a3 bellard
// 0
756 e8af50a3 bellard
    T2 = !FFLAG_SET(FSR_FCC0) & !FFLAG_SET(FSR_FCC1);
757 e8af50a3 bellard
}
758 e8af50a3 bellard
759 e8af50a3 bellard
void OPPROTO op_eval_fbue(void)
760 e8af50a3 bellard
{
761 e8af50a3 bellard
// 0 or 3
762 e8af50a3 bellard
    T2 = !(FFLAG_SET(FSR_FCC1) ^ FFLAG_SET(FSR_FCC0));
763 e8af50a3 bellard
}
764 e8af50a3 bellard
765 e8af50a3 bellard
void OPPROTO op_eval_fbge(void)
766 e8af50a3 bellard
{
767 e8af50a3 bellard
// 0 or 2
768 e8af50a3 bellard
    T2 = !FFLAG_SET(FSR_FCC0);
769 e8af50a3 bellard
}
770 e8af50a3 bellard
771 e8af50a3 bellard
void OPPROTO op_eval_fbuge(void)
772 e8af50a3 bellard
{
773 e8af50a3 bellard
// !1
774 e8af50a3 bellard
    T2 = !(FFLAG_SET(FSR_FCC0) & !FFLAG_SET(FSR_FCC1));
775 e8af50a3 bellard
}
776 e8af50a3 bellard
777 e8af50a3 bellard
void OPPROTO op_eval_fble(void)
778 e8af50a3 bellard
{
779 e8af50a3 bellard
// 0 or 1
780 e8af50a3 bellard
    T2 = !FFLAG_SET(FSR_FCC1);
781 e8af50a3 bellard
}
782 e8af50a3 bellard
783 e8af50a3 bellard
void OPPROTO op_eval_fbule(void)
784 e8af50a3 bellard
{
785 e8af50a3 bellard
// !2
786 e8af50a3 bellard
    T2 = !(!FFLAG_SET(FSR_FCC0) & FFLAG_SET(FSR_FCC1));
787 e8af50a3 bellard
}
788 e8af50a3 bellard
789 e8af50a3 bellard
void OPPROTO op_eval_fbo(void)
790 e8af50a3 bellard
{
791 e8af50a3 bellard
// !3
792 e8af50a3 bellard
    T2 = !(FFLAG_SET(FSR_FCC0) & FFLAG_SET(FSR_FCC1));
793 e8af50a3 bellard
}
794 e8af50a3 bellard
795 cf495bcf bellard
void OPPROTO op_movl_T2_0(void)
796 cf495bcf bellard
{
797 cf495bcf bellard
    T2 = 0;
798 cf495bcf bellard
}
799 cf495bcf bellard
800 cf495bcf bellard
void OPPROTO op_movl_T2_1(void)
801 cf495bcf bellard
{
802 cf495bcf bellard
    T2 = 1;
803 cf495bcf bellard
}
804 cf495bcf bellard
805 cf495bcf bellard
void OPPROTO op_jmp_im(void)
806 cf495bcf bellard
{
807 cf495bcf bellard
    env->pc = PARAM1;
808 cf495bcf bellard
}
809 cf495bcf bellard
810 cf495bcf bellard
void OPPROTO op_movl_npc_im(void)
811 cf495bcf bellard
{
812 cf495bcf bellard
    env->npc = PARAM1;
813 cf495bcf bellard
}
814 7a3f1944 bellard
815 cf495bcf bellard
void OPPROTO op_movl_npc_T0(void)
816 7a3f1944 bellard
{
817 cf495bcf bellard
    env->npc = T0;
818 7a3f1944 bellard
}
819 7a3f1944 bellard
820 cf495bcf bellard
void OPPROTO op_next_insn(void)
821 7a3f1944 bellard
{
822 cf495bcf bellard
    env->pc = env->npc;
823 cf495bcf bellard
    env->npc = env->npc + 4;
824 7a3f1944 bellard
}
825 7a3f1944 bellard
826 72cbca10 bellard
void OPPROTO op_branch(void)
827 72cbca10 bellard
{
828 72cbca10 bellard
    env->npc = PARAM3; /* XXX: optimize */
829 72cbca10 bellard
    JUMP_TB(op_branch, PARAM1, 0, PARAM2);
830 72cbca10 bellard
}
831 72cbca10 bellard
832 72cbca10 bellard
void OPPROTO op_branch2(void)
833 7a3f1944 bellard
{
834 cf495bcf bellard
    if (T2) {
835 72cbca10 bellard
        env->npc = PARAM2 + 4; 
836 72cbca10 bellard
        JUMP_TB(op_branch2, PARAM1, 0, PARAM2);
837 cf495bcf bellard
    } else {
838 72cbca10 bellard
        env->npc = PARAM3 + 4; 
839 72cbca10 bellard
        JUMP_TB(op_branch2, PARAM1, 1, PARAM3);
840 72cbca10 bellard
    }
841 72cbca10 bellard
    FORCE_RET();
842 72cbca10 bellard
}
843 72cbca10 bellard
844 72cbca10 bellard
void OPPROTO op_branch_a(void)
845 72cbca10 bellard
{
846 72cbca10 bellard
    if (T2) {
847 72cbca10 bellard
        env->npc = PARAM2; /* XXX: optimize */
848 72cbca10 bellard
        JUMP_TB(op_generic_branch_a, PARAM1, 0, PARAM3);
849 72cbca10 bellard
    } else {
850 72cbca10 bellard
        env->npc = PARAM3 + 8; /* XXX: optimize */
851 72cbca10 bellard
        JUMP_TB(op_generic_branch_a, PARAM1, 1, PARAM3 + 4);
852 cf495bcf bellard
    }
853 cf495bcf bellard
    FORCE_RET();
854 7a3f1944 bellard
}
855 7a3f1944 bellard
856 72cbca10 bellard
void OPPROTO op_generic_branch(void)
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{
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    if (T2) {
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        env->npc = PARAM1;
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    } else {
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        env->npc = PARAM2;
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    }
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    FORCE_RET();
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}
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void OPPROTO op_flush_T0(void)
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{
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    helper_flush(T0);
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}
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void OPPROTO op_fnegs(void)
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{
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    FT0 = -FT1;
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}
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void OPPROTO op_fabss(void)
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{
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    do_fabss();
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}
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void OPPROTO op_fsqrts(void)
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{
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    do_fsqrts();
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}
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void OPPROTO op_fsqrtd(void)
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{
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    do_fsqrtd();
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}
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void OPPROTO op_fmuls(void)
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{
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    FT0 *= FT1;
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}
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void OPPROTO op_fmuld(void)
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{
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    DT0 *= DT1;
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}
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void OPPROTO op_fsmuld(void)
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{
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    DT0 = FT0 * FT1;
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}
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void OPPROTO op_fadds(void)
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{
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    FT0 += FT1;
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}
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void OPPROTO op_faddd(void)
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{
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    DT0 += DT1;
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}
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void OPPROTO op_fsubs(void)
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{
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    FT0 -= FT1;
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}
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void OPPROTO op_fsubd(void)
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{
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    DT0 -= DT1;
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}
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void OPPROTO op_fdivs(void)
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{
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    FT0 /= FT1;
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}
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void OPPROTO op_fdivd(void)
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{
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    DT0 /= DT1;
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}
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void OPPROTO op_fcmps(void)
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{
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    do_fcmps();
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}
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void OPPROTO op_fcmpd(void)
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{
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    do_fcmpd();
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}
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#ifdef USE_INT_TO_FLOAT_HELPERS
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void OPPROTO op_fitos(void)
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{
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    do_fitos();
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}
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void OPPROTO op_fitod(void)
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{
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    do_fitod();
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}
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#else
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void OPPROTO op_fitos(void)
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{
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    FT0 = (float) *((int32_t *)&FT1);
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}
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void OPPROTO op_fitod(void)
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{
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    DT0 = (double) *((int32_t *)&FT1);
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}
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#endif
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void OPPROTO op_fdtos(void)
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{
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    FT0 = (float) DT1;
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}
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void OPPROTO op_fstod(void)
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{
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    DT0 = (double) FT1;
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}
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void OPPROTO op_fstoi(void)
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{
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    *((int32_t *)&FT0) = (int32_t) FT1;
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}
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void OPPROTO op_fdtoi(void)
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{
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    *((int32_t *)&FT0) = (int32_t) DT1;
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}
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void OPPROTO op_ld_asi()
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{
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    helper_ld_asi(PARAM1, PARAM2, PARAM3);
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}
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void OPPROTO op_st_asi()
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{
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    helper_st_asi(PARAM1, PARAM2, PARAM3);
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}