Revision d46ccfce
b/hw/milkymist-pfpu.c | ||
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118 | 118 |
|
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struct MilkymistPFPUState { |
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SysBusDevice busdev; |
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MemoryRegion regs_region; |
|
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CharDriverState *chr; |
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qemu_irq irq; |
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|
... | ... | |
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return (512 * s->regs[R_CODEPAGE]) + addr - MICROCODE_BEGIN; |
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} |
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static uint32_t pfpu_read(void *opaque, target_phys_addr_t addr) |
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static uint64_t pfpu_read(void *opaque, target_phys_addr_t addr, |
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unsigned size) |
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{ |
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MilkymistPFPUState *s = opaque; |
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uint32_t r = 0; |
... | ... | |
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return r; |
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} |
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static void |
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pfpu_write(void *opaque, target_phys_addr_t addr, uint32_t value)
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static void pfpu_write(void *opaque, target_phys_addr_t addr, uint64_t value,
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unsigned size)
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{ |
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MilkymistPFPUState *s = opaque; |
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|
... | ... | |
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} |
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} |
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static CPUReadMemoryFunc * const pfpu_read_fn[] = { |
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NULL, |
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NULL, |
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&pfpu_read, |
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}; |
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|
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static CPUWriteMemoryFunc * const pfpu_write_fn[] = { |
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NULL, |
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NULL, |
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&pfpu_write, |
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static const MemoryRegionOps pfpu_mmio_ops = { |
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.read = pfpu_read, |
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.write = pfpu_write, |
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.valid = { |
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.min_access_size = 4, |
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.max_access_size = 4, |
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}, |
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.endianness = DEVICE_NATIVE_ENDIAN, |
|
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}; |
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|
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static void milkymist_pfpu_reset(DeviceState *d) |
... | ... | |
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static int milkymist_pfpu_init(SysBusDevice *dev) |
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{ |
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MilkymistPFPUState *s = FROM_SYSBUS(typeof(*s), dev); |
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int pfpu_regs; |
|
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|
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sysbus_init_irq(dev, &s->irq); |
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pfpu_regs = cpu_register_io_memory(pfpu_read_fn, pfpu_write_fn, s,
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DEVICE_NATIVE_ENDIAN);
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sysbus_init_mmio(dev, MICROCODE_END * 4, pfpu_regs);
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memory_region_init_io(&s->regs_region, &pfpu_mmio_ops, s,
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"milkymist-pfpu", MICROCODE_END * 4);
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sysbus_init_mmio_region(dev, &s->regs_region);
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return 0; |
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} |
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