Revision d47ede60 hw/r2d.c
| b/hw/r2d.c | ||
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| 34 | 34 |
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#define SM501_VRAM_SIZE 0x800000 |
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#define PA_IRLMSK 0x00 |
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#define PA_POWOFF 0x30 |
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#define PA_VERREG 0x32 |
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#define PA_OUTPORT 0x36 |
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typedef struct {
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uint16_t bcr; |
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uint16_t irlmsk; |
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uint16_t irlmon; |
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uint16_t cfctl; |
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uint16_t cfpow; |
| ... | ... | |
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uint16_t inport; |
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uint16_t outport; |
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uint16_t bverreg; |
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/* output pin */ |
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qemu_irq irl; |
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} r2d_fpga_t; |
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enum r2d_fpga_irq {
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PCI_INTD, CF_IDE, CF_CD, PCI_INTC, SM501, KEY, RTC_A, RTC_T, |
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SDCARD, PCI_INTA, PCI_INTB, EXT, TP, |
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NR_IRQS |
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}; |
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static const struct { short irl; uint16_t msk; } irqtab[NR_IRQS] = {
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[CF_IDE] = { 1, 1<<9 },
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[CF_CD] = { 2, 1<<8 },
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[PCI_INTA] = { 9, 1<<14 },
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[PCI_INTB] = { 10, 1<<13 },
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[PCI_INTC] = { 3, 1<<12 },
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[PCI_INTD] = { 0, 1<<11 },
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[SM501] = { 4, 1<<10 },
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[KEY] = { 5, 1<<6 },
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[RTC_A] = { 6, 1<<5 },
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[RTC_T] = { 7, 1<<4 },
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[SDCARD] = { 8, 1<<7 },
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[EXT] = { 11, 1<<0 },
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[TP] = { 12, 1<<15 },
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}; |
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static void update_irl(r2d_fpga_t *fpga) |
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{
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int i, irl = 15; |
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for (i = 0; i < NR_IRQS; i++) |
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if (fpga->irlmon & fpga->irlmsk & irqtab[i].msk) |
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if (irqtab[i].irl < irl) |
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irl = irqtab[i].irl; |
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qemu_set_irq(fpga->irl, irl ^ 15); |
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} |
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static void r2d_fpga_irq_set(void *opaque, int n, int level) |
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{
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r2d_fpga_t *fpga = opaque; |
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if (level) |
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fpga->irlmon |= irqtab[n].msk; |
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else |
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fpga->irlmon &= ~irqtab[n].msk; |
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update_irl(fpga); |
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} |
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static uint32_t r2d_fpga_read(void *opaque, target_phys_addr_t addr) |
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{
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r2d_fpga_t *s = opaque; |
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switch (addr) {
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case PA_IRLMSK: |
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return s->irlmsk; |
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case PA_OUTPORT: |
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return s->outport; |
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case PA_POWOFF: |
| ... | ... | |
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r2d_fpga_t *s = opaque; |
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switch (addr) {
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case PA_IRLMSK: |
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s->irlmsk = value; |
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update_irl(s); |
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break; |
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case PA_OUTPORT: |
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s->outport = value; |
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break; |
| ... | ... | |
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NULL, |
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}; |
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static void r2d_fpga_init(target_phys_addr_t base)
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static qemu_irq *r2d_fpga_init(target_phys_addr_t base, qemu_irq irl)
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{
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int iomemtype; |
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r2d_fpga_t *s; |
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s = qemu_mallocz(sizeof(r2d_fpga_t)); |
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if (!s) |
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return; |
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return NULL; |
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s->irl = irl; |
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iomemtype = cpu_register_io_memory(0, r2d_fpga_readfn, |
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r2d_fpga_writefn, s); |
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cpu_register_physical_memory(base, 0x40, iomemtype); |
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return qemu_allocate_irqs(r2d_fpga_irq_set, s, NR_IRQS); |
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} |
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static void r2d_init(ram_addr_t ram_size, int vga_ram_size, |
| ... | ... | |
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CPUState *env; |
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struct SH7750State *s; |
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ram_addr_t sdram_addr, sm501_vga_ram_addr; |
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qemu_irq *irq; |
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if (!cpu_model) |
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cpu_model = "SH7751R"; |
| ... | ... | |
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sdram_addr = qemu_ram_alloc(SDRAM_SIZE); |
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cpu_register_physical_memory(SDRAM_BASE, SDRAM_SIZE, sdram_addr); |
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/* Register peripherals */ |
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r2d_fpga_init(0x04000000); |
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s = sh7750_init(env); |
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irq = r2d_fpga_init(0x04000000, sh7750_irl(s)); |
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sm501_vga_ram_addr = qemu_ram_alloc(SM501_VRAM_SIZE); |
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sm501_init(ds, 0x10000000, sm501_vga_ram_addr, SM501_VRAM_SIZE, |
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serial_hds[2]); |
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/* onboard CF (True IDE mode, Master only). */ |
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mmio_ide_init(0x14001000, 0x1400080c, NULL, 1,
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drives_table[drive_get_index(IF_IDE, 0, 0)].bdrv, NULL);
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mmio_ide_init(0x14001000, 0x1400080c, irq[CF_IDE], 1,
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drives_table[drive_get_index(IF_IDE, 0, 0)].bdrv, NULL); |
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/* Todo: register on board registers */ |
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{
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