root / hw / pxa2xx_gpio.c @ d4970b07
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1 | c1713132 | balrog | /*
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2 | c1713132 | balrog | * Intel XScale PXA255/270 GPIO controller emulation.
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3 | c1713132 | balrog | *
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4 | c1713132 | balrog | * Copyright (c) 2006 Openedhand Ltd.
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5 | c1713132 | balrog | * Written by Andrzej Zaborowski <balrog@zabor.org>
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6 | c1713132 | balrog | *
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7 | c1713132 | balrog | * This code is licensed under the GPL.
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8 | c1713132 | balrog | */
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9 | c1713132 | balrog | |
10 | 87ecb68b | pbrook | #include "hw.h" |
11 | 0bb53337 | Dmitry Eremin-Solenikov | #include "sysbus.h" |
12 | 87ecb68b | pbrook | #include "pxa.h" |
13 | c1713132 | balrog | |
14 | c1713132 | balrog | #define PXA2XX_GPIO_BANKS 4 |
15 | c1713132 | balrog | |
16 | 0bb53337 | Dmitry Eremin-Solenikov | typedef struct PXA2xxGPIOInfo PXA2xxGPIOInfo; |
17 | bc24a225 | Paul Brook | struct PXA2xxGPIOInfo {
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18 | 0bb53337 | Dmitry Eremin-Solenikov | SysBusDevice busdev; |
19 | 0bb53337 | Dmitry Eremin-Solenikov | qemu_irq irq0, irq1, irqX; |
20 | c1713132 | balrog | int lines;
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21 | 0bb53337 | Dmitry Eremin-Solenikov | int ncpu;
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22 | c1713132 | balrog | CPUState *cpu_env; |
23 | c1713132 | balrog | |
24 | c1713132 | balrog | /* XXX: GNU C vectors are more suitable */
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25 | c1713132 | balrog | uint32_t ilevel[PXA2XX_GPIO_BANKS]; |
26 | c1713132 | balrog | uint32_t olevel[PXA2XX_GPIO_BANKS]; |
27 | c1713132 | balrog | uint32_t dir[PXA2XX_GPIO_BANKS]; |
28 | c1713132 | balrog | uint32_t rising[PXA2XX_GPIO_BANKS]; |
29 | c1713132 | balrog | uint32_t falling[PXA2XX_GPIO_BANKS]; |
30 | c1713132 | balrog | uint32_t status[PXA2XX_GPIO_BANKS]; |
31 | 2b76bdc9 | balrog | uint32_t gpsr[PXA2XX_GPIO_BANKS]; |
32 | c1713132 | balrog | uint32_t gafr[PXA2XX_GPIO_BANKS * 2];
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33 | c1713132 | balrog | |
34 | c1713132 | balrog | uint32_t prev_level[PXA2XX_GPIO_BANKS]; |
35 | 38641a52 | balrog | qemu_irq handler[PXA2XX_GPIO_BANKS * 32];
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36 | 38641a52 | balrog | qemu_irq read_notify; |
37 | c1713132 | balrog | }; |
38 | c1713132 | balrog | |
39 | c1713132 | balrog | static struct { |
40 | c1713132 | balrog | enum {
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41 | c1713132 | balrog | GPIO_NONE, |
42 | c1713132 | balrog | GPLR, |
43 | c1713132 | balrog | GPSR, |
44 | c1713132 | balrog | GPCR, |
45 | c1713132 | balrog | GPDR, |
46 | c1713132 | balrog | GRER, |
47 | c1713132 | balrog | GFER, |
48 | c1713132 | balrog | GEDR, |
49 | c1713132 | balrog | GAFR_L, |
50 | c1713132 | balrog | GAFR_U, |
51 | c1713132 | balrog | } reg; |
52 | c1713132 | balrog | int bank;
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53 | c1713132 | balrog | } pxa2xx_gpio_regs[0x200] = {
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54 | c1713132 | balrog | [0 ... 0x1ff] = { GPIO_NONE, 0 }, |
55 | c1713132 | balrog | #define PXA2XX_REG(reg, a0, a1, a2, a3) \
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56 | 5fafdf24 | ths | [a0] = { reg, 0 }, [a1] = { reg, 1 }, [a2] = { reg, 2 }, [a3] = { reg, 3 }, |
57 | c1713132 | balrog | |
58 | c1713132 | balrog | PXA2XX_REG(GPLR, 0x000, 0x004, 0x008, 0x100) |
59 | c1713132 | balrog | PXA2XX_REG(GPSR, 0x018, 0x01c, 0x020, 0x118) |
60 | c1713132 | balrog | PXA2XX_REG(GPCR, 0x024, 0x028, 0x02c, 0x124) |
61 | c1713132 | balrog | PXA2XX_REG(GPDR, 0x00c, 0x010, 0x014, 0x10c) |
62 | c1713132 | balrog | PXA2XX_REG(GRER, 0x030, 0x034, 0x038, 0x130) |
63 | c1713132 | balrog | PXA2XX_REG(GFER, 0x03c, 0x040, 0x044, 0x13c) |
64 | c1713132 | balrog | PXA2XX_REG(GEDR, 0x048, 0x04c, 0x050, 0x148) |
65 | c1713132 | balrog | PXA2XX_REG(GAFR_L, 0x054, 0x05c, 0x064, 0x06c) |
66 | c1713132 | balrog | PXA2XX_REG(GAFR_U, 0x058, 0x060, 0x068, 0x070) |
67 | c1713132 | balrog | }; |
68 | c1713132 | balrog | |
69 | bc24a225 | Paul Brook | static void pxa2xx_gpio_irq_update(PXA2xxGPIOInfo *s) |
70 | c1713132 | balrog | { |
71 | c1713132 | balrog | if (s->status[0] & (1 << 0)) |
72 | 0bb53337 | Dmitry Eremin-Solenikov | qemu_irq_raise(s->irq0); |
73 | c1713132 | balrog | else
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74 | 0bb53337 | Dmitry Eremin-Solenikov | qemu_irq_lower(s->irq0); |
75 | c1713132 | balrog | |
76 | c1713132 | balrog | if (s->status[0] & (1 << 1)) |
77 | 0bb53337 | Dmitry Eremin-Solenikov | qemu_irq_raise(s->irq1); |
78 | c1713132 | balrog | else
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79 | 0bb53337 | Dmitry Eremin-Solenikov | qemu_irq_lower(s->irq1); |
80 | c1713132 | balrog | |
81 | c1713132 | balrog | if ((s->status[0] & ~3) | s->status[1] | s->status[2] | s->status[3]) |
82 | 0bb53337 | Dmitry Eremin-Solenikov | qemu_irq_raise(s->irqX); |
83 | c1713132 | balrog | else
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84 | 0bb53337 | Dmitry Eremin-Solenikov | qemu_irq_lower(s->irqX); |
85 | c1713132 | balrog | } |
86 | c1713132 | balrog | |
87 | c1713132 | balrog | /* Bitmap of pins used as standby and sleep wake-up sources. */
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88 | 38641a52 | balrog | static const int pxa2xx_gpio_wake[PXA2XX_GPIO_BANKS] = { |
89 | c1713132 | balrog | 0x8003fe1b, 0x002001fc, 0xec080000, 0x0012007f, |
90 | c1713132 | balrog | }; |
91 | c1713132 | balrog | |
92 | 38641a52 | balrog | static void pxa2xx_gpio_set(void *opaque, int line, int level) |
93 | c1713132 | balrog | { |
94 | bc24a225 | Paul Brook | PXA2xxGPIOInfo *s = (PXA2xxGPIOInfo *) opaque; |
95 | c1713132 | balrog | int bank;
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96 | c1713132 | balrog | uint32_t mask; |
97 | c1713132 | balrog | |
98 | c1713132 | balrog | if (line >= s->lines) {
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99 | c1713132 | balrog | printf("%s: No GPIO pin %i\n", __FUNCTION__, line);
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100 | c1713132 | balrog | return;
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101 | c1713132 | balrog | } |
102 | c1713132 | balrog | |
103 | c1713132 | balrog | bank = line >> 5;
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104 | c1713132 | balrog | mask = 1 << (line & 31); |
105 | c1713132 | balrog | |
106 | c1713132 | balrog | if (level) {
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107 | c1713132 | balrog | s->status[bank] |= s->rising[bank] & mask & |
108 | c1713132 | balrog | ~s->ilevel[bank] & ~s->dir[bank]; |
109 | c1713132 | balrog | s->ilevel[bank] |= mask; |
110 | c1713132 | balrog | } else {
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111 | c1713132 | balrog | s->status[bank] |= s->falling[bank] & mask & |
112 | c1713132 | balrog | s->ilevel[bank] & ~s->dir[bank]; |
113 | c1713132 | balrog | s->ilevel[bank] &= ~mask; |
114 | c1713132 | balrog | } |
115 | c1713132 | balrog | |
116 | c1713132 | balrog | if (s->status[bank] & mask)
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117 | c1713132 | balrog | pxa2xx_gpio_irq_update(s); |
118 | c1713132 | balrog | |
119 | c1713132 | balrog | /* Wake-up GPIOs */
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120 | c1713132 | balrog | if (s->cpu_env->halted && (mask & ~s->dir[bank] & pxa2xx_gpio_wake[bank]))
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121 | c1713132 | balrog | cpu_interrupt(s->cpu_env, CPU_INTERRUPT_EXITTB); |
122 | c1713132 | balrog | } |
123 | c1713132 | balrog | |
124 | bc24a225 | Paul Brook | static void pxa2xx_gpio_handler_update(PXA2xxGPIOInfo *s) { |
125 | c1713132 | balrog | uint32_t level, diff; |
126 | c1713132 | balrog | int i, bit, line;
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127 | c1713132 | balrog | for (i = 0; i < PXA2XX_GPIO_BANKS; i ++) { |
128 | c1713132 | balrog | level = s->olevel[i] & s->dir[i]; |
129 | c1713132 | balrog | |
130 | c1713132 | balrog | for (diff = s->prev_level[i] ^ level; diff; diff ^= 1 << bit) { |
131 | c1713132 | balrog | bit = ffs(diff) - 1;
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132 | c1713132 | balrog | line = bit + 32 * i;
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133 | 38641a52 | balrog | qemu_set_irq(s->handler[line], (level >> bit) & 1);
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134 | c1713132 | balrog | } |
135 | c1713132 | balrog | |
136 | c1713132 | balrog | s->prev_level[i] = level; |
137 | c1713132 | balrog | } |
138 | c1713132 | balrog | } |
139 | c1713132 | balrog | |
140 | c227f099 | Anthony Liguori | static uint32_t pxa2xx_gpio_read(void *opaque, target_phys_addr_t offset) |
141 | c1713132 | balrog | { |
142 | bc24a225 | Paul Brook | PXA2xxGPIOInfo *s = (PXA2xxGPIOInfo *) opaque; |
143 | c1713132 | balrog | uint32_t ret; |
144 | c1713132 | balrog | int bank;
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145 | c1713132 | balrog | if (offset >= 0x200) |
146 | c1713132 | balrog | return 0; |
147 | c1713132 | balrog | |
148 | c1713132 | balrog | bank = pxa2xx_gpio_regs[offset].bank; |
149 | c1713132 | balrog | switch (pxa2xx_gpio_regs[offset].reg) {
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150 | c1713132 | balrog | case GPDR: /* GPIO Pin-Direction registers */ |
151 | c1713132 | balrog | return s->dir[bank];
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152 | c1713132 | balrog | |
153 | 2b76bdc9 | balrog | case GPSR: /* GPIO Pin-Output Set registers */ |
154 | 2b76bdc9 | balrog | printf("%s: Read from a write-only register " REG_FMT "\n", |
155 | 2b76bdc9 | balrog | __FUNCTION__, offset); |
156 | 2b76bdc9 | balrog | return s->gpsr[bank]; /* Return last written value. */ |
157 | 2b76bdc9 | balrog | |
158 | e1dad5a6 | balrog | case GPCR: /* GPIO Pin-Output Clear registers */ |
159 | e1dad5a6 | balrog | printf("%s: Read from a write-only register " REG_FMT "\n", |
160 | e1dad5a6 | balrog | __FUNCTION__, offset); |
161 | e1dad5a6 | balrog | return 31337; /* Specified as unpredictable in the docs. */ |
162 | e1dad5a6 | balrog | |
163 | c1713132 | balrog | case GRER: /* GPIO Rising-Edge Detect Enable registers */ |
164 | c1713132 | balrog | return s->rising[bank];
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165 | c1713132 | balrog | |
166 | c1713132 | balrog | case GFER: /* GPIO Falling-Edge Detect Enable registers */ |
167 | c1713132 | balrog | return s->falling[bank];
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168 | c1713132 | balrog | |
169 | c1713132 | balrog | case GAFR_L: /* GPIO Alternate Function registers */ |
170 | c1713132 | balrog | return s->gafr[bank * 2]; |
171 | c1713132 | balrog | |
172 | c1713132 | balrog | case GAFR_U: /* GPIO Alternate Function registers */ |
173 | c1713132 | balrog | return s->gafr[bank * 2 + 1]; |
174 | c1713132 | balrog | |
175 | c1713132 | balrog | case GPLR: /* GPIO Pin-Level registers */ |
176 | c1713132 | balrog | ret = (s->olevel[bank] & s->dir[bank]) | |
177 | c1713132 | balrog | (s->ilevel[bank] & ~s->dir[bank]); |
178 | 38641a52 | balrog | qemu_irq_raise(s->read_notify); |
179 | c1713132 | balrog | return ret;
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180 | c1713132 | balrog | |
181 | c1713132 | balrog | case GEDR: /* GPIO Edge Detect Status registers */ |
182 | c1713132 | balrog | return s->status[bank];
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183 | c1713132 | balrog | |
184 | c1713132 | balrog | default:
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185 | 2ac71179 | Paul Brook | hw_error("%s: Bad offset " REG_FMT "\n", __FUNCTION__, offset); |
186 | c1713132 | balrog | } |
187 | c1713132 | balrog | |
188 | c1713132 | balrog | return 0; |
189 | c1713132 | balrog | } |
190 | c1713132 | balrog | |
191 | c1713132 | balrog | static void pxa2xx_gpio_write(void *opaque, |
192 | c227f099 | Anthony Liguori | target_phys_addr_t offset, uint32_t value) |
193 | c1713132 | balrog | { |
194 | bc24a225 | Paul Brook | PXA2xxGPIOInfo *s = (PXA2xxGPIOInfo *) opaque; |
195 | c1713132 | balrog | int bank;
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196 | c1713132 | balrog | if (offset >= 0x200) |
197 | c1713132 | balrog | return;
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198 | c1713132 | balrog | |
199 | c1713132 | balrog | bank = pxa2xx_gpio_regs[offset].bank; |
200 | c1713132 | balrog | switch (pxa2xx_gpio_regs[offset].reg) {
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201 | c1713132 | balrog | case GPDR: /* GPIO Pin-Direction registers */ |
202 | c1713132 | balrog | s->dir[bank] = value; |
203 | c1713132 | balrog | pxa2xx_gpio_handler_update(s); |
204 | c1713132 | balrog | break;
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205 | c1713132 | balrog | |
206 | c1713132 | balrog | case GPSR: /* GPIO Pin-Output Set registers */ |
207 | c1713132 | balrog | s->olevel[bank] |= value; |
208 | c1713132 | balrog | pxa2xx_gpio_handler_update(s); |
209 | 2b76bdc9 | balrog | s->gpsr[bank] = value; |
210 | c1713132 | balrog | break;
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211 | c1713132 | balrog | |
212 | c1713132 | balrog | case GPCR: /* GPIO Pin-Output Clear registers */ |
213 | c1713132 | balrog | s->olevel[bank] &= ~value; |
214 | c1713132 | balrog | pxa2xx_gpio_handler_update(s); |
215 | c1713132 | balrog | break;
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216 | c1713132 | balrog | |
217 | c1713132 | balrog | case GRER: /* GPIO Rising-Edge Detect Enable registers */ |
218 | c1713132 | balrog | s->rising[bank] = value; |
219 | c1713132 | balrog | break;
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220 | c1713132 | balrog | |
221 | c1713132 | balrog | case GFER: /* GPIO Falling-Edge Detect Enable registers */ |
222 | c1713132 | balrog | s->falling[bank] = value; |
223 | c1713132 | balrog | break;
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224 | c1713132 | balrog | |
225 | c1713132 | balrog | case GAFR_L: /* GPIO Alternate Function registers */ |
226 | c1713132 | balrog | s->gafr[bank * 2] = value;
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227 | c1713132 | balrog | break;
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228 | c1713132 | balrog | |
229 | c1713132 | balrog | case GAFR_U: /* GPIO Alternate Function registers */ |
230 | c1713132 | balrog | s->gafr[bank * 2 + 1] = value; |
231 | c1713132 | balrog | break;
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232 | c1713132 | balrog | |
233 | c1713132 | balrog | case GEDR: /* GPIO Edge Detect Status registers */ |
234 | c1713132 | balrog | s->status[bank] &= ~value; |
235 | c1713132 | balrog | pxa2xx_gpio_irq_update(s); |
236 | c1713132 | balrog | break;
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237 | c1713132 | balrog | |
238 | c1713132 | balrog | default:
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239 | 2ac71179 | Paul Brook | hw_error("%s: Bad offset " REG_FMT "\n", __FUNCTION__, offset); |
240 | c1713132 | balrog | } |
241 | c1713132 | balrog | } |
242 | c1713132 | balrog | |
243 | d60efc6b | Blue Swirl | static CPUReadMemoryFunc * const pxa2xx_gpio_readfn[] = { |
244 | c1713132 | balrog | pxa2xx_gpio_read, |
245 | c1713132 | balrog | pxa2xx_gpio_read, |
246 | c1713132 | balrog | pxa2xx_gpio_read |
247 | c1713132 | balrog | }; |
248 | c1713132 | balrog | |
249 | d60efc6b | Blue Swirl | static CPUWriteMemoryFunc * const pxa2xx_gpio_writefn[] = { |
250 | c1713132 | balrog | pxa2xx_gpio_write, |
251 | c1713132 | balrog | pxa2xx_gpio_write, |
252 | c1713132 | balrog | pxa2xx_gpio_write |
253 | c1713132 | balrog | }; |
254 | c1713132 | balrog | |
255 | 0bb53337 | Dmitry Eremin-Solenikov | DeviceState *pxa2xx_gpio_init(target_phys_addr_t base, |
256 | e1f8c729 | Dmitry Eremin-Solenikov | CPUState *env, DeviceState *pic, int lines)
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257 | aa941b94 | balrog | { |
258 | 0bb53337 | Dmitry Eremin-Solenikov | DeviceState *dev; |
259 | aa941b94 | balrog | |
260 | 0bb53337 | Dmitry Eremin-Solenikov | dev = qdev_create(NULL, "pxa2xx-gpio"); |
261 | 0bb53337 | Dmitry Eremin-Solenikov | qdev_prop_set_int32(dev, "lines", lines);
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262 | 0bb53337 | Dmitry Eremin-Solenikov | qdev_prop_set_int32(dev, "ncpu", env->cpu_index);
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263 | 0bb53337 | Dmitry Eremin-Solenikov | qdev_init_nofail(dev); |
264 | aa941b94 | balrog | |
265 | 0bb53337 | Dmitry Eremin-Solenikov | sysbus_mmio_map(sysbus_from_qdev(dev), 0, base);
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266 | e1f8c729 | Dmitry Eremin-Solenikov | sysbus_connect_irq(sysbus_from_qdev(dev), 0,
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267 | e1f8c729 | Dmitry Eremin-Solenikov | qdev_get_gpio_in(pic, PXA2XX_PIC_GPIO_0)); |
268 | e1f8c729 | Dmitry Eremin-Solenikov | sysbus_connect_irq(sysbus_from_qdev(dev), 1,
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269 | e1f8c729 | Dmitry Eremin-Solenikov | qdev_get_gpio_in(pic, PXA2XX_PIC_GPIO_1)); |
270 | e1f8c729 | Dmitry Eremin-Solenikov | sysbus_connect_irq(sysbus_from_qdev(dev), 2,
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271 | e1f8c729 | Dmitry Eremin-Solenikov | qdev_get_gpio_in(pic, PXA2XX_PIC_GPIO_X)); |
272 | aa941b94 | balrog | |
273 | 0bb53337 | Dmitry Eremin-Solenikov | return dev;
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274 | aa941b94 | balrog | } |
275 | aa941b94 | balrog | |
276 | 0bb53337 | Dmitry Eremin-Solenikov | static int pxa2xx_gpio_initfn(SysBusDevice *dev) |
277 | c1713132 | balrog | { |
278 | c1713132 | balrog | int iomemtype;
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279 | bc24a225 | Paul Brook | PXA2xxGPIOInfo *s; |
280 | c1713132 | balrog | |
281 | 0bb53337 | Dmitry Eremin-Solenikov | s = FROM_SYSBUS(PXA2xxGPIOInfo, dev); |
282 | c1713132 | balrog | |
283 | 0bb53337 | Dmitry Eremin-Solenikov | s->cpu_env = qemu_get_cpu(s->ncpu); |
284 | c1713132 | balrog | |
285 | 0bb53337 | Dmitry Eremin-Solenikov | qdev_init_gpio_in(&dev->qdev, pxa2xx_gpio_set, s->lines); |
286 | 0bb53337 | Dmitry Eremin-Solenikov | qdev_init_gpio_out(&dev->qdev, s->handler, s->lines); |
287 | c1713132 | balrog | |
288 | 0bb53337 | Dmitry Eremin-Solenikov | iomemtype = cpu_register_io_memory(pxa2xx_gpio_readfn, |
289 | 0bb53337 | Dmitry Eremin-Solenikov | pxa2xx_gpio_writefn, s, DEVICE_NATIVE_ENDIAN); |
290 | 38641a52 | balrog | |
291 | 0bb53337 | Dmitry Eremin-Solenikov | sysbus_init_mmio(dev, 0x1000, iomemtype);
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292 | 0bb53337 | Dmitry Eremin-Solenikov | sysbus_init_irq(dev, &s->irq0); |
293 | 0bb53337 | Dmitry Eremin-Solenikov | sysbus_init_irq(dev, &s->irq1); |
294 | 0bb53337 | Dmitry Eremin-Solenikov | sysbus_init_irq(dev, &s->irqX); |
295 | c1713132 | balrog | |
296 | 0bb53337 | Dmitry Eremin-Solenikov | return 0; |
297 | c1713132 | balrog | } |
298 | c1713132 | balrog | |
299 | c1713132 | balrog | /*
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300 | c1713132 | balrog | * Registers a callback to notify on GPLR reads. This normally
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301 | c1713132 | balrog | * shouldn't be needed but it is used for the hack on Spitz machines.
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302 | c1713132 | balrog | */
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303 | 0bb53337 | Dmitry Eremin-Solenikov | void pxa2xx_gpio_read_notifier(DeviceState *dev, qemu_irq handler)
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304 | 38641a52 | balrog | { |
305 | 0bb53337 | Dmitry Eremin-Solenikov | PXA2xxGPIOInfo *s = FROM_SYSBUS(PXA2xxGPIOInfo, sysbus_from_qdev(dev)); |
306 | c1713132 | balrog | s->read_notify = handler; |
307 | c1713132 | balrog | } |
308 | 0bb53337 | Dmitry Eremin-Solenikov | |
309 | 0bb53337 | Dmitry Eremin-Solenikov | static const VMStateDescription vmstate_pxa2xx_gpio_regs = { |
310 | 0bb53337 | Dmitry Eremin-Solenikov | .name = "pxa2xx-gpio",
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311 | 0bb53337 | Dmitry Eremin-Solenikov | .version_id = 1,
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312 | 0bb53337 | Dmitry Eremin-Solenikov | .minimum_version_id = 1,
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313 | 0bb53337 | Dmitry Eremin-Solenikov | .minimum_version_id_old = 1,
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314 | 0bb53337 | Dmitry Eremin-Solenikov | .fields = (VMStateField []) { |
315 | 0bb53337 | Dmitry Eremin-Solenikov | VMSTATE_INT32(lines, PXA2xxGPIOInfo), |
316 | 0bb53337 | Dmitry Eremin-Solenikov | VMSTATE_UINT32_ARRAY(ilevel, PXA2xxGPIOInfo, PXA2XX_GPIO_BANKS), |
317 | 0bb53337 | Dmitry Eremin-Solenikov | VMSTATE_UINT32_ARRAY(olevel, PXA2xxGPIOInfo, PXA2XX_GPIO_BANKS), |
318 | 0bb53337 | Dmitry Eremin-Solenikov | VMSTATE_UINT32_ARRAY(dir, PXA2xxGPIOInfo, PXA2XX_GPIO_BANKS), |
319 | 0bb53337 | Dmitry Eremin-Solenikov | VMSTATE_UINT32_ARRAY(rising, PXA2xxGPIOInfo, PXA2XX_GPIO_BANKS), |
320 | 0bb53337 | Dmitry Eremin-Solenikov | VMSTATE_UINT32_ARRAY(falling, PXA2xxGPIOInfo, PXA2XX_GPIO_BANKS), |
321 | 0bb53337 | Dmitry Eremin-Solenikov | VMSTATE_UINT32_ARRAY(status, PXA2xxGPIOInfo, PXA2XX_GPIO_BANKS), |
322 | 0bb53337 | Dmitry Eremin-Solenikov | VMSTATE_UINT32_ARRAY(gafr, PXA2xxGPIOInfo, PXA2XX_GPIO_BANKS * 2),
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323 | 0bb53337 | Dmitry Eremin-Solenikov | VMSTATE_END_OF_LIST(), |
324 | 0bb53337 | Dmitry Eremin-Solenikov | }, |
325 | 0bb53337 | Dmitry Eremin-Solenikov | }; |
326 | 0bb53337 | Dmitry Eremin-Solenikov | |
327 | 0bb53337 | Dmitry Eremin-Solenikov | static SysBusDeviceInfo pxa2xx_gpio_info = {
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328 | 0bb53337 | Dmitry Eremin-Solenikov | .init = pxa2xx_gpio_initfn, |
329 | 0bb53337 | Dmitry Eremin-Solenikov | .qdev.name = "pxa2xx-gpio",
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330 | 0bb53337 | Dmitry Eremin-Solenikov | .qdev.desc = "PXA2xx GPIO controller",
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331 | 0bb53337 | Dmitry Eremin-Solenikov | .qdev.size = sizeof(PXA2xxGPIOInfo),
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332 | 0bb53337 | Dmitry Eremin-Solenikov | .qdev.props = (Property []) { |
333 | 0bb53337 | Dmitry Eremin-Solenikov | DEFINE_PROP_INT32("lines", PXA2xxGPIOInfo, lines, 0), |
334 | 0bb53337 | Dmitry Eremin-Solenikov | DEFINE_PROP_INT32("ncpu", PXA2xxGPIOInfo, ncpu, 0), |
335 | 0bb53337 | Dmitry Eremin-Solenikov | DEFINE_PROP_END_OF_LIST(), |
336 | 0bb53337 | Dmitry Eremin-Solenikov | } |
337 | 0bb53337 | Dmitry Eremin-Solenikov | }; |
338 | 0bb53337 | Dmitry Eremin-Solenikov | |
339 | 0bb53337 | Dmitry Eremin-Solenikov | static void pxa2xx_gpio_register(void) |
340 | 0bb53337 | Dmitry Eremin-Solenikov | { |
341 | 0bb53337 | Dmitry Eremin-Solenikov | sysbus_register_withprop(&pxa2xx_gpio_info); |
342 | 0bb53337 | Dmitry Eremin-Solenikov | } |
343 | 0bb53337 | Dmitry Eremin-Solenikov | device_init(pxa2xx_gpio_register); |